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1
Raman, Karthik, and Andreas Wagner. "The evolvability of programmable hardware." Journal of The Royal Society Interface 8, no. 55 (June 9, 2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.
Повний текст джерелаАнотація:
In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10 45 logic circuits (‘genotypes’) and 10 19 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.
2
D'Ari, Richard, and René Thomas. "Hardware (DNA) circuits." Comptes Rendus Biologies 326, no. 2 (February 2003): 215–17. http://dx.doi.org/10.1016/s1631-0691(03)00066-0.
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Li, Zeyu, Junjie Wang, Zhao Huang, Nan Luo, and Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware." Applied Sciences 12, no. 13 (June 29, 2022): 6601. http://dx.doi.org/10.3390/app12136601.
Повний текст джерелаАнотація:
Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.
4
Kerschbaumer, Ricardo, Robson R. Linhares, Jean M. Simão, Paulo C. Stadzisz, and Carlos R. Erig Lima. "Notification-Oriented Paradigm to Implement Digital Hardware." Journal of Circuits, Systems and Computers 27, no. 08 (April 12, 2018): 1850124. http://dx.doi.org/10.1142/s0218126618501244.
Повний текст джерелаАнотація:
The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.
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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (May 28, 2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.
Повний текст джерелаАнотація:
<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.<strong></strong></p>
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PARK, SUNGWOO, and HYEONSEUNG IM. "A calculus for hardware description." Journal of Functional Programming 21, no. 1 (November 19, 2010): 21–58. http://dx.doi.org/10.1017/s0956796810000249.
Повний текст джерелаАнотація:
AbstractIn efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a calculus, called lλ (linear lambda), which may serve as an intermediate functional language just above netlists in the hierarchy of hardware description languages. In order to support higher-order functions, lλ uses a linear type system, which enforces the linear use of variables of function type. The translation of lλ into structural descriptions of hardware circuits is sound and complete in the sense that it maps expressions only to realizable hardware circuits, and that every realizable hardware circuit has a corresponding expression in lλ. To illustrate the use of lλ as a practical intermediate language for hardware description, we design a simple hardware description language that extends lλ with polymorphism, and use it to implement a fast Fourier transform circuit and a bitonic sorting network.
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Li, Chun Feng, Ke Ming Li, and Xiang Zhang. "Research on Circuit Design for Speed Adjusting Hardware of Brushless DC Motor Based on the Two-Dimensional Fuzzy Controller." Advanced Materials Research 705 (June 2013): 509–15. http://dx.doi.org/10.4028/www.scientific.net/amr.705.509.
Повний текст джерелаАнотація:
The essay first establishes the general design for intelligent rotary speed system of the brushless DC motors, then based on the general design scheme, two-dimensional fuzzy controller, adaptive current adjustor and mainly used hardware circuits are designed. The mainly used hardware circuit design includes the circuit design of current detecting circuit, voltage detecting circuit, high-speed optocoupler, motor driver circuit, zero-crossing comparator circuit, etc. At last the designed controller and hardware circuits are tested to achieve optimum effects for rotary speed control through validation of experimental devices.
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Shibata, Tadashi, and Tadahiro Ohmi. "Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors." Journal of Robotics and Mechatronics 8, no. 6 (December 20, 1996): 508–15. http://dx.doi.org/10.20965/jrm.1996.p0508.
Повний текст джерелаАнотація:
The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.
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Katoh, Yusuke, Hironari Yoshiuchi, Yoshio Murata, and Hironori Nakajo. "Scalable Hardware Mechanism for Partitioned Circuits Operation." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 12, no. 2 (December 16, 2018): 90–97. http://dx.doi.org/10.37936/ecti-cit.2018122.142511.
Повний текст джерелаАнотація:
For designing hardware with a high-level synthesis tool using a programming language such as C or Java, its large size of logic circuit makes it difficult to implement the design in a single FPGA. In such a case, partitioning the logic circuit and implementing in multiple FPGAs is a commonly used approach.
We propose the Scalable Hardware Mechanism, which enables the operation of a partitioned circuit to prevent the degradation of clock frequency by minimizing its dependence on the usage and the type of FPGA. Our mechanism provides a reduced delay by the collective signal transmission with the partitioned AES code generation circuit and the character string edit distance calculation circuit as partitioned circuits. The collective signal transmission has attained 1.27 times improvement in the speed for the AES code generation circuit and 3.16 times improvement for the character string edit distance calculation circuit compared with the circuit by the conventional method.
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Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.
Повний текст джерелаАнотація:
Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to develop a qualitative appreciation for the circuits under study.
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Shi, Zhendong, Haocheng Ma, Qizhi Zhang, Yanjiang Liu, Yiqiang Zhao, and Jiaji He. "Test Generation for Hardware Trojan Detection Using Correlation Analysis and Genetic Algorithm." ACM Transactions on Embedded Computing Systems 20, no. 4 (June 2021): 1–20. http://dx.doi.org/10.1145/3446837.
Повний текст джерелаАнотація:
Hardware Trojan (HT) is a major threat to the security of integrated circuits (ICs). Among various HT detection approaches, side channel analysis (SCA)-based methods have been extensively studied. SCA-based methods try to detect HTs by comparing side channel signatures from circuits under test with those from trusted golden references. The pre-condition for SCA-based HT detection to work is that the testers can collect extra signatures/anomalies introduced by activated HTs. Thus, activation of HTs and amplification of the differences between circuits under test and golden references are the keys to SCA-based HT detection methods. Test vectors are of great importance to the activation of HTs, but existing test generation methods have two major limitations. First, the number of test vectors required to trigger HTs is quite large. Second, the HT circuit’s activities are marginal compared with the whole circuit’s activities. In this article, we propose an optimized test generation methodology to assist SCA-based HT detection. Considering the HTs’ inherent surreptitious nature, inactive nodes with low transition probability are more likely to be selected as HT trigger nodes. Therefore, the correlations between circuit inputs and inactive nodes are first exploited to activate HTs. Then a test reordering process based on the genetic algorithm (GA) is implemented to increase the proportion of the HT circuit’s activities to the whole circuit’s activities. Experiments on 10 selected ISCAS benchmarks, wb_conmax benchmark, and b17 benchmark demonstrate that the number of test vectors required to trigger HTs reduces 28.8% on average compared with the result of MERO and MERS methods. After the test vector reordering process, the proportion of the HT circuit’s activities to the whole circuit’s activities is improved by 95% on average, compared with the result of MERS method.
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Rajeswaran, N., T. Madhu, and M. Suryakalavathi. "Hardware Testable Design of Genetic Algorithm for VLSI Circuits." Applied Mechanics and Materials 367 (August 2013): 245–49. http://dx.doi.org/10.4028/www.scientific.net/amm.367.245.
Повний текст джерелаАнотація:
Accurate and fast testing of digital circuits is very much essential in real time applications. Hardware analysis of digital circuits, which is otherwise very tedious and time consuming, is attempted using the artificial intelligence technique: Genetic Algorithms (GA). GA is used to find an input sequence to a digital circuit for testing, as it reduces the hardware utilization, complexity and computational time of the circuits. All the GA processes are simulated and implemented by using Xilinx 10.1 and SPARTAN 3E.
13
Xu, Wei, and Ning Cao. "A General Chaotic Circuit Design and Hardware Implementation via the Inductance Integrators." Journal of Circuits, Systems and Computers 29, no. 10 (December 16, 2019): 2050159. http://dx.doi.org/10.1142/s0218126620501595.
Повний текст джерелаАнотація:
This paper presents a scheme for the modified chaotic circuits based on inductance integration. In view of the fact that the DC resistance of an inductor in the circuit cannot be ignored, this way of constructing the circuits is provided that can eliminate its influence on the integral circuits. By means of cascading an inverting adder circuit and inductance integral circuit, the output signal of the integral circuit is fed back to the inverting adder circuit, and its additive term is artificially added to match the actual inductance integrated circuit to achieve integral circuit based on the actual inductor which can offset the effect of its DC resistance. In order to verify the generality of the design, the process of designing Lorenz chaotic circuit is given and its attractors can also be observed from the oscilloscope.
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Yang, Le, Zhao Yang Guo, Shan Shan Yong, Feng Guo, and Xin An Wang. "A Hardware Implementation of Real Time Lossless Data Compression and Decompression Circuits." Applied Mechanics and Materials 719-720 (January 2015): 554–60. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.554.
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This paper presents a hardware implementation of real time data compression and decompression circuits based on the LZW algorithm. LZW is a dictionary based data compression, which has the advantage of fast speed, high compression, and small resource occupation. In compression circuit, the design creatively utilizes two dictionaries alternately to improve efficiency and compressing rate. In decompression circuit, an integrated State machine control module is adopted to save hardware resource. Through hardware description and language programming, the circuits finally reach function simulation and timing simulation. The width of data sample is 12bits, and the dictionary storage capacity is 1K. The simulation results show the compression and decompression circuits have complete function. Compared to software method, hardware implementation can save more storage and compressing time. It has a high practical value in the future.
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Zhang, Ping, and Zuo Cheng Xing. "Design and Implementation of Debugging Structure in Full-Custom CPU." Advanced Materials Research 211-212 (February 2011): 861–65. http://dx.doi.org/10.4028/www.scientific.net/amr.211-212.861.
Повний текст джерелаАнотація:
With the development of integrated circuit technology, it is more and more difficult for debugging circuits. Generally, to achieve a powerful debugging capability of circuits is often at the expense of larger cost of hardware overhead .This paper propose a method of debugging structure designed in full-custom CPU based on scan-set testability methods and combed with the boundary-scan technology. This debugging structure can reduces much scan chains hardware overheads and is applicable to all general-purpose CPU chips. Moreover, it owns a powerful debugging capability which is observing and controlling the internal registers of circuits from JTAG port. This structure only increases the difficulty of the circuit logic design, but greatly decreases the cost of hardware.
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Weder, Benjamin, Johanna Barzen, Frank Leymann, and Marie Salm. "Automated Quantum Hardware Selection for Quantum Workflows." Electronics 10, no. 8 (April 20, 2021): 984. http://dx.doi.org/10.3390/electronics10080984.
Повний текст джерелаАнотація:
The execution of a quantum algorithm typically requires various classical pre- and post-processing tasks. Hence, workflows are a promising means to orchestrate these tasks, benefiting from their reliability, robustness, and features, such as transactional processing. However, the implementations of the tasks may be very heterogeneous and they depend on the quantum hardware used to execute the quantum circuits of the algorithm. Additionally, today’s quantum computers are still restricted, which limits the size of the quantum circuits that can be executed. As the circuit size often depends on the input data of the algorithm, the selection of quantum hardware to execute a quantum circuit must be done at workflow runtime. However, modeling all possible alternative tasks would clutter the workflow model and require its adaptation whenever a new quantum computer or software tool is released. To overcome this problem, we introduce an approach to automatically select suitable quantum hardware for the execution of quantum circuits in workflows. Furthermore, it enables the dynamic adaptation of the workflows, depending on the selection at runtime based on reusable workflow fragments. We validate our approach with a prototypical implementation and a case study demonstrating the hardware selection for Simon’s algorithm.
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Huang, Kun, Li Hua Wang, and Xiao Jiang Hao. "The Measure and Control System Design for Temperature and Humidity in General Storeroom." Advanced Materials Research 710 (June 2013): 515–18. http://dx.doi.org/10.4028/www.scientific.net/amr.710.515.
Повний текст джерелаАнотація:
Based on the STC89C52 MCU as the core, this paper designs the measure and control system for temperature and humidity in general storeroom. The system includes two parts: hardware circuits design and software design. The hardware circuits include MCU smallest system, temperature and humidity signal acquisition circuit, keyboard circuit, LCD display circuit, control circuit and alarm circuit; the software includes main program and subroutines (temperature and humidity setting, acquisition, display and overrun processing, etc.). Through system function debugging, the system can realize the temperature and humidity information acquisition, display and control.
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Curtis, K. M. "Warnier-Orr: An Electronic Hardware Design Methodology." International Journal of Electrical Engineering & Education 26, no. 3 (July 1989): 197–205. http://dx.doi.org/10.1177/002072098902600302.
Повний текст джерелаАнотація:
The paper considers the application of a well-known computer programming methodology to the design of electronic circuits. Parallels are drawn between real-life situations, computer programs and electronic circuit design. Examples of the application of the methodology are given in each case.
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Mohan, Navya, and J. P. Anita. "Early Detection of Clustered Trojan Attacks on Integrated Circuits Using Transition Delay Fault Model." Cryptography 7, no. 1 (January 28, 2023): 4. http://dx.doi.org/10.3390/cryptography7010004.
Повний текст джерелаАнотація:
The chances of detecting a malicious reliability attack induced by an offshore foundry are grim. The hardware Trojans affecting a circuit’s reliability do not tend to alter the circuit layout. These Trojans often manifest as an increased delay in certain parts of the circuit. These delay faults easily escape during the integrated circuits (IC) testing phase, hence are difficult to detect. If additional patterns to detect delay faults are generated during the test pattern generation stage, then reliability attacks can be detected early without any hardware overhead. This paper proposes a novel method to generate patterns that trigger Trojans without altering the circuit model. The generated patterns’ ability to diagnose clustered Trojans are also analyzed. The proposed method uses only single fault simulation to detect clustered Trojans, thereby reducing the computational complexity. Experimental results show that the proposed algorithm has a detection ratio of 99.99% when applied on ISCAS’89, ITC’99 and IWLS’05 benchmark circuits. Experiments on clustered Trojans indicate a 46% and 34% improvement in accuracy and resolution compared to a standard Automatic Test Pattern Generator (ATPG)Tool.
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Breslin, Catherine, and Adrian O'Lenskie. "Neuromorphic hardware databases for exploring structure–function relationships in the brain." Philosophical Transactions of the Royal Society of London. Series B: Biological Sciences 356, no. 1412 (August 29, 2001): 1249–58. http://dx.doi.org/10.1098/rstb.2001.0904.
Повний текст джерелаАнотація:
Neuromorphic hardware is the term used to describe full custom–designed integrated circuits, or silicon ‘chips’, that are the product of neuromorphic engineering—a methodology for the synthesis of biologically inspired elements and systems, such as individual neurons, retinae, cochleas, oculomotor systems and central pattern generators. We focus on the implementation of neurons and networks of neurons, designed to illuminate structure–function relationships. Neuromorphic hardware can be constructed with either digital or analogue circuitry or with mixed–signal circuitry—a hybrid of the two. Currently, most examples of this type of hardware are constructed using analogue circuits, in complementary metal–oxide–semiconductor technology. The correspondence between these circuits and neurons, or networks of neurons, can exist at a number of levels. At the lowest level, this correspondence is between membrane ion channels and field–effect transistors. At higher levels, the correspondence is between whole conductances and firing behaviour, and filters and amplifiers, devices found in conventional integrated circuit design. Similarly, neuromorphic engineers can choose to design Hodgkin–Huxley model neurons, or reduced models, such as integrate–and–fire neurons. In addition to the choice of level, there is also choice within the design technique itself; for example, resistive and capacitive properties of the neuronal membrane can be constructed with extrinsic devices, or using the intrinsic properties of the materials from which the transistors themselves are composed. So, silicon neurons can be built, with dendritic, somatic and axonal structures, and endowed with ionic, synaptic and morphological properties. Examples of the structure–function relationships already explored using neuromorphic hardware include correlation detection and direction selectivity. Establishing a database for this hardware is valuable for two reasons: first, independently of neuroscientific motivations, the field of neuromorphic engineering would benefit greatly from a resource in which circuit designs could be stored in a form appropriate for reuse and re–fabrication. Analogue designers would benefit particularly from such a database, as there are no equivalents to the algorithmic design methods available to designers of digital circuits. Second, and more importantly for the purpose of this theme issue, is the possibility of a database of silicon neuron designs replicating specific neuronal types and morphologies. In the future, it may be possible to use an automated process to translate morphometric data directly into circuit design compatible formats. The question that needs to be addressed is: what could a neuromorphic hardware database contribute to the wider neuroscientific community that a conventional database could not? One answer is that neuromorphic hardware is expected to provide analogue sensory–motor systems for interfacing the computational power of symbolic, digital systems with the external, analogue environment. It is also expected to contribute to ongoing work in neural–silicon interfaces and prosthetics. Finally, there is a possibility that the use of evolving circuits, using reconfigurable hardware and genetic algorithms, will create an explosion in the number of designs available to the neuroscience community. All this creates the need for a database to be established, and it would be advantageous to set about this while the field is relatively young. This paper outlines a framework for the construction of a neuromorphic hardware database, for use in the biological exploration of structure–function relationships.
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Tymoshchuk, Pavlo, and s. Shatny. "Hardware Implementation of Parallelized Fuzzy Adaptive Resonance Theory Neural Network." Computer Design Systems. Theory and Practice, no. 1 (2020): 1–11. http://dx.doi.org/10.23939/cds2019.01.001.
Повний текст джерелаАнотація:
A hardware implementation design of parallelized fuzzy Adaptive Resonance Theory neural network is described and simulated. Parallel category choice and resonance are implemented in the network. Continuous-time and discrete-time winner-take-all neural circuits identifying the largest of M inputs are used as the winner-take-all units. The continuous-time circuit is described by a state equation with a discontinuous right-hand side. The discrete-time counterpart is governed by a difference equation. Corresponding functional block-diagrams of the circuits include M feed-forward hard- limiting neurons and one feedback neuron, which is used to compute the dynamic shift of inputs. The circuits combine arbitrary finite resolution of inputs, high convergence speed to the winner-take-all operation, low computational and hardware implementation complexity, and independence of initial conditions. The circuits are also used for finding elements of input vector with minimal/maximal values to normalize them in the range [0,1].
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Khan, Wilayat, Basim Azam, Noman Shahid, Abdul Moeed Khan, and Ahtisham Shaheen. "Formal Verification of Digital Circuits Using Simulator with Mathematical Foundation." Applied Mechanics and Materials 892 (June 2019): 134–42. http://dx.doi.org/10.4028/www.scientific.net/amm.892.134.
Повний текст джерелаАнотація:
To ease hardware design process, circuits are normally designed in description languages such as Verilog and VHDL. The correctness of circuits is normally checked by exhaustive simulation in simulators such as Icarus and VCS. Both the description languages Verilog/VHDL and simulators Icarus/VCS do not have mathematical foundations and hence are not reliable and cannot be used to mathematically prove correctness of circuit designs. Hardware description languages with mathematical (formal) foundation such as VeriFormal, on the other hand, are more reliable, trustworthy and can be used for robust design. In this paper, we report our results of formal verifications of two simple hardware circuits designed in the formal description language VeriFormal. Using the VeriFormal simulator and the accompanied type checker tools, we prove reliability properties type safety, functional correctness and functional equivalence of the digital circuits.
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Funcke, Lena, Tobias Hartung, Karl Jansen, Stefan Kühn, and Paolo Stornati. "Dimensional Expressivity Analysis of Parametric Quantum Circuits." Quantum 5 (March 29, 2021): 422. http://dx.doi.org/10.22331/q-2021-03-29-422.
Повний текст джерелаАнотація:
Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.
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Dhar, Tapobrata, Surajit Kumar Roy, and Chandan Giri. "Hardware Trojan Horse Detection through Improved Switching of Dormant Nets." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–22. http://dx.doi.org/10.1145/3439951.
Повний текст джерелаАнотація:
Covert Hardware Trojan Horses (HTH) introduced by malicious attackers during the fabless manufacturing process of integrated circuits (IC) have the potential to cause malignant functions within the circuit. This article employs a Design-for-Security technique to detect any HTHs present in the circuit by inserting tri-state buffers (TSB) in the ICs that inject the internal nets with weighted logic values during the test phase. This increases the transitions in the logic values of the nets within the IC, thereby stimulating any inserted HTH circuits. The TSBs are efficiently inserted in the IC considering various circuit parameters and testability measures to bolster the transitions in logic values of the nets throughout the IC while minimising the area overhead. Simulation results show a significant increase in transitions in logic values within HTH triggers using this method, thus aiding in their detection through side-channel analysis or direct activation of the payload.
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Mao, Jiajie, Xiaowen Jiang, Dehong Liu, Jianjun Chen, and Kai Huang. "A Hardware Trojan-Detection Technique Based on Suspicious Circuit Block Partition." Electronics 11, no. 24 (December 12, 2022): 4138. http://dx.doi.org/10.3390/electronics11244138.
Повний текст джерелаАнотація:
To ensure that a hardware Trojan remains hidden in a circuit, it is usually necessary to ensure that the trigger signal has a low testability, which has been widely recognized and proven. The most advanced testability-based detection methods are rather slow for large circuits, and the false-positive rate is not as low as that for small circuits. In this paper, a hardware Trojan, through the low testability of the trigger signal and its position characteristics in the circuit, was detected, which greatly improves the detection speed while maintaining a lower false positive rate when being applied to large circuits. First, the Sandia Controllability/Observability Analysis Program (SCOAP) was applied to obtain the 0–1 controllability of the signals in the netlist. Secondly, the controllability value was calculated by the differential amplification model, in order to facilitate K-means clustering to get better results. Then, we calculate the shortest path between each suspicious signal to get the connection between each suspicious signal. Finally, we divide the suspicious signals into several suspicious circuit blocks to screen the real trigger signal. As a result, the false-negative rate of 0% and the highest false-positive rate of 5.02% were obtained on the Trust-Hub benchmarks.
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Al-Khaleel, Osama, Zakaria Al-Qudah, Mohammad Al-Khaleel, Raed Bani-Hani, Christos Papachristou, and Francis Wolff. "Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1550019. http://dx.doi.org/10.1142/s021812661550019x.
Повний текст джерелаАнотація:
This paper proposes two high performance binary-to-binary coded decimal (BCD) conversion algorithms for use in BCD multiplication. These algorithms are based on splitting the 7-bit binary partial product of two BCD digits into two groups, computing the contribution of each group to the equivalent BCD partial product, and adding these contributions to compute the final BCD partial product. Designs for the proposed architectures and their implementations targeting both ASIC and FPGA are compared with others. Implementations of BCD array multipliers using both our conversion circuits and existing conversion circuits have been performed. The synthesis results for both ASIC and FPGA show that the proposed designs are faster and occupying less area than the state-of-the-art conversion circuits. Furthermore, the results obtained from comparing BCD multipliers of various sizes show that the enhancement in the area of the conversion circuit grows into a sizable area improvement in the multiplier circuit.
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Mirmohammadi, Zahra, and Shahram Etemadi Borujeni. "A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic Locking." Electronics 12, no. 5 (February 23, 2023): 1107. http://dx.doi.org/10.3390/electronics12051107.
Повний текст джерелаАнотація:
Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated. In recent years, various obfuscation methods have been proposed. One is logic locking, the most prominent hardware protection technique since it can protect against untrusted items. Logic locking induces functional and structural changes to a design even before the layout generation. We secured the circuit against hardware Trojan insertion with a secure logic locking method based on the insertion of key gates in interference mode. We call our proposed method Secure Interference Logic Locking, SILL. SILL is based on minimum controllability in paths with maximum fan-out. In this method, we have reduced the number of key gates required for circuit obfuscation and created the maximum Hamming distance between normal and obscure outputs. In addition, the key gates are added to the circuit’s complete interference, and the AES algorithm is used to generate the key. Our proposed method, SILL, was simulated in the Vivado simulation environment; the algorithms used in this method were prepared in VHDL language and designed to allow parallel execution, then applied on the original Netlist of the ISCAS85 benchmark circuits. By analyzing and comparing the results of this simulation to recent works, the amount of hardware consumption has decreased (about 5% space consumption and about a 0.15-nanosecond time delay). Then, the SAT attack algorithm was tested on ISCAS85 benchmark circuits that were obfuscated with SILL. The execution time of the attack in the second attempt was 0.24 nanoseconds longer compared to similar recent works, and it timed out in the fourth attempt. The resistance of our proposed method, having less hardware overhead and higher speed is more effective against SAT attacks than the existing conventional methods.
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Gao, Hua Qiang, Yu Jing Wang, Shou Qiang Kang, Zhang Le, Jian Qing Wang, and Jing Jing Wei. "Realization of Digital Chaotic Signal Generation Circuits." Applied Mechanics and Materials 716-717 (December 2014): 1352–55. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1352.
Повний текст джерелаАнотація:
To overcome the shortcomings of realizing chaotic system by analog circuits, digital chaotic signal generation circuits based on DSP are designed. Computer simulation of chaotic system is performed firstly, and the discrete equations are obtained using discretization algorithm. On this basis, the design of hardware circuits based on DSP is made, and the corresponding C programs are constructed. Through the debugging of software and hardware, digital design of chaotic system based on DSP is achieved, and chaotic attractor is observed through an oscilloscope by digital-to-analog conversion circuit. The experimental results coincide with the simulation, proving the correctness of the design. The chaotic signal generation circuits can provide rich digital chaotic signals sources for the application of chaotic systems in engineering.
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Zolotorevich, L. A., and V. A. Ilyinkov. "Monitoring the reliability of integrated circuits protection against Trojans: encoding and decoding of combinational structures." Informatics 18, no. 3 (September 30, 2021): 7–17. http://dx.doi.org/10.37661/1816-0301-2021-18-3-7-17.
Повний текст джерелаАнотація:
Integrated circuits, systems on a chip are the key links in various industrial systems and state defense systems. The emergence of counterfeit integrated circuits, problems of piracy, overproduction, unauthorized interference in the design of microcircuit, hardware Trojans require the development of methods and means of their timely detection. Trojans can be introduced into the integrated circuits structure both on the development stage and during the production process, including the stages of specification, design, verification and manufacturing. The inclusion of additional elements in the integrated circuits structure jeopardizes the functional suitability and reliability of the system as a whole. For the purpose of hardware protection of projects, the methods of hardware coding are currently used.The paper discusses the features and reliability of logical coding of combinational circuits. An algorithm for cracking the code of combinational circuits is proposed, based on the description of encoded structure by the resolution function and reducing the problem to SAT CNF. The initial data for decoding the structure of a digital device is the structural implementation of encoded circuit, obtained, for example, by reverse engineering (prototype design), as well as an activated physical sample of an integrated circuit, when into protected from unauthorized access memory the correct key value is loaded. This sample can be used as a black box model. The main idea of breaking a key is to solve a problem without research on a large interval of values of input and output variables.
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Amelian, Atieh, and Shahram Etemadi Borujeni. "A Side-Channel Analysis for Hardware Trojan Detection Based on Path Delay Measurement." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850138. http://dx.doi.org/10.1142/s0218126618501384.
Повний текст джерелаАнотація:
Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be detected by conventional testing methods. Due to dangerous effects of them, Hardware Trojan Detection has become a major concern in hardware security. In this paper, a new HTH detection method is presented based on side-channel analysis that uses path delay measurement. In this method, we find and observe the paths that Trojans have most effect on them. Most of the previous works add some structures to the circuit and need a large overhead cost. But, in our method, there is no modification in the circuit and we can use it for testing the circuits received after fabrication. The proposed method is evaluated with Xilinx FPGA over a number of test circuits. The results show that measuring the delays on 20 paths with an accuracy of 0.01[Formula: see text]ns can detect more than 80% of Trojans.
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G S, Nisarga, Dr Punith Kumar M B, Dr Mahesh, and M. Subramanyam. "Comparative Research of Neuron Circuits." International Journal for Research in Applied Science and Engineering Technology 10, no. 7 (July 31, 2022): 4121–26. http://dx.doi.org/10.22214/ijraset.2022.45944.
Повний текст джерелаАнотація:
Abstract: Spiking neurons can be implemented in hardware, for example, to model large neural systems, simulate real-time behaviour, and interface bi-directionally between brains and machines. Circuit solutions used to implement silicon neuron circuits depend on the application requirements. Various neuron circuits are presented in this thesis, including spike-event generators (Axon Hillock neuron circuits), above-threshold neuron circuits (Quadratic Integrate and Fire neuron circuits), and differential pair integrator circuits. Cadence's tool simulates these circuits using 180nm technology. Comparing these circuits is based on their working properties and simulation results, and their features are demonstrated with experiments.
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Chaithra P., Divyashree S., K. Rithesh, Sahana, H.V. Manjunath, Adithya T.G., Pavithra G., Sindhu Sree M., and T.C.Manjunath. "Hardware design & development of a fire alarm circuit in crowded places." international journal of engineering technology and management sciences 6, no. 6 (November 28, 2022): 262–65. http://dx.doi.org/10.46647/ijetms.2022.v06i06.042.
Повний текст джерелаАнотація:
This paper gives the brief design of the hardware model & its development of a fire alarm circuit in crowded places is presented in brief. Fire Alarm Circuit is a simple circuit that detects the fire and activates the Siren Sound or Buzzer. Fire Alarm Circuits are very important devices to detect fire in the right time and prevent any damage to people or property. Fire Alarm Circuits and Smoke Sensors are a part of the security systems which help in detecting or preventing damage. Installing Fire Alarm Systems and Smoke Sensors in commercial buildings like offices, movie theatres, shopping malls and other public places is compulsory. There are many expensive and sophisticated Fire Alarm Circuit in the form of stand-alone devices, but we have designed five very simple Fire Alarm Circuits using common components like Thermistor, LM358, Germanium Diode, LM341 and NE555.This is a very simple alarm circuit using Thermistor, LM358 Operational Amplifier and a Buzzer. The primary purpose of fire alarm system is to provide an early warning of fire so that people can be. evacuated & immediate action can be taken to stop or eliminate of the fire effect as soon as possible Alarm can be triggered by using detectors or by manual call point (Remotely). The work presented here is the mini-project work of the second sem students of Electronics & Communication Engineering Department of Dayananda Sagar College of Engg., Bangalore.
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Materzok, Marek. "Generating circuits with generators." Proceedings of the ACM on Programming Languages 6, ICFP (August 29, 2022): 52–79. http://dx.doi.org/10.1145/3549821.
Повний текст джерелаАнотація:
The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away. We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.
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Lu, S. L. "Design of hardware efficient selftimed circuits." Electronics Letters 29, no. 1 (January 7, 1993): 6–7. http://dx.doi.org/10.1049/el:19930004.
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Wirth, N. "Hardware compilation: translating programs into circuits." Computer 31, no. 6 (June 1998): 25–31. http://dx.doi.org/10.1109/2.683004.
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Tezak, Nikolas, Armand Niederberger, Dmitri S. Pavlichin, Gopal Sarma, and Hideo Mabuchi. "Specification of photonic circuits using quantum hardware description language." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 370, no. 1979 (November 28, 2012): 5270–90. http://dx.doi.org/10.1098/rsta.2011.0526.
Повний текст джерелаАнотація:
Following the simple observation that the interconnection of a set of quantum optical input–output devices can be specified using structural mode VHSIC hardware description language, we demonstrate a computer-aided schematic capture workflow for modelling and simulating multi-component photonic circuits. We describe an algorithm for parsing circuit descriptions to derive quantum equations of motion, illustrate our approach using simple examples based on linear and cavity-nonlinear optical components, and demonstrate a computational approach to hierarchical model reduction.
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张, 福兴. "Design of Hardware Circuits for Vacuum Circuit Breaker Online Monitoring Systems." Journal of Sensor Technology and Application 11, no. 01 (2023): 28–41. http://dx.doi.org/10.12677/jsta.2023.111004.
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Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (June 1, 2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.
Повний текст джерелаАнотація:
Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.
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Song, Shihao, Jui Hanamshet, Adarsha Balaji, Anup Das, Jeffrey L. Krichmar, Nikil D. Dutt, Nagarajan Kandasamy, and Francky Catthoor. "Dynamic Reliability Management in Neuromorphic Computing." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (July 19, 2021): 1–27. http://dx.doi.org/10.1145/3462330.
Повний текст джерелаАнотація:
Neuromorphic computing systems execute machine learning tasks designed with spiking neural networks. These systems are embracing non-volatile memory to implement high-density and low-energy synaptic storage. Elevated voltages and currents needed to operate non-volatile memories cause aging of CMOS-based transistors in each neuron and synapse circuit in the hardware, drifting the transistor’s parameters from their nominal values. If these circuits are used continuously for too long, the parameter drifts cannot be reversed, resulting in permanent degradation of circuit performance over time, eventually leading to hardware faults. Aggressive device scaling increases power density and temperature, which further accelerates the aging, challenging the reliable operation of neuromorphic systems. Existing reliability-oriented techniques periodically de-stress all neuron and synapse circuits in the hardware at fixed intervals, assuming worst-case operating conditions, without actually tracking their aging at run-time. To de-stress these circuits, normal operation must be interrupted, which introduces latency in spike generation and propagation, impacting the inter-spike interval and hence, performance (e.g., accuracy). We observe that in contrast to long-term aging, which permanently damages the hardware, short-term aging in scaled CMOS transistors is mostly due to bias temperature instability. The latter is heavily workload-dependent and, more importantly, partially reversible. We propose a new architectural technique to mitigate the aging-related reliability problems in neuromorphic systems by designing an intelligent run-time manager (NCRTM), which dynamically de-stresses neuron and synapse circuits in response to the short-term aging in their CMOS transistors during the execution of machine learning workloads, with the objective of meeting a reliability target. NCRTM de-stresses these circuits only when it is absolutely necessary to do so, otherwise reducing the performance impact by scheduling de-stress operations off the critical path. We evaluate NCRTM with state-of-the-art machine learning workloads on a neuromorphic hardware. Our results demonstrate that NCRTM significantly improves the reliability of neuromorphic hardware, with marginal impact on performance.
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Sun, Yuan Jing, Meng Xiao, Na Na Li, and Cui Ying Yang. "The Design of Intelligent Charger for Electric Car." Advanced Materials Research 619 (December 2012): 78–80. http://dx.doi.org/10.4028/www.scientific.net/amr.619.78.
Повний текст джерелаАнотація:
This thesis designed a high degree of intelligence charger to solve the Lead-acid batteries’ problems. The design of charger including two parts, hardware design and software design. PIC16F877 is the core control component in hardware part, on this basis, design the corresponding peripheral circuits .And the designing of hardware circuit and driver software of the whole system is explained in detail.
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Cui, Li Gong, Guo Xin Li, and Hong Qiang Guo. "Design and Realization of Driving Circuit for 5-Inch Nixie Tube Based on CH452." Advanced Materials Research 926-930 (May 2014): 1277–80. http://dx.doi.org/10.4028/www.scientific.net/amr.926-930.1277.
Повний текст джерелаАнотація:
Nixie tubes are widely used in industry, but the design of the driving circuits is one of the biggest challenges. Aiming at the characteristics of the large-size nixie tube, this paper designs the hardware circuits for 5-inch nixie tube at first, including the driving power, the bit drive circuit and the segment drive circuit. Then, the design programs to drive CH452 chip were given. During the realization process of the circuits, the perennial problems and the corresponding solving methods were given at last. This paper provides guidance for the design of driving circuit for nixie tube.
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Žemva, Andrej, Andrej Trost, and Baldomir Zajc. "Educational Programmable System for Prototyping Digital Circuits." International Journal of Electrical Engineering & Education 35, no. 3 (July 1998): 236–44. http://dx.doi.org/10.1177/002072099803500306.
Повний текст джерелаАнотація:
In this paper, we present an educational programmable system for prototyping digital circuits. The system is composed of the PC and the prototyping board composed of 3 FPGAs. PC is used for designing a digital circuit, programming the FPGAs, automatic generation of the interface logic and hardware verification of the designed circuit.
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Zhu, Jun, Wan Kui Li, Hai Xing Wang, and Li Li Han. "The Hardware System Design of PMSM Controller Based on DSP2812." Applied Mechanics and Materials 273 (January 2013): 454–59. http://dx.doi.org/10.4028/www.scientific.net/amm.273.454.
Повний текст джерелаАнотація:
For the efficiency of PMSM, in the paper the matched controller was developed to improve the servo performance of permanent magnet synchronous servo system. According to the basic principle of vector control for PMSM, the hardware system of PMSM controller was constituted based on TMS320F2812, it contains power drive circuit, control circuit, feedback circuit and other auxiliary circuits. It can provide reference scheme for the design of PMSM controller, and laid the foundation for the industrial production of the PMSM controller.
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WAH WU, CHAI, GUO-QUN ZHONG, and LEON O. CHUA. "SYNCHRONIZING NONAUTONOMOUS CHAOTIC SYSTEMS WITHOUT PHASE-LOCKING." Journal of Circuits, Systems and Computers 06, no. 03 (June 1996): 227–41. http://dx.doi.org/10.1142/s0218126696000182.
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Pecora and Carroll1 have shown how two nonautonomous chaotic circuits driven by periodic forcing can be synchronized using the master-slave driving principle. However, in their scheme, the periodic forcing in both circuits needs to be phase-locked through some additional circuitry for the system to synchronize. In this paper, we show two ways in which this can be avoided. In the first scheme, the two circuits are connected in a master-slave driving configuration and the periodic forcing is included in the driving signal such that it eliminates the need for the slave circuit to have an external periodic forcing signal. In addition, we can recover the periodic forcing signal at the slave circuit. In the second scheme, the two circuits are connected in a mutual coupling configuration. The two circuits will synchronize regardless of what the periodic forcing signals of the two circuits are. In particular, the two periodic forcing signals could have different phases, different frequencies, or different shapes. We discuss two interpretations of these synchronization schemes. First, we consider them as communication systems when the periodic forcing signal is replaced by a properly encoded information signal. We illustrate this in a physical circuit implementation. Second, we consider them as synchronization schemes for nonidentical systems by considering the external forcing signal as an error signal due to the difference between the two systems.
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Gao, Quan Qin, Hai Yang Sun, and Jia Dang Li. "Applied Technology in Multi-Frequency Eddy Detection Signal Processing Using Kalman Filter." Applied Mechanics and Materials 508 (January 2014): 183–87. http://dx.doi.org/10.4028/www.scientific.net/amm.508.183.
Повний текст джерелаАнотація:
Based on the Kalman filter, A multi-frequency eddy current signal demodulation method is proposed. By directly sampling the analog signal of multi-frequency eddy system, the multi-frequency phase and amplitude information of eddy current will be obtained by the proposed method immediately and synchronously. Contrasting the traditional method, the proposed method does not need hardware demodulation circuits and the circuit structures are also simple. Moreover, the proposed method is more flexible, which may be configured to any frequencies parameters by software way and no longer dependent on specific hardware circuits.
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Yoshikawa, Masaya, Yusuke Mori, and Takeshi Kumaki. "Implementation Aware Hardware Trojan Trigger." Advanced Materials Research 933 (May 2014): 482–86. http://dx.doi.org/10.4028/www.scientific.net/amr.933.482.
Повний текст джерелаАнотація:
Recently, the threat of hardware Trojans has garnered attention. Hardware Trojans are malicious circuits that are incorporated into large-scale integrations (LSIs) during the manufacturing process. When predetermined conditions specified by an attacker are satisfied, the hardware Trojan is triggered and performs subversive activities without the LSI users even being aware of these activities. In previous studies, a hardware Trojan was incorporated into a cryptographic circuit to estimate confidential information. However, Trojan triggers have seldom been studied. The present study develops several new Trojan triggers and each of them is embedded in a field-programmable gate array (FPGA). Subsequently, the ease of detection of each trigger is verified from the standpoint of area.
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Chattopadhyay, Saranyu, Pranesh Santikellur, Rajat Subhra Chakraborty, Jimson Mathew, and Marco Ottavi. "A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (November 30, 2021): 1–24. http://dx.doi.org/10.1145/3460004.
Повний текст джерелаАнотація:
Physically Unclonable Function (PUF) circuits are promising low-overhead hardware security primitives, but are often gravely susceptible to machine learning–based modeling attacks. Recently, chaotic PUF circuits have been proposed that show greater robustness to modeling attacks. However, they often suffer from unacceptable overhead, and their analog components are susceptible to low reliability. In this article, we propose the concept of a conditionally chaotic PUF that enhances the reliability of the analog components of a chaotic PUF circuit to a level at par with their digital counterparts. A conditionally chaotic PUF has two modes of operation: bistable and chaotic , and switching between these two modes is conveniently achieved by setting a mode-control bit (at a secret position) in an applied input challenge. We exemplify our PUF design framework for two different PUF variants—the CMOS Arbiter PUF and a previously proposed hybrid CMOS-memristor PUF, combined with a hardware realization of the Lorenz system as the chaotic component. Through detailed circuit simulation and modeling attack experiments, we demonstrate that the proposed PUF circuits are highly robust to modeling and cryptanalytic attacks, without degrading the reliability of the original PUF that was combined with the chaotic circuit, and incurs acceptable hardware footprint.
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KILIÇ, RECAI, MUSTAFA ALÇI, and ENIS GÜNAY. "TWO IMPULSIVE SYNCHRONIZATION STUDIES USING SC-CNN-BASED CIRCUIT AND CHUA'S CIRCUIT." International Journal of Bifurcation and Chaos 14, no. 09 (September 2004): 3277–93. http://dx.doi.org/10.1142/s0218127404011193.
Повний текст джерелаАнотація:
The impulsive synchronization method has been applied to several well-known chaotic circuits and systems such as Chua's circuit, Lorenz system and hyperchaotic circuit in the literature. In this paper, we also present two impulsive synchronization studies using SC-CNN-based circuit and Chua's circuit. In the first study, we have investigated the impulsive synchronization between two SC-CNN-based circuits. Pspice simulation results show that two SC-CNN-based circuits can be synchronized impulsively via x1 and x2 cell dynamics for different impulse width and impulse period values. And in the second study, we have investigated the impulsive synchronization between SC-CNN-based circuit and Chua's circuit. Pspice simulation results verify that two chaotic circuits, which have identical dynamical systems via appropriate parameter transformations but having quite different hardware implementations, can be synchronized impulsively for different impulse width and impulse period values.
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Hu, Wei, Armaiti Ardeshiricham, and Ryan Kastner. "Hardware Information Flow Tracking." ACM Computing Surveys 54, no. 4 (May 2021): 1–39. http://dx.doi.org/10.1145/3447867.
Повний текст джерелаАнотація:
Information flow tracking (IFT) is a fundamental computer security technique used to understand how information moves through a computing system. Hardware IFT techniques specifically target security vulnerabilities related to the design, verification, testing, manufacturing, and deployment of hardware circuits. Hardware IFT can detect unintentional design flaws, malicious circuit modifications, timing side channels, access control violations, and other insecure hardware behaviors. This article surveys the area of hardware IFT. We start with a discussion on the basics of IFT, whose foundations were introduced by Denning in the 1970s. Building upon this, we develop a taxonomy for hardware IFT. We use this to classify and differentiate hardware IFT tools and techniques. Finally, we discuss the challenges yet to be resolved. The survey shows that hardware IFT provides a powerful technique for identifying hardware security vulnerabilities, as well as verifying and enforcing hardware security properties.
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Shindo, Tomokazu, Hiroshi Yokoi, and Yukinori Kakazu. "Adaptive Logic Circuits Based on Net-list Evolution." Journal of Robotics and Mechatronics 12, no. 2 (April 20, 2000): 144–49. http://dx.doi.org/10.20965/jrm.2000.p0144.
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We discuss adaptive hardware evolution, evolvable hardware, describing system functions as logic circuits rather than programs. Evolution occurs in circuit formation and then functions are generated from the formation. In general approaches, possibility of formation is restricted by device structure, so we propose net-list evolution and apply it a wall following problem with a Khepera robot, confirming solution of the interface problem between the robot and environment using the proposed method.