Статті в журналах з теми "Hardware/algorithm co-design"
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Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (October 18, 2018): 122. http://dx.doi.org/10.3390/jimaging4100122.
Повний текст джерелаKrawczyk, Kamil, Paweł Tomaszewicz, and Mariusz Rawski. "Whirlpool SoPC Implementation - Hardware/Software Co-Design Example." International Journal of Electronics and Telecommunications 58, no. 1 (March 1, 2012): 21–26. http://dx.doi.org/10.2478/v10177-012-0003-9.
Повний текст джерелаLópez, M., J. Daugman, and E. Cantó. "Hardware–software co-design of an iris recognition algorithm." IET Information Security 5, no. 1 (2011): 60. http://dx.doi.org/10.1049/iet-ifs.2009.0267.
Повний текст джерелаLi, Shih-An, Chen-Chien Hsu, Ching-Chang Wong, and Chia-Jun Yu. "Hardware/software co-design for particle swarm optimization algorithm." Information Sciences 181, no. 20 (October 2011): 4582–96. http://dx.doi.org/10.1016/j.ins.2010.07.017.
Повний текст джерелаAlecsa, Bogdan, and Alexandru Onea. "Hardware-Software Co-Design for BLDC Motor Speed Controller Design." Advanced Materials Research 463-464 (February 2012): 1256–59. http://dx.doi.org/10.4028/www.scientific.net/amr.463-464.1256.
Повний текст джерелаZhang, Xinyi, Yawen Wu, Peipei Zhou, Xulong Tang, and Jingtong Hu. "Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–24. http://dx.doi.org/10.1145/3477002.
Повний текст джерелаIsmael, Sarmad, Omar Tareq, and Yahya Taher Qassim. "Hardware/software co-design for a parallel three-dimensional bresenham’s algorithm." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 148. http://dx.doi.org/10.11591/ijece.v9i1.pp148-156.
Повний текст джерелаGrout, Ian Andrew, and Lenore Mullin. "Realizing Mathematics of Arrays Operations as Custom Architecture Hardware-Software Co-Design Solutions." Information 13, no. 11 (November 4, 2022): 528. http://dx.doi.org/10.3390/info13110528.
Повний текст джерелаRaghunathan, Shriram, Sumeet K. Gupta, Himanshu S. Markandeya, Kaushik Roy, and Pedro P. Irazoqui. "A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications." Journal of Neuroscience Methods 193, no. 1 (October 2010): 106–17. http://dx.doi.org/10.1016/j.jneumeth.2010.08.008.
Повний текст джерелаDrumond, Mario, Alexandros Daglis, Nooshin Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi, Boris Grot, and Dionisios Pnevmatikatos. "Algorithm/Architecture Co-Design for Near-Memory Processing." ACM SIGOPS Operating Systems Review 52, no. 1 (August 28, 2018): 109–22. http://dx.doi.org/10.1145/3273982.3273992.
Повний текст джерелаANDO, Kota, Kodai UEYOSHI, Yuka OBA, Kazutoshi HIROSE, Ryota UEMATSU, Takumi KUDO, Masayuki IKEBE, Tetsuya ASAI, Shinya TAKAMAEDA-YAMAZAKI, and Masato MOTOMURA. "Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks." IEICE Transactions on Information and Systems E102.D, no. 12 (December 1, 2019): 2341–53. http://dx.doi.org/10.1587/transinf.2019pap0009.
Повний текст джерелаGhaffari, Sina, Parastoo Soleimani, Kin Fun Li, and David W. Capson. "A Novel Hardware–Software Co-Design and Implementation of the HOG Algorithm." Sensors 20, no. 19 (October 2, 2020): 5655. http://dx.doi.org/10.3390/s20195655.
Повний текст джерелаSchumann, Thomas, Herbert Krauß, Yeong Kang Lai, and Yu Fan Lai. "Hardware/Software Co-Design of 2D-to-3D Video Conversion on FPGA." Applied Mechanics and Materials 284-287 (January 2013): 3230–34. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.3230.
Повний текст джерелаHou, Neng, Xiaohu Yan, and Fazhi He. "A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design." Design Automation for Embedded Systems 23, no. 1-2 (April 30, 2019): 57–77. http://dx.doi.org/10.1007/s10617-019-09220-7.
Повний текст джерелаZhou, Wenqian. "Fast Implementation of Genetic Algorithm Based on Software/Hardware Co-design Method." Journal of Physics: Conference Series 1952, no. 3 (June 1, 2021): 032044. http://dx.doi.org/10.1088/1742-6596/1952/3/032044.
Повний текст джерелаYang, Fu, Liu Xin, and Pei Yuan Guo. "A Multi-Objective Optimization Genetic Algorithm for SOPC Hardware-Software Partitioning." Advanced Materials Research 457-458 (January 2012): 1142–48. http://dx.doi.org/10.4028/www.scientific.net/amr.457-458.1142.
Повний текст джерелаJOHNSTON, S. P., G. PRASAD, L. MAGUIRE, and T. M. MCGINNITY. "AN FPGA HARDWARE/SOFTWARE CO-DESIGN TOWARDS EVOLVABLE SPIKING NEURAL NETWORKS FOR ROBOTICS APPLICATION." International Journal of Neural Systems 20, no. 06 (December 2010): 447–61. http://dx.doi.org/10.1142/s0129065710002541.
Повний текст джерелаDessai, Sanket, and Sandeep G. "Embedded Hardware Circuit and Software Development of USB based Hardware Accelerator." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (May 30, 2018): 21. http://dx.doi.org/10.11591/ijres.v7.i1.pp21-33.
Повний текст джерелаFarouk, Yasmeen, and Sherine Rady. "Optimizing MRI Registration using Software/Hardware Co-Design Model on FPGA." International Journal of Innovative Technology and Exploring Engineering 10, no. 2 (December 10, 2020): 128–37. http://dx.doi.org/10.35940/ijitee.b8300.1210220.
Повний текст джерелаFeng, Xiao Jing, Xi Li, Wang Chao, Xue Hai Zhou, and Jun Neng Zhang. "A Hardware/Software Co-Design Flow for Dynamic Partial Reconfiguration." Advanced Materials Research 433-440 (January 2012): 5172–77. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5172.
Повний текст джерелаXiao, Hao, Yuxuan Liu, Zhenmin Li, and Guangzhu Liu. "Algorithm-hardware co-design of ultra-high radix based high throughput modular multiplier." IEICE Electronics Express 18, no. 10 (May 25, 2021): 20210135. http://dx.doi.org/10.1587/elex.18.20210135.
Повний текст джерелаYan, Xiaohu, Fazhi He, Neng Hou, and Haojun Ai. "An Efficient Particle Swarm Optimization for Large-Scale Hardware/Software Co-Design System." International Journal of Cooperative Information Systems 27, no. 01 (March 2018): 1741001. http://dx.doi.org/10.1142/s0218843017410015.
Повний текст джерелаAn, Jianjing, Dezheng Zhang, Ke Xu, and Dong Wang. "An OpenCL-Based FPGA Accelerator for Faster R-CNN." Entropy 24, no. 10 (September 23, 2022): 1346. http://dx.doi.org/10.3390/e24101346.
Повний текст джерелаSabir, Brahim, Yassine Khazri, Mohamed Moussetad, and Bouzekri Touri. "Hardware and Software Co-Design of Arabic Alphabets Recognition Platform for Blind and Visually Impaired Persons." Open Electrical & Electronic Engineering Journal 11, no. 1 (November 16, 2017): 193–200. http://dx.doi.org/10.2174/1874129001711010193.
Повний текст джерелаZheng, Xin, Xianghong Hu, Jinglong Zhang, Jian Yang, Shuting Cai, and Xiaoming Xiong. "An Efficient and Low-Power Design of the SM3 Hash Algorithm for IoT." Electronics 8, no. 9 (September 14, 2019): 1033. http://dx.doi.org/10.3390/electronics8091033.
Повний текст джерелаHoward, Neil J., Andrew M. Tyrrell, and Nigel M. Allinson. "The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks." VLSI Design 4, no. 2 (January 1, 1996): 135–39. http://dx.doi.org/10.1155/1996/17505.
Повний текст джерелаZhou, Zhen, Debiao He, Zhe Liu, Min Luo, and Kim-Kwang Raymond Choo. "A Software/Hardware Co-Design of Crystals-Dilithium Signature Scheme." ACM Transactions on Reconfigurable Technology and Systems 14, no. 2 (June 5, 2021): 1–21. http://dx.doi.org/10.1145/3447812.
Повний текст джерелаYusuf, Yusmardiah, Darmawaty Mohd Ali, and Norsuzila Ya’acob. "Hardware simulation for exponential blind equal throughput algorithm using system generator." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 1 (February 1, 2019): 170. http://dx.doi.org/10.11591/ijece.v9i1.pp170-180.
Повний текст джерелаDang, Tuan Linh, and Yukinobu Hoshino. "Hardware/Software Co-design for a Neural Network Trained by Particle Swarm Optimization Algorithm." Neural Processing Letters 49, no. 2 (March 30, 2018): 481–505. http://dx.doi.org/10.1007/s11063-018-9826-4.
Повний текст джерелаRanjith, C., and S. P. Joy Vasantha Rani. "A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design." Journal of Circuits, Systems and Computers 29, no. 01 (April 4, 2019): 2050014. http://dx.doi.org/10.1142/s0218126620500140.
Повний текст джерелаGan, Jiayan, Ang Hu, Ziyi Kang, Zhipeng Qu, Zhanxiang Yang, Rui Yang, Yibing Wang, Huaizong Shao, and Jun Zhou. "SAS-SEINet: A SNR-Aware Adaptive Scalable SEI Neural Network Accelerator Using Algorithm–Hardware Co-Design for High-Accuracy and Power-Efficient UAV Surveillance." Sensors 22, no. 17 (August 30, 2022): 6532. http://dx.doi.org/10.3390/s22176532.
Повний текст джерелаWEI, WENLONG, BIN LI, YI ZOU, WENCONG ZHANG, and ZHENQUAN ZHUANG. "A MULTI-OBJECTIVE HW–SW CO-SYNTHESIS ALGORITHM BASED ON QUANTUM-INSPIRED EVOLUTIONARY ALGORITHM." International Journal of Computational Intelligence and Applications 07, no. 02 (June 2008): 129–48. http://dx.doi.org/10.1142/s146902680800220x.
Повний текст джерелаKhoud, Khaled Ben, Soufiene Bouallègue, and Mounir Ayadi. "Design and co-simulation of a fuzzy gain-scheduled PID controller based on particle swarm optimization algorithms for a quad tilt wing unmanned aerial vehicle." Transactions of the Institute of Measurement and Control 40, no. 14 (January 8, 2018): 3933–52. http://dx.doi.org/10.1177/0142331217740947.
Повний текст джерелаISSAD, M., B. BOUDRAA, M. ANANE, and N. ANANE. "SOFTWARE/HARDWARE CO-DESIGN OF MODULAR EXPONENTIATION FOR EFFICIENT RSA CRYPTOSYSTEM." Journal of Circuits, Systems and Computers 23, no. 03 (March 2014): 1450032. http://dx.doi.org/10.1142/s0218126614500327.
Повний текст джерелаEl-MALAKI, M. H., M. WATHEQ El-KHARASHI, S. HAMMAD, A. SALEM, and A. WAHDAN. "A PLATFORM APPROACH FOR HARDWARE/SOFTWARE CO-DESIGN WITH SUPPORT FOR RTOS-BASED SYSTEMS." Journal of Circuits, Systems and Computers 16, no. 06 (December 2007): 961–79. http://dx.doi.org/10.1142/s0218126607004015.
Повний текст джерелаMekala, Priyanka, Jeffrey Fan, Wen-Cheng Lai, and Ching-Wen Hsue. "Gesture Recognition Using Neural Networks Based on HW/SW Cosimulation Platform." Advances in Software Engineering 2013 (February 24, 2013): 1–13. http://dx.doi.org/10.1155/2013/707248.
Повний текст джерелаChen, Yi-Jung, Chia-Lin Yang, and Yen-Sheng Chang. "An architectural co-synthesis algorithm for energy-aware Network-on-Chip design." Journal of Systems Architecture 55, no. 5-6 (May 2009): 299–309. http://dx.doi.org/10.1016/j.sysarc.2009.02.002.
Повний текст джерелаXIAO, Hao, Yanming FAN, Fen GE, Zhang ZHANG, and Xin CHENG. "Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation." IEICE Transactions on Information and Systems E103.D, no. 10 (October 1, 2020): 2047–58. http://dx.doi.org/10.1587/transinf.2020pcp0002.
Повний текст джерелаLee, Jinsu, Sanghoon Kang, Jinmook Lee, Dongjoo Shin, Donghyeon Han, and Hoi-Jun Yoo. "The Hardware and Algorithm Co-Design for Energy-Efficient DNN Processor on Edge/Mobile Devices." IEEE Transactions on Circuits and Systems I: Regular Papers 67, no. 10 (October 2020): 3458–70. http://dx.doi.org/10.1109/tcsi.2020.3021397.
Повний текст джерелаMigliore, Vincent, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, and Guy Gogniat. "Hardware/Software Co-Design of an Accelerator for FV Homomorphic Encryption Scheme Using Karatsuba Algorithm." IEEE Transactions on Computers 67, no. 3 (March 1, 2018): 335–47. http://dx.doi.org/10.1109/tc.2016.2645204.
Повний текст джерелаNiu, Wen Liang, Wen Zheng Li, and Kai Shuang Yin. "Application of DFG Model on SOPC Technology." Applied Mechanics and Materials 198-199 (September 2012): 696–700. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.696.
Повний текст джерелаJaved, Hassan, Muhammad Bilal, and Shahid Masud. "A Hardware–Software Co-Design Framework for Real-Time Video Stabilization." Journal of Circuits, Systems and Computers 29, no. 02 (May 3, 2019): 2050027. http://dx.doi.org/10.1142/s0218126620500279.
Повний текст джерелаFasfous, Nael, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Nguyen Anh Vu Doan, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, and Walter Stechele. "HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–25. http://dx.doi.org/10.1145/3476997.
Повний текст джерелаRavi, Aadithya, Easwara E. A. Moorthy, D. Vidya, and G. Mahesh Kumar. "Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing." Applied Mechanics and Materials 110-116 (October 2011): 5057–62. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5057.
Повний текст джерелаZhang, Jun An, Ya Hong Guo, and Guo Min Mo. "A Software Hardware Co-Design Approach for FPGAs on Nios II Soft-Core Processors." Applied Mechanics and Materials 373-375 (August 2013): 1591–94. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.1591.
Повний текст джерелаMemon, Farida, Aamir Hussain Memon, Shahnawaz Talpur, Fayaz Ahmed Memon, and Rafia Naz Memon. "Design and Co-Simulation of Depth Estimation Using Simulink HDL Coder and Modelsim." July 2016 35, no. 3 (July 1, 2016): 473–82. http://dx.doi.org/10.22581/muet1982.1603.17.
Повний текст джерелаLi, Guihong, Sumit K. Mandal, Umit Y. Ogras, and Radu Marculescu. "FLASH: F ast Neura l A rchitecture S earch with H ardware Optimization." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–26. http://dx.doi.org/10.1145/3476994.
Повний текст джерелаRojas-Muñoz, Luis Felipe, Horacio Rostro-González, Carlos Hugo García-Capulín, and Santiago Sánchez-Solano. "Hardware/Software Co-Design of a Circle Detection System Based on Evolutionary Computing." Electronics 11, no. 17 (August 27, 2022): 2686. http://dx.doi.org/10.3390/electronics11172686.
Повний текст джерелаAl-Musawi, Wisal Adnan, Wasan A. Wali, and Mohammed Abd Ali Al-Ibadi. "New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 2 (April 1, 2022): 1955. http://dx.doi.org/10.11591/ijece.v12i2.pp1955-1964.
Повний текст джерелаAdiono, Trio, Aditya F. Ardyanto, Nur Ahmadi, Idham Hafizh, and Septian G. P. Putra. "An SoC Architecture for Real-Time Noise Cancellation System Using Variable Speech PDF Method." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 6 (December 1, 2015): 1336. http://dx.doi.org/10.11591/ijece.v5i6.pp1336-1346.
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