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Статті в журналах з теми "GHz low-power receivers"
Malika Begum, N., and W. Yasmeen. "A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers." International Journal of Engineering & Technology 7, no. 3.6 (July 4, 2018): 84. http://dx.doi.org/10.14419/ijet.v7i3.6.14944.
Повний текст джерелаCeolin, Giovana, and Lucas Compassi Severo. "0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers." Journal of Integrated Circuits and Systems 17, no. 2 (September 17, 2022): 1–8. http://dx.doi.org/10.29292/jics.v17i2.559.
Повний текст джерелаFRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, MICHAEL J. DEGERSTROM, MICHAEL J. LORSUNG, JASON F. PRAIRIE, ERIC L. H. AMUNDSEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.
Повний текст джерелаAbbasi, Arash, and Frederic Nabki. "A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications." Electronics 11, no. 9 (May 6, 2022): 1493. http://dx.doi.org/10.3390/electronics11091493.
Повний текст джерелаZhang, Xin, Chunhua Wang, Yichuang Sun, and Haijun Peng. "A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1850047. http://dx.doi.org/10.1142/s0218126618500470.
Повний текст джерелаTouati, F., and M. Loulou. "High-Performance BiCMOS Transimpedance Amplifiers for Fiber-Optic Receivers." Journal of Engineering Research [TJER] 4, no. 1 (December 1, 2007): 69. http://dx.doi.org/10.24200/tjer.vol4iss1pp69-74.
Повний текст джерелаKumar Vishnoi, Manoj, and Satya Sai Srikant. "Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 160. http://dx.doi.org/10.11591/ijres.v7.i3.pp160-166.
Повний текст джерелаKumar Vishnoi, Manoj, and Satya Sai Srikant. "Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 166. http://dx.doi.org/10.11591/ijres.v7.i3.pp166-172.
Повний текст джерелаDeyun Cai, Yang Shang, Hao Yu, and Junyan Ren. "Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS." IEEE Transactions on Microwave Theory and Techniques 61, no. 9 (September 2013): 3360–72. http://dx.doi.org/10.1109/tmtt.2013.2268738.
Повний текст джерелаD'Amico, Stefano, Annachiara Spagnolo, Andrea Donno, Vincenzo Chironi, Piet Wambacq, and Andrea Baschirotto. "A Low-Power Analog Baseband Section for 60-GHz Receivers in 90-nm CMOS." IEEE Transactions on Microwave Theory and Techniques 62, no. 8 (August 2014): 1724–35. http://dx.doi.org/10.1109/tmtt.2014.2332877.
Повний текст джерелаДисертації з теми "GHz low-power receivers"
張智凱. "2.4/5.8-GHz Low-Power Low-Noise CMOS Direct Conversion Receivers." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/66804380155634515813.
Повний текст джерела國立交通大學
電信工程研究所
98
In this thesis, the radios which are suitable for Wireless Personal Area Network (WPAN) applications are designed and implemented. The thesis consists of two parts. The first part focuses on the most important part in front-end circuits - Low Noise Amplifier, and implements in low & high frequency. The second part implements receivers which are suitable for ISM band applications. First, we study low noise amplifier schematics and its different low-power techniques. And then, we discuss for cascode low noise amplifier and implement 2.4-GHz & 5.8-GHz power-constrained single-band amplifier in TSMC 0.18-?慆 CMOS technology. Otherwise, we use trifilar-type component implementing dual-band amplifier in TSMC 0.13-?慆 CMOS technology. Finally, 60-GHz dual-gate LNA is implemented in TSMC 90-nm CMOS technology. Because power-constrained amplifier implemented in former chapter, we can use it to extending to the low power receivers. First , we consider various performance in active mixer and VGA. Composed with various LO generator individually , we implement low power low noise receivers on the power restriction in TSMC 0.18-?慆 CMOS technology.
Lu, Hsi-Liang, and 陸熙良. "2.4-GHz Low-Power Receiver and 60-GHz Transmitter CMOS Circuits." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/04940497941411884265.
Повний текст джерела國立交通大學
電信工程系所
97
In this thesis, the radios which are suitable for Wireless Personal Area Network (WPAN) applications are designed and implemented. The thesis consists of two parts. The first part focuses on studying various low-power techniques and realizes two different 2.4-GHz low-power receivers. The second part implements high quality component circuits which are suitable for 60-GHz band applications. First, we study different low-power techniques. Because the passive mixer is a common component of a direct-conversion receiver, we also investigate the flicker noise of passive mixers. Then, we implement a 2.4-GHz low-power receiver with passive mixers, and a 2.4-GHz low-power receiver with subthreshold biasing technique. Both chips are implemented in TSMC 0.18-um CMOS technology. Second, we implement different types of 60-GHz sub-harmonic upconverters in TSMC 0.13-um CMOS technology, and propose transformer-type balun to combine RF signal. In order to provide good LO source, we design a QVCO using three-line coupler. This QVCO operates at 0.6V, and consumes 7.6mW. And the FoM is -203.6dBc/Hz.
Lu, Yi-Yu, and 盧宜佑. "Design of a 2.4-GHz Low-Power Receiver RFIC." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/50737759321008101369.
Повний текст джерела國立中正大學
電機工程研究所
92
Two low-IF receiver RFICs and two T/R switches for 2.4 GHz wireless personal network applications have been designed in this thesis work. The first receiver front-end CMOS RFIC includes a low-noise amplifier and a down-mixer. The measured results showed power gain of 11.2 dB, input P1dB of —19.5 dBm, input IP3 of —15 dBm, noise figure of 8.2 dB, and LO-RF isolation greater than 47 dB, where the total DC power consumption is below 9.1 mW. The second single-chip receiver IC includes a low-noise amplifier, a down-mixer, an IF variable gain amplifier, a high-order low-pass filter and a buffer amplifier, which was implemented with TSMC 0.18um CMOS technology. The peak-voltage of baseband input I/Q signals was greater than 600 mV, which was sufficient to drive the following A/D converter. The simulated 66 dB gain tuning range was, adequate to cover the dynamic range of WPAN received RF signal. The entire chip consumed less than 12.7 mW DC power. For the T/R switches, SPDT and DPDT switches were designed with feedback inductions such that the measured isolation was larger than 31.5 dB and insertion loss was less than 1.4 dB.
Chung, Kuo-Sheng, and 鍾國聖. "Design and Implementation of5-GHz CMOS Ultra-Low-Power Receiver Frontends." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65345929631918244426.
Повний текст джерела國立臺灣大學
電子工程學研究所
93
With recent advances in the high-frequency characteristics, CMOS has become very attractive process for the implementation of low-cost wireless communication systems. In addition to conventional RF systems, low-power and low-voltage applications, such as RFID and wireless sensor networks, have motivated the development of fully integrated transceivers using CMOS process. However, the inherently low transconductance and the required threshold voltage for CMOS process make it extremely difficult to operate reduced supply voltage and power dissipation. In this thesis, a down-conversion mixer, a voltage-controlled oscillator (VCO) and a receiver frontend fabricated in 0.18-μm CMOS are presented to demonstrate the potential of CMOS frontend circuits for low-power and low-voltage operation. A novel mixer with stacked complementary transistors and a current bleeding resistor is proposed for low-voltage application while maintaining reasonable conversion gain. The 5.2-GHz mixer exhibits a conversion gain of 3dB and an IIP3 of -8dBm with a power dissipation of 792 μW from a 0.6-V supply voltage. As for the proposed VCO topology, the tail current source of a LC-tank VCO has been eliminated to support ultra-low voltage operation. 5.8-GHz VCO achieves a tuning range of 8.9% and phase noise of -97dBc/Hz @ 1MHz. The VCO core consumes 696-μW dc power from a 0.6-V supply voltage. Finally, by combining the fabricated mixer, VCO with a single stage LNA, the receiver frontend is designed for the 5-GHz frequency band. Based on the simulation results, the receiver frontend demonstrates a conversion gain of 15dB and IIP3 of -19dBm. The complete receiver is operated at a reduced supply voltage of 0.6 V with a power dissipation of 2.3mW.
Kuo-Sheng, Chung. "Design and Implementation of 5-GHz CMOS Ultra-Low-Power Receiver Frontends." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2207200517094300.
Повний текст джерелаLiu, Yen-Lin, and 劉燕霖. "Low-Voltage Low-Power 5-GHz Receiver Front-End Circuit Design for Wireless Sensor Networks." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/13482087189832994108.
Повний текст джерела國立交通大學
電子工程系所
95
This thesis aims at design of a low-voltage low-power receiver front-end circuit applicable to wireless sensor networks. Two chips are realized. In the first chip, a low-power double-balanced mixer is designed in a folded topology. A transconductance stage with phase splitting function which is composed of a common-gate and common-source transistors is adopted for low power consideration. Output balanced condition, input matching, and noise of the transconductance stage are analyzed. Realized in 0.18-um CMOS technology, the measured input return loss and voltage conversion gain are 11dB and 10.4dB, respectively. The input third-order intercept point (IIP3) is 3.8dBm while consuming 2mW from a 1V supply. In the second chip, a receiver front-end circuit is designed for low supply voltage as low as 0.6V. The circuit consists of a low noise amplifier, switching stage, and on-chip transformer which provides AC coupling between stages connected to it in a folded structure. The transformer is designed not only to convert single-ended signal into differential form without excess power consumption, but also to operate in resonant mode to have current transfer gain. The power consumption of the circuit is effectively cut down. Also, a figure of merit for bias consideration and stabilization design for LNA is analyzed for the optimum design condition under low supply voltage case. The measured input return loss and voltage conversion gain are 16.9dB and 12dB, respectively. The input third-order intercept point (IIP3) is -2.8dBm while consuming only 0.29mW from a 0.6V supply.
Chen, Wen-Sheng, and 陳文生. "Design and Analysis of 3.1-10.6 GHz UWB LNA and 24-GHz Low-Power High-Gain Receiver Front-End Circuit." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/76027471132284029500.
Повний текст джерела國立交通大學
電信工程研究所
103
This thesis consists of two parts. All the proposed circuits were implemented in TSMC 0.18μm mixed-signal/RF CMOS 1P6M technology. Part I presents an ultra-wide band low-noise amplifier applied to WPAN (Wireless Personal Area Network.), and a common gate architecture and noise-cancelling technique are employed in this amplifier. Using these techniques can not only suppress the total noise contribution in the output but increase the total gain with an excellent input wideband matching. According to the measured results, the LNA achieves the small signal gain of 9.7~11.6 dB, a noise figure of 4.54~4.85 dB, the input P1dB of -19 dBm, and the input IP3 of -9.5 dBm over the whole working range. The power consumption is about 16.9 mW at the supply voltage of 1.8V. Part II proposes a low-power high-gain receiver front-end applied to 24-GHz ISM band. The receiver front-end contains a low-noise amplifier, a transformer balun, a down-conversion mixer and an intermediate frequency amplifier. In LNA design, using two stage common source structure cascaded with common gate structure realizes performance of high gain and low-noise with the limited power dissipation; in down-conversion mixer design, making use of cross-coupling and current-bleeding techniques obtains high gain and low power consumption. Furthermore, an intermediate frequency amplifier is added after the down-conversion mixer so the whole conversion gain increases once more. Therefore, the proposed receiver front-end has advantage of low power and high gain compared to other researches. This circuit achieves a conversion gain of 37.1 dB and a double-side band noise figure of 5.65 dB with the input P1dB of -33.5 dBm, output P1dB of 2.1 dBm, and input IP3 of -23 dBm consuming 37.1 mW.
Ou, Meng-Yueh, and 歐孟岳. "A Low-Voltage and Low-Power 2.4 GHz CMOS Direct-Conversion Receiver for Bio-Acquisition in Wireless Sensor Network." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/71452723754265650575.
Повний текст джерела國立成功大學
電機工程學系碩博士班
96
This work describes the design of a wireless receiver front-end circuit for Bio-Acquisition in Wireless Sensor Network (WSN). The front-end circuit includes a cascode low noise amplifier (LNA), an active balun and a folded-cascode even-harmonic mixer. The balun employs differential amplifier architecture utilizing the concept of RC feedback to transform single-ended signal into differential form. The frequency-doubling circuit in the LO stage is employed to double the LO frequency, thus the self-mixing resulted from LO leakage could be avoided. The even-harmonic (EH) mixer with folded technique and complementary frequency-doubling circuits is adopted for low voltage topology to achieve large stable LO turning range. This work possesses conversion gain of 8.5 dB, 1-dB compression point (IP1dB) of -36 dBm, power consumption of 5.0 mW at 1V supply voltage.
Частини книг з теми "GHz low-power receivers"
Yu, Hang, Yan Li, Wongchen Wei, Lai Jiang, Shengyue Lin, and Zhen Ji. "A Low Power Limiting Amplifier Designed for the RSSI of a 5.8 GHz ETC Receiver." In Lecture Notes in Electrical Engineering, 95–102. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1839-5_11.
Повний текст джерелаKhatun, Sabira, Rashid A. Saeed, Nor Kamariah Nordin, and Borhanuddin Mohd Ali. "Ultra-Wideband Solutions for Last Mile Access Network." In Encyclopedia of Multimedia Technology and Networking, Second Edition, 1443–52. IGI Global, 2009. http://dx.doi.org/10.4018/978-1-60566-014-1.ch195.
Повний текст джерелаYellampalli, Siva Sankar, and Rashmi S. B. "Review on 60GHz Low Noise Amplifier for Low Power and Linearity." In Advances in Wireless Technologies and Telecommunication, 283–315. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-0773-4.ch009.
Повний текст джерелаNg, Wan Yeen, and Xhiang Rhung Ng. "The Design and Modeling of 30 GHz Microwave Front-End." In Advances in Monolithic Microwave Integrated Circuits for Wireless Systems, 205–38. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch009.
Повний текст джерелаMarzuki, Arjuna. "Inventions of Monolithic Microwave Integrated Circuits." In Advances in Monolithic Microwave Integrated Circuits for Wireless Systems, 240–332. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch010.
Повний текст джерелаMaltsev, Alexander, Alexander Shikov, Andrey Pudeev, Seonwook Kim, and Suckchel Yang. "A Method for Power Amplifier Distortions Compensation at the RX Side for the 5G NR Communication Systems." In Frontiers in Artificial Intelligence and Applications. IOS Press, 2022. http://dx.doi.org/10.3233/faia220526.
Повний текст джерелаMabrouk, Mohamed. "RF and Microwave Test of MMICs from Qualification to Mass Production." In Advances in Monolithic Microwave Integrated Circuits for Wireless Systems, 333–45. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-60566-886-4.ch011.
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Повний текст джерелаТези доповідей конференцій з теми "GHz low-power receivers"
Moreno, L., D. Gomez, J. L. Gonzalez, D. Mateo, X. Aragones, R. Berenguer, and H. Solar. "A low-power RF front-end for 2.5 GHz receivers." In 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4541583.
Повний текст джерелаMahdavi, Amir, and Fatemeh Geran. "A low power UWB CMOS low noise amplifier for 3.1–10.6 GHz in receivers." In 2016 8th International Symposium on Telecommunications (IST). IEEE, 2016. http://dx.doi.org/10.1109/istel.2016.7881892.
Повний текст джерелаJingru Sun, Chunhua Wang, and Kui Fu. "An ultra low power low noise amplifier for 3.1∼10.6 GHz UWB receivers." In 2013 IEEE Global High Tech Congress on Electronics (GHTCE). IEEE, 2013. http://dx.doi.org/10.1109/ghtce.2013.6767256.
Повний текст джерелаHassan, Khursheed, Theodore S. Rappaport, and Jeffrey G. Andrews. "Analog Equalization for Low Power 60 GHz Receivers in Realistic Multipath Channels." In GLOBECOM 2010 - 2010 IEEE Global Communications Conference. IEEE, 2010. http://dx.doi.org/10.1109/glocom.2010.5683699.
Повний текст джерелаKuba, Matthias, Janina Ziller, Tobias Drager, Heinrich Milosiu, Alexander Jaschke, and Hans Adel. "Automatic 2.4 GHz communication standard recognition based on ultra-low power receivers." In 2017 14th IEEE Annual Consumer Communications & Networking Conference (CCNC). IEEE, 2017. http://dx.doi.org/10.1109/ccnc.2017.7983105.
Повний текст джерелаLin, Yao-chian, Wan-rone Liou, Jyh-jier Ho, and Mei-ling Yeh. "An Low Power Ultra-Wideband CMOS LNA for 3.1~8.2-GHz Wireless Receivers." In 2006 International Conference on Communications, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/icccas.2006.284880.
Повний текст джерелаAnsari, Kimia T., and Calvin Plett. "A low power ultra-wideband CMOS LNA for 3.1–10.6-GHz wireless receivers." In 2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010. IEEE, 2010. http://dx.doi.org/10.1109/iscas.2010.5537968.
Повний текст джерелаDjugova, Alena, Jelena Radic, and Mirjana Videnovic-Misic. "A 0.18μm CMOS low power LNA for 6–8.5 GHz UWB receivers." In 2011 International Semiconductor Conference (CAS 2011). IEEE, 2011. http://dx.doi.org/10.1109/smicnd.2011.6095762.
Повний текст джерелаPerumana, Bevin G., Jing-Hong C. Zhan, Stewart S. Taylor, and Joy Laskar. "A 12 mW, 7.5 GHz Bandwidth, Inductor-less CMOS LNA for Low-Power, Low-Cost, Multi-Standard Receivers." In 2007 IEEE Radio Frequency Integrated Circuits Symposium. IEEE, 2007. http://dx.doi.org/10.1109/rfic.2007.380832.
Повний текст джерелаKao, H. L., Albert Chin, K. C. Chang, and S. P. McAlister. "A Low-Power Current-Reuse LNA for Ultra-Wideband Wireless Receivers from 3.1 to 10.6 GHz." In 2007 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. IEEE, 2007. http://dx.doi.org/10.1109/smic.2007.322807.
Повний текст джерела