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Автор: Grafiati

Опубліковано: 11 вересня 2023

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1

Saxena, Rimjhim, and Kiran Sharma. "Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique." SMART MOVES JOURNAL IJOSCIENCE 6, no. 2 (February 1, 2020): 1–12. http://dx.doi.org/10.24113/ijoscience.v6i2.264.

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Анотація:

In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.

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2

A.S., Prabhu, Naveena B, Parimaladevi K, Samundeswari M, and Thilagavathy P. "Serial Divider Using Modified GDI Technique." IJIREEICE 3, no. 10 (October 15, 2015): 73–76. http://dx.doi.org/10.17148/ijireeice.2015.31017.

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3

Solomon, Merrin Mary, Neeraj Gupta, and Rashmi Gupta. "HIGH SPEED ADDER USING GDI TECHNIQUE." International Journal of Engineering Technologies and Management Research 5, no. 2 (April 30, 2020): 130–36. http://dx.doi.org/10.29121/ijetmr.v5.i2.2018.634.

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Анотація:

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

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4

Anitha, M., J. Princy Joice, and Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select Adder Using Modified GDI Technique." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 173. http://dx.doi.org/10.11591/ijres.v4.i3.pp173-177.

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Анотація:

Adders are of fundamental importance in a wide variety of digital systems. This paper presents a novel bit block structure which computes propagate signals as carry strength. Power consumption is one of the most significant parameters of carry select adder.The proposed method aims on GDI(Gate Diffusion Input) Technique. Modified GDI is a novel technique for low power digital circuits design further to reduce the swing degradation problem. This techniques allows reduction in power consumption, carry propagation delay and transistor count of the carry select adder.This technique can be used to reduce the number of transistors compared to conventional CSLA and made comparison with known conventional adders which gives that the usage of carry-strength signals allows high-speed adders to be realised at lower cost as well as consuming lower power than previous designs. Hence, this paper we are concentrating on the area level &we are reducing the power using modified GDI logic.

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5

B Sangeeth Kumar,, Pyasa Dileep and A. Satyanarayana. "Design of Low Power & Area Efficient of 8-Bit Comparator using GDI Technique." International Journal for Modern Trends in Science and Technology, no. 8 (August 7, 2020): 62–65. http://dx.doi.org/10.46501/ijmtst060812.

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Анотація:

In this paper we are design a circuit based on data selector and distributor networks in which we will not realize the circuit based upon the expressions but off course the circuit which have designed will have internally some expression. In the recent trends the need for low power and less on-chip area is on high note for the portable devices. In this project we want to focus on the design constraints of VLSI. Innovative design of 8-Bit GDI based Comparator will be proposed and implemented. Optimization depends on selection of GDI Cell as well as selection of primary inputs to the terminals of GDI cell. 8-Bit GDI based Comparator will be designed and simulated using Tanner EDATool. Comparator has three main outputs where it can compare the weight of two words and generates three functions. GDI has the advantage of low power consumption because the total number of logic devices needed willbe less and it can also operate with high speed due to affective realization of logic using minimal hardware. Comparator circuits is designed using tanner tools and also observe the simulation results in H-SPICE attaining low power and less delay.

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6

Sehrawat, Arjun, Vandana Khanna, and Kushal Jindal. "Comparative Study of CMOS Logic and Modified GDI Technique for Basic Logic Gates and Code Convertor." International Journal of Advance Research and Innovation 9, no. 3 (2021): 70–85. http://dx.doi.org/10.51976/ijari.932111.

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Анотація:

For designing low power digital circuits with better reliability and performance along with less propagation delay, Gate Diffusion Input (GDI) is one such technique. It also significantly reduces the area and delay of a circuit. It is a low power technique which requires a smaller number of transistors to achieve desired outputs with lower design complexity as compared to CMOS logic or Pass Transistor Logic. In a basic GDI cell, 3 terminals namely Gate, Source and Drain are treated as inputs. In this work, circuits like logic gates, and Binary to Gray code convertor have been designed using CMOS logic and a Modified GDI technique. Also, the power dissipation of all these circuits have been calculated and compared for CMOS and Modified GDI. The designing and simulations have been done on Cadence Virtuoso tool in 90 nm technology and power supply voltage has been taken as 1 V.

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7

Tyagi, Priyanka, Sanjay Kumar Singh, and Piyush Dua. "Gate Diffusion Input Based 10-T CNTFET Power Efficient Full Adder." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 14, no. 4 (June 17, 2021): 415–27. http://dx.doi.org/10.2174/2352096514666210106094136.

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Анотація:

Background: Full adder is the key element of digital electronics. The CNTFET is the most promising device in modern electronics. To enhance the performance of the full adder, CNTFET is used in place of the CMOS. Objective: To implement the high speed full adder circuit for advance applications of the digital world. Methods: Full adder circuit with a new Gate diffusion technique has been implemented in this work. This is a comparative study of the 10-T CNTFET full adder with GDI technique and the 10-T Finfet based full adder using GDI technique. Ultra-low-power feature is the additional advantage of the GDI technique. This technology provides the full swing voltage to the circuit. Moreover, it also reduces the number of transistors required. This technique has been used with CNTFET to upgrade the full adder in terms of the dissipated power and product of power consumed and delay introduced in the circuit. Results: The proposed design shows that the low power dissipation comes out to be approximately 4.3nW at 0.5volts. The power delay product is 4.7x10-20 J at the same voltage level. The FinFET design also shows the better performance with GDI. But GDI enhances CNTFET based design power consumption by about 32% from the FinFET. Conclusions: CNTFET showed a better response due to good current conductivity as compared to the FinFET. This work has been implemented and simulated on the 32nm node technology.

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8

R., Manjunath. "LOW POWER OPTIMIZATION OF FULL ADDER CIRCUIT BASED ON GDI LOGIC FOR BIOMEDICAL APPLICATIONS." International Journal of Advanced Research 10, no. 10 (October 31, 2022): 457–67. http://dx.doi.org/10.21474/ijar01/15511.

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Advanced Electronic Devices have recently become more prevalent, designers have opted for low power, quick speed, and compact designs and processes. Even though there are numerous design methodologies currently in use for VLSI system design optimization, very few design techniques produce solutions that are optimally optimal. GDI-based circuits are becoming increasingly important since they use less space, power, and energy. The GDI technique ensures minimal propagation delay, power, and area in low-power design strategies. For 45nm technology, the Cadence Virtuoso EDA tool is utilised to determine delay and power. The proposed designs examination of delay and power performance at 1.0V voltage produced positive findings. The Gate Diffusion Input concept serves as the foundation for the proposed design in this work. In order to achieve a full voltage swing of the output, a 1-bit full adder circuit design using GDI is demonstrated in this work. The GDI with the Full Swing Technique is presented in this work. Applying the suggested way to a 45nm complete adder from 14 Transistors. It is evident from the obtained simulation results that the suggested design uses the least power and the least amount of delay when compared to other full adder circuits that are already in use. Consequently, compared to previous full adder GDI circuit designs, the output voltage swing is in full and the overall power-delay product is improved by 60 percent.

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9

Gupta, Shashank, and Subodh Wairya. "Hybrid Code Converters using Modified GDI Technique." International Journal of Computer Applications 143, no. 7 (June 17, 2016): 12–19. http://dx.doi.org/10.5120/ijca2016910248.

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10

Hari Kishore, K., K. DurgaKoteswara Rao, G. Manvith, K. Biswanth, and P. Alekhya. "Area, power and delay efficient 2-bit magnitude comparator using modified gdi technique in tanner 180nm technology." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 222. http://dx.doi.org/10.14419/ijet.v7i2.8.10413.

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Анотація:

Of late, low power configuration took shape into the mostimportant concentrations in designing the latest VLSI circuits. By considering the same at the maximum priority, another outline of two-bit GDI based Magnitude or Digital Comparator are recommended and actualized with the assistance of Modified GDI transistors. Comparators are building blocks in advanced VLSI configuration circuits. In the current patterns the necessity for occupying less area in chip and low power compact devices. In this paper we introduced another Magnitude Comparator which willutilize low power, and gives a quick results and occupying less chip area in Modified GDI technology. The modified GDI procedure dependent extent comparator has favorable position of less control utilization as for different outline parameters; few on-chip zones secured as small number of transistors are utilized in circuit configuration when related with traditional CMOS size comparator. Either of the circuits is outlined and executed utilizing Tanner EDA Tool version 16.0 at 180nm processing technologies.

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11

Ponnian, Jebashini, Senthil Pari, Uma Ramadass, and Chee Pun Ooi. "A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm." Emerging Science Journal 7, no. 4 (July 12, 2023): 1364–94. http://dx.doi.org/10.28991/esj-2023-07-04-022.

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Анотація:

The challenges of innovative IC technology typically come with various new design constraints in terms of circuit implementation, behaviour, scaling, and an accurate power-delay model to evaluate the circuit's performance. The circuit realization technique using GDI is gaining popularity because of its power and transistor utilization factors. Considering the core advantage of the GDI technique, this research presents the creation of new GDI library cells implemented using the MUX-based algorithm and its delay-power model. This research defines two goals; the former goal depicts the proposal of GDI library cells with full swing using a MUX-based signal connectivity model, and the later presents the mathematical delay-power model for the proposed GDI library cells. The number of attributes defined in the delay and power model incorporates minimum variables without sacrificing precision. It calculates the delay for simple RC networks and combinational circuits with multiple paths. The power model is given using the node activity factor and the power factor related to the internal node capacitances, wiring, and gate capacitances of the driving and receiving GDI nodes. The experimental results of this study, which conform to the specifications of the sub-micron library supported for the SilTerra 130 nm 6-metal layer fabricated for the CMOS n-well process, demonstrate that the proposed GDI library is indeed superior in terms of delay-transistor and power utilisation to PTL and CMOS technology. The simulation results reveal that there is 55 to 65 % improvement in terms of power and delay factor with the existing CMOS and PTL logic. The proposed delay model demonstrates that GDI cells require less logical effort than CMOS technology. The proposed power model shows that the node activity factor of the proposed GDI cells lies between 0.1 and 0.2, while in CMOS, it is between 0.1 and 0.3. Doi: 10.28991/ESJ-2023-07-04-022 Full Text: PDF

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12

N., Alivelu Manga. "Design of High-Speed Low Power Computational Blocks for DSP Processors." Revista Gestão Inovação e Tecnologias 11, no. 2 (June 5, 2021): 1419–29. http://dx.doi.org/10.47059/revistageintec.v11i2.1768.

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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

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13

Kumre, Laxmi, Ajay Somkuwar, and Ganga Agnihotri. "Analysis of GDI Technique for Digital Circuit Design." International Journal of Computer Applications 76, no. 16 (August 23, 2013): 41–48. http://dx.doi.org/10.5120/13335-0934.

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14

Durga, Gaddam Naga, and D. V. A. N. Ravi Kumar. "Gdi Technique Based Carry Look Ahead Adder Design." IOSR Journal of VLSI and Signal Processing 4, no. 6 (2014): 01–09. http://dx.doi.org/10.9790/4200-04610109.

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15

Reissing, J., H. Peters, J. M. Kech, and U. Spicher. "Experimental and numerical analyses of the combustion process in a direct injection gasoline engine." International Journal of Engine Research 1, no. 2 (April 1, 2000): 147–61. http://dx.doi.org/10.1243/1468087001545100.

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Gasoline direct injection (GDI) spark ignition engine technology is advancing at a rapid rate. The development and optimization of GDI engines requires new experimental methods and numerical models to analyse the in-cylinder processes. Therefore the objective of this paper is to present numerical and experimental methods to analyse the combustion process in GDI engines. The numerical investigation of a four-stroke three-valve GDI engine was performed with the code KIVA-3V [1]. For the calculation of the turbulent combustion a model for partially premixed combustion, developed and implemented by Kech [4], was used. The results of the numerical investigation are compared to experimental results, obtained using an optical fibre technique in combination with spectroscopic temperature measurements under different engine conditions. This comparison shows good agreement in temporal progression of pressure. Both the numerical simulation and the experimental investigation predicted comparable combustion phenomena.

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16

Suresh, N., K. Subba Rao, and R. Vassoudevan. "Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques." Journal of Computational and Theoretical Nanoscience 17, no. 4 (April 1, 2020): 1595–99. http://dx.doi.org/10.1166/jctn.2020.8407.

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Анотація:

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

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17

Pokhriyal, Nidhi, and Neelam Rup Prakash. "Area Efficient Low Power Compressor Design Using GDI Technique." International Journal of Engineering Trends and Technology 12, no. 3 (June 25, 2014): 132–35. http://dx.doi.org/10.14445/22315381/ijett-v12p224.

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18

Kowsalya, P., M. Malathi, and Palaniappan Ramanathan. "Low Power Parallel Prefix Adder." Applied Mechanics and Materials 573 (June 2014): 194–200. http://dx.doi.org/10.4028/www.scientific.net/amm.573.194.

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Анотація:

Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

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19

Kuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan, and Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques." Journal of Signal Processing 8, no. 2 (June 22, 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.

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Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

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20

Panarelli, Joseph F., and Anna T. Do. "Bleb Management Following Trabeculectomy and Glaucoma Drainage Device Implantation." US Ophthalmic Review 16, no. 2 (2022): 76. http://dx.doi.org/10.17925/usor.2022.16.2.76.

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While treatment options available to patients with glaucoma are expanding, trabeculectomy and glaucoma drainage device implantation (GDI) remain a mainstay in glaucoma surgical care. This article reviews key aspects of bleb management following trabeculectomy and GDI surgery. Basics of postoperative management of trabeculectomy and GDIs are reviewed, as well as how to manage complications such as early and late bleb leaks, fibrosis, bleb dysesthesia and the hypertensive phase. In general, careful surgical technique, close postoperative monitoring and appropriate intervention can help patients achieve safe outcomes and long-term control of intraocular pressure.

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21

Pokhriyal, Nidhi, and Neelam Rup Prakash. "Area Efficient Low Power Vedic Multiplier Design Using GDI Technique." International Journal of Engineering Trends and Technology 15, no. 4 (September 25, 2014): 196–99. http://dx.doi.org/10.14445/22315381/ijett-v15p238.

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22

Kaur, Ranbirjeet, and Rajesh Mehra. "Power and Area Efficient CMOS Half Adder using GDI Technique." International Journal of Engineering Trends and Technology 36, no. 8 (June 25, 2016): 401–5. http://dx.doi.org/10.14445/22315381/ijett-v36p274.

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23

Dabhade, Priyanka, and Amol Boke. "Design and Analyse Low Power Wallace Multiplier Using GDI Technique." IOSR Journal of Electronics and Communication Engineering 12, no. 02 (April 2017): 49–54. http://dx.doi.org/10.9790/2834-1202034954.

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24

Nagarajan, Manikandan, Rajappa Muthaiah, Yuvaraja Teekaraman, Ramya Kuppusamy, and Arun Radhakrishnan. "Power and Area Efficient Cascaded Effectless GDI Approximate Adder for Accelerating Multimedia Applications Using Deep Learning Model." Computational Intelligence and Neuroscience 2022 (March 19, 2022): 1–15. http://dx.doi.org/10.1155/2022/3505439.

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Анотація:

Approximate computing is an upsurging technique to accelerate the process through less computational effort while keeping admissible accuracy of error-tolerant applications such as multimedia and deep learning. Inheritance properties of the deep learning process aid the designer to abridge the circuitry and also to increase the computation speed at the cost of the accuracy of results. High computational complexity and low-power requirement of portable devices in the dark silicon era sought suitable alternate for Complementary Metal Oxide Semiconductor (CMOS) technology. Gate Diffusion Input (GDI) logic is one of the prompting alternatives to CMOS logic to reduce transistors and low-power design. In this work, a novel energy and area efficient 1-bit GDI-based full swing Energy and Area efficient Full Adder (EAFA) with minimum error distance is proposed. The proposed architecture was constructed to mitigate the cascaded effect problem in GDI-based circuits. It is proved by extending the proposed 1-bit GDI-based adder for different 16-bit Energy and Area Efficient High-Speed Error-Tolerant Adders (EAHSETA) segmented as accurate and inaccurate adder circuits. The proposed adder’s design metrics in terms of delay, area, and power dissipation are verified through simulation using the Cadence tool. The proposed logic is deployed to accelerate the convolution process in the Low-Weight Digit Detector neural network for real-time handwritten digit classification application as a case study in the Intel Cyclone IV Field Programmable Gate Array (FPGA). The results confirm that our proposed EAHSETA occupies fewer logic elements and improves operation speed with the speed-up factor of 1.29 than other similar techniques while producing 95% of classification accuracy.

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25

Anitha, M., J. Princy joice, and Mrs Rexlin Sheeba.I. "A New-High Speed-Low Power-Carry Select adder Using Modified GDI Technique." International Journal of Engineering Research 4, no. 3 (March 1, 2015): 127–29. http://dx.doi.org/10.17950/ijer/v4s3/309.

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26

Et. al., J. Nageswara Reddy ,. "Power Efficient Two Transistor Exclusiveor Gate for Full Adder Usinggdi in 45NM." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 2 (April 11, 2021): 1342–47. http://dx.doi.org/10.17762/turcomat.v12i2.1230.

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Анотація:

The principle part of ALU (Arithmetic rationale unit) is the Full Adder. This paper tells the best way to perform quick arithmetic activities created utilizing GDI. The fundamental point of this paper is to plan the full adder of two semiconductor utilizing Gate diffusion input (GDI) strategy. The plan of full adder is appropriate for the two semiconductor EX-OR gate. The primary intension of novel technique is fully founded on Full adder plan of 2TEX OR gate which is utilized to decrease power and improve the speed with an advanced territory of number of semiconductor check which is less similar with CMOS innovation. The best strategy for GDI is to plan advanced rationale circuits and which will in general improve the conditions.GDI system is functional to Full adder plan. The Cadence apparatus is to figure power, postponement and region for two semiconductor EX-OR gate .The total work is done in 45 nm innovation. The investigation of the outcomes show that the planned strategy is superior to traditional CMOS innovation.

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27

Sharma, Priyanka. "High Performance Sense Amplifier based Flip Flop Design using GDI Technique." International Journal of Advanced engineering, Management and Science 3, no. 4 (2017): 350–54. http://dx.doi.org/10.24001/ijaems.3.4.11.

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28

Murthy, CRavindra. "Low Power Design Bi – Directional Shift Register By using GDI Technique." International Journal on Recent and Innovation Trends in Computing and Communication 3, no. 4 (2015): 2367–73. http://dx.doi.org/10.17762/ijritcc2321-8169.1504128.

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29

Sivathanu, Yudaya, Jongmook Lim, Ariel Muliadi, Oana Nitulescu, and Tom Shieh. "Estimating velocity in Gasoline Direct Injection sprays using statistical pattern imaging velocimetry." International Journal of Spray and Combustion Dynamics 11 (June 28, 2018): 175682771877828. http://dx.doi.org/10.1177/1756827718778289.

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Statistical pattern imaging velocimetry (SPIV) is a new technique for the estimation of the planar velocity field from the high-speed videos. SPIV utilizes an ensemble of either backlit or side lit videos to obtain full planar velocities in sprays and flames. Unlike conventional particle imaging velocimetry, statistical pattern imaging velocimetry does not require well-resolved images of particles within turbulent flows. Instead, the technique relies of patterns formed by coherent structures in the flow. Therefore, SPIV is well suited for the estimating planar velocities in sprays and turbulent flames, both of which have well-defined patterns embedded in the flow videos. The implementation of the SPIV technique is relatively quite straightforward since high-speed videos can be readily obtained either in a laboratory or production floor setting. The biggest challenge for the SPIV techniques is that the procedure is computationally expensive even with an ordinary mega-pixel camera. To improve the computation speed, a successive partitioning scheme was employed. In addition, to improve spatial resolution to subpixel dimensions, a weighted central averaging scheme was used. With these two enhancements, the SPIV method was used to obtain planar radial and axial velocities in a spray emanating from a GDI injector. Sprays from GDI injectors are very dense (with obscuration levels close to the injector being greater than 99%), and velocity measurements are difficult. However, further away from the nozzle, a Phase Doppler Anemometer can be used to obtain velocity measurements. The velocities obtained using these two methods showed reasonable agreement.

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30

Sharma, Satish, Shyam Babu Singh, and Shyam Akashe. "A Power Efficient GDI Technique for Reversible Logic Multiplexer of Emerging Nanotechnologies." International Journal of Computer Applications 73, no. 14 (July 26, 2013): 8–14. http://dx.doi.org/10.5120/12807-9900.

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31

Ramya . S, Sri Phani, and Nimmy Maria Jose. "A Low Power Binary to Excess-1 Code Converter Using GDI Technique." International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, no. 01 (January 20, 2015): 209–14. http://dx.doi.org/10.15662/ijareeie.2015.0401031.

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32

kaur, Simran, Balwinder Singh, and Jain D.K. "Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique." International Journal of VLSI Design & Communication Systems 6, no. 5 (October 30, 2015): 45–56. http://dx.doi.org/10.5121/vlsic.2015.6504.

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33

Naveenkumar, Majety. "Novel Design of Reversible MUX and DEMUX using GDI Techinque." International Journal of Advances in Applied Sciences 4, no. 3 (September 1, 2015): 103. http://dx.doi.org/10.11591/ijaas.v4.i3.pp103-108.

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Now a day’s Reversible logic is playing a crucial role in designing of digital circuits and it is used in reducing power consumption in digital design. By regaining the bit loss it reduces the power consumption in digital circuits. Gate diffusion input (GDI) is a technique of low-power digital circuit design. This technique reduces the power consumption, delay, and transistor count by maintaining the complexity very low of logic design. In these paper a novel MUX and DEMUX has been presented, which can be extended up to 1:2n and 2n:1 respectively and these are developed by using only one type of Reversible gate i.e. Fredkin Gate (FRG) and Not Gate. The simulations are done in H-Spice using 90nm technology.

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34

Di Ilio, Giovanni, Vesselin K. Krastev, and Giacomo Falcucci. "Evaluation of a Scale-Resolving Methodology for the Multidimensional Simulation of GDI Sprays." Energies 12, no. 14 (July 15, 2019): 2699. http://dx.doi.org/10.3390/en12142699.

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The introduction of new emissions tests in real driving conditions (Real Driving Emissions—RDE) as well as of improved harmonized laboratory tests (World Harmonised Light Vehicle Test Procedure—WLTP) is going to dramatically cut down NOx and particulate matter emissions for new car models that are intended to be fully Euro 6d compliant from 2020 onwards. Due to the technical challenges related to exhaust gases’ aftertreatment in small-size diesel engines, the current powertrain development trend for light passenger cars is shifted towards the application of different degrees of electrification to highly optimized gasoline direct injection (GDI) engines. As such, the importance of reliable multidimensional computational tools for GDI engine optimization is rapidly increasing. In the present paper, we assess a hybrid scale-resolving turbulence modeling technique for GDI fuel spray simulation, based on the Engine Combustion Network “Spray G” standard test case. Aspects such as the comparison with Reynolds-averaged methods and the sensitivity to the spray model parameters are discussed, and strengths and uncertainties of the analyzed hybrid approach are pointed out. The outcomes of this study serve as a basis for the evaluation of scale-resolving turbulence modeling options for the development of next-generation directly injected thermal engines.

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35

Gujjula, Ramana Reddy, Chitra Perumal, Prakash Kodali, and Bodapati Venkata Rajanna. "Datasets design of gate diffusion input based pipeline architecture for numerically controlled oscillator." Indonesian Journal of Electrical Engineering and Computer Science 26, no. 1 (April 1, 2022): 253. http://dx.doi.org/10.11591/ijeecs.v26.i1.pp253-260.

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<span lang="EN-US">Gate diffusion input (GDI) is a technique, which enables reducing power consumption, area and delay in the digital circuits significantly, at the same time maintains low complexity of the logical design. This paper focuses on the analysis and interpretation of the design and implementation of GDI-based pipeline architecture for numerically controlled oscillator (NCO) using look up table (LUT). Based on the input signal and the alternate signal, this phase separation will separate the phase difference signal. The NCO generates a frequency and phase harmonized output signal with an antecedence fixed frequency clock. The 32-bit counter then compares the current count to the value stored in the compare register. Here the Coherent control comes into picture. It controls the carrier synchronizer by employing data from the 32-bit counter and the obtained data will be saved. It is updated and advanced using the third peer group of frequency synthesis technology. The test outcomes are accompanied with the theoretical concept and reproduced the results. The main objective of GDI-based pipeline architecture for NCO using LUT is to reduce the usage of metal oxide semiconductor field effect transistors (MOSFET’s). NCO is an indispensable component in many digital communication systems linked to modems, software-defined radios, and digital radio, digital down/upconverters for cellular and personal communications service base stations.</span>

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36

Jeyasree, C., and R. Arul Raj. "Design Of Low Power And Area Efficient SRAM Architecture Based on GDI Technique." International Journal of MC Square Scientific Research 9, no. 1 (April 16, 2017): 18–25. http://dx.doi.org/10.20894/ijmsr.117.009.001.003.

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37

ce, Prin, and Rajesh Mehra. "Design of an Energy Efficient, Low Power Dissipation Half Subtractor using GDI Technique." International Journal of Engineering Trends and Technology 36, no. 2 (June 25, 2016): 53–59. http://dx.doi.org/10.14445/22315381/ijett-v36p211.

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38

Y, Syamala, Srilakshmi K, and Somasekhar Varma N. "Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI) Technique." International Journal of VLSI Design & Communication Systems 4, no. 5 (October 31, 2013): 89–95. http://dx.doi.org/10.5121/vlsic.2013.4507.

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39

Sharma, Sandesh, and Vangmayee Sharda. "Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 759. http://dx.doi.org/10.14419/ijet.v7i3.12.16496.

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Vedic mathematics is an old mathematics which is more effective than other mathematic procedures. Vedic maths is utilized as a part of numerous applications, for example, hypothesis of numbers, compound duplications, squaring, cubing, square root and solid shape root and so on. Absolutely there are 16 sutras and 14 sub-sutras in Vedic maths. Among those sutras, just 3 sutras and 2 sub-sutras are utilized for augmentation. Multiplier is a very important part of a microprocessor as multiplication is performed continuously in all calculative procedures. This paper is in importance of a 8-bit multiplier designed in 90 nm technology. Urdhva-Tiryakbyham is the sutra that is used for multiplication in Vedic mathematics. Actualizing the different scientific operations utilizing Vedic Mathematics causes us accomplish better speed, bring down unpredictability and higher execution.[2] The technique used is Gate Diffusion Input (GDI) which is a more refined way to design a circuit which less complex than circuits designed by other techniques.

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40

Saxena, Rimjhim, and Kiran Sharma. "A Comparative Review on ALU using CMOS and GDI techniques for Power Dissipation and Propagation Delay." IJOSTHE 7, no. 1 (February 19, 2020): 4. http://dx.doi.org/10.24113/ojssports.v7i1.119.

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Arithmetic and Logic Circuits are to be designed with less power, compact size, less propagation delay in this fast growing era of technology. Arithmetic operations are indispensable and the basic functions for any high speed low power applications like digital signal processing, microprocessors, image processing, etc. Consumption of power is the major issue in designing these circuits. Also the number of transistors required is also the one of the issues in designing the circuits. To minimize the transistors required in designing the circuits and to reduce the power consumption of the circuits, the authors have referred some techniques to overcome these problems in this paper. By reviewing all these techniques, the authors try to implement the GDI technique to reduce the power consumption and transistors count or the area required to design the circuits.

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41

Khokha, Simran, and Rahul Reddy K. "Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Technique." International Journal of VLSI Design & Communication Systems 7, no. 4 (August 30, 2016): 57–69. http://dx.doi.org/10.5121/vlsic.2016.7406.

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42

Jung, Seungmin. "A Study on the VLSI Implementation of Fingerprint Thinning Processors Using Hybrid GDI Technique." Journal of Computing Science and Engineering 17, no. 1 (March 31, 2023): 20–29. http://dx.doi.org/10.5626/jcse.2023.17.1.20.

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43

Parvathi, M., N. Vasantha, and K. Satya Prasad. "BIST Architecture using Area Efficient Low Current LFSR for Embedded Memory Testing Applications Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 1 (March 1, 2018): 1. http://dx.doi.org/10.11591/ijres.v7.i1.pp1-11.

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One of the important block of BIST controller is LFSR and the speed with which BIST operates depends on LFSR systems design. There are methods in implementing LFSR using field programmable gate arrays (FPGAs) or digital signal processors (DSPs). BIST controller system speed is then limited to FPGAs and DSPs, which may influence other parameters such as overall area, maximum current, limit and power dissipation. This paper proposes a technique to achieve an efficient BIST controller by redesigning LFSR using GDI based D flip-flops that resulted with low area and low current capabilities. This paper presents three different techniques for implementing flip-flops for an efficient LFSR so that the layout area will be minimized as well as the maximum current drawn will be lower.

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44

Lakshmaiah, Dayadi, Dr M. V. Subramanyam, and Dr K. Sathya Prasad. "A Novel Design of Low-Power 1-Bit CMOS Full-Adder Cell using XNOR and MUX." INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY 7, no. 3 (December 15, 2013): 1155–65. http://dx.doi.org/10.24297/ijmit.v7i3.702.

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This paper process a novel design for low power 1-bit CMOS full adder using XNOR and MUX, with reduced number of transistors using GDI cell. The circuits were simulated with supply voltage scaling from 1.2V to 0.6V &0.6V to 0.3V. To achieve the desired performance of power delay product, area, capacitance the transistors with low threshold voltage were used at critical paths and high threshold voltage at non critical paths. The results show the efficiency of the proposed technique in terms of power consumption, delay and area.

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45

Yadav, Neetika, and Preeti Kumari. "Design and Implementation of Power and Area Efficient 3-Bit Flash ADC using GDI Technique." International Journal of Computer Applications 182, no. 2 (July 16, 2018): 13–16. http://dx.doi.org/10.5120/ijca2018917452.

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46

Singh, Haramardeep, and Harmeet Kaur. "Design and Simulation of Novel 10-T Subtraction logic for ALU design using GDI Technique." International Journal of Hybrid Information Technology 8, no. 10 (October 31, 2015): 405–16. http://dx.doi.org/10.14257/ijhit.2015.8.10.37.

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47

Singh, Haramardeep, and Harmeet Kaur. "Design and Simulation of Novel 10-T Subtraction Logic for ALU Design Using GDI Technique." International Journal of Hybrid Information Technology 8, no. 7 (July 31, 2015): 293–304. http://dx.doi.org/10.14257/ijhit.2015.8.7.27.

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48

Singh, Haramardeep, and Harmeet Kaur. "Design and Simulation of Novel 10-T Subtraction Logic for ALU Design using GDI Technique." International Journal of Hybrid Information Technology 9, no. 2 (February 28, 2016): 203–14. http://dx.doi.org/10.14257/ijhit.2016.9.2.18.

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49

Chen, Hao, Chenxi Wang, Xiang Li, Yongzhi Li, Miao Zhang, Zhijun Peng, Yiqiang Pei, et al. "Quantitative Analysis of Water Injection Mass and Timing Effects on Oxy-Fuel Combustion Characteristics in a GDI Engine Fuelled with E10." Sustainability 15, no. 13 (June 29, 2023): 10290. http://dx.doi.org/10.3390/su151310290.

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The climate change issue has become a growing concern due to the increasing greenhouse gas emissions. To achieve carbon neutrality for mitigating the climate problem, the oxy-fuel combustion (OFC) technique on internal combustion engines (ICEs) has attracted much attention. Furthermore, the water injection (WI) strategy was proven effective in improving the combustion process and thermal efficiency in engines under OFC mode. However, WI strategy effects on gasoline direct injection (GDI) engines fuelled with gasoline–alcohol blends have not been reported. This study quantitatively analysed WI mass and timing effects on oxy-fuel combustion performance from a GDI engine fuelled with E10 (10% ethanol and 90% gasoline in mass) by simulation. The results show that equivalent brake-specific fuel consumption (BSFCE) shows a monotonically decreasing trend with the increase in the water–fuel mass ratio (Rwf) from 0 to 0.2. However, further increasing Rwf would cause a deterioration in BSFCE due to the enhanced cooling effects of water vaporisation. Moreover, an appropriate water injection timing (tWI) could be explored for improving OFC performance, especially for large Rwf conditions. The difference in BSFCE between tWI = −100°CA and tWI = −60°CA can be up to around 6.3 g/kWh by increasing Rwf to 0.6.

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50

Potenza, Marco, Marco Milanese, Fabrizio Naccarato, and Arturo de Risi. "In-cylinder soot concentration measurement by Neural Network Two Colour technique (NNTC) on a GDI engine." Combustion and Flame 217 (July 2020): 331–45. http://dx.doi.org/10.1016/j.combustflame.2020.03.024.

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