Статті в журналах з теми "GATE LEVEL SIMULATION"
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Chatterjee, Debapriya, Andrew Deorio, and Valeria Bertacco. "Gate-Level Simulation with GPU Computing." ACM Transactions on Design Automation of Electronic Systems 16, no. 3 (June 2011): 1–26. http://dx.doi.org/10.1145/1970353.1970363.
Повний текст джерелаViamontes, George F., Igor L. Markov, and John P. Hayes. "Improving Gate-Level Simulation of Quantum Circuits." Quantum Information Processing 2, no. 5 (October 2003): 347–80. http://dx.doi.org/10.1023/b:qinp.0000022725.70000.4a.
Повний текст джерелаUbar, Raimund, Jaan Raik, Eero Ivask, and Marina Brik. "Defect-oriented mixed-level fault simulation in digital systems." Facta universitatis - series: Electronics and Energetics 15, no. 1 (2002): 123–36. http://dx.doi.org/10.2298/fuee0201123u.
Повний текст джерелаChih-Shun Ding, Chi-Ying Tsui, and M. Pedram. "Gate-level power estimation using tagged probabilistic simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17, no. 11 (1998): 1099–107. http://dx.doi.org/10.1109/43.736184.
Повний текст джерелаSvensson, C. M., and R. Tjarnstrom. "Switch-level simulation and the pass transistor EXOR gate." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7, no. 9 (1988): 994–97. http://dx.doi.org/10.1109/43.7797.
Повний текст джерелаBagrodia, Rajive, Yu-an Chen, Vikas Jha, and Nicki Sonpar. "Parallel gate-level circuit simulation on shared memory architectures." ACM SIGSIM Simulation Digest 25, no. 1 (July 1995): 170–74. http://dx.doi.org/10.1145/214283.214336.
Повний текст джерелаVandris, Evstratios, and Gerald Sobelman. "Switch-level Differential Fault Simulation of MOS VLSI Circuits." VLSI Design 4, no. 3 (January 1, 1996): 217–29. http://dx.doi.org/10.1155/1996/34084.
Повний текст джерелаCORNO, FULVIO, MATTEO SONZA REORDA, and GIOVANNI SQUILLERO. "EVOLUTIONARY SIMULATION-BASED VALIDATION." International Journal on Artificial Intelligence Tools 13, no. 04 (December 2004): 897–916. http://dx.doi.org/10.1142/s0218213004001880.
Повний текст джерелаHigami, Yoshinobu, Kewal K. Saluja, Hiroshi Takahashi, Sin-ya Kobayashi, and Yuzo Takamatsu. "An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation." IPSJ Transactions on System LSI Design Methodology 2 (2009): 250–62. http://dx.doi.org/10.2197/ipsjtsldm.2.250.
Повний текст джерелаBoliolo, A., L. Benini, G. de Micheli, and B. Ricco. "Gate-level power and current simulation of CMOS integrated circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, no. 4 (December 1997): 473–88. http://dx.doi.org/10.1109/92.645074.
Повний текст джерелаWood, Kenneth R. "Distributing gate-level digital timing simulation over arrays of transputers." Concurrency: Practice and Experience 3, no. 4 (August 1991): 367–79. http://dx.doi.org/10.1002/cpe.4330030413.
Повний текст джерелаCheng, Rui, Lin-Zi Yin, Zhao-Hui Jiang, and Xue-Mei Xu. "Gate-Level Circuit Partitioning Algorithm Based on Clustering and an Improved Genetic Algorithm." Entropy 25, no. 4 (March 31, 2023): 597. http://dx.doi.org/10.3390/e25040597.
Повний текст джерелаHungse Cha, E. M. Rudnick, J. H. Patel, R. K. Iyer, and G. S. Choi. "A gate-level simulation environment for alpha-particle-induced transient faults." IEEE Transactions on Computers 45, no. 11 (1996): 1248–56. http://dx.doi.org/10.1109/12.544481.
Повний текст джерелаFahmi, M. I., M. F. Mukmin, H. F. Liew, C. L. Wai, M. A. Aazmi, and S. N. M. Arshad. "Design new voltage balancing control series connected for HV-IGBT`s." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 4 (August 1, 2021): 2899. http://dx.doi.org/10.11591/ijece.v11i4.pp2899-2906.
Повний текст джерелаAlamin, Mochammad Machlul, Hendrawan Armanto, and Indra Maryati. "Penerapan Teknologi Augmented Reality Untuk Pembelajaran Gerbang Logika Pada Mata Pelajaran Sistem Komputer." JURNAL MEDIA INFORMATIKA BUDIDARMA 4, no. 3 (July 20, 2020): 503. http://dx.doi.org/10.30865/mib.v4i3.2128.
Повний текст джерелаMeraji, Sina, Wei Zhang, and Carl Tropper. "On the Scalability and Dynamic Load-Balancing of Optimistic Gate Level Simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, no. 9 (September 2010): 1368–80. http://dx.doi.org/10.1109/tcad.2010.2049044.
Повний текст джерелаBatagin Armelin, Fábio, Lírida Alves de Barros Naviner, and Roberto d’Amore. "Soft-Error Vulnerability Estimation Approach Based on the SET Susceptibility of Each Gate." Electronics 8, no. 7 (July 2, 2019): 749. http://dx.doi.org/10.3390/electronics8070749.
Повний текст джерелаZhao, Weiguo, Shuo Li, Honggang Fan, and Liying Wang. "Fluctuation in the Water Level of the Air Hole of the Gate Shaft in the Pumped Storage Power Station." Processes 11, no. 3 (March 16, 2023): 905. http://dx.doi.org/10.3390/pr11030905.
Повний текст джерелаFehr, E. Scott, Stephen A. Szygenda, and Granville E. Ott. "An Integrated Hardware Array for Very High Speed Logic Simulation." VLSI Design 4, no. 2 (January 1, 1996): 107–18. http://dx.doi.org/10.1155/1996/13931.
Повний текст джерелаKim, Hong K., and Jack Jean. "Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation." VLSI Design 9, no. 3 (January 1, 1999): 253–70. http://dx.doi.org/10.1155/1999/18373.
Повний текст джерелаPrasad, G. Durga, and V. Jegathesan. "FPGA Based Symmetrical Multi Level Inverter with Reduced Gate Driver Circuits." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 1 (May 28, 2018): 53. http://dx.doi.org/10.11591/ijres.v6.i1.pp53-68.
Повний текст джерелаZamri, Muhammad Harith Bin, Yoshihiro Ujihara, Masanori Nakamura, Mohammad R. K. Mofrad, and Shukei Sugita. "Decoding the Effect of Hydrostatic Pressure on TRPV1 Lower-Gate Conformation by Molecular-Dynamics Simulation." International Journal of Molecular Sciences 23, no. 13 (July 1, 2022): 7366. http://dx.doi.org/10.3390/ijms23137366.
Повний текст джерелаRAGUL, DURAISAMY, and VENKATRAMAN THIYAGARAJAN. "A NOVEL FAULT TOLERANT ASYMMETRICAL 21-LEVEL INVERTER TOPOLOGY WITH REDUCED COMPONENTS." REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE 68, no. 2 (July 3, 2023): 200–205. http://dx.doi.org/10.59277/rrst-ee.2023.68.2.14.
Повний текст джерелаSarhan, Sarhan Abdulsatar, and Shaker Abdulatif Jalil. "Analysis of Simulation Outputs for the Mutual Effect of Flow in Weir and Gate System." Journal of University of Babylon for Engineering Sciences 26, no. 6 (April 10, 2018): 48–59. http://dx.doi.org/10.29196/jubes.v26i6.1050.
Повний текст джерелаAamali, Kaoutar, Abdelhakim Alali, Mohamed Sadik, and Zineb El Hariti. "A Review of the Different Levels of Abstraction for Systems-on-Chip (SoC)." E3S Web of Conferences 229 (2021): 01025. http://dx.doi.org/10.1051/e3sconf/202122901025.
Повний текст джерелаFang, Tianyu, Yu Gu, Xiangli He, Xiaodong Liu, Yu Han, and Jian Chen. "Numerical Simulation of Gate Control for Unsteady Irrigation Flow to Improve Water Use Efficiency in Farming." Water 10, no. 9 (September 5, 2018): 1196. http://dx.doi.org/10.3390/w10091196.
Повний текст джерелаMuroi, Hiromichi, Kensuke Mine, and Yoshiki Eguchi. "Scenario Analysis of Sluice Gate Operations for Evaluating Inland Flood Damage." Journal of Disaster Research 16, no. 3 (April 1, 2021): 429–36. http://dx.doi.org/10.20965/jdr.2021.p0429.
Повний текст джерелаZhang, Meng, Baikui Li, and Jin Wei. "Exploring SiC Planar IGBTs towards Enhanced Conductivity Modulation Comparable to SiC Trench IGBTs." Crystals 10, no. 5 (May 23, 2020): 417. http://dx.doi.org/10.3390/cryst10050417.
Повний текст джерелаQiu, Chun, and Cheng Lan Liu. "3D Dynamic Numerical Simulation of Water Flow in Stilling Basin with Flaring Gate Pier." Applied Mechanics and Materials 580-583 (July 2014): 1971–74. http://dx.doi.org/10.4028/www.scientific.net/amm.580-583.1971.
Повний текст джерелаBertrand-Krajewski, J. L., J. P. Bardin, C. Gibello, and D. Laplace. "Hydraulics of a sewer flushing gate." Water Science and Technology 47, no. 4 (February 1, 2003): 129–36. http://dx.doi.org/10.2166/wst.2003.0237.
Повний текст джерелаLi, Ran, Jie Zhang, and Jianbo Xiao. "Operation State Evaluation of Miter Gate Based on On-Line Monitoring and Finite Element Analysis." Applied Sciences 13, no. 1 (December 28, 2022): 381. http://dx.doi.org/10.3390/app13010381.
Повний текст джерелаAshenden, Peter J., Henry Detmold, and Wayne S. McKeen. "Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms." VLSI Design 2, no. 1 (January 1, 1994): 1–16. http://dx.doi.org/10.1155/1994/86178.
Повний текст джерелаJmai, Bassem, Vitor Silva, and Paulo M. Mendes. "2D Electronics Based on Graphene Field Effect Transistors: Tutorial for Modelling and Simulation." Micromachines 12, no. 8 (August 18, 2021): 979. http://dx.doi.org/10.3390/mi12080979.
Повний текст джерелаVanijjirattikhan, Rangsarit, Chinoros Thongthamchart, Patsorn Rakcheep, Unpong Supakchukul, and Jittiwut Suwatthikul. "Reservoir Flood Routing Simulation for Dam Safety Management in Thailand." Journal of Disaster Research 16, no. 4 (June 1, 2021): 596–606. http://dx.doi.org/10.20965/jdr.2021.p0596.
Повний текст джерелаChen, Haotian, Hongjun Lv, Zhang Zhang, Xin Cheng, and Guangjun Xie. "Design and Analysis of a Novel Low-Power Exclusive-OR Gate Based on Quantum-Dot Cellular Automata." Journal of Circuits, Systems and Computers 28, no. 08 (July 2019): 1950141. http://dx.doi.org/10.1142/s021812661950141x.
Повний текст джерелаChen, Jie Ren, and Shi Feng Xu. "The Numerical Simulation of Hydrodynamics in the Sancha River Mouth." Advanced Materials Research 1065-1069 (December 2014): 2978–82. http://dx.doi.org/10.4028/www.scientific.net/amr.1065-1069.2978.
Повний текст джерелаChen, Shi Gui, and Xi Zhang. "Optimized Simulation of Automatic Gate System of Beijing Tianjin Intercity Line on Beijing South Railway Station." Applied Mechanics and Materials 602-605 (August 2014): 1391–94. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.1391.
Повний текст джерелаSu, Ching-Lung, Tse-Min Chen, and Kuo-Hsuan Wu. "A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation." VLSI Design 2013 (May 16, 2013): 1–10. http://dx.doi.org/10.1155/2013/529150.
Повний текст джерелаJohannesson, Daniel, and Muhammad Nawaz. "Development of a PSpice Model for SiC MOSFET Power Modules." Materials Science Forum 858 (May 2016): 1074–77. http://dx.doi.org/10.4028/www.scientific.net/msf.858.1074.
Повний текст джерелаAl jewari, Maher Abd Ibrahim, Auzani Jidin, Siti Azura Ahmad Tarusan, and Mohammed Rasheed. "Implementation of SVM for five-level cascaded H-Bridge multilevel inverters utilizing FPGA." International Journal of Power Electronics and Drive Systems (IJPEDS) 11, no. 3 (September 1, 2020): 1132. http://dx.doi.org/10.11591/ijpeds.v11.i3.pp1132-1144.
Повний текст джерелаShah, M. J., K. S. Pandya, and P. Chauhan. "Direct ADC Controlled Asymmetric Cascaded Multilevel Inverter." Engineering, Technology & Applied Science Research 12, no. 4 (August 1, 2022): 9071–77. http://dx.doi.org/10.48084/etasr.5164.
Повний текст джерелаIvancova, Olga, Vladimir Korenkov, Olga Tyatyushkina, Sergey Ulyanov, and Toshio Fukuda. "Quantum supremacy in end-to-end intelligent IT. Pt. I:Quantum software engineering–quantum gate level applied models simulators." System Analysis in Science and Education, no. 1 (2020) (2020): 52–84. http://dx.doi.org/10.37005/2071-9612-2020-1-52-84.
Повний текст джерелаGuo, Huaixin, Tangsheng Chen, and Shang Shi. "Transient Simulation for the Thermal Design Optimization of Pulse Operated AlGaN/GaN HEMTs." Micromachines 11, no. 1 (January 9, 2020): 76. http://dx.doi.org/10.3390/mi11010076.
Повний текст джерелаYang, Seiyang. "Performance Improvement of Prediction-Based Parallel Gate-Level Timing Simulation Using Prediction Accuracy Enhancement Strategy." KIPS Transactions on Computer and Communication Systems 5, no. 12 (December 31, 2016): 439–46. http://dx.doi.org/10.3745/ktccs.2016.5.12.439.
Повний текст джерелаJiang, Yu, Linyan Zeng, and Yuxiao Luo. "Multiobjective Gate Assignment Based on Passenger Walking Distance and Fairness." Mathematical Problems in Engineering 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/361031.
Повний текст джерелаChampac, Victor H., and Joan Figueras. "Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects." VLSI Design 5, no. 3 (January 1, 1997): 273–84. http://dx.doi.org/10.1155/1997/97381.
Повний текст джерелаRaj, Sumit, Rajib Kumar Mandal, Mala De, and Ashutosh Kumar Singh. "Nine-level inverter with lesser number of power semiconductor switches using dSPACE." International Journal of Power Electronics and Drive Systems (IJPEDS) 13, no. 1 (March 1, 2022): 39. http://dx.doi.org/10.11591/ijpeds.v13.i1.pp39-46.
Повний текст джерелаDeng, Chengfa, and Jincheng Du. "Numerical Simulation of Hydraulic Characteristics of Spillway Tunnel with Gradually Expanding Outlet and Lower outlet height." Journal of Physics: Conference Series 2271, no. 1 (May 1, 2022): 012031. http://dx.doi.org/10.1088/1742-6596/2271/1/012031.
Повний текст джерелаKim, Dong-Wook, and Tae-Yong Choi. "Delay Time Estimation Model for Large Digital CMOS Circuits." VLSI Design 11, no. 2 (January 1, 2000): 161–73. http://dx.doi.org/10.1155/2000/18189.
Повний текст джерелаSihombing, Fiktor, and Nova Juwita Siburian. "Perancangan Gerbang Otomatis Menggunakan Frekuensi Berbasis Arduino." Jurnal ELPOTECS 4, no. 2 (September 30, 2021): 10–21. http://dx.doi.org/10.51622/elpotecs.v4i2.430.
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