Статті в журналах: "Gate array circuits"

1

Abraitis, Vidas, and Žydrūnas Tamoševičius. "Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA." Solid State Phenomena 144 (September 2008): 214–19. http://dx.doi.org/10.4028/www.scientific.net/ssp.144.214.

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Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.

2

Mowafy, Aya Nabeel. "Asynchronous Circuits Design Using a Field Programmable Gate Array." International Journal for Research in Applied Science and Engineering Technology 6, no. 4 (April 30, 2018): 2423–32. http://dx.doi.org/10.22214/ijraset.2018.4412.

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3

Mohammadi, Hossein, and Keivan Navi. "Energy-Efficient Single-Layer QCA Logical Circuits Based on a Novel XOR Gate." Journal of Circuits, Systems and Computers 27, no. 14 (August 23, 2018): 1850216. http://dx.doi.org/10.1142/s021812661850216x.

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Quantum-dot Cellular Automata (QCA) as a nanoscale transistor-less device technology offers distinguishing advantages over the limitations of CMOS circuits. This nanoelectronic is based on the mapping of binary logic in the two excess electrons configuration within a four-dot cell. In this paper, we propose a new ultra-low energy and low-complexity two-input XOR gate which can be employed as a basic component in designing a wide range of QCA logical circuits. For performance evaluation of the presented design in a large array of QCA structures, even parity generator circuit with different lengths up to 32 bits as well as LFSR circuit are designed and analyzed as instances of logical circuits. The simulation results reveal that our proposed designs have significant improvements in contrast to counterparts from hardware implementation requirements and energy consumption aspects. QCADesigner tool is utilized to evaluate functional correctness of the proposed circuits and power dissipation is evaluated using QCAPro simulator as an accurate power estimator tool.

4

Sato, Ryoichi, Yuta Kodera, Md Arshad Ali, Takuya Kusaka, Yasuyuki Nogami, and Robert H. Morelos-Zaragoza. "Consideration for Affects of an XOR in a Random Number Generator Using Ring Oscillators." Entropy 23, no. 9 (September 5, 2021): 1168. http://dx.doi.org/10.3390/e23091168.

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A cloud service to offer entropy has been paid much attention to. As one of the entropy sources, a physical random number generator is used as a true random number generator, relying on its irreproducibility. This paper focuses on a physical random number generator using a field-programmable gate array as an entropy source by employing ring oscillator circuits as a representative true random number generator. This paper investigates the effects of an XOR gate in the oscillation circuit by observing the output signal period. It aims to reveal the relationship between inputs and the output through the XOR gate in the target generator. The authors conduct two experiments to consider the relevance. It is confirmed that combining two ring oscillators with an XOR gate increases the complexity of the output cycle. In addition, verification using state transitions showed that the probability of the state transitions was evenly distributed by increasing the number of ring oscillator circuits.

5

Kuboki, S., I. Masuda, T. Hayashi, and S. Torii. "A 4K CMOS gate array with automatically generated test circuits." IEEE Journal of Solid-State Circuits 20, no. 5 (October 1985): 1018–24. http://dx.doi.org/10.1109/jssc.1985.1052430.

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6

AKELLA, KAPILAN MAHESWARAN VENKATESH. "PGA-STC: programmable gate array for implementing self-timed circuits." International Journal of Electronics 84, no. 3 (March 1998): 255–67. http://dx.doi.org/10.1080/002072198134823.

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7

Murtaza, Ali Faisal, and Hadeed Ahmed Sher. "A Reconfiguration Circuit to Boost the Output Power of a Partially Shaded PV String." Energies 16, no. 2 (January 4, 2023): 622. http://dx.doi.org/10.3390/en16020622.

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An optical isolator circuit is developed to detect and dynamically relocate the photovoltaic (PV) module under partial shading. The suggested system control structure operates in two modes. Mode 1 governs the system at global maxima (GM) by tracing the power-voltage (PV) curve. Mode 2 detects and separates all the bypassed modules from a PV string/array by means of a decentralized control and stores its power in the battery. Simulations are performed on different shading patterns to verify the efficacy of the suggested system. The results showcase that the averaged harnessed power using the proposed circuit is 25.26% more than the total cross-tied (TCT) and series-parallel (SP) array configurations. The proposed circuit does not require complex gate driver circuits and large switch counts. The circuit is scalable and can be implemented on an “N × N” array.

8

Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

9

Cherepacha, Don, and David Lewis. "DP-FPGA: An FPGA Architecture Optimized for Datapaths." VLSI Design 4, no. 4 (January 1, 1996): 329–43. http://dx.doi.org/10.1155/1996/95942.

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This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry skip circuit, a four-bit register with enable and direct input capabilities, and four three-state buffers. Further estimates of implementation area predict that the area of a design's datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.

10

Reaungepattanawiwat, Chalermpol, and Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter." Applied Mechanics and Materials 781 (August 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.

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This paper presents a high voltage gain of a DC-DC converter. The proposed system consists of voltage multiplier circuits and a coupled inductor of a boost DC-DC converter. The input voltage of the voltage multiplier circuit is the induced voltage of inductor at a boost DC-DC converter. The field programmable gate array (FGPA) is used for generating the control signal of the proposed system. To verify the proposed circuit, an experiment was conducted from the prototype circuit. The proposed circuit can step-up the voltage with high voltage gain. Moreover, the voltage across the switch is very low.

11

Harrison, R. R., J. A. Bragg, P. Hasler, B. A. Minch, and S. P. Deweerth. "A CMOS programmable analog memory-cell array using floating-gate circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 1 (2001): 4–11. http://dx.doi.org/10.1109/82.913181.

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12

TANAKA, YU. "EXACT NON-IDENTITY CHECK IS NQP-COMPLETE." International Journal of Quantum Information 08, no. 05 (August 2010): 807–19. http://dx.doi.org/10.1142/s0219749910006599.

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To understand quantum gate array complexity, we define a problem named exact non-identity check, which is a decision problem to determine whether a given classical description of a quantum circuit is strictly equivalent to the identity or not. We show that the computational complexity of this problem is non-deterministic quantum polynomial-time (NQP)-complete. As corollaries, it is derived that exact non-equivalence check of two given classical descriptions of quantum circuits is also NQP-complete and that minimizing the number of quantum gates for a given quantum circuit without changing the implemented unitary operation is NQP-hard.

13

Chin, Scott Y. L., Clarence S. P. Lee, and Steven J. E. Wilton. "On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays." International Journal of Reconfigurable Computing 2008 (2008): 1–13. http://dx.doi.org/10.1155/2008/751863.

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We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

14

Lin, Y., Fei Li, and Lei He. "Circuits and architectures for field programmable gate array with configurable supply voltage." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13, no. 9 (September 2005): 1035–47. http://dx.doi.org/10.1109/tvlsi.2005.857180.

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15

Liu, Lijun, Jie Han, Lin Xu, Jianshuo Zhou, Chenyi Zhao, Sujuan Ding, Huiwen Shi, et al. "Aligned, high-density semiconducting carbon nanotube arrays for high-performance electronics." Science 368, no. 6493 (May 21, 2020): 850–56. http://dx.doi.org/10.1126/science.aba5980.

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Single-walled carbon nanotubes (CNTs) may enable the fabrication of integrated circuits smaller than 10 nanometers, but this would require scalable production of dense and electronically pure semiconducting nanotube arrays on wafers. We developed a multiple dispersion and sorting process that resulted in extremely high semiconducting purity and a dimension-limited self-alignment (DLSA) procedure for preparing well-aligned CNT arrays (within alignment of 9 degrees) with a tunable density of 100 to 200 CNTs per micrometer on a 10-centimeter silicon wafer. Top-gate field-effect transistors (FETs) fabricated on the CNT array show better performance than that of commercial silicon metal oxide–semiconductor FETs with similar gate length, in particular an on-state current of 1.3 milliamperes per micrometer and a recorded transconductance of 0.9 millisiemens per micrometer for a power supply of 1 volt, while maintaining a low room-temperature subthreshold swing of <90 millivolts per decade using an ionic-liquid gate. Batch-fabricated top-gate five-stage ring oscillators exhibited a highest maximum oscillating frequency of >8 gigahertz.

16

Sotohebo, Takashi, Minoru Watanabe, and Funtinori Kobayashi. "An FPGA Implementation of Finite Physical Quantity Neural Network." Journal of Robotics and Mechatronics 15, no. 2 (April 20, 2003): 136–42. http://dx.doi.org/10.20965/jrm.2003.p0136.

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We propose installing a finite physical quantity neural network model on a high-density field programmable gate array (FPGA) at high speed by reducing multipliers. We could thereby downsize circuits without loss of precision. We evaluated its installation and experimental results for image recognition.

17

Trost, Andrej, Andrej Zemva, and Matjaz Verderber. "Prototyping Hardware and Software Environment for Teaching Digital Circuit Design." International Journal of Electrical Engineering & Education 38, no. 4 (October 2001): 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.

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In the paper, we present our latest achievements and experience in undergraduate teaching of digital circuits, integrated circuits and embedded systems by exploiting our prototyping hardware and software environment. The hardware environment is based on Field Programmable Gate Array (FPGA) modules that provide sufficient flexibility and support a broad scope of digital design applications. In addition, the designed software environment supports user-friendly hardware verification of the logic circuits implemented on the hardware system. We describe some typical applications and student projects implemented on the programmable prototyping system.

18

Cabrita, Daniel Mealha, and Carlos Raimundo Erig Lima. "A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms." Journal of Circuits, Systems and Computers 25, no. 02 (December 23, 2015): 1650009. http://dx.doi.org/10.1142/s0218126616500092.

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Current works on generation of combinational logic circuits (CLC) using evolutionary algorithms (EA) propose solutions using field-programmable gate array (FPGA) to accelerate the process of combinational circuit simulation, a step needed in order to evaluate the level of correctness of each individual circuit. However, the current works fail to separate the two distinct problems: the EA and the circuit simulator. The insistence of treating both problem as a single one results in works that fail to address either properly, restricting solutions to simple circuits and to topologically restrictive circuit simulators, while providing very limited data on the results. In this work, we address the circuit simulator problem exclusively, where we propose an architecture for fast simulation of n-LUT CLC of arbitrary topology. The proposed architecture is modular and makes no assumptions on the specific EA to be used with. We provide detailed performance results for varying circuit dimensions, and those results show that our architecture is able to surpass other works both in terms of performance and topological flexibility.

19

Zheng, Fang Yan, Zi Ran Chen, and Zhi Cheng Yu. "Signal Processing Circuit Design Based on SOPC Technology for the Electric Field Type Time Grating Sensors." Applied Mechanics and Materials 635-637 (September 2014): 755–59. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.755.

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Signal processing circuits are proposed for the electric field type time grating sensors. The proposed design scheme integrates sampling function and processing function into a signal field programmable gate array (FPGA) based on system on programmable chip (SOPC) technology. Employing NiosII technology and adding self-defined instructions improve data processing speed for time grating sensors. The proposed signal processing circuits are simple and stabile. The proposed signal processing circuits are applied to electric field type linear time grating sensors, the experiments results that the peak-to peak measuring error is 0.3um within 200mm without any corrections.

20

Takahashi, T., M. Uchida, T. Takahashi, R. Yoshino, M. Yamamoto, and N. Kitamura. "A CMOS gate array with 600 Mb/s simultaneous bidirectional I/O circuits." IEEE Journal of Solid-State Circuits 30, no. 12 (1995): 1544–46. http://dx.doi.org/10.1109/4.482204.

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21

Fehr, E. Scott, Stephen A. Szygenda, and Granville E. Ott. "An Integrated Hardware Array for Very High Speed Logic Simulation." VLSI Design 4, no. 2 (January 1, 1996): 107–18. http://dx.doi.org/10.1155/1996/13931.

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A hardware architecture is proposed which allows direct mapping of design simulation topology onto an acceleration platform. In order to clarify architectural principles, the simulation is confined to functional verification of unit delay, binary valued gate level logic designs. Under this approach, a rank ordered design description is executed on a massively parallel processor grid which implements an efficient and direct model of the design, similar to prototyping. Architectural innovation reduces logic complexity and execution time of boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

22

Rayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar, and Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes." Computer Science and Information Technologies 3, no. 1 (March 1, 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.

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Nowadays low power design circuits are major important for data transmission and processing the information among various system designs. One of the major multipliers used for synchronizing the data transmission is the systolic array multiplier, low power designs are mostly used for increasing the performance and reducing the hardware complexity. Among all the mathematical operations, multiplier plays a major role where it processes more information and with the high complexity of circuit in the existing irreversible design. We develop a systolic array multiplier using reversible gates for low power appliances, faults and coverage of the reversible logic are calculated in this paper. To improvise more, we introduced a reversible logic gate and tested the reversible systolic array multiplier using the fault injection method of built-in self-test block observer (BILBO) in which all corner cases are covered which shows 97% coverage compared with existing designs. Finally, Xilinx ISE 14.7 was used for synthesis and simulation results and compared parameters with existing designs which prove more efficiency.

23

Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

24

Pfänder, O. A., R. Nopper, H. J. Pfleiderer, S. Zhou, and A. Bermak. "Comparison of reconfigurable structures for flexible word-length multiplication." Advances in Radio Science 6 (May 26, 2008): 113–18. http://dx.doi.org/10.5194/ars-6-113-2008.

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Abstract. Binary multiplication continues to be one of the essential arithmetic operations in digital circuits. Even though field-programmable gate arrays (FPGAs) are becoming more and more powerful these days, the vendors cannot avoid implementing multiplications with high word-lengths using embedded blocks instead of configurable logic. But on the other hand, the circuit's efficiency decreases if the provided word-length of the hard-wired multipliers exceeds the precision requirements of the algorithm mapped into the FPGA. Thus it is beneficial to use multiplier blocks with configurable word-length, optimized for area, speed and power dissipation, e.g. regarding digital signal processing (DSP) applications. In this contribution, we present different approaches and structures for the realization of a multiplication with variable precision and perform an objective comparison. This includes one approach based on a modified Baugh and Wooley algorithm and three structures using Booth's arithmetic operand recoding with different array structures. All modules have the option to compute signed two's complement fix-point numbers either as an individual computing unit or interconnected to a superior array. Therefore, a high throughput at low precision through parallelism, or a high precision through concatenation can be achieved.

25

Okuno, Hirotsugu, and Tetsuya Yagi. "Bio-Inspired Real-Time Robot Vision for Collision Avoidance." Journal of Robotics and Mechatronics 20, no. 1 (February 20, 2008): 68–74. http://dx.doi.org/10.20965/jrm.2008.p0068.

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A mixed analog-digital integrated vision sensor was designed to detect an approaching object in real-time. To respond selectively to approaching stimuli, the sensor employed an algorithm inspired by the visual nervous system of a locust, which can avoid collisions robustly by using visual information. An electronic circuit model was designed to mimic the architecture of the locust nervous system. Computer simulations showed that the model provided appropriate responses for collision avoidance. We implemented the model with a compact hardware system consisting of a silicon retina and field-programmable gate array (FPGA) circuits; the system was confirmed to respond selectively to approaching stimuli that constituted a collision threat.

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Hidalgo-López, José A., Óscar Oballe-Peinado, Julián Castellanos-Ramos, and José A. Sánchez-Durán. "Two-Capacitor Direct Interface Circuit for Resistive Sensor Measurements." Sensors 21, no. 4 (February 22, 2021): 1524. http://dx.doi.org/10.3390/s21041524.

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Direct interface circuits (DICs) avoid the need for signal conditioning circuits and analog-to-digital converters (ADCs) to obtain digital measurements of resistive sensors using only a few passive elements. However, such simple hardware can lead to quantization errors when measuring small resistance values as well as high measurement times and uncertainties for high resistances. Different solutions to some of these problems have been presented in the literature over recent years, although the increased uncertainty in measurements at higher resistance values is a problem that has remained unaddressed. This article presents an economical hardware solution that only requires an extra capacitor to reduce this problem. The circuit is implemented with a field-programmable gate array (FPGA) as a programmable digital device. The new proposal significantly reduces the uncertainty in the time measurements. As a result, the high resistance errors decreased by up to 90%. The circuit requires three capacitor discharge cycles, as is needed in a classic DIC. Therefore, the time to estimate resistance increases slightly, between 2.7% and 4.6%.

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Yoshikawa, Masaya, Yusuke Mori, and Takeshi Kumaki. "Implementation Aware Hardware Trojan Trigger." Advanced Materials Research 933 (May 2014): 482–86. http://dx.doi.org/10.4028/www.scientific.net/amr.933.482.

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Recently, the threat of hardware Trojans has garnered attention. Hardware Trojans are malicious circuits that are incorporated into large-scale integrations (LSIs) during the manufacturing process. When predetermined conditions specified by an attacker are satisfied, the hardware Trojan is triggered and performs subversive activities without the LSI users even being aware of these activities. In previous studies, a hardware Trojan was incorporated into a cryptographic circuit to estimate confidential information. However, Trojan triggers have seldom been studied. The present study develops several new Trojan triggers and each of them is embedded in a field-programmable gate array (FPGA). Subsequently, the ease of detection of each trigger is verified from the standpoint of area.

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Liu, Yixuan, Qiao Hu, Qiqiao Wu, Xuanzhi Liu, Yulin Zhao, Donglin Zhang, Zhongze Han, et al. "Probabilistic Circuit Implementation Based on P-Bits Using the Intrinsic Random Property of RRAM and P-Bit Multiplexing Strategy." Micromachines 13, no. 6 (June 10, 2022): 924. http://dx.doi.org/10.3390/mi13060924.

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Probabilistic computing is an emerging computational paradigm that uses probabilistic circuits to efficiently solve optimization problems such as invertible logic, where traditional digital computations are difficult to solve. This paper proposes a true random number generator (TRNG) based on resistive random-access memory (RRAM), which is combined with an activation function implemented by a piecewise linear function to form a standard p-bit cell, one of the most important parts of a p-circuit. A p-bit multiplexing strategy is also applied to reduce the number of p-bits and improve resource utilization. To verify the superiority of the proposed probabilistic circuit, we implement the invertible p-circuit on a field-programmable gate array (FPGA), including AND gates, full adders, multi-bit adders, and multipliers. The results of the FPGA implementation show that our approach can significantly save the consumption of hardware resources.

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Sun, Jun-Wei, Xing-Tong Zhao, and Yan-Feng Wang. "Multi-Input Look-Up-Table Design Based on Nanometer Memristor." Journal of Nanoelectronics and Optoelectronics 15, no. 1 (January 1, 2020): 113–21. http://dx.doi.org/10.1166/jno.2020.2721.

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The logic blocks of Field Programmable Gate Array (FPGA) basic unit are mainly composed of Look-Up-Tables (LUTs). The traditional LUTs use the static random access memory (SRAM), which causes FPGA reach the limitation in term of the density, speed, and configuration overhead. In this paper, a novel nanometer memristor-based LUT (NMLUT) is composed of memristors, MOS field effect transistors, decoders, resistors. A three-input NMLUT and a four-input NMLUT circuits are investigated. Moreover, an adder is used to verify the practicality of NMLUT circuit. The proposed NMLUT circuit can implement some combinational logic functions through specific configuration and it is better in data transmission and data storage than the traditional LUT. Since NMLUT circuit is compatible with the mainstream circuit in the FPGA, it can effectively solve the limitations of the field FPGA. The correctness of the results is verified in PSPICE software.

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Cheng, Shi, JinBao Zhang, Zhan Gao, and Jiehua Wang. "Circuit Implementation of Respiratory Information Extracted from Electrocardiograms." Journal of Database Management 33, no. 2 (April 1, 2022): 1–12. http://dx.doi.org/10.4018/jdm.314211.

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Breathing is an important physiological process in the human body. The wavelet transform method can extract respiratory information from electrocardiogram (ECG) data; thus, the authors designed an integrated circuit of ECG-derived respiration (EDR). They propose a discrete wavelet transform (DWT) EDR algorithm based on an analysis of the heartbeat frequency and respiration. They verified the algorithm in both the time domain and the frequency domain using Matlab. Next, the DWT EDR digital circuit was designed using the QUARTUS program. Finally, they used a field programmable gate array (FPGA) for downloading and simulation, and they verified the designed circuits using a logic analyzer, where they compared the waveform of the data obtained from the EDR circuit with the waveform obtained after processing the wavelet transform EDR in Matlab. The experimental results showed that the circuit can allow the extraction of respiratory information from ECG data.

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Poghossian, Arshak, Rene Welden, Vahe V. Buniatyan, and Michael J. Schöning. "An Array of On-Chip Integrated, Individually Addressable Capacitive Field-Effect Sensors with Control Gate: Design and Modelling." Sensors 21, no. 18 (September 14, 2021): 6161. http://dx.doi.org/10.3390/s21186161.

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The on-chip integration of multiple biochemical sensors based on field-effect electrolyte-insulator-semiconductor capacitors (EISCAP) is challenging due to technological difficulties in realization of electrically isolated EISCAPs on the same Si chip. In this work, we present a new simple design for an array of on-chip integrated, individually electrically addressable EISCAPs with an additional control gate (CG-EISCAP). The existence of the CG enables an addressable activation or deactivation of on-chip integrated individual CG-EISCAPs by simple electrical switching the CG of each sensor in various setups, and makes the new design capable for multianalyte detection without cross-talk effects between the sensors in the array. The new designed CG-EISCAP chip was modelled in so-called floating/short-circuited and floating/capacitively-coupled setups, and the corresponding electrical equivalent circuits were developed. In addition, the capacitance-voltage curves of the CG-EISCAP chip in different setups were simulated and compared with that of a single EISCAP sensor. Moreover, the sensitivity of the CG-EISCAP chip to surface potential changes induced by biochemical reactions was simulated and an impact of different parameters, such as gate voltage, insulator thickness and doping concentration in Si, on the sensitivity has been discussed.

32

Mayacela, Margarita, Leonardo Rentería, Luis Contreras, and Santiago Medina. "Comparative Analysis of Reconfigurable Platforms for Memristor Emulation." Materials 15, no. 13 (June 25, 2022): 4487. http://dx.doi.org/10.3390/ma15134487.

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The memristor is the fourth fundamental element in the electronic circuit field, whose memory and resistance properties make it unique. Although there are no electronic solutions based on the memristor, interest in application development has increased significantly. Nevertheless, there are only numerical Matlab or Spice models that can be used for simulating memristor systems, and designing is limited to using memristor emulators only. A memristor emulator is an electronic circuit that mimics a memristor. In this way, a research approach is to build discrete-component emulators of memristors for its study without using the actual models. In this work, two reconfigurable hardware architectures have been proposed for use in the prototyping of a non-linearity memristor emulator: the FPAA (Field Programing Analog Arrays) and the FPGA (Field Programming Gate Array). The easy programming and reprogramming of the first architecture and the performance, high area density, and parallelism of the second one allow the implementation of this type of system. In addition, a detailed comparison is shown to underline the main differences between the two approaches. These platforms could be used in more complex analog and/or digital systems, such as neural networks, CNN, digital circuits, etc.

33

Ye, A., and J. Rose. "Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 5 (May 2006): 462–73. http://dx.doi.org/10.1109/tvlsi.2006.876095.

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34

Żbik, Mateusz, and Piotr Wieczorek. "Charge-Line Dual-FET High-Repetition-Rate Pulsed Laser Driver." Applied Sciences 9, no. 7 (March 27, 2019): 1289. http://dx.doi.org/10.3390/app9071289.

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Most modern pulsed laser systems require versatile laser diode drivers. A state-of-the-art pulsed laser driver should provide precise peak power regulation, high repetition rate, and pulse duration control. A new, charge line dual-FET transistor circuit structure was developed to provide all these features. The pulsed modulation current is adjustable up to Imax = 1.2 A, with the laser diode forward voltage acceptable up to UF max = 20 V. The maximum repetition rate is limited by a charge line circuit to frep max = 20 MHz. Compared to the conventional single transistor drivers, the solution proposed in this paper allows a precise, high resolution width regulation to be obtained, whereas a low pulse jitter is ensured. In the solution, two separate, out-of-phase signals are used to trigger the individual Field Effect Transistors (FET). The resultant pulsed modulation current full-width-at-half-maxima (FWHM) is regulated from ~200 ps up to 2 ns. All control and timing signals are generated with a popular Field-Programmable Gate Array (FPGA) digital circuitry. The use of standard FPGA devices ensures the low cost and high reliability of the circuit, which are not available in laser drivers consisting of sophisticated analogue adjustable delay circuits.

35

Ramezani, Hadise, Majid Mohammadi, and Amir Sabbagh Molahosseini. "An efficient look up table based approximate adder for field programmable gate array." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (January 1, 2022): 144. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp144-151.

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The approximate computing is an alternative computing approach which can lead to high-performance implementation of audio and image processing as well as deep learning applications. However, most of the available approximate adders have been designed using application specific integrated circuits (ASICs), and they would not result in an efficient implementation on field programmable gate arrays (FPGAs). In this paper, we have designed a new approximate adder customized for efficient implementation on FPGAs, and then it has been used to build the Gaussian filter. The experimental results of the implementation of Gaussian filter based on the proposed approximate adder on a Virtex-7 FPGA, indicated that the resource utilization has decreased by 20-51%, and the designed filter delay based on the modified design methodology for building approximate adders for FPGA-based systems (MDeMAS) adder has improved 10-35%, due to the obtained output quality.

36

Xu, Baohe, Li Lu, and Dawei Gong. "Research on Real-time Simulation of Power Electronic Circuits Based on Simscape." Journal of Physics: Conference Series 2196, no. 1 (February 1, 2022): 012025. http://dx.doi.org/10.1088/1742-6596/2196/1/012025.

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Abstract In order to realize hardware-in-the-loop simulation of commonly used power electronic circuits, a method of joint simulation using Simcape and field programmable gate array (FPGA) is proposed. This article adopts a switch modeling method suitable for high-frequency characteristics, namely the switch function method. It effectively solves the problem of rigidity non-convergence in the modeling of the binary resistance method, as well as the transient error caused by the binary LC method when the system state is switched with the increase of the switching frequency, which reduces the simulation accuracy. Taking the single-phase full-bridge inverter circuit as an example, a Simscape model based on the state-space averaging method was established, and the HDL code was automatically generated using the Simscape HDL Workflow Advisor tool, and the hardware-in-the-loop simulation was completed with FPGA. Finally, the simulation results with Simulink comparison verify the effectiveness and feasibility of the method.

37

Kondo, Jun, Murali Lingalugari, Pik-Yiu Chan, Evan Heller, and Faquir Jain. "Modeling and Fabrication of Quantum Dot Channel Field Effect Transistors Incorporating Quantum Dot Gate." MRS Proceedings 1551 (2013): 149–54. http://dx.doi.org/10.1557/opl.2013.899.

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ABSTRACTQuantum dot gate (QDG) field-effect transistors (FET) have shown three-state transfer characteristics. Quantum dot channel (QDC) field-effect transistors (FET) have exhibited fourstate ID-VG characteristics. This project aims at studying the effect of incorporating cladded quantum dot layers in the gate region of QDC-FET. Four-state characteristics are explained by carrier transport in narrow energy mini-bands which are manifested in a quantum dot superlattice (QDSL) channel. QDSL is formed by an array of cladded quantum dots (such as SiOx-Si and GeOx-Ge). Multi-state FETs are needed in multi-valued logic (MVL) that can reduce the number of gates and transistors in digital circuits. The fabricated device showed the four-state characteristic (OFF, ‘I1’, ‘I2’, ON).

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Abbas, Abdulkareem Dawah. "Review of high-speed phase accumulator for direct digital frequency synthesizer." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 4 (August 1, 2020): 4008. http://dx.doi.org/10.11591/ijece.v10i4.pp4008-4014.

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A review of high-speed pipelined phase accumulator (PA) is proposed in this paper. The detail explanation of ideas, methods and techniques used in previous researches to improve the PA throughput designs were surveyed. The Brent–Kung (BK) adder was modified in this paper to be applied in pipelined PA architecture. A comparison of different adder circuits, includes a modified BK, ripple carry adder (RCA), Kogge-Stone adder (KS) and other prefix adders were applied to architect the PA based on Pipeline technique. The presented pipelined PA design circuit with multiple frequency control word (FCW) and different adders were coded Verilog hardware description language (HDL) code, compiled and verified with field programmable gate array (FPGA) kit platform. The comparison result shows that the modified BK adder has fast performances. The shifted clocking technique is utilized in the proposed pipelined PA circuit to reduce the unwanted repetitive D-flip flop (DFF) registers (coming from the pipeline technique), while preserving the high speed.

39

Poudel, Bikash, Arslan Munir, Joonho Kong, and Muazzam A. Khan. "Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem." Journal of Low Power Electronics and Applications 11, no. 4 (November 12, 2021): 43. http://dx.doi.org/10.3390/jlpea11040043.

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The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).

40

sriraman, Harini, and Pattabiraman Venkatasubbu. "SeRA: Self-Repairing Architecture for Dark Silicon Era." Journal of Circuits, Systems and Computers 29, no. 04 (June 13, 2019): 2050053. http://dx.doi.org/10.1142/s021812662050053x.

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The lifetime reliability of processors has become a major design constraint in the dark silicon era. Processor reliability issues are mainly due to design defects and aging. Unlike design defects, however, aging faults gradually accumulate over time. Many methods have recently been proposed to monitor the performance degradation of circuits. In this study, an architectural solution that extends the circuit-level age monitoring to processor stages is proposed for monitoring performance degradation. When degradation of a stage quantified as delay of half of the reference clock occurs, a self-repairing mechanism is triggered. This mechanism configures an field programmable gate array (FPGA), which takes over the functions of the degraded unit. The proposed self-repairing mechanism is applied to the stages of the processor data-path. This method (SeRA) has lesser area overhead compared with the state-of-art solutions.

41

Ward, Tyler, Neil Grabham, Chris Freeman, Yang Wei, Ann-Marie Hughes, Conor Power, John Tudor, and Kai Yang. "Multichannel Biphasic Muscle Stimulation System for Post Stroke Rehabilitation." Electronics 9, no. 7 (July 17, 2020): 1156. http://dx.doi.org/10.3390/electronics9071156.

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We present biphasic stimulator electronics developed for a wearable functional electrical stimulation system. The reported stimulator electronics consist of a twenty four channel biphasic stimulator. The stimulator circuitry is physically smaller per channel and offers a greater degree of control over stimulation parameters than existing functional electrical stimulator systems. The design achieves this by using, off the shelf multichannel high voltage switch integrated circuits combined with discrete current limiting and dc blocking circuitry for the frontend, and field programmable gate array based logic to manage pulse timing. The system has been tested on both healthy adults and those with reduced upper limb function following a stroke. Initial testing on healthy users has shown the stimulator can reliably generate specific target gestures such as palm opening or pointing with an average accuracy of better than 4 degrees across all gestures. Tests on stroke survivors produced some movement but this was limited by the mechanical movement available in those users’ hands.

42

M, Saravanan, Nandakumar R, and Veerabalaji G. "Effectual SVPWM Techniques and Implementation of FPGA Based Induction Motor Drive." International Journal of Reconfigurable and Embedded Systems (IJRES) 1, no. 1 (March 1, 2012): 11. http://dx.doi.org/10.11591/ijres.v1.i1.pp11-18.

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This paper presents a field programmable gate array(FPGA)-based control integrated circuits(IC) for controlling the pulsewidth modulation (PWM) inverter used in power conditioning system for ac-voltage regulation. Space vector pulsewidth modulation(SVPWM) algorithm offers great flexibility to optimise switching waveform. Among them,double edge triggering can be implemented, It consumes less power compare to other PWM techniques. The SVPWM pulses thus generated through Xilinx is given as switching pulses to voltage source inverter(VSI) circuit to trigger the motor. The delay time of PWM output is programmable and SVPWM control IC is reprogrammable.It shows the advantage of lower total harmonic distortion(THD) without increasing the switching losses. Results are provided along with simulation analysis in terms of THD,output fundamental voltage and voltage transfer ratio to verify the feasibility of operation. The SVPWM switching pattern has been achieved with a fundamental frequency of 50HZ.

43

Lee, Bong Wan, Min Seong Seo, Ho Guen Oh, and Chan Yik Park. "High-Speed Wavelength Interrogator of Fiber Bragg Gratings for Capturing Impulsive Strain Waveforms." Advanced Materials Research 123-125 (August 2010): 867–70. http://dx.doi.org/10.4028/www.scientific.net/amr.123-125.867.

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It is highly desirable to increase the sampling rate of a fiber Bragg grating (FBG) interrogator in other to sense dynamic strains caused by impulsive acoustic wave. We have developed a wavelength interrogator featuring 100k samplings per second that consists of a solid-state spectrometer, a photodiode array and fully parallel read-out circuits. Central wavelengths on the reflected partial spectra corresponding to FBGs are calculated by the centroid method with the selected groups of the consecutive photodiodes at which each FBG spectrum is imaged. The centroid calculation is simple to be implemented in a field-programmable gate array (FPGA) and fast enough to capture impulsive strain waveforms in real time. Short-term noise on the interrogated wavelengths is estimated to be around 0.5 in terms of stain within the sampling bandwidth.

44

Zhang, Kai, Jihao Gao, YunFei Wang, and MingLiang Liang. "Hardware Realization of Kinematic Mechanism and Control System of Multifunctional Industrial Robot." Security and Communication Networks 2022 (September 10, 2022): 1–5. http://dx.doi.org/10.1155/2022/1940708.

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In order to improve the position control accuracy of industrial robots and solve the problems of poor real-time and reconfigurability of traditional motion controllers, a hardware implementation method for the motion mechanism and control system of multi-functional industrial robots is proposed. The video acquisition system is suitable for infrared detectors containing 4 channels or readout circuits in 4 channels. The video display system is compatible with the old AV/S-Video interface, and is also suitable for computer system video graphics array (VGA) analog video interface and high-definition video interface. Multimedia Interface (HDMI) digital high-definition video interface display terminal equipment. The hardware circuit of video acquisition and corresponding video interface image output is designed, including signal amplification circuit, analog-to-digital conversion circuit, video information buffer circuit, video display digital-to-analog conversion circuit, and interface hardware circuit, to realize the digitization of image information acquisition and image information. Display simulation, construct VGA, AV/S-Video, and HDMI timing sequence with hardware description language through Field programmable gate array (FPGA) to complete the display of corresponding terminal equipment. The experimental results show that the experimental data was substituted into the formula and the variance σ = 0.09 mm was found, indicating that the detection error of the system is less than 0.27 mm, which meets the detection requirements. Through the 3D contour reconstruction experiment of the workpiece, the expected function realization of each module is proved, and the feasibility of the system software and hardware system is verified. This design has good scalability and stability, reducing labor costs.

45

Fang, R. C. Y., K. Y. Su, and J. J. Hsu. "A two-dimensional analysis of sheet and contact resistance effects in basic cells of gate-array circuits." IEEE Journal of Solid-State Circuits 20, no. 2 (April 1985): 481–88. http://dx.doi.org/10.1109/jssc.1985.1052333.

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46

Vu, T. T., R. D. Nelson, G. M. Lee, P. C. T. Roberts, K. W. Lee, S. K. Swanson, A. Peczalski, et al. "Low-power 2K-cell SDFL gate array and DCFL circuits using GaAs self-aligned E/D MESFETs." IEEE Journal of Solid-State Circuits 23, no. 1 (February 1988): 224–38. http://dx.doi.org/10.1109/4.283.

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47

Li, Xin, Qiufan Cheng, Shiliang Guo, and Zhiquan Li. "Research of Gate-Tunable Phase Modulation Metasurfaces Based on Epsilon-Near-Zero Property of Indium-Tin-Oxide." Photonics 9, no. 5 (May 9, 2022): 323. http://dx.doi.org/10.3390/photonics9050323.

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In this paper, we proposed a reflection phase electrically tunable metasurface composed of an Au/Al2O3/ITO/Au grating structure. This antenna array can achieve a broad phase shift continuously and smoothly from 0° to 320° with a 5.85 V applied voltage bias. Tunability arises from field-effect modulation of the carrier concentrations or accumulation layer at the Al2O3/ITO interface, which excites electric and magnetic resonances in the epsilon-near-zero region. To make the reflected phase tuning range as wide as possible, some of the intensity of the reflected light is lost due to the excited surface plasmon effect. Simulation results show that the effect of optimal phase modulation can be realized at a wavelength range of 1550 nm by modulating the carrier concentration in our work. Additionally, we utilized an identical 13-unit array metasurface to demonstrate its application to the beam steering function. This active optical metasurface can enable a new realm of applications in ultrathin integrated photonic circuits.

48

Oukaira, Aziz, Ahmad Hassan, Mohamed Ali, Yvon Savaria, and Ahmed Lakhssassi. "Towards Real-Time Monitoring of Thermal Peaks in Systems-on-Chip (SoC)." Sensors 22, no. 15 (August 7, 2022): 5904. http://dx.doi.org/10.3390/s22155904.

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This paper presents a method to monitor the thermal peaks that are major concerns when designing Integrated Circuits (ICs) in various advanced technologies. The method aims at detecting the thermal peak in Systems on Chip (SoC) using arrays of oscillators distributed over the area of the chip. Measured frequencies are mapped to local temperatures that are used to produce a chip thermal mapping. Then, an indication of the local temperature of a single heat source is obtained in real-time using the Gradient Direction Sensor (GDS) technique. The proposed technique does not require external sensors, and it provides a real-time monitoring of thermal peaks. This work is performed with Field-Programmable Gate Array (FPGA), which acts as a System-on-Chip, and the detected heat source is validated with a thermal camera. A maximum error of 0.3 °C is reported between thermal camera and FPGA measurements.

49

Zhang, Bingda, Xianglong Jin, Sijia Tu, Zhao Jin, and Jie Zhang. "A New FPGA-Based Real-Time Digital Solver for Power System Simulation." Energies 12, no. 24 (December 8, 2019): 4666. http://dx.doi.org/10.3390/en12244666.

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Considering the rational use of field programmable gate array (FPGA) resources, this paper proposes a new FPGA-based real-time digital solver (FRTDS) for power system simulation. Based on the relationship between the number of computing components, the operating frequency, and the pipeline length, the best selection principle is given. By analyzing the implementation method of the Multi-Port Read/Write Circuit, the computing formula of the Look-Up-Table (LUT) consumption was derived. Given the excessive use of LUTs in the original computing components, the computing components were assembled in a single typical arithmetic expression of the power system simulation program, as the basic computing formula was characterized by a subset of the typical computing formula and multiple uses of the same variable. Data communication between different computing components was realized by using Multi-Port Input Circuits that share some outputs of read controller, and Multi-Port Output Circuits, which share some outputs of computing cores. According to the test results of original FRTDS and new FRTDS, it was found that the solution proposed in this paper had a shorter ideal simulation time and a higher parallel computing capability, which was very suitable for real-time digital simulation of power systems.

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Ohkawa, Takeshi, Daichi Uetake, Takashi Yokota, and Kanemitsu Ootsu. "Component-Based FPGA Circuit Design and Verification for Robotic Systems Using JavaRock and ORB Engine - A Case Study." Applied Mechanics and Materials 433-435 (October 2013): 1849–52. http://dx.doi.org/10.4028/www.scientific.net/amm.433-435.1849.

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In order to improve flexibility and productivity of designing complex robot systems which consists of a number of sensors, actuators and processors for control, component-based design methodology is a key issue. Meanwhile, an FPGA (Field Programmable Gate Array) is a potential candidate for controlling real-time system like a robot, because it can achieve shorter response time and higher performance-power efficiency by its parallel processing of hardwired digital circuits. However, it is difficult to introduce an FPGA for robot systems because designing an FPGA requires implementation of the user application into a circuit using HDL (Hardware Description Language). In this paper, design and verification flow using a Java-to-HDL synthesizer (JavaRock) and a distributed object environment (ORB Engine) is proposed. A case study of designing an inverted pendulum robot system is described, which achieves below 10 us processing time for controlling the inverted pendulum system successfully within a small FPGA chip in battery operation.

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