Дисертації з теми "Fully Integrated Voltage Regulators"
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Tong, Tao. "Improving SoC Power Delivery With Fully Integrated Switched-Capacitor Voltage Regulators." Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:23845472.
Повний текст джерелаEngineering and Applied Sciences - Engineering Sciences
Park, Yongwan. "Fully Integrated Hybrid Voltage Regulator for Low Voltage Applications." Thesis, State University of New York at Stony Brook, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10132969.
Повний текст джерелаA novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed topology targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 10% of the output voltage) and power density. The first implementation of the proposed topology operates in a single frequency mode. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm2. This single-frequency hybrid voltage regulator is useful (due to its fast and continuous response and high power efficiency) when the output load current is relatively constant at a certain nominal value. However, the performance is degraded when the load current varies significantly beyond the nominal current since the current provided by switched-capacitor converter is constant. The second implementation of the proposed hybrid regulator topology partially alleviates this issue by employing two different frequencies depending on the load current. This design is also implemented in 45 nm technology. It is demonstrated that the power efficiency is maintained within 60% to 80% even though the load current varies by more than 100 mA. The power density remains the same (0.5 W/mm2). The simulation results of the proposed topology are highly competitive with recent work on integrated voltage regulators.
Parker, Abdul Basit. "Design Approaches for Reliable Fully Integrated Voltage Regulators of High Performance Microprocessors for Highly Autonomous Systems." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021. http://amslaurea.unibo.it/23784/.
Повний текст джерелаAbdelfattah, Moataz. "Switched-Capacitor DC-DC Converters for Near-Threshold Design." The Ohio State University, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=osu1500631539574741.
Повний текст джерелаLüders, Michael [Verfasser], Doris [Akademischer Betreuer] Schmitt-Landsiedel, Walter [Gutachter] Stechele, and Doris [Gutachter] Schmitt-Landsiedel. "A Fully-Integrated, Digitally-Enhanced Low-Dropout Voltage Regulator for Energy-Constrained Microcontroller Systems / Michael Lüders ; Gutachter: Walter Stechele, Doris Schmitt-Landsiedel ; Betreuer: Doris Schmitt-Landsiedel." München : Universitätsbibliothek der TU München, 2016. http://d-nb.info/1182536123/34.
Повний текст джерелаQuintero, Francisco Javier 1955. "Analysis of an integrated voltage regulator amplifier and design alternatives." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276753.
Повний текст джерелаZhang, Xin. "Fully Distributed Control and Its Analog IC Design For Scalable Multiphase Voltage Regulators." Diss., Virginia Tech, 2005. http://hdl.handle.net/10919/29576.
Повний текст джерелаPh. D.
Banerjee, Saptarshi. "Power Supply Rejection (PSR) Enhancement Techniques for Fully Integrated Low-Dropout (LDO) Regulators." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171553.
Повний текст джерелаI dagens värld finns det stora behov av bärbara enheter och krav på analys avregulatorer (LDO). För varje typ av enhet finns det en energibudget som fungerarsom huvudsaklig begränsning för att utforma en LDO. LDO-konstruktion syftar tillatt leverera brusfri eller lågbrusig utspänning. Detta examensarbete visar på flerakonstruktioner av utgångskondensatorfria LDO-arkitekturer för att förbättra PowerSupply Rejection (PSR). Optimering av idéer från olika litteraturkällor görs för attuppnå låg viloström och stabilitet med snabb respons med låg ingångsspänning överett brett intervall av lastström. Olika typer av konstruktioner schemanivå för precisa LDO-specifikationer, mestadelsintegrerade med de viktigaste komponenter såsom felförstärkare (Error Amplifier,EA) och passtransistor, återkopplingsmotstånd och relativt små utgångskonden-satorer, har studerats. Buffertdämpningstekniker som kan förbättra PSR har ocksåinkluderats. Konstruktion av LDO:er på komponentnivå och man utformar pass-enheten och dess kompromisser diskuteras också. Implementering av några olikatekniker för PSR-förbättring illustreras med schema. En studie av utförda teknikerenligt specifikationerna med jämförande resultat ingår också. Resultat är en LDO som har simulerats i Cadence Spectre i en CMOS FinFETprocess med en matningsspänning på 0,95 V, en belastningsström på 50 mA - 75mA, en utspänning på 0,75 V och med en liten utgångskondensator på 200 pF. PSRpå−25 dB vid 100 MHz har uppnåtts medan strömförbrukningen vid belastningenär 245μA, samtidigt som kraven på marginal för förstärkning på 47 dB och fas 63°har uppnåtts. Ett litet spänningsfall på 36,6 mV för stigande signal och−15,99 mV för fallande signal under en förändring från 100 μA till 75 mA på 10 ns harobserverats.
ISY
Garcha, Preetinder (Preetinder Kaur). "Fully integrated ultra low voltage cold start system for thermal energy harvesting . ." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/105579.
Повний текст джерелаThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 93-96).
Wireless sensor networks used in various monitoring and sensing applications rely on energy harvesting for battery-less operation, as it minimizes the need for human intervention, and offers long term monitoring solutions. Typical energy harvesters use high efficiency boost converters, which are able to step-up voltages from as low as 10 mV. However, they often need > 200 mV in order to start up initially. Current solutions for achieving a low voltage start up require the use of bulky off-chip transformers, leading to undesired area overhead. This research work presents proof-of-concept for a fully integrated start-up system, which can cold-start from < 50 mV using on-chip magnetics, and also be used as an energy harvesting charger for ultra low power applications. The use of lossy on-chip transformers in a Meissner Oscillator compared to high-quality off-chip transformers pose new design and optimization challenges. Hence, we have derived intuitive analytical expressions that are well-suited for use with the on-chip magnetics, and used them to co-optimize the oscillator components. An optimized depletion mode MOS transistor was fabricated and tested with an off-chip transformer, to exhibit oscillations from <3 mV DC input voltage. An optimized on-chip transformer, 36x smaller in area than the off-chip transformers, is currently awaiting layout and fabrication. A switched capacitor DC-DC circuit has also been designed, which can rectify and boost up the oscillator's output voltage to 1.2 V, to have a complete start-up system for energy harvesting.
by Preetinder Garcha.
S.M.
Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.
Повний текст джерелаLow, Aichen. "A floating-gate low dropout voltage regulator." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/14886.
Повний текст джерелаKim, Wonyoung. "Reducing Power Loss, Cost and Complexity of SoC Power Delivery Using Integrated 3-Level Voltage Regulators." Thesis, Harvard University, 2012. http://dissertations.umi.com/gsas.harvard:10721.
Повний текст джерелаEngineering and Applied Sciences
Bunch, Ryan Lee. "A Fully Monolithic 2.5 GHz LC Voltage Controlled Oscillator in 0.35 um CMOS Technology." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/32287.
Повний текст джерелаMaster of Science
Hardikar, Shyam. "Development of MOS-controlled devices and fully implanted processes for power and high voltage integrated microelectronics." Thesis, De Montfort University, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.271930.
Повний текст джерелаBhavnagarwala, Azeez Jenúddin. "Voltage scaling constraints for static CMOS logic and memory cirucits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15401.
Повний текст джерелаWipf, Christian [Verfasser], Dietmar [Akademischer Betreuer] Kissinger, Dietmar [Gutachter] Kissinger, Friedel [Gutachter] Gerfers, and Peter [Gutachter] Weger. "Fully integrated BiCMOS high-voltage driver circuits for on-chip RF-MEMS switch matrices / Christian Wipf ; Gutachter: Dietmar Kissinger, Friedel Gerfers, Peter Weger ; Betreuer: Dietmar Kissinger." Berlin : Technische Universität Berlin, 2019. http://d-nb.info/1202071422/34.
Повний текст джерелаMansano, Andre Luis Rodrigues. "Reguladores integrados charge-pump multiplicadores de tensão para aplicações de alta corrente." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259226.
Повний текст джерелаDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Neste trabalho de Mestrado, foi projetado um conversor DC/DC charge-pump (CP) duplicador de tensão para corrente de carga máxima de 20mA, e que necessita de circuitos de controle para o apropriado acionamento das chaves, regulação de tensão e proteção do estágio duplicador de tensão. O sistema de controle projetado é composto por um circuito de regulação linear (CRL), um regulador Skip, um limitador de corrente (LC) e um circuito de bootstrapping (BOOT) que auxilia o acionamento do estágio duplicador. CP corresponde ao estágio de potência do sistema que faz interface direta com a carga, sendo sua tensão de entrada (PVIN) nominal no valor de 1,5V. O trabalho objetiva obter um conversor DC/DC funcional (demonstrado por resultados de Silício) atingindo resultados experimentais com o menor desvio possível comparados aos valores simulados durante o projeto. A tensão simulada de saída (VOUT), a vazio (sem carga), é 3V. Para carga máxima DC (20mA), o valor de VOUT simulado é de 2,4V. O circuito BOOT gera uma tensão na faixa de 4,5V - 5V, para uma carga DC de 1mA. A corrente limitada pelo bloco LC no circuito duplicador é 30mA. O CLR gera uma tensão inversamente proporcional a VOUT, tendo seus limites mínimo e máximo de 1,3V e 5,2V, respectivamente. Todo o sistema foi integrado no processo de fabricação AMS 0.35um HV, exceto os capacitores do estágio duplicador e do circuito de bootstrapping que são externos. Os resultados experimentais mostram desvio (comparados com simulação) de -12,5% em VOUT @ 20mA DC e -0,13% sem carga, -6% à saída de BOOT @ 1mA DC, +23% CLR mínimo, -3,85% em CRL máximo e +10% na corrente limitada. Durante o desenvolvimento deste trabalho, o Circuito de Regulação Linear (CRL) foi publicado no SBCCI 2009 apresentando sua rápida resposta à transientes de carga, o que é sua grande vantagem comparado a circuitos anteriormente propostos
Abstract: In this work, a DC/DC charge-pump voltage-doubler converter, for maximum load current of 20mA, was designed and fabricated. The Charge Pump (CP) needs control circuits for properly switching, voltage regulation and protection of voltage doubler stage. The control system designed comprises a linear regulation circuit (CRL), a Skip mode regulator, current limitation circuit (LC) and a bootstrapping circuit (BOOT), which provides the appropriate voltage to turn on CP power transistors. The voltage doubler is the power stage that interfaces directly to the load and its nominal input voltage PVIN is 1.5V. The objective of this work is to guarantee that the proposed DC/DC converter works properly (proved by Silicon results) and to achieve experimental results with the least deviation possible compared to simulation. The nominal output voltage (VOUT) with no load is 3V. For maximum DC load (20mA), simulated VOUT is 2.4V. BOOT circuit provides voltage within 4.5V - 5V for DC current load of 1mA. The LC limits the drawn current through the voltage-doubler at 30mA. The CRL provides a control voltage inversely proportional to VOUT and its minimum and maximum are 1.3V and 5.2V respectively. The whole system has been integrated in AMS 0.35um HV except the capacitors of CP and BOOT circuits. The experimental results show deviation (comparing to simulation) of -12,5% on VOUT @ 20mA DC and -0,13% @ no load , -6% on BOOT output @ 1mA DC, +23% CLR minimum, -3,85% CRL maximum and +10% on LC circuit. During the development of this work, the CRL circuit has been published in the SBCCI 2009 conference to present its fast-response to stringent load transient which is the biggest CRL advantage compared to previously proposed circuits
Mestrado
Mestre em Engenharia Elétrica
Zampronho, Neto Fernando. "Analise, projeto e layout de uma topologia de circuito regulador de tensão para aplicação em microprocessadores." [s.n.], 2009. http://repositorio.unicamp.br/jspui/handle/REPOSIP/259236.
Повний текст джерелаDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: Este trabalho tem como objetivo o estudo de uma arquitetura de regulador de tensão do tipo multi-fase para alimentação de microprocessadores, os quais demandam pequena variação em sua tensão, mesmo face aos seus agressivos transitórios de corrente. O estudo engloba a análise, que descreve as vantagens e desvantagens de topologias de reguladores chaveados, o projeto, a simulação, a fabricação e a caracterização experimental do regulador. Na etapa de projeto, uma nova abordagem no dimensionamento do filtro externo LC é apresentada, considerando-se seus respectivos elementos parasitas, a partir da introdução do parâmetro .fator de não idealidade., ou n, que é compreendido no intervalo [0, 1]. Quanto mais n se aproxima da unidade, menores serão os elementos parasitas do filtro, facilitando a escolha dos capacitores e indutores no mercado. Adicionalmente, é proposta uma técnica de projeto do compensador em freqüência, aplicada em topologias realimentadas por tensão. Esta consiste na soma de sua tensão de saída com a diferença de potencial entre dois de seus nós internos, que ocorre apenas durante o transitório de carga, reduzindo o tempo de resposta do regulador. Simulações mostraram uma queda de mais de 25% na ondulação da tensão de carga utilizando esta técnica, em comparação com a solução convencional. O processo, simulador e modelos utilizados neste trabalho são, respectivamente, o AMS H35, PSPICE e Bsim3v3. O layout do regulador foi feito via Mentor Graphics e possui área efetiva de 0,444mm2. A fabricação na foundry AMS foi viabilizada pelo programa multi-usuário da FAPESP. A caracterização experimental compara o tempo de resposta do regulador nas mesmas condições da etapa de simulação. Resultados experimentais indicaram uma redução de 96,1% na ondulação da tensão de carga durante seu transitório de corrente utilizando a técnica proposta, em comparação a solução convencional, validando a nova técnica de projeto do compensador em freqüência. O presente trabalho é concluído enfatizando-se os objetivos alcançados e principais resultados experimentais obtidos, dificuldades de projeto e limitações da arquitetura do regulador chaveado estudada
Abstract: This work aims to study the topology of multi-phase voltage regulators applied to microprocessors, where only tiny variations in the supply voltage are allowed, even when facing aggressive current transients. This study consists in the analysis, which describes the advantages and disadvantages of switched voltage regulator topologies, design, simulation, layout and experimental characterization of the proposed regulator. In the design phase, a new approach in sizing the external LC filter is herein described, considering their stray elements, through the introduction of the .non ideality. parameter, or n, which is valid within interval [0,1]. As more as n approaches unity, less parasitic elements the filter will have, easing the choice of the capacitors and inductors commercially available. In addition to this, a new technique applied to voltage feedback topologies is proposed, which consists in adding the output voltage of the frequency compensator to a voltage between two of its internal nodes. With such an approach, the response time of the regulator to load transients decreases. Simulation results show a reduction over 25% in the output voltage ripple using this new approach, when comparing to the traditional solution. The process, simulator and models used in this work are, respectively, AMS H35, PSPICE and Bsim 3v3. The layout of the regulator was edited through Mentor Graphics, and it has an effective area of 0.444mm2. The fabrication in foundry AMS was done by multi-user program of FAPESP. The experimental characterization compares the response time of the regulator in the same conditions of simulation phase. Experimental results indicated a 96,1% reduction in load voltage ripple during transient, when comparing the purposed technique with the traditional solution, validating the excellent performance of the regulator with the new design technique. This work is concluded by emphasizing the reached objectives and main experimental results reached, design difficulties and limitations of the switched-regulator architecture studied
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
"Wide Input Common-mode Range Fully Integrated Low-dropout Voltage Regulators." Master's thesis, 2016. http://hdl.handle.net/2286/R.I.38373.
Повний текст джерелаDissertation/Thesis
Masters Thesis Electrical Engineering 2016
Kim, Doyun. "Fully Integrated Digital Low-Drop-Out Regulator Design based on Event-Driven PI Control." Thesis, 2019. https://doi.org/10.7916/d8-kfrq-qa27.
Повний текст джерелаGovindan, Srinivasan. "Fast Methods for Modelling and Simulation of Fully Integrated Voltage Regulators in Microprocessors." Thesis, 2022. https://etd.iisc.ac.in/handle/2005/5982.
Повний текст джерелаIntel Technology India Pvt Ltd
McCue, Benjamin Matthew. "A Fully Integrated High-Temperature, High-Voltage, BCD-on-SOI Voltage Regulator." 2010. http://trace.tennessee.edu/utk_gradthes/646.
Повний текст джерела"Time-Domain/Digital Frequency Synchronized Hysteresis Based Fully Integrated Voltage Regulator." Doctoral diss., 2019. http://hdl.handle.net/2286/R.I.55562.
Повний текст джерелаDissertation/Thesis
Doctoral Dissertation Electrical Engineering 2019
Fletcher, Jay Brady. "Control and implementation of integrated voltage regulators." Thesis, 2013. http://hdl.handle.net/2152/23345.
Повний текст джерелаtext
Aklimi, Eyal. "Magnetics and GaN for Integrated CMOS Voltage Regulators." Thesis, 2016. https://doi.org/10.7916/D87H1JQS.
Повний текст джерелаSturcken, Noah. "Integrated Voltage Regulators with Thin-Film Magnetic Power Inductors." Thesis, 2013. https://doi.org/10.7916/D8JW8N36.
Повний текст джерелаJHAO, SYUAN-NENG, and 趙炫能. "Integrated Power Supply with Linear and Switching Voltage Regulators." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/tmtv5d.
Повний текст джерела南臺科技大學
電機工程系
104
The thesis proposed a hybrid power system with combined advantageous features of switching power supply and linear power amplifier. The switching power supply would provide the primary output voltage and power to the load, while the linear power amplifier would act as a correcting amplifying device to compensate for power ripple as a way to stabilize voltage output. Combination of these two components not only reduced the output voltage ripple but improved the overall efficiency simultaneously, as the power output level could be higher, in comparison with the low efficiency of a system with only the linear power amplifier. The thesis would explore two practical approaches of using alternating and direct current power supply. For alternating power supply, it combined the linear power amplifier and the full-bridge inverter to produce alternating voltage which had adjustable output frequency and voltage. The direct current power supply would use a linear power amplifier and a phase shift full-bridge converter to produce wide-ranged and low-rippled direct current which had adjustable output voltage. And, two prototypes of electric circuit with the maximum output power of 500W to produce final output of hybrid alternating power at 70 to 110 with the maximum frequency of 1 and a hybrid direct power at 5 to 50 would be modeled to prove the control method as practicable.
Cheng, Gwong-Wai, and 鄭光偉. "A 5.25GHz Fully Integrated CMOS Quadrature Voltage-Controlled Oscillator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/70224069224159570959.
Повний текст джерела國立交通大學
電信工程系
90
A 5.25GHz fully integrated CMOS quadrature Voltage-Controlled Oscillator for IEEE 802.11a direct conversion receiver is presented. The quadrature VCO is fabricated by TSMC 0.25um CMOS process using accumulation mode MOS varactor to upgrade tuning range and lower phase noise. The architecture of VCO adopts both NMOS and PMOS cross-coupled pair to enhance negative conductance, and connects two differential LC-tank VCOs to generate four 0,90,180,270 degrees signals The measured result attain a oscillation frequency sweep from 5.260GHz ~ 5.525GHz, tuning range 265MHz, phase noise of -102.83dBc/Hz at 1MHz offset and 17.5mW power consumption at 2.5V DC supply.
Hong, Yu-Bin, and 洪育彬. "A Fully Integrated DC-DC Converter for Dynamic Voltage Scaling." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/e7p3nq.
Повний текст джерела國立中興大學
電機工程學系所
99
In this era of technology explosion, the idea of designing electronic products are tending to compact size much more than before, particularly the biomedical products, such as pacemakers, sensors etc., which products emphasize the size and energy consumption. The capacitors and inductors in the voltage converters which we used before were both external components, and it could occupy a large amount of volume in this way. In order to overcome this problem, if we can integrate those passive components on a single chip, then it can greatly reduce the size of the converter. The GIPD (tMt Glass Substrate Integrated Passive Device Process) can be used on a glass board to complete the production of the inductor and capacitor. The control circuit can be made on the Si board (CMOS18),and then use bump to connect two boards and utilize 3D technology to complete the micro-integration of the initiative control circuit and the passive components. The size of capacitors and inductors must be reduced to nano-scale so that they can be integrated in one chip, but it also brought some challenges. The voltage control Pulse Width Modulation (PWM) used in this thesis is to control circuit with fast transient response. And the converter can be used for dynamic voltage scaling (DVS) applications that it can change with the different voltage requirements from the loading and increase the life of the batteries and the whole system effectively. The circuit architecture is composed of error amplifier, comparator, triangle wave generator, non-overlap, digital-to-analog converter, buffer, power MOS. First, the feedback voltage and Vref are sent into the error amplifier for comparison. Then, the output voltage will be compared with a triangle wave to get a PWM control signal. To avoid energy consumption that caused by a large amount of current flowing from PMOS to NMOS while switch frequently, use the non-overlap circuit to reduce the leakage current directly from the battery to the ground and increase efficiency. The circuit uses TSMC_0.18um & GIPD process, which are combined with 3D technology. The voltage conversion is from 1.8V down to 1.3 ~ 0.6V. The maximum voltage conversion efficiency is 78.5% and the maximum load current is 150mA.
Ramachandran, Vishwa. "Analysis of total dose effects in a low-dropout voltage regulator." Diss., 2006. http://etd.library.vanderbilt.edu/ETD-db/available/etd-12192006-190448/.
Повний текст джерелаLiang, Yu-An, and 梁佑安. "The Design of Fully-Integrated CMOS Multiple Low Dropout Regulators for Implantable Biomedical SoCs." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36550372845105714735.
Повний текст джерела國立交通大學
電子研究所
100
For epilepsy detection and stimulation application, the medical device should be fully implantable. In order to minimize the area consumption and eliminate the negative effect of parasitic inductance, the LDO regulators should be fully-integrated without any external component. Moreover, in an implantable medical SoC powered by inductive link power supply, a single LDO is difficult to satisfy different performance requirements of analog, digital, and reference circuits. Therefore, a topology of LDO is designed, fabricated, and tested to realize three fully-integrated LDOs with 2V to 1.8V output voltages for analog, digital, and reference circuits. The maximum driving current capabilities are 5mA, 20mA and 1.5mA, respectively. By connecting the input voltage of the LDOs to a full-wave CMOS active rectifier which is operated at 13.56MHz and powered by near-field coils with an inductive link structure. The measured ripple voltages of analog output, digital output, and reference output are 3mVp-p, 6.2mVp-p, and 0.7mVp-p, respectively.
黃俊諺. "A Fully Integrated CMOS LC-VCO with Low Voltage and Low Power." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92130496642238310362.
Повний текст джерела國立交通大學
電信工程系所
96
Abstract As the advancement of wireless communication system growing rapidly. Development of radio frequency (RF) integrated circuits in low cost, high performance and low power consumption is more and more imminently. In the past, the RF front-end circuits are made by SiGe BiCMOS process technologies due to its high performance in high frequency. However, with the standard CMOS process technology getting proficient, RF front-end circuits made by CMOS process are more and more popular. As far as the actual applications are concerned, the RFICs are power-hungry devices which cause the battery life time could not be extended effectively. The problem of power consumption further restricts the applications in wireless electronic devices, especially in the demands of light, thin, short and small devices. Therefore, development of RFIC more efficient in cost and low power consumption is an emergent issue to solve. This thesis focuses on the design of low supply voltage and low power consumption and maintains comparable level of phase noise simultaneously. Using a conventional NMOS cross-coupled LC-VCO architecture which has the least stages stacked in vertical could be reduced the supply voltage. By adding a proposed NMOS pair which paralleled the LC-tank, the parasitic capacitances Cgs, Cgd of the proposed NMOS pair generate an additional negative conductance, as a result, the phase noise can be degrade effectively in low power, low supply voltage operation level. Besides, the bodies of proposed NMOS pair are biased, which generate an opposite voltage drop as compared with varactors. As a result, the common mode noise is reduced. Eventually, the goals of low power consumption and low supply voltage can be achieve due to most of the supply voltage feed the cross-couple NMOS and the added NMOS pair take no voltage drop. The proposed low voltage, low power LC-VCO is implemented by TSMC 0.18-μm 1P6M CMOS process. With only 0.51 V bias, the power consumption of the proposed LC-VCO is 1 mW. The phase noise is -112.24 dBc/Hz from 1 MHz offset frequency at 3.3GHz and the chip size of 0.61 (μm) × 0.76 (μm).
"Design and implementation of fully integrated low-voltage low-noise CMOS VCO." 2002. http://library.cuhk.edu.hk/record=b5891102.
Повний текст джерелаThesis (M.Phil.)--Chinese University of Hong Kong, 2002.
Includes bibliographical references (leaves 95-100).
Abstracts in English and Chinese.
Abstract --- p.I
Acknowledgement --- p.III
Table of Contents --- p.IV
Chapter Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Objective --- p.6
Chapter Chapter 2 --- Theory of Oscillators --- p.7
Chapter 2.1 --- Oscillator Design --- p.7
Chapter 2.1.1 --- Loop-Gain Method --- p.7
Chapter 2.1.2 --- Negative Resistance-Conductance Method --- p.8
Chapter 2.1.3 --- Crossed-Coupled Oscillator --- p.10
Chapter Chapter 3 --- Noise Analysis --- p.15
Chapter 3.1 --- Origin of Noise Sources --- p.16
Chapter 3.1.1 --- Flicker Noise --- p.16
Chapter 3.1.2 --- Thermal Noise --- p.17
Chapter 3.1.3 --- Noise Model of Varactor --- p.18
Chapter 3.1.4 --- Noise Model of Spiral Inductor --- p.19
Chapter 3.2 --- Derivation of Resonator --- p.19
Chapter 3.3 --- Phase Noise Model --- p.22
Chapter 3.3.1 --- Leeson's Model --- p.23
Chapter 3.3.2 --- Phase Noise Model defined by J. Cranincks and M Steyaert --- p.24
Chapter 3.3.3 --- Non-linear Analysis of Phase Noise --- p.26
Chapter 3.3.4 --- Flicker-Noise Upconversion Mechanism --- p.31
Chapter 3.4 --- Phase Noise Reduction Techniques --- p.33
Chapter 3.4.1 --- Conventional Tank Circuit Structure --- p.33
Chapter 3.4.2 --- Enhanced Q tank circuit Structure --- p.35
Chapter 3.4.3 --- Tank Circuit with parasitics --- p.37
Chapter 3.4.4 --- Reduction of Up-converted Noise --- p.39
Chapter Chapter 4 --- CMOS Technology and Device Modeling --- p.42
Chapter 4.1 --- Device Modeling --- p.42
Chapter 4.1.1 --- FET model --- p.42
Chapter 4.1.2 --- Layout of Interdigitated FET --- p.46
Chapter 4.1.3 --- Planar Inductor --- p.48
Chapter 4.1.4 --- Circuit Model of Planar Inductor --- p.50
Chapter 4.1.5 --- Inductor Layout Consideration --- p.54
Chapter 4.1.6 --- CMOS RF Varactor --- p.55
Chapter 4.1.7 --- Parasitics of PMOS-type varactor --- p.57
Chapter Chapter 5 --- Design of Integrated CMOS VCOs --- p.59
Chapter 5.1 --- 1.5GHz CMOS VCO Design --- p.59
Chapter 5.1.1 --- Equivalent circuit model of differential LC VCO --- p.59
Chapter 5.1.2 --- Reference Oscillator Circuit --- p.61
Chapter 5.1.3 --- Proposed Oscillator Circuit --- p.62
Chapter 5.1.4 --- Output buffer --- p.63
Chapter 5.1.5 --- Biasing Circuitry --- p.64
Chapter 5.2 --- Spiral Inductor Design --- p.65
Chapter 5.3 --- Determination of W/L ratio of FET --- p.67
Chapter 5.4 --- Varactor Design --- p.68
Chapter 5.5 --- Layout (Cadence) --- p.69
Chapter 5.6 --- Circuit Simulation (SpectreRF) --- p.74
Chapter Chapter 6 --- Experimental Results and Discussion --- p.76
Chapter 6.1 --- Measurement Setup --- p.76
Chapter 6.2 --- Measurement results: Reference Oscillator Circuit --- p.81
Chapter 6.2.1 --- Output Spectrum --- p.81
Chapter 6.2.2 --- Phase Noise Performance --- p.82
Chapter 6.2.3 --- Tuning Characteristic --- p.83
Chapter 6.2.4 --- Microphotograph --- p.84
Chapter 6.3 --- Measurement results: Proposed Oscillator Circuit --- p.85
Chapter 6.3.1 --- Output Spectrum --- p.85
Chapter 6.3.2 --- Phase Noise Performance --- p.86
Chapter 6.3.3 --- Tuning Characteristic --- p.87
Chapter 6.3.4 --- Microphotograph --- p.88
Chapter 6.4 --- Comparison of Measured Results --- p.89
Chapter 6.4.1 --- Phase Noise Performance --- p.89
Chapter 6.4.2 --- Tuning Characteristic --- p.90
Chapter Chapter 7 --- Conclusion and Future Work --- p.93
Chapter 7.1 --- Conclusion --- p.93
Chapter 7.2 --- Future Work --- p.94
References --- p.95
Author's Publication --- p.100
Appendix A --- p.101
Appendix B --- p.104
Appendix C --- p.106
Jhe-JiaJhang and 張哲嘉. "Fully-Integrated Boost DC-DC Converter with Low-Startup Voltage for Thermoelectric Harvester." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/2z847v.
Повний текст джерела國立成功大學
電機工程學系
106
The most critical issue of using energy harvesters is their low output voltage, which makes it difficult to power up traditional electronic circuits. Therefore, this thesis proposes a fully-integrated inductor-based dc-dc boost converter with low startup voltage for thermoelectric harvester. In the initial state, low-voltage ring oscillator built by low supply voltage logic, charge pump and voltage-triggered pulse generator are used to charge the output capacitor and increase the output voltage (VOUT). When VOUT is high enough, the system will enter the open-loop state. When VOUT is increased to exceed another predefined voltage, the system will operate in the closed-loop state and VOUT will be regulated at 1.8V finally. It is worth mentioning that the startup technique in the proposed chip does not need to use any post-fabrication process, secondary energy source, or extra off-chip components. The proposed chip was fabricated by TSMC 0.18μm 1P6M mixed-signal standard CMOS process, and chip area is 720×735μm2. According to measurement results, the minimal startup voltage of the converter is as low as 82mV, and VOUT can be regulated between 1 V and 1.8 V. Moreover, the measured peak efficiency achieves 78.55%.
Bull, Nora Dianne. "Design and Implementation of a High Temperature Fully-Integrated BCD-on-SOI Under Voltage Lock Out Circuit." 2009. http://trace.tennessee.edu/utk_gradthes/511.
Повний текст джерелаHsieh, Hsien-Cheng, and 謝先成. "The Design of Low Power Voltage Controlled Oscillator and Fully Integrated 2.4GHz CMOS Integer-N Frequency Synthesizer." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/35062195162625409055.
Повний текст джерела國立交通大學
電信工程系
91
Through this thesis, we demonstrated a fully integrated frequency synthesizer for direct conversion receiver. The working frequency is at 2.45GHz. We begin from the design of voltage controlled oscillator (VCO), devising it at the purpose of low power consumption, and established a VCO consumes less than 1mW (It consumes only 53μA when biased at 1.5V VDD).In the design of frequency divider part, we adopt integer-N topology which provides a less power consumption for low current use consideration. The measurement results are listed as following: the oscillation frequency is tunable between 2351~2517MHz, locking time is approximately 25μs, phase noise is -88.4dBc/Hz@1MHz offset, spurious tones are less than carrier 14dB; the power consumption is 58.625mW using a 2.5V power supply.
"Development of high-performance low-dropout regulators for SoC applications." 2010. http://library.cuhk.edu.hk/record=b5894389.
Повний текст джерела"July 2010."
Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references.
Abstracts in English and Chinese.
Acknowledgments
Table of Content
List of Figures
List of Tables
List of Publications
Chapter Chapter 1 - --- Background of LDO Research
Chapter 1.1 --- Structure of a LDO --- p.1-1
Chapter 1.2 --- Principle of Operation of LDO --- p.1-2
Chapter 1.3 --- Steady-State Specification of LDO --- p.1-3
Chapter 1.4 --- High-Frequency Specification of LDO --- p.1-3
Chapter 1.5 --- Dynamic Specification of LDO --- p.1-4
Chapter 1.6 --- An Advanced LDO Structure --- p.1-4
Chapter 1.7 --- Contribution and Outline of the Thesis --- p.1-5
References --- p.1-6
Chapter Chapter 2 - --- PSRR Analysis
Chapter 2.1 --- Modeling of the PSRR of LDO --- p.2-3
Chapter 2.2 --- Analysis of LDO Circuit Using Proposed Modeling --- p.2-6
Chapter 2.3 --- Conclusion of Chapter --- p.2-12
References --- p.2-13
Chapter Chapter 3- --- An Output-Capacitorless LDO with Direct Voltage-Spike Detection
Chapter 3.1 --- Analysis of Output-Capacitorless LDO --- p.3-5
Chapter 3.2 --- LDO with Proposed Voltage-Spike Detection Circuit --- p.3-7
Chapter 3.3 --- Experimental Results --- p.3-15
Chapter 3.4 --- Conclusion of Chapter --- p.3-21
References --- p.3-22
Chapter Chapter 4 - --- A LDO with Impedance Adjustment and Loop-Gain Boosting Technique
Chapter 4.1 --- Proposed LDO --- p.4-3
Chapter 4.2 --- Experimental Results --- p.4-7
Chapter 4.3 --- Comparison --- p.4-11
Chapter 4.4 --- Conclusion of Chapter --- p.4-12
Reference --- p.4-13
Chapter Chapter 5 - --- Conclusion and Future Work
Kim, Sung Justin. "Integrated and Distributed Digital Low-Drop-Out Regulators with Event-Driven Controls and Side-Channel Attack Resistance." Thesis, 2021. https://doi.org/10.7916/d8-mbs2-4z84.
Повний текст джерела"Fast transient LDO using digital detection." 2012. http://library.cuhk.edu.hk/record=b5549104.
Повний текст джерелаLDO的負載瞬間變化取決於功率金氧半場效電晶體的大小、偏置電流和誤差放大器的增益。檢測輸出電壓,並使用大電容和電阻通過電容耦合,增加偏置電流是一個簡單的方法來改善負載瞬間變化。然而,電阻電容佔據較大的芯片面積。
權衡功耗和芯片尺寸,本論文中提出用數字檢測電路取代用於瞬態耦合的大電容和電阻。所提出的電路是讓功率金氧半場效電晶體的栅極電容電流增加充電或放電,以提高LDO的負載瞬間響應速度。產生這種電流通過檢測內部的變化,並產生一個電壓脈衝控制迴轉電流,然後通過使用一組數字電路去改變充電或放電的電量。
擬議的設計已在UMC0.18微米 CMOS制程技術實現。LDO的輸入電壓為0.9伏至1.3伏和穩壓0.7伏。最大輸出電流為50豪安。經過測量,負載瞬間變化得到改善。負載瞬間的響應時間可以從75微秒(傳統)減少到75納秒。
Power-management IC is widely used in portable electronic applications. Different supply voltage levels are required in the same chip. Due to the size, speed and power requirements, low-dropout regulator (LDO) is generally adopted for applications which need fast transient response, low noise and high accuracy.
Transient response of a LDO is limited by the size of power MOSFET, biasing current and gain of error amplifier. Detecting the output voltage and using large RC components for capacitive coupling to increase the biasing current is a straightforward method to improve the transient response. However, this requires a large chip size for the RC components.
By considering power consumption and size, digital detection circuit is proposed to replace the large capacitors and resistors used for transient coupling. The proposed circuit is to increase the charging or discharging current to the gate of the power MOSFET to increase the transient speed of LDO. This current is generated by detecting the internal changes and generating a voltage pulse to control the slewing current by using a set of digital circuit.
The proposed design has been realized in UMC 0.18μm CMOS technology. The input voltage of the LDO is 0.9 to 1.3V and the regulated voltage is 0.7V. The maximum output current is 50mA. From the measurement, the transient response is improved. The response time due to load transient changes can be reduced from 75s (conventional) to 75ns.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Kwong, Ka Yee.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references.
Abstracts also in Chinese.
Abstract
Acknowledgments
Table of Content
List of Figures
List of Tables
Chapter Chapter 1 --- LDO regulator research background
Introduction
Chapter Section 1.1 --- Generic LDO regulator structure
Chapter Section 1.2 --- Principle of LDO regulator operation
Chapter Section 1.3 --- Specifications
Chapter References
Chapter Chapter 2 --- Review of state-of-the-art transient-improvement techniques for LDO regulators
Introduction
Chapter Section 2.1 --- Slew rate improvement at power transistor gate
Chapter Section 2.2 --- Frequency compensation
Chapter Section 2.3 --- Short summary
References
Chapter Chapter 3 --- A proposed output-capacitorless LDO regulator with digital voltage spike detection
Chapter Introduction
Chapter Section 3.1 --- LDO regulator core structure
Chapter Section 3.2 --- Digital switches based LDO regulator
Chapter Section 3.3 --- LDO regulator with proposed digital voltage spike detection circuit
Chapter Section 3.4 --- Simulation result
Chapter Section 3.5 --- Short summary
References
Chapter Chapter 4 --- Measurement results
Introduction
Chapter Chapter 5 --- Conclusion and Future Work
Gatavi, Ehsan. "Voltage regulation and reactive power compensation to improve low voltage ride-through capability for doubly fed induction generator-based wind turbine." Thesis, 2019. http://hdl.handle.net/1959.7/uws:54766.
Повний текст джерелаChang, Pei-Ke, and 張培格. "The Integrated Circuit Design of Reconfigurable Low-Power High-Performance Low-Drop-Out Voltage Regulators for Biomedical And IoT Applications." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/avs6c4.
Повний текст джерела國立臺灣科技大學
電機工程系
104
Two reconfigurable power-efficient high-performance output-capacitor-less (OCL)linear voltage regulators are proposed in this thesis. These low-drop-out (LDO) voltage regulators are designed for wearable devices in biomedical or internet of things (IoT) applications. Both regulators employ floating-gate programming technologies to achieve reconfigurability and low power consumption. These regulators adopt a floating-gate nMOS pass transistor, an adaptively biased error amplifier, and capacitive circuits for voltage reference generation and for feedback sensing. With a floating-gate nMOS pass transistor, the proposed regulators exhibit superior line regulation to conventional regulators that usually employ a pMOS pass transistor. The error amplifier adopts a class-AB input differential pair and an adaptively biased regulated cascode topology to improve transient response under the stringent constraint of low quiescent current consumption. The reference voltage is implemented by programming charges on capacitors without employing a bandgap circuit. As a result, the power consumption for bandgap reference circuit can be saved. The measured output voltage temperature coefficient can be lower than 45 ppm/◦C. By programming charges in floating-gate transistors, the regulated output voltage can be adjusted in continuum depending on the applications. The proposed first regulator is designed for low-power analog sensing front-end circuits. The designed output voltage ranges from 1.2V to 2.5V and the designed maximum load current is 1mA with output voltage drop less than 0.1%. Since the load current does not change dramatically, the design focus is on line regulation rather on load regulation. A prototype chip is designed and fabricated in a 0.35um CMOS process to demonstrate the reconfigurability and to validate the performance. With programmable quiescent current levels less than 1 A, the current efficiency is higher than 99.9%. From measurements, the line regulation is 0.17mV/V or 75dB. The designed output-capacitor-less regulator remains stable with maximum output load capacitance upto 1nF under the zero load condition. The second regulator is designed for low-power digital circuits. To cope with the dramatic changes of the load current and reduced output voltage, the second regulator improves the required minimum supply voltage of the error amplifier and employs a load transient enhancement circuit that consumes no static power. To prevent huge current consumption during the circuit start-up phase, a power-on-reset (POR) circuit is designed and verified. A folded-class-AB differential pair circuit is employed to reduce the required error amplifier minimum supply voltage to 0.9V. The maximum load current is designed to be 2mA. With programmable quiescent current levels less than 1 A, the current efficiency is higher than 99.95%. From simulations, the line regulation is 0.056mV/V or
"Development of low-power high-accuracy ultrafast-transient-response low-dropout regulators for battery-powered applications." 2013. http://library.cuhk.edu.hk/record=b5884387.
Повний текст джерелаThesis (Ph.D.)--Chinese University of Hong Kong, 2013.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Santos, Ângelo Emanuel Neves dos. "Design and simulation of a smart bottle with fill-level sensing based on oxide TFT technology." Master's thesis, 2016. http://hdl.handle.net/10362/19593.
Повний текст джерела