Добірка наукової літератури з теми "Floating Gate Memory"
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Статті в журналах з теми "Floating Gate Memory"
Rajput, Renu, and Rakesh Vaid. "Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review." Facta universitatis - series: Electronics and Energetics 33, no. 2 (2020): 155–67. http://dx.doi.org/10.2298/fuee2002155r.
Повний текст джерелаLi, Bei, Jianlin Liu, G. F. Liu, and J. A. Yarmoff. "Ge∕Si heteronanocrystal floating gate memory." Applied Physics Letters 91, no. 13 (September 24, 2007): 132107. http://dx.doi.org/10.1063/1.2793687.
Повний текст джерелаAl-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (September 25, 2019): 643. http://dx.doi.org/10.3390/mi10100643.
Повний текст джерелаNoor, Fatimah Arofiati, Gilang Mardian Kartiwa, and Muhammad Amin Sulthoni. "Studi Elektrostatik Elektroda Runcing dan Aplikasinya pada Perangkat Floating Gate Memory." POSITRON 11, no. 1 (October 15, 2021): 1. http://dx.doi.org/10.26418/positron.v11i1.44881.
Повний текст джерелаLingalugari, Murali, Evan Heller, Barath Parthasarathy, John Chandy, and Faquir Jain. "Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing." International Journal of High Speed Electronics and Systems 27, no. 01n02 (March 2018): 1840006. http://dx.doi.org/10.1142/s0129156418400062.
Повний текст джерелаZhang, Pengfei, Dong Li, Mingyuan Chen, Qijun Zong, Jun Shen, Dongyun Wan, Jingtao Zhu, and Zengxing Zhang. "Floating-gate controlled programmable non-volatile black phosphorus PNP junction memory." Nanoscale 10, no. 7 (2018): 3148–52. http://dx.doi.org/10.1039/c7nr08515j.
Повний текст джерелаLee, Boong-Joo. "Operating characteristics of Floating Gate Organic Memory." Journal of the Korea Academia-Industrial cooperation Society 15, no. 8 (August 31, 2014): 5213–18. http://dx.doi.org/10.5762/kais.2014.15.8.5213.
Повний текст джерелаPark, Byoungjun, Kyoungah Cho, Sungsu Kim, and Sangsig Kim. "Transparent nano-floating gate memory on glass." Nanotechnology 21, no. 33 (July 26, 2010): 335201. http://dx.doi.org/10.1088/0957-4484/21/33/335201.
Повний текст джерелаCellere, G., P. Pellati, A. Chimenton, J. Wyss, A. Modelli, L. Larcher, and A. Paccagnella. "Radiation effects on floating-gate memory cells." IEEE Transactions on Nuclear Science 48, no. 6 (2001): 2222–28. http://dx.doi.org/10.1109/23.983199.
Повний текст джерелаLee, Jang-Sik. "Review paper: Nano-floating gate memory devices." Electronic Materials Letters 7, no. 3 (September 2011): 175–83. http://dx.doi.org/10.1007/s13391-011-0901-5.
Повний текст джерелаДисертації з теми "Floating Gate Memory"
Ostraat, Michele L. Atwater Harry Albert. "Synthesis and characterization of aerosol silicon nanoparticle nonvolatile floating gate memory devices /." Diss., Pasadena, Calif. : California Institute of Technology, 2001. http://resolver.caltech.edu/CaltechETD:etd-04072005-081230.
Повний текст джерелаFakher, Sundes Juma. "Advanced study of pentacene-based organic memory structures." Thesis, Bangor University, 2014. https://research.bangor.ac.uk/portal/en/theses/advanced-study-of-pentacenebased-organic-memory-structures(5319a571-2c4c-4f90-a26c-fa5e7da82cfb).html.
Повний текст джерелаCouto, Andre Luis do. "Caracterização de memorias analogicas implementadas com transistores MOS floating gate." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.
Повний текст джерелаDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005
Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área
Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
Marron, Dominique. "Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche." Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.
Повний текст джерелаMarzaki, Abderrezak. "Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4768.
Повний текст джерелаThe component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first electrical simulations of elementary circuits composed with this new component are presented. The performance improvement of some elementary circuits is demonstrated
Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.
Повний текст джерелаLiu, Yueran 1975. "Novel flash memory with nanocrystal floating gate." Thesis, 2006. http://hdl.handle.net/2152/2819.
Повний текст джерелаZHAO, CHUAN-ZHEN, and 趙傳珍. "Floating-gate mos transistors as analog memory devices." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/33712669387087189947.
Повний текст джерелаLee, Jong Jin Kwong Dim-Lee. "A study on the nanocrystal floating-gate nonvolatile memory." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1975/leej77040.pdf.
Повний текст джерелаLee, Jong Jin. "A study on the nanocrystal floating-gate nonvolatile memory." Thesis, 2005. http://hdl.handle.net/2152/1975.
Повний текст джерелаЧастини книг з теми "Floating Gate Memory"
Zhou, Ye, Su-Ting Han, and Arul Lenus Roy Vellaisamy. "Flexible Floating Gate Memory." In Flexible and Stretchable Medical Devices, 215–28. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2018. http://dx.doi.org/10.1002/9783527804856.ch9.
Повний текст джерелаFakher, S., A. Sleiman, A. Ayesh, A. AL-Ghaferi, M. C. Petty, D. Zeze, and Mohammed Mabrook. "Organic Floating Gate Memory Structures." In Charge-Trapping Non-Volatile Memories, 123–56. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-48705-2_4.
Повний текст джерелаConte, Antonino, Fabio Disegni, Francesco La Rosa, and Alfonso Maurelli. "Floating-Gate 1Tr-NOR eFlash Memory." In Integrated Circuits and Systems, 75–129. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-55306-1_4.
Повний текст джерелаDo, Nhan, Hieu Van Tran, Alex Kotov, and Vipin Tiwari. "Split-Gate Floating Poly SuperFlash® Memory Technology, Design, and Reliability." In Integrated Circuits and Systems, 131–78. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-55306-1_5.
Повний текст джерелаThean, A., and J. P. Leburton. "Three-Dimensional Self-Consistent Simulation of Silicon Quantum Dot Floating-Gate Flash Memory Device." In Physical Models for Quantum Dots, 807–14. New York: Jenny Stanford Publishing, 2021. http://dx.doi.org/10.1201/9781003148494-51.
Повний текст джерелаDi Spigna, Neil, Daniel Schinke, Srikant Jayanti, Veena Misra, and Paul Franzon. "Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 217–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_12.
Повний текст джерела"Floating Gate Planar Devices." In Nonvolatile Semiconductor Memory Technology. IEEE, 2009. http://dx.doi.org/10.1109/9780470545409.ch2.
Повний текст джерела"Floating Gate Nonplanar Devices." In Nonvolatile Semiconductor Memory Technology. IEEE, 2009. http://dx.doi.org/10.1109/9780470545409.ch3.
Повний текст джерела"Floating Gate Flash Memories." In Nonvolatile Semiconductor Memory Technology. IEEE, 2009. http://dx.doi.org/10.1109/9780470545409.ch4.
Повний текст джерелаKAHNG, D., and S. M. SZE. "A Floating Gate and Its Application to Memory Devices." In Semiconductor Devices: Pioneering Papers, 639–46. WORLD SCIENTIFIC, 1991. http://dx.doi.org/10.1142/9789814503464_0082.
Повний текст джерелаТези доповідей конференцій з теми "Floating Gate Memory"
Martins, R., L. Pereira, P. Barquinha, N. Correia, G. Gonçalves, I. Ferreira, C. Dias, and E. Fortunato. "Floating gate memory paper transistor." In OPTO, edited by Ferechteh H. Teherani, David C. Look, Cole W. Litton, and David J. Rogers. SPIE, 2010. http://dx.doi.org/10.1117/12.841036.
Повний текст джерелаChan, N., M. F. Beug, R. Knoefler, T. Mueller, T. Melde, M. Ackermann, S. Riedel, M. Specht, C. Ludwig, and A. T. Tilke. "Metal control gate for sub-30nm floating gate NAND memory." In 2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2008. http://dx.doi.org/10.1109/nvmt.2008.4731199.
Повний текст джерелаChiang, Pei Wei, Yu Ting Ling, Bo Chih Chen, and Hsiao Tien Chang. "Gate Bridge to Drain Contact Characteristic in Floating Gate Memory." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0456.
Повний текст джерелаTempel, Georg. "Floating gate type nonvolatile memory reliability issues." In 2003 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2003. http://dx.doi.org/10.7567/ssdm.2003.b-3-1.
Повний текст джерелаArai, Fumitaka. "Future Outlook of Floating Gate Flash Memory." In 2006 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2006. http://dx.doi.org/10.7567/ssdm.2006.c-6-1.
Повний текст джерелаChang, Chi. "Reliability Issues of Floating Gate Flash Memory." In 1998 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1998. http://dx.doi.org/10.7567/ssdm.1998.b-3-1.
Повний текст джерелаMotwani, R. "Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory." In 2011 IEEE Global Communications Conference (GLOBECOM 2011). IEEE, 2011. http://dx.doi.org/10.1109/glocom.2011.6134528.
Повний текст джерелаLi, Bei, Yan Zhu, and Jianlin Liu. "Ge/Si hetero-nanocrystal nonvolatile floating gate memory." In 2007 65th Annual Device Research Conference. IEEE, 2007. http://dx.doi.org/10.1109/drc.2007.4373725.
Повний текст джерелаDi Spigna, Neil, Daniel Schinke, Srikant Jayanti, Veena Misra, and Paul Franzon. "A novel double floating-gate unified memory device." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.6379005.
Повний текст джерелаDi Spigna, Neil, Daniel Schinke, Srikant Jayanti, Veena Misra, and Paul Franzon. "A novel double floating-gate unified memory device." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.7332076.
Повний текст джерела