Добірка наукової літератури з теми "Flasher calibration"
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Статті в журналах з теми "Flasher calibration"
Chepurnov, A. S., M. B. Gromov, E. A. Litvinovich, I. N. Machulin, M. D. Skorokhvatov, and A. F. Shamarin. "The Calibration System Based On the Controllable UV/visible LED Flasher for the Veto System of the DarkSide Detector." Journal of Physics: Conference Series 798 (January 2017): 012118. http://dx.doi.org/10.1088/1742-6596/798/1/012118.
Повний текст джерелаSuggs, R. M., S. R. Ehlert, and D. E. Moser. "A comparison of radiometric calibration techniques for lunar impact flashes." Planetary and Space Science 143 (September 2017): 225–29. http://dx.doi.org/10.1016/j.pss.2017.04.016.
Повний текст джерелаSaint-Maurice, Pedro F., Youngwon Kim, Paul Hibbing, April Y. Oh, Frank M. Perna, and Gregory J. Welk. "Calibration and Validation of the Youth Activity Profile: The FLASHE Study." American Journal of Preventive Medicine 52, no. 6 (June 2017): 880–87. http://dx.doi.org/10.1016/j.amepre.2016.12.010.
Повний текст джерелаZhang, Daile, Kenneth L. Cummins, Phillip Bitzer, and William J. Koshak. "Evaluation of the Performance Characteristics of the Lightning Imaging Sensor." Journal of Atmospheric and Oceanic Technology 36, no. 6 (June 2019): 1015–31. http://dx.doi.org/10.1175/jtech-d-18-0173.1.
Повний текст джерелаKim, Sang-Hun, Sang-Geun Hong, Han-Yeol Lee, Won-Ki Park, Wang-Yong Lee, Sung-Chul Lee, and Young-Chan Jang. "1V 1.6-GS/s 6-bit Flash ADC with Clock Calibration Circuit." Journal of the Korean Institute of Information and Communication Engineering 16, no. 9 (September 30, 2012): 1847–55. http://dx.doi.org/10.6109/jkiice.2012.16.9.1847.
Повний текст джерелаZhao, Li, Laurence R. Rilett, and Ernest Tufuor. "Calibrating the Robertson’s Platoon Dispersion Model on a Coordinated Corridor with Advance Warning Flashers." Transportation Research Record: Journal of the Transportation Research Board 2623, no. 1 (January 2017): 10–18. http://dx.doi.org/10.3141/2623-02.
Повний текст джерелаFrye, G. E., C. K. Hauser, G. Townsend, and E. W. Sellers. "Suppressing flashes of items surrounding targets during calibration of a P300-based brain–computer interface improves performance." Journal of Neural Engineering 8, no. 2 (March 24, 2011): 025024. http://dx.doi.org/10.1088/1741-2560/8/2/025024.
Повний текст джерелаBraune, Markus, Günter Brenner, Siarhei Dziarzhytski, Pavle Juranić, Andrey Sorokin, and Kai Tiedtke. "A non-invasive online photoionization spectrometer for FLASH2." Journal of Synchrotron Radiation 23, no. 1 (January 1, 2016): 10–20. http://dx.doi.org/10.1107/s1600577515022675.
Повний текст джерелаLu, Shan, Xinwei Wang, Tianzheng Wang, Xinran Qin, Xilin Wang, and Zhidong Jia. "Analysis of Salt Mixture Contamination on Insulators via Laser-Induced Breakdown Spectroscopy." Applied Sciences 10, no. 7 (April 10, 2020): 2617. http://dx.doi.org/10.3390/app10072617.
Повний текст джерелаHueso, R., M. Delcroix, A. Sánchez-Lavega, S. Pedranghelu, G. Kernbauer, J. McKeon, A. Fleckstein, et al. "Small impacts on the giant planet Jupiter." Astronomy & Astrophysics 617 (September 2018): A68. http://dx.doi.org/10.1051/0004-6361/201832689.
Повний текст джерелаДисертації з теми "Flasher calibration"
Crasso, Anthony. "Background Calibration of a 6-Bit 1Gsps Split-Flash ADC." Digital WPI, 2013. https://digitalcommons.wpi.edu/etd-theses/54.
Повний текст джерелаCicalo, James. "An embedded calibration technique for high-resolution flash time-to-digital converters." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31637.
Повний текст джерелаApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Garambois, Pierre-André. "Etude régionale des crues éclair de l'arc méditerranéen français. Elaboration de méthodologies de transfert à des bassins versants non jaugés." Thesis, Toulouse, INPT, 2012. http://www.theses.fr/2012INPT0102/document.
Повний текст джерелаClimate and orography in the Mediterranean region tend to promote intense rainfalls, particularly in autumn. Storms often hit steep catchments. Flood quickness only let a very short time lapse for forecasts. Peak flow intensity depends on the great variability of rainfalls and catchment characteristics. As a matter of facts, observation networks are not adapted to these small space-time scales and event severity often affects data fiability when they exist thus the notion of ungauged catchment emerges. Regionalization in hydrology seeks to determine hydrological variables at locations where these data lack. This work contributes to pose the bases of a methodology adapted to transpose parameterizations of a flash flood dedicated distributed hydrologic model from gauged catchments to ungauged ones, and for a large study area. The MARINE distributed hydrologic model is used [Roux et al., 2011], its originality lies in the automatically differentiated adjoint model able to perform calibrations and spatial-temporal sensitivity analysis, in order to improve understanding in flash flood generating mechanisms and real time data assimilation for hydrometeorological forecasts. MARINE sensitivity analysis addresses the question of physical process understanding. A large panel of hydrologic behaviours is explored. General catchment behaviours are highlighted for the study area [Garambois et al., 2012a]. Selected flood events and a multiple events calibration technique help to extract catchment parameter sets. Those parameterizations are tested on validation events. A variance decomposition method leads to parameter temporal sensitivity analysis. It enables better understanding in catching dynamics of physical processes involved in flash floods formation [Garambois et al., 2012c]. Parameterizations are then transfered from gauged catchments with hydrologic similarity to ungauged ones with a view to develop real time flood forecasting
Douinot, Audrey. "Analyse des processus d'écoulement lors de crues à cinétique rapide sur l'arc méditerranéen." Thesis, Toulouse 3, 2016. http://www.theses.fr/2016TOU30265/document.
Повний текст джерелаThe purpose of this thesis is to improve the knowledge of hydrological processes during flash flood events using rainfall-runoff modelling. The project focuses on hydrological processes occurring into soil and subsoil horizons. A preliminary data analysis corroborates the activity of the weathered bedrock during flash floods. The hydrological response, simulated by the MARINE model, is then investigated to detect the sensitivity of subsurface flow processes to model assumptions. It leads to several modifications of the model structure in order to make it more robust. Moreover a two-layered soil column is implemented to explicitly integrate the activity of the weathered bedrock into the model. Assuming preferential path flows at the soil-bedrock interface, the model performs well on sedimentary watersheds, but underestimate recession curves and second flood peaks on granitic ones, showing the need to simulate as well significantcontribution from the weathered bedrock
Swaby, David. "Flasher calibration of the T1 and T2 CANGAROO telescopes and TeV gamma ray observation of Markarian 421 and EXO 055625-3838.6 BL Lacertae blazars." Thesis, 2010. http://hdl.handle.net/2440/66096.
Повний текст джерелаThesis (M.Sc.) -- University of Adelaide, School of Chemistry and Physics, 2010
Sung, Chih-Kuo, and 宋治國. "A 6-bit 1GSPS Flash ADC with Background Offset Calibration." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/24460788734903512727.
Повний текст джерела國立成功大學
電機工程學系碩博士班
96
Offset calibration is a technique which detects the offset and adjusts the circuit configuration accordingly. However, foreground calibration only processes once which is not easy to prevent offset variations caused by temperature and supply voltage. In this thesis, the offset calibration circuit is proposed to make the circuit of the preamplifier and the comparator-latch match. It means that the offset voltages of the preamplifier and the comparator-latch are calibrated. Since the offset calibration circuit is based on the switch-capacitor circuit, the requirement of the power is less. The switch-capacitor circuit does not located at the connection of the conversion circuits, which does not affect the operating rate of the conversion. With the new switch network, the background offset calibration technique is implemented to prevent the offset variation. A 6-bit 1GSample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. After calibration, the simulation results show that SNDR is 36dB with 480MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW where output buffers are not included. FoM of this ADC is 259fJ/conversion-step. Other comparable designs have FOMs between 0.5 to 10 pJ.
Liau, Jiun-Jie, and 廖俊杰. "A 4-Bit 1GSPS Flash ADC with Step-Shifted Background Calibration." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/85125639040706939529.
Повний текст джерела國立成功大學
電機工程學系碩博士班
96
A 4-bit flash ADC with step-shifted background calibration method is proposed in this thesis. This system would increase one comparator, switches for resistor ladder and use the random phase generator to generate shifted and non-shifted states. For the same comparator, its reference voltage would shift 1LSB in the two states. Because of the offset due to device mismatch, the probability of the input signal hitting into the same thermometer in shifted and non-shifted states would not be the same. Then, the system calculates the probability of the two states by ripple counter and applies the DAC circuit to cancel the offset. The counter would only work where the input signal hits in the thermometer code. Therefore, all of the counters wouldn’t work at the same time. Finally, the performance of the system would improve and keep after some calibration periods. This ADC is fabricated in a 0.13μm 1P8M CMOS process. The active area is only 0.027mm2. The ADC achieves a measured ENOB of 3.83b for a 435MHz input at 1GS/s. The power consumption (including clock buffer and resistor ladder) is 5mW at 1GS/s.
Chiou, Ming-Chi, and 邱銘吉. "A 6-bit 1GSPS Flash ADC with Step-Shifted Background Calibration." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/96974104278031857942.
Повний текст джерела國立成功大學
電機工程學系碩博士班
98
In this thesis, a 6-bit 1GSPS Flash ADC is implemented, and a background offset calibration circuit is proposed to calibrate the offset of the preamplifier and the latch due to mismatch. By using the switches for resistor ladder, the 1LSB step-shifted voltage from its reference voltage is generated. The probability of the input signal hitting into the same thermometer code would be not be the same in differential step-shifted. According to the output thermometer code and use the DAC with the ripple counter circuit to calibrate the offset. The two-level step-shifted method is proposed for higher resolution. A 6-bit 1G Sample/s flash ADC is implemented by TSMC 0.13um 1P8M CMOS process. Simulation results show that SNDR is 37dB with 441MHz input frequency at 1GHz sample rate. The power consumption is 13.2mW with a 1.2-V supply where output buffers are excluded.
Chang, Hsuan-Yu, and 張軒瑜. "Design of Low-Power Flash Analog-to-Digital Converters Using Digital Calibration." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/47809309624999322555.
Повний текст джерела國立中興大學
電機工程學系所
104
Flash-type ADCs have the inherent advantage on high-speed sampling rates. Although the flash ADC is superiority in sampling rate but its large power consumption makes itself bottleneck in many applications. Speed, power and accuracy are tradeoff in high-speed CMOS ADC design. Process technology scaling trends toward smaller transistor dimensions and low supply voltage, and thereby it leads to greatly reduce power consumption in flash ADCs. The never-ending story of CMOS technology trending toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Transistor size scaling results in significant offset voltage and supply voltage scaling makes it more difficult in higher accuracy design. In order to improving above design issues, many techniques have been proposed, such as resistor-averaging networks and digital calibrated techniques. Especially, the digital calibrated techniques are main solutions recently. In this thesis, the new idea of digital calibrated technique is proposed to realize high-speed ADCs. First chip, using tree-type metal layout and digital calibration, a 6-bit 2-GS/s flash ADC without track-and-hold is presented. Since large offset voltages caused by using small device sizes in front-end of high-speed ADCs usually result in nonlinearity in output, a digitally calibrated method is applied to improve the performance of the proposed ADC. In addition, no track-and-hold circuit used will cause dynamic error but tree-type metal layout will avoid it. Measurement results show the ADC achieves a SNDR of 35.6 dB for a low frequency input at 2 GS/s sampling frequency, and 32.7 dB for an ERBW input frequency. The power consumption is 28 mW at 2 GS/s from a 1.2-V supply. The core area is 0.56mm × 0.62mm and the figure of merit is 0.54pJ/conv. Second chip, a 6-bit flash ADC using reference-voltage- interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs successive approximation algorithm and minimized residue algorithm to determine precise calibration levels. Implemented by 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 LSB and 0.42 LSB, respectively. The power consumption is 25 mW at 2-GS/s from a 1.2-V supply. The core area is 0.32 mm × 0.62 mm, and the figure of merit is 0.34 pJ/conversion step. Finally, we compare the two chips design considerations and improvements. The first chip is suitable only in single ADC system application due to no track-and-hold circuit. The second chip is suitable in multi-sub ADCs system application, such as time-interleaved ultra-high speed ADCs. The second chip consumes less power comparing to the first chip due to wider calibration range. Transistor size of the comparator in flash ADC can be designed smaller due to wide calibration range, and it consumes less dynamic power. Performance summary and comparison table will be shown finally.
Lin, Yi-Huan, and 林依寰. "A 1.2V 6-bit 1GS/s Flash ADC with Foreground Offset Calibration." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/92064142758735397577.
Повний текст джерела國立中正大學
電機工程研究所
99
A 1.2V 6-bit 1G sample/s flash ADC with foreground digital calibration is designed and implemented in TSMC standard 90nm 1P9M mixed-signal process technology. The design considerations and analyses of the resistor ladder, track-and-hold circuits, comparator, and encoder are presented. To alleviate random offsets caused by process variation, a digital calibration technique is adopted. Considering power consumption and operating speed, current mode logic (CML) circuits are chosen instead of CMOS logic circuits. Post layout simulation shows with calibration the SNDR is improved to 35dB, where input frequency is 490MHz and the sampling rate is 1Gsample/s. The total power consumption of this converter at full speed is 156mW and the area is 1mm2.
Частини книг з теми "Flasher calibration"
Rajab, Mohammed. "Error characteristics and read threshold calibration for flash memories." In Channel and Source Coding for Non-Volatile Flash Memories, 5–28. Wiesbaden: Springer Fachmedien Wiesbaden, 2020. http://dx.doi.org/10.1007/978-3-658-28982-9_2.
Повний текст джерелаMark, Howard, and Jerry Workman. "Linearity in Calibration, Act III Scene VI: Quantifying Nonlinearity, Part II, and a News Flash ☆." In Chemometrics in Spectroscopy, 465–75. Elsevier, 2018. http://dx.doi.org/10.1016/b978-0-12-805309-6.00069-6.
Повний текст джерелаMark, Howard, and Jerry Workman. "Linearity in Calibration: Act III Scene VI – Quantifying Nonlinearity, Part II, and a News Flash." In Chemometrics in Spectroscopy, 459–69. Elsevier, 2007. http://dx.doi.org/10.1016/b978-012374024-3/50069-6.
Повний текст джерелаHuang, M. H. A., S. Ahmad, P. Barrillon, S. Brandt, C. Budtz-Jørgensen, A. J. Castro-Tirado, S. H. Chang, et al. "THE CALIBRATION AND SIMULATION OF THE GRB TRIGGER DETECTOR OF THE ULTRA FAST FLASH OBSERVATORY." In Gamma-ray Bursts: 15 Years of GRB Afterglows, 531–36. EDP Sciences, 2020. http://dx.doi.org/10.1051/978-2-7598-1002-4-088.
Повний текст джерелаHuang, M. H. A., S. Ahmad, P. Barrillon, S. Brandt, C. Budtz-Jørgensen, A. J. Castro-Tirado, S. H. Chang, et al. "THE CALIBRATION AND SIMULATION OF THE GRB TRIGGER DETECTOR OF THE ULTRA FAST FLASH OBSERVATORY." In Gamma-ray Bursts: 15 Years of GRB Afterglows, 531–36. EDP Sciences, 2020. http://dx.doi.org/10.1051/978-2-7598-1002-4.c088.
Повний текст джерелаMark, Howard, and Jerry Workman. "Linearity in Calibration, Act III, Scene VI: Quantifying Nonlinearity, Part II: A Calculus-Based Approach, and A News Flash." In Chemometrics in Spectroscopy, 465–75. Elsevier, 2018. http://dx.doi.org/10.1016/b978-0-323-91164-1.00069-4.
Повний текст джерелаТези доповідей конференцій з теми "Flasher calibration"
Patterson, John R. "Calibration of Cangaroo II telescope using a fast blue LED light flasher." In The international symposium on high energy gamma-ray astronomy. AIP, 2001. http://dx.doi.org/10.1063/1.1370838.
Повний текст джерелаBrown, Anthony, Thomas Armstrong, Paula Chadwick, Michael Daniel, and Richard White. "Flasher and muon-based calibration of the GCT telescopes proposed for the Cherenkov Telescope Array." In The 34th International Cosmic Ray Conference. Trieste, Italy: Sissa Medialab, 2016. http://dx.doi.org/10.22323/1.236.0934.
Повний текст джерелаIslam Gamal, Islam Gamal. "AUTOSAR-Compliant Methodology for Calibrating ECUs using Universal Calibration and Measurement Protocol." In FISITA World Congress 2021. FISITA, 2021. http://dx.doi.org/10.46720/f2021-ves-039.
Повний текст джерелаRajab, Mohammed, Johann-Philipp Thiers, and Jurgen Freudenberger. "Read Threshold Calibration for Non-Volatile Flash Memories." In 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin). IEEE, 2019. http://dx.doi.org/10.1109/icce-berlin47944.2019.8966181.
Повний текст джерелаYun-Shiang Shu, Jui-Yuan Tsai, Ping Chen, Tien-Yu Lo, and Pao-Cheng Chiu. "A background calibration technique for fully dynamic flash ADCs." In 2013 International Symposium on VLSI Design, Automation and Test (VLSI-DAT). IEEE, 2013. http://dx.doi.org/10.1109/vldi-dat.2013.6533857.
Повний текст джерелаKijima, Masashi, Kenji Ito, Kuniyoshi Kamei, and Sanroku Tsukamoto. "A 6b 3GS/s flash ADC with background calibration." In 2009 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2009. http://dx.doi.org/10.1109/cicc.2009.5280860.
Повний текст джерелаR., Pradeep, Siddharth R.K., Nithin Kumar Y.B., and Vasantha M.H. "Process Corner Calibration for Standard Cell Based Flash ADC." In 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS). IEEE, 2019. http://dx.doi.org/10.1109/ises47678.2019.00051.
Повний текст джерелаTzu-Yi Tang, Jhao-Wei Zeng, K. Chen, and Tsung-Heng Tsai. "A threshold-embedded offset calibration technique for folding flash ADCs." In 2013 2nd International Symposium on Next-Generation Electronics (ISNE 2013). IEEE, 2013. http://dx.doi.org/10.1109/isne.2013.6512277.
Повний текст джерелаBaboi, N., P. Castro, O. Hensler, J. Lund-Nielsen, D. Nolle, L. Petrosyan, E. Prat, T. Traber, M. Krasilnikov, and W. Riesch. "Beam position monitor calibration at the FLASH linac at DESY." In 2007 IEEE Particle Accelerator Conference (PAC). IEEE, 2007. http://dx.doi.org/10.1109/pac.2007.4439937.
Повний текст джерелаChatterjee, Shatadal, Maryaradhiya Daimari, and Sounak Roy. "A Fully Digital Foreground Calibration Technique of A Flash ADC." In 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2021. http://dx.doi.org/10.1109/isvlsi51109.2021.00012.
Повний текст джерела