Статті в журналах: "FILTER IMPLEMENTATION"

1

Singh, Gurpadam, and Neelam R. Prakash. "FPGA Implementation of Higher Order FIR Filter." International Journal of Electrical and Computer Engineering (IJECE) 7, no. 4 (August 1, 2017): 1874. http://dx.doi.org/10.11591/ijece.v7i4.pp1874-1881.

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The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.

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2

Horváth, Dušan, Zuzana Červeňanská, and Janette Kotianová. "Digital Implementation of Butterworth First–Order Filter Type IIR." Research Papers Faculty of Materials Science and Technology Slovak University of Technology 27, no. 45 (September 1, 2019): 85–93. http://dx.doi.org/10.2478/rput-2019-0030.

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Abstract The paper deals with the solution of the first–order passive filters (low–pass and high–pass) applying electrotechnical elements (resistor, capacitor - analogue filter) and digital Butterworth filter type IIR (Infinite Impulse Response). Procedure of the filters design and implementation is described, and the analogue and digital filter outputs with the same input signal are compared. The designed filters have already served for education purposes with the intention to bring an explanation of techniques for designing required functionality of the signal processing filters.

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3

Wen, Hui, and Shu Ming Li. "DSP-Based FIR Filter Design and Circular Buffer Implementation." Advanced Materials Research 403-408 (November 2011): 1755–58. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.1755.

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The digital filter technology includes two aspects, which are the filter design process and filter realization. The article expounded the basic structure of FIR filter, with examples on the use Matlab to determine the FIR filter coefficient, analysis of the cycle of the buffer zone algorithm Principle, based on the algorithm, combination of filters designed to achieve the input of mixed-signal FIR digital filter. In the end, the filter is given before and after the input and output signal waveform simulation.

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4

Satyanarayana, Dr S. V. V., K. Teja Sri, K. Madhavi, G. Jhansi, and B. Jaya Sri. "Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications." International Journal of Recent Technology and Engineering (IJRTE) 12, no. 1 (May 30, 2023): 27–32. http://dx.doi.org/10.35940/ijrte.a7564.0512123.

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This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

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5

Chen, Jin Lun. "A Multi-Rate Implementation of Auditory Filter Bank." Applied Mechanics and Materials 373-375 (August 2013): 579–82. http://dx.doi.org/10.4028/www.scientific.net/amm.373-375.579.

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The auditory filter-bank is the key component of auditory model, and its implementation involves a lot of computations. The time spent by an auditory filter-bank to finish its work has a significant effect on the real-time implementation of auditory model-based audio signal processing systems. In this paper, a multi-rate implementation of auditory filter bank is presented. Through using low sampling rate for the filters with low centre frequency, and using high sampling rate for the filters with high centre frequency, we can greatly reduce the computation requirement.

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6

Pushpalatha, P., and K. Babulu. "Design and implementation of systolic architecture based FIR filter." i-manager's Journal on Digital Signal Processing 10, no. 1 (2022): 17. http://dx.doi.org/10.26634/jdp.10.1.18852.

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In signal processing, a filter is a device or process that removes some unwanted components or features from a signal. Digital filters are mainly divided into Infinite Impulse Response (IIR) filters and Finite Impulse Response (FIR) filters. FIR filters are mostly used in applications like image processing, communications, Digital Signal Processing (DSP) etc. One of the most used filters for designing of VLSI circuits is FIR filter. Systolic architecture is a Processing Element (PE) network that generates and passes data rhythmically through the system. The concept of systolic architecture can map high-level computing into hardware structures. FIR filter with systolic architectures provide better examples for efficient VLSI and FPGA implementations of many digital signal processing applications because of their modularity and regularity features.

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7

Shaik, Samdhani, and P. Balanagu. "Functional Verification Architecture Implementation for Power Optimized FIR Filter." International Journal of Engineering & Technology 7, no. 2.20 (April 18, 2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.

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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.

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8

Qiu, Xinyi, Hui Feng, and Bo Hu. "Fractional Order Graph Filters: Design and Implementation." Electronics 10, no. 4 (February 10, 2021): 437. http://dx.doi.org/10.3390/electronics10040437.

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Existing graph filters, polynomial or rational, are mainly of integer order forms. However, there are some frequency responses which are not easily achieved by integer order approximation. It will substantially increase the flexibility of the filters if we relax the integer order to fractional ones. Motivated by fractional order models, we introduce the fractional order graph filters (FOGF), and propose to design the filter coefficients by genetic algorithm. In order to implement distributed computation on a graph, an FOGF can be approximated by the continued fraction expansion and transformed to an infinite impulse response graph filter.

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9

Baranowski, Jerzy, and Paweł Piątek. "Fractional Band-Pass Filters: Design, Implementation and Application to EEG Signal Processing." Journal of Circuits, Systems and Computers 26, no. 11 (March 21, 2017): 1750170. http://dx.doi.org/10.1142/s0218126617501705.

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Fractional band-pass filters are a promising area in the signal processing. They are especially attractive as a method for processing of biomedical signals, such as EEG, where large signal distortion is undesired. We present two structures of fractional band-pass filters: one as an analog of classical second-order filter, and one arising from parallel connection of two fractional low-pass filters. We discuss a method for filter implementation — Laguerre Impulse Response Approximation (LIRA) — along with sufficient conditions for when the filter can be realized with it. We then discuss methods of filter tuning, in particular we present some analytical results along with optimization algorithm for numerical tuning. Filters are implemented and tested with EEG signals. We discuss the results highlighting the possible limitations and potential for development.

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10

Stojanovic, Vidosav, Negovan Stamenkovic, and Nikola Stojanovic. "Active RC filter based implementation analysis part of two channel hybrid filter bank." Serbian Journal of Electrical Engineering 11, no. 4 (2014): 565–84. http://dx.doi.org/10.2298/sjee1404565s.

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In the present paper, a new design method for continuous-time powersymmetric active RC filters for Hybrid Filter Bank (HFB) is proposed. Some theoretical properties of continious-time power-symmetric filters bank in a more general perspective are studied. This includes the derivation of a new general analytical form, and a study of poles and zeros locations in s-plane. In the proposed design method the analytic solution of filter coefficients is solved in sdomain using only one nonlinear equation Finally, the proposed approximation is compared to standard approximations. It was shown that attenuation and group delay characteristic of the proposed filter lie between Butterworth and elliptic characteristics.

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11

Hu, Dan Hua, Zhao Xiong Zeng, Jing Song Meng, and Chang Hua Zhang. "Implementation of the Variable Center Frequency Band-Pass Filter Based on FPGA." Advanced Materials Research 1049-1050 (October 2014): 642–45. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.642.

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Digital band-pass filters play a very important role in instrument design. For some special applications, such as corrosion inspection of buried oil or gas pipeline, more than one band-pass filter with different center frequencies are needed to process different frequency signals. FPGA (Field-Programmable Gate Array) are widely used in these applications because of its high compute velocity and flexibility. For low cost and high reliability purposes, it is expected that one digital filter with a fixed configuration parameters can serve as multi different center frequency digital filter. In this paper a design method is proposed to realize two different center frequency band-pass filters which have the same filtering effect. Through analysis of design process for FIR band-pass filter, it’s easy to find that if the ratios (filter’ sample rate of input data to its cut-off frequency) of two filters keep equal, the normalized frequency will also equal. Thus according to this, two band-pass filters can have the same coefficients only if they have the same ratio of sample rate to cut-off frequency. This relationship is discussed here and MATLAB experiment is used to prove its effectiveness. This method is already used to design filters in pipeline current mapper instrument to inspect pipeline corrosion.

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12

Payandehnia, P., J. L. Ceballos, and G. C. Temes. "Noise‐shaped filter implementation." Electronics Letters 54, no. 1 (January 2018): 20–21. http://dx.doi.org/10.1049/el.2017.3245.

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13

Bhattacharya, S., T. M. Frank, D. M. Divan, and B. Banerjee. "Active filter system implementation." IEEE Industry Applications Magazine 4, no. 5 (1998): 47–63. http://dx.doi.org/10.1109/2943.715508.

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14

Hiam, Sohani Munteha. "Implementation of Optimized Filter Order to the PSD Analysis of QRS Detected ECG Signal." International Journal of Recent Technology and Engineering (IJRTE) 11, no. 4 (November 30, 2022): 33–37. http://dx.doi.org/10.35940/ijrte.d7328.1111422.

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Filtration of ECG signal is an important part in the analysis and signal processing of ECG signal. There are different types of digital and analog filters available for the filtration of an ECG signal. And choosing the right filter order for different filters has always been a tough task in biomedical signal processing. This study aims to solve this problem of filter order optimization by cascading digital filters and evaluating their performance based on SNR using ECG-ID Database from PHYSIONET. Besides, this optimized filter order has been applied to both normal and abnormal QRS detected ECG signals to choose the right filter order based on average power received from PSD analysis. QRS detection has been performed by differentiation technique. In this study, design of the filters has been carried out using MATLAB software-based FDA tool in both monitoring and diagnostic modes. This analysis has strong potential for analyzing low amplitude based biological signals like ECG or EEG.

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15

GUSTAFSSON, OSCAR, HÅKAN JOHANSSON, and LARS WANHAMMAR. "SINGLE FILTER FREQUENCY-RESPONSE MASKING FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 601–30. http://dx.doi.org/10.1142/s0218126603001094.

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In this work filter structures that decrease the required number of multipliers and adders for implementation of linear-phase FIR filters using frequency-response masking techniques are introduced. The basic idea of the proposed structures is that identical subfilters are used. This leads to the same arithmetic structure can be multiplexed in the implementation, reducing the number of required multipliers and adders. The subfilters are mapped using the folding transformation to obtain an area-efficient time-multiplexed (or pipeline/interleaved) implementation. Both narrow-band and wide-band frequency-response masking as well as arbitrary bandwidth frequency-response masking techniques are considered. The filter design is discussed and for each filter structure the limits on the specifications are derived. Designed examples show the usefulness of the proposed structures.

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16

Assimakis, Nicholas, and Maria Adam. "Global Systems for Mobile Position Tracking Using Kalman and Lainiotis Filters." Scientific World Journal 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/130512.

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We present two time invariant models for Global Systems for Mobile (GSM) position tracking, which describe the movement inx-axis andy-axis simultaneously or separately. We present the time invariant filters as well as the steady state filters: the classical Kalman filter and Lainiotis Filter and the Join Kalman Lainiotis Filter, which consists of the parallel usage of the two classical filters. Various implementations are proposed and compared with respect to their behavior and to their computational burden: all time invariant and steady state filters have the same behavior using both proposed models but have different computational burden. Finally, we propose a Finite Impulse Response (FIR) implementation of the Steady State Kalman, and Lainiotis filters, which does not require previous estimations but requires a well-defined set of previous measurements.

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17

LIAN, YONG. "A MODIFIED FREQUENCY-RESPONSE MASKING STRUCTURE FOR HIGH-SPEED FPGA IMPLEMENTATION OF SHARP FIR FILTERS." Journal of Circuits, Systems and Computers 12, no. 05 (October 2003): 643–54. http://dx.doi.org/10.1142/s0218126603001069.

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This paper presents the design and implementation of high-speed, multiplierless, arbitrary bandwidth sharp FIR filters based on frequency-response masking (FRM) technique. The FRM filter structure has been modified to improve the throughput rate by replacing long band-edge shaping filter in the original FRM approach with two to three cascaded short filters. The proposed structure is suitable for FPGA as well as VLSI implementation for sharp digital FIR filters. It is shown by an example that a near 200-tap equivalent Remez FIR filter can be implemented in a single Xilinx XC4044XLA device that operates at sampling frequency of 5.5 MHz.

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18

Mardiono, Djoko Anwar, Gunawan Toto Hadiyanto, and Intan Kumala Sari. "Penggunaan Common-Mode Filter dan Differential-Mode Filter Pada EMI Driver Lampu LED." Zona Teknik: Jurnal Ilmiah 15, no. 2 (December 29, 2021): 1. http://dx.doi.org/10.37776/zt.v15i2.811.

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Power Energy efficiency for public application commonly used driver IC that operate by (Pulse Width Modulation) PWM, The effect of this implementation will generate EMI (Electromagnetic Interference) that can make radio signal distortion or other electronic distortion in the around device area. The action to reduce the signal distortions shall use Filter implementation in the electronic device circuit. The filter to reduce signal distortion are power line filter or ferrite beads filter. Power line filter used for reduce and to filtering noise signal from Power line source from PLN power line or from power line distribution Conduction emission., The ferrite beads filter implementation for noise reduction or filtering from Source power supply to load. Implement of both filters at the circuit diagram will impact to reduce noise signal that make distortion to the signal source.

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19

Venkatesan, C., T. Thamaraimanalan, and R. Latha. "VLSI Implementation of DENLMS Adaptive Filter for Biomedical Applications." Middle East Journal of Applied Science & Technology 05, no. 01 (2022): 119–27. http://dx.doi.org/10.46431/mejast.2022.5109.

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Very Large Scale Integration (VLSI) implementation of the Delayed Error Normalized LMS (DENLMS) adaptive filter using a pipelined architecture is proposed and it can be used for biomedical applications. The proposed pipelined VLSI architecture increases the performance of adaptive filters by lowering the amount of time spent on critical path calculation. When compared to the current Error Normalized Least Mean Square (ENLMS) method for pipelining purposes, the DENLMS technique requires an additional delay element, and because of the delay element, the algorithm functions faster and more effective in low-power applications. The proposed pipelined architecture of the DENLMS filter, on the other hand, improves the efficiency while consuming less power overall. The cell leakage power reduction and total dynamic power reduction obtained by using the DENLMS filter are 31.8% and 33.5%, respectively, although the overall area of the filter has increased by 20.4%.

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Venkatesan, C., T. Thamaraimanalan, and R. Latha. "VLSI Implementation of DENLMS Adaptive Filter for Biomedical Applications." Middle East Journal of Applied Science & Technology 05, no. 01 (2022): 119–27. http://dx.doi.org/10.46431/mejast.2022.5109.

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Very Large Scale Integration (VLSI) implementation of the Delayed Error Normalized LMS (DENLMS) adaptive filter using a pipelined architecture is proposed and it can be used for biomedical applications. The proposed pipelined VLSI architecture increases the performance of adaptive filters by lowering the amount of time spent on critical path calculation. When compared to the current Error Normalized Least Mean Square (ENLMS) method for pipelining purposes, the DENLMS technique requires an additional delay element, and because of the delay element, the algorithm functions faster and more effective in low-power applications. The proposed pipelined architecture of the DENLMS filter, on the other hand, improves the efficiency while consuming less power overall. The cell leakage power reduction and total dynamic power reduction obtained by using the DENLMS filter are 31.8% and 33.5%, respectively, although the overall area of the filter has increased by 20.4%.

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21

Anderson, Jeffrey L., and Nancy Collins. "Scalable Implementations of Ensemble Filter Algorithms for Data Assimilation." Journal of Atmospheric and Oceanic Technology 24, no. 8 (August 1, 2007): 1452–63. http://dx.doi.org/10.1175/jtech2049.1.

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Abstract A variant of a least squares ensemble (Kalman) filter that is suitable for implementation on parallel architectures is presented. This parallel ensemble filter produces results that are identical to those from sequential algorithms already described in the literature when forward observation operators that relate the model state vector to the expected value of observations are linear (although actual results may differ due to floating point arithmetic round-off error). For nonlinear forward observation operators, the sequential and parallel algorithms solve different linear approximations to the full problem but produce qualitatively similar results. The parallel algorithm can be implemented to produce identical answers with the state variable prior ensembles arbitrarily partitioned onto a set of processors for the assimilation step (no caveat on round-off is needed for this result). Example implementations of the parallel algorithm are described for environments with low (high) communication latency and cost. Hybrids of these implementations and the traditional sequential ensemble filter can be designed to optimize performance for a variety of parallel computing environments. For large models on machines with good communications, it is possible to implement the parallel algorithm to scale efficiently to thousands of processors while bit-wise reproducing the results from a single processor implementation. Timing results on several Linux clusters are presented from an implementation appropriate for machines with low-latency communication. Most ensemble Kalman filter variants that have appeared in the literature differ only in the details of how a prior ensemble estimate of a scalar observation is updated given an observed value and the observational error distribution. These details do not impact other parts of either the sequential or parallel filter algorithms here, so a variety of ensemble filters including ensemble square root and perturbed observations filters can be used with all the implementations described.

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22

Xu, Wei, Anyu Li, Boya Shi, and Jiaxiang Zhao. "A Novel Design of Sparse FIR Multiple Notch Filters with Tunable Notch Frequencies." Mathematical Problems in Engineering 2018 (2018): 1–7. http://dx.doi.org/10.1155/2018/3490830.

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We focus on the design of finite impulse response (FIR) multiple notch filters. To reduce the computational complexity and hardware implementation complexity, a novel algorithm is developed based on the mixture of the tuning of notch frequencies and the sparsity of filter coefficients. The proposed design procedure can be carried out as follow: first, since sparse FIR filters have lower implementation complexity than full filters, a sparse linear phase FIR single notch filter with the given rejection bandwidth and passband attenuation is designed. Second, a tuning procedure is applied to the computed sparse filter to produce the desired sparse linear phase FIR multiple notch filter. When the notch frequencies are varied, the same tuning procedure can be employed to render the new multiple notch filter instead of designing the filter from scratch. The effectiveness of the proposed algorithm is demonstrated through three design examples.

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23

Lian, Feng, Chongzhao Han, Jing Liu, and Hui Chen. "Convergence Results for the Gaussian Mixture Implementation of the Extended-Target PHD Filter and Its Extended Kalman Filtering Approximation." Journal of Applied Mathematics 2012 (2012): 1–20. http://dx.doi.org/10.1155/2012/141727.

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The convergence of the Gaussian mixture extended-target probability hypothesis density (GM-EPHD) filter and its extended Kalman (EK) filtering approximation in mildly nonlinear condition, namely, the EK-GM-EPHD filter, is studied here. This paper proves that both the GM-EPHD filter and the EK-GM-EPHD filter converge uniformly to the true EPHD filter. The significance of this paper is in theory to present the convergence results of the GM-EPHD and EK-GM-EPHD filters and the conditions under which the two filters satisfy uniform convergence.

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24

Chen, Jing, Chang Yin Liu, and Xue Ping Li. "The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB." Advanced Materials Research 791-793 (September 2013): 2122–26. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.2122.

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Polyphase FIR filters are applied in many practical Digital Signal Processing applications where the sampling rate needs to be changed. This paper focuses on the implementation of polyphase square root raised cosine (SRRC) FIR filter based on Field Programmable Gate Array (FPGA). The filter employs methods like filter's multiphase structure, symmetrical coefficients, I/Q channel multiplexing, pipeline addition and so on to design the SRRC filter. Compared with the traditional method, the designed FIR filter exhibits the advantages of high response speed and low hardware resource s consumption.

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25

Rao, Dr B. Rama. "Design and Implementation of 6-Tap FIR Filter Using MAC for Low Power Applications." International Journal for Research in Applied Science and Engineering Technology 10, no. 6 (June 30, 2022): 1506–11. http://dx.doi.org/10.22214/ijraset.2022.44081.

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Abstract: A Significant number of mathematical operations, such as multiplication and accumulation, are often required by a digital signal processing (DSP) algorithm. Many DSP applications have latency limitations, which mean that the DSP operation must be performed within a certain amount of time for the system to function, and because DSP gives high accuracy, filters constructed in DSP have tighter control over the output accuracy. As a result, DSP applications must be fast, have a high throughput, and use little power. Filters with a finite impulse response (FIR) are commonly employed in digital signal processing (DSP) applications. A FIR filter that is efficient in terms of electricity is being built. The multiplier and accumulator (MAC) unit used a new implementation approach to develop this system. FIR filter is a type of filter. Multipliers, adders, and a variety of other components are commonly used in FIR filters. Multipliers, adders, and a series of delays are used to form the filter's output in FIR filters. The goal of this project is to design and implement a 6-tap finite impulse response (FIR) filter by replacing multipliers with an 8-bit Multiplier and Accumulator (MAC) unit within the FIR filter, where a low-power MAC unit is always a key to achieving high performance in a DSP system, and D flip-flops are used in place of delays and constructed using a latch-based design. The Wallace tree Multiplier was utilised in the construction of the MAC unit because it reduces the amount of partial products, and the adders used for accumulation are half adders and full adders. In the FIR filter, for the purpose of summing This work evaluates performance of FIR filter in terms of speed and power and synthesis are executed in Xilinx Vivado 2018.1 software environment and the implementation is done using VHDL codes. The result analysis shows that the proposed FIR filter consumes low power than conventional (standard) FIR filter. As the dynamic power results up to 11.932W and after implementation it results up to 12.029W. Keywords: MAC, Low power, latch-based design.

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26

Rao, Chaolin, and Xin Lou. "Multiplication and Accumulation Co-Optimization for Low Complexity FIR Filter Implementation." Electronics 11, no. 11 (May 28, 2022): 1721. http://dx.doi.org/10.3390/electronics11111721.

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In multiplierless finite impulse response (FIR) filters, the product accumulation block (PAB) could be the major contributor to hardware complexity, especially for high-order filters. In this paper, an optimization scheme where the constant multiplication block and the PAB are jointly optimized at the bit-level is proposed to minimize the hardware complexity. In the proposed joint optimization, the multiple constant multiplications (MCM) block is rearranged into several MCM sub-blocks. The products are summed locally before accumulation to reduce the word-length of the structural adders. It is shown that the symmetric property of linear phase FIR filters can be utilized in some cases to further reduce the complexity of the constant multiplications. Quantitative analyses are also presented to study the relationship between the optimum group size and the coefficient values as well as the filter orders. It is shown that there is no fixed optimum structure for filters with different coefficient word-lengths and filter orders, and each filter needs to be optimized specifically to achieve the minimum hardware complexity. Implementation results are presented to validate the effectiveness of the proposed method.

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27

RAMÍREZ, JAVIER, UWE MEYER-BÄSE, and ANTONIO GARCÍA. "EFFICIENT RNS-BASED DESIGN OF PROGRAMMABLE FIR FILTERS TARGETING FPL TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 01 (February 2005): 165–77. http://dx.doi.org/10.1142/s0218126605002131.

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FIR filters are routinely used in the implementation of modern digital signal processing systems. Their efficient implementation using commercially available VLSI technology is a subject of continuous study and development. This paper presents the residue number system (RNS) implementation of reduced-complexity and high-performance FIR filters, using modern Altera APEX20K field-programmable logic (FPL) devices. Index arithmetic over Galois fields and the Quadratic Residue Number System (QRNS), along with a selection of a small wordwidth modulus set, are the keys for attaining low complexity and high throughput in real and complex FIR filters. RNS–FPL merged FIR filters demonstrated its superiority when compared to 2C (two's complement) filters, being about 65% faster and requiring fewer logic elements for most study cases. Special attention was paid to an efficient implementation of the multi-operand modulo adders. The replacement of a classical modulo adder tree by a binary adder with extended precision followed by a single modulo reduction stage reduced area requirements by 10% for a 32-tap FIR filter. On the other hand, an index arithmetic QRNS-based complex FIR filter yielded up to 60% performance improvement over a three-multiplier-per-tap 2C filter, while requiring fewer LEs for filters having more than eight taps. Particularly, a 32-tap filter needed 24% LEs less than the classical design.

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28

Başak, Muhammed Emin. "CMOS Implementation of Current Differencing Operational Amplifier and Its Notch Filter Application." Journal of Circuits, Systems and Computers 29, no. 08 (October 15, 2019): 2050132. http://dx.doi.org/10.1142/s0218126620501327.

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Active elements are fundamental circuits for a wide scope of scientific and industrial processes. Many researchers have examined active devices to implement filters, oscillators, rectifiers, and converters. This paper presents the current differencing operational amplifier (CDOA) as an active element, firstly implemented with CMOS transistors. The input part of this circuit is a current differencing unit and the conventional operational amplifier (Op-Amp) pursues it. A new realization of a notch filter consists of CDOA is suggested. Voltage-mode band-pass filter and current-mode notch filter are presented as a different filter applications. Simulation results using TSMC 0.18-[Formula: see text]m CMOS process model are used to verify the theoretical analyses. The sensitivity, noise, total harmonic distortion (THD) and the Monte Carlo analysis have been performed to demonstrate the effectiveness of the proposed active element and notch filter.

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29

Bojjawar, Satish, and Prabhu G. Benakop. "VLSI Implementation of Low Power FIR Filter using Variable Precision Two-Dimensional Pipeline Gating Multiplier." YMER Digital 21, no. 08 (August 3, 2022): 66–75. http://dx.doi.org/10.37896/ymer21.08/08.

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The low-power FIR filter is required for many DSP applications. The crucial and powerhungry block in the filter is a multiplier. To implement the low power FIR filter a twodimensional variable precision fine-grain pipeline gating technique is introduced in the multiplier. The optimized multiplier is used to implement the transposed form-based FIR filter for the order N = 8 in ASIC design tools from Cadence in CMOS 45nm Technology. The designed FIR filter is compared with the existing multiplier-based FIR filters. The power-saving is achieved by the proposed filter is 22% without any degradation in the speed. The area penalty is 3% only due to the variable precision two-dimensional pipeline gating technique. Keywords: FIR filter, Fine grain pipeline, dynamic power, clock gating, low power multiplier, VLSI, and variable precision.

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30

Addina, Adella Acqha Vico. "Implementation of the Finite Impulse Response (FIR) Filter on the DSK TMS320C6713 Transceiver Using Windowing Techniques." Jurnal Jartel: Jurnal Jaringan Telekomunikasi 6, no. 1 (May 7, 2018): 1–8. http://dx.doi.org/10.33795/jartel.v6i1.128.

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In this study, implementing the FIR filter with the Blackman window and Rectangular window methods with the types of low pass, highpass, and bandpass filters using 2 DSK TMS320C6713 boards as sender (Tx) and receiver (Rx) using the code composer studio (CCS) V software program. .3.1, which will then be displayed on Matlab to observe the output results. From the test results, data will be obtained which are then analyzed to determine the filter performance of the design results and the real implementation results using the DSK TMS320C6713. The results showed that the design of the low pass, high pass and bandpass filters was in accordance with the desired specifications, although in the highpass filter design, the filter results were still incomplete.

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31

Patel, Vandana, and Ankit Shah. "Denoising electrocardiogram signals using multiband filter and its implementation on FPGA." Serbian Journal of Electrical Engineering 19, no. 2 (2022): 115–28. http://dx.doi.org/10.2298/sjee2202115p.

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The electrocardiogram (ECG) signal carries vital information related to cardiac activities. While measuring ECG using electrodes, the signal is contaminated with powerline interference (PLI) from harmonics, baseline wandering (BW), motion artefacts (MA) and high frequency (HF) noise. The extraction of the ECG signal, without the loss of useful information from the noisy environment, is required. Therefore, the selection and implementation of an efficient filter design is proposed. The Finite Impulse Response (FIR)-based multiband needs separate digital filters, such as Lowpass, Highpass, and Bandstop Filter in cascade. The coefficients of the FIR multiband filter are optimised using a least squares optimisation method and realised in a direct form symmetrical structure. The capability of the proposed filter is evaluated on a Physionet ECG ID database, having records of inherent noisy ECG signals. The performance is also verified by measuring the power spectrum of the noisy and filtered ECG waveform. Also, the feasibility of the proposed multiband filter is investigated on Xilinx ISE and the design is implemented on a field programmable gate array (FPGA) platform. A low order simple multiband filter structure is designed and implemented on the reconfigurable FPGA device.

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32

Mousa, Wail A., Said Boussakta, Desmond C. McLernon, and Mirko Van der Baan. "Implementation of 2D explicit depth extrapolation FIR digital filters for 3D seismic volumes using singular value decomposition." GEOPHYSICS 75, no. 1 (January 2010): V1—V12. http://dx.doi.org/10.1190/1.3294424.

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We propose a new scheme for implementing predesigned 2D complex-valued wavefield extrapolation finite impulse response (FIR) digital filters, which are used for extrapolating 3D seismic wavefields. The implementation is based on singular value decomposition (SVD) of quadrantally symmetric 2D FIR filters (extrapolators). To simplify the SVD computations for such a filter impulse response structure, we apply a special matrix transformation on the extrapolation FIR filter impulse responses where we guarantee the retention of their wavenumber phase response. Unlike the existing 2D FIR filter implementation methods that are used for this geophysical application such as the McClellan transformation or its improved version, this implementation via SVD results in perfect circularly symmetrical magnitude and phase wavenumber responses. In this paper, we also demonstrate that the SVD method can save (depending on the filter size) more than 23% of the number of multiplications per output sample and approximately 62% of the number of additions per output sample when compared to direct implementation with quadrantal symmetry via true 2D convolution. Finally, an application to extrapolation of a seismic impulse is shown to prove our theoretical conclusions.

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33

Hansche, Bruce D., J. Jeff Mason, and Fred M. Dickey. "Quad-phase-only filter implementation." Applied Optics 28, no. 22 (November 15, 1989): 4840. http://dx.doi.org/10.1364/ao.28.004840.

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34

Parameshappa, G., and D. Jayadevapp. "Efficient uniform digital filter bank with linear phase and FRM technique for hearing aids." International Journal of Engineering & Technology 7, no. 1.9 (March 1, 2018): 69. http://dx.doi.org/10.14419/ijet.v7i1.9.9738.

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This paper attempts to present an uniform digital filter bank based on linear phase FIR and IIR filters applied for Frequency Response Masking (FRM) technique in hearing aid applications.In the proposed filter bank, nine uniformly spaced sub-bands are formed with the help of half band filters and masking filters. These nine channel FIR filter bank is realized using an interpolated half band linear phase FIR filter and an appropriate number of masking FIR filters. The nine channel IIR filter bank is realized using an interpolated half band approximately linear phase IIR filter and an appropriate number of masking filters. The proposed approximately linear phase IIR half band filter bank is compared with filter bank based on linear phase FIR half band filters in terms of area, power, memory and number of gates needed for implementation. The experiment was carried on various hearing loss cases and the results obtained from these tests proves that, the proposed filter bank achieved the required matching between audiograms and magnitude response of the filter bank at very reasonable range with less computational complexity.

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35

Liu, Ying, Jiang Hua Song, Jia Ning Cui, Ying Wang, and Tie Liu Wang. "Design and Implementation of a Single Clock Dual-Band Switched-Capacitor Filter." Applied Mechanics and Materials 705 (December 2014): 195–98. http://dx.doi.org/10.4028/www.scientific.net/amm.705.195.

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This paper introduces two bands switched capacitor filters which are realized by using a single clock. The chip is LTC1068 that contains four 2 order band-pass filter. By reasonable selection of working mode and clever collocation of resistances to realize two 4 order band-pass filter which used in acoustic receiving amplifier circuit. Amplitude-frequency characteristic curves are tested in paper by frequency sweeper.

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36

Hamad, Rasha W. "Design and FPGA implementation of 11th order Efficient IIR Wavelet Filter Banks with Approximate Linear-phase." Academic Journal of Nawroz University 7, no. 4 (December 21, 2018): 207. http://dx.doi.org/10.25007/ajnu.v7n4a291.

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In this paper. Bireciprocal Lattice Wave Digital Filters (BLWDFs) are utilized in an approximate linear-phase in pass-band design of order IIR wavelet filter banks (FBs). These filter banks are efficiently designed by replacement one of branches for (BLWDFs) by only a unit delay. The coefficients of the designed filter are achieved by simulating the IIR response suggested in [1]. The design is first simulated using Matlab programming in order to investigate the resulting wavelet filter properties and to find the suitable wordlength for the BLWDFs coefficients. FPGA implemtation of the proposed IIR wavelet filter bank is also achived for three levels with less complexity and high operating frequency.

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37

Hamad, Rasha W. "Design and FPGA implementation of 11th order Efficient IIR Wavelet Filter Banks with Approximate Linear-phase." Academic Journal of Nawroz University 7, no. 4 (December 21, 2018): 207. http://dx.doi.org/10.25007/ajnu.v7n4a301.

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Анотація:

In this paper. Bireciprocal Lattice Wave Digital Filters (BLWDFs) are utilized in an approximate linear-phase in pass-band design of order IIR wavelet filter banks (FBs). These filter banks are efficiently designed by replacement one of branches for (BLWDFs) by only a unit delay. The coefficients of the designed filter are achieved by simulating the IIR response suggested in [1]. The design is first simulated using Matlab programming in order to investigate the resulting wavelet filter properties and to find the suitable wordlength for the BLWDFs coefficients. FPGA implemtation of the proposed IIR wavelet filter bank is also achived for three levels with less complexity and high operating frequency.

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38

Balaji, M., and N. Padmaja. "High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 17 (December 31, 2022): 549–56. http://dx.doi.org/10.37394/23203.2022.17.60.

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Digital FIR Filters plays a major role in many signal processing applications. Generally, these filters are designed with multipliers and adders to find the filter output. This paper acquaints how to reduce the complexity of higher order FIR filter by using performance optimization techniques like retiming and pipelining. The filter’s throughput, energy efficiency, and latency, as well as the complexity of its technology, all need to be improved. By adopting pipelining technique, the arithmetic processes of addition and multiplication are separated. The break addition procedure is retimed. The architecture of Pipelining and Retiming with m-tap filters and n-bit word lengths were designed. The smallest delay achieved by the proposed distributed arithmetic-based FIR Filter with pipelining was 2.564ns for a 4tap implementation receiving an 8bit input, while the largest delay achieved was 56.04ns for a 64-tap implementation receiving a 32-bit word length. Delays as low as 0.68ns for a 4-tap implementation receiving an 8-bit input and as high as 4.53ns for a 64tap implementation receiving a 32bit word length have been achieved by using the suggested distributed arithmetic-based FIR Filter with retiming approach. Delay has been reduced by 73.2% for 4tap with 8bit input and by 91.9% for 64tap with 32bit word length compared to the pipelining approach.

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39

Grati, Khaled, Nadia Khouja, Bertrand Le Gal, and Adel Ghazel. "Power Consumption Models for Decimation FIR Filters in Multistandard Receivers." VLSI Design 2012 (May 27, 2012): 1–15. http://dx.doi.org/10.1155/2012/870546.

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Decimation filters are widely used in communication-embedded systems. In fact, decimation filters are useful for implementing channel filtering or selection with low-computation complexity requirements. Many multistandard receiver designs that are required in ubiquitous embedded systems are based on a cascade of decimation filter processing. Filter number and implementation architectures have a significant impact on system performances, such as computation complexity, area, throughput, and power consumption. In this work, we present filter power consumption estimation models for FIR filters. Power consumption models were obtained from a large number of FIR filter syntheses using a direct form. Several curves that estimate power consumption were extracted from these synthesis results. Then, we have evaluated the impact of polyphase decomposition on power consumption of FIR filter and compared it with the direct form results. Some tips regarding power consumption were deduced for the polyphase implementation form. The aim of this work is to help a system designer to select an efficient implementation for FIR in terms of power consumption without having to implement and synthesize the different possible solutions. The proposed method is applied for STMicroelectronics libraries 90 nm and 65 nm low power then validated with a use case of multistandard receiver designing.

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40

Sarika R, Sarika R. "Design and Implementation of GABOR Type Filter on FPGA." International Journal of Scientific Research 3, no. 5 (June 1, 2012): 248–50. http://dx.doi.org/10.15373/22778179/may2014/75.

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41

Basheer, Jamshid M., and Murugesh V. "FPGA Implementation of a Novel Gaussian Filter Using Power Optimized Approximate Adders." Indonesian Journal of Electrical Engineering and Computer Science 11, no. 3 (September 1, 2018): 1048. http://dx.doi.org/10.11591/ijeecs.v11.i3.pp1048-1059.

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Smoothing filters are essential for noise removal and image restoration. Gaussian filters are used in many digital image and video processing systems. Hence the hardware implementation of the Gaussian filter becomes a reliable solution for real time image processing applications. This paper discusses the implementation of a novel Gaussian smoothing filter with low power approximate adders in Field Programmable Gate Array (FPGA). The proposed Gaussian filter is applied to restore the noisy images in the proposed system. Original test images with 512x512 pixels were taken and divided in to 4x4 blocks with 256x256 pixels. The proposed technique has been applied and the performance metrics were measured for various simulation criteria. The proposed algorithm is also implemented using approximate adders, since approximate adders had been recognized as a reliable alternate for error tolerant applications in circuit based metrics such as power, area and delay where the accuracy may be considered for trade off.

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42

Jwo, Dah-Jing, and Amita Biswal. "Implementation and Performance Analysis of Kalman Filters with Consistency Validation." Mathematics 11, no. 3 (January 18, 2023): 521. http://dx.doi.org/10.3390/math11030521.

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This paper provides a useful supplement note for implementing the Kalman filters. The material presented in this work points out several significant highlights with emphasis on performance evaluation and consistency validation between the discrete Kalman filter (DKF) and the continuous Kalman filter (CKF). Several important issues are delivered through comprehensive exposition accompanied by supporting examples, both qualitatively and quantitatively for implementing the Kalman filter algorithms. The lesson learned assists the readers to capture the basic principles of the topic and enables the readers to better interpret the theory, understand the algorithms, and correctly implement the computer codes for further study on the theory and applications of the topic. A wide spectrum of content is covered from theoretical to implementation aspects, where the DKF and CKF along with the theoretical error covariance check based on Riccati and Lyapunov equations are involved. Consistency check of performance between discrete and continuous Kalman filters enables readers to assure correctness on implementing and coding for the algorithm. The tutorial-based exposition presented in this article involves the materials from a practical usage perspective that can provide profound insights into the topic with an appropriate understanding of the stochastic process and system theory.

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43

Jan Kikkert, Cornelis. "A Phasor Measurement Unit Algorithm Using IIR Filters for FPGA Implementation." Electronics 8, no. 12 (December 11, 2019): 1523. http://dx.doi.org/10.3390/electronics8121523.

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Phasor measurement units (PMU) are increasingly used in electrical power transmission networks, to maintain stability and protect the network. PMUs accurately measure voltage, phase, frequency, and rate of change of frequency (ROCOF). For reliability, it is desirable to implement a PMU using an FPGA. This paper describes a novel algorithm, suited to implementation in an FPGA and based on a simple PMU block diagram. A description of its realization using low hardware complexity infinite impulse response (IIR) filters is given. The IEC/IEEE standard 60255-118-1:2018 Part 118-1: Synchrophasor measurements for power systems, describes “reference” Finite Impulse Response (FIR) filters for implementing PMU hardware. At the 10 kHz sampling frequency used for our implementation, each “reference” FIR filter requires 100 multipliers, while an 8th order IIR filter only requires 12 multipliers. This paper compares the performance of different order IIR filter-based PMUs with the performance of the same PMU algorithm using the IEC/IEEE FIR reference filter. The IIR-based PMU easily satisfies all the requirements of IEC/IEEE standard and has a much better out of band signal rejection performance than a FIR-based PMU. Steady state errors for a rated voltage ± 10% and a rated frequency ± 5 Hz are < 0.000001% for total vector error (TVE) and < 1 µHz for frequency, with a latency of two mains cycles.

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44

Ali, Randall, Hannes Rosseel, and Toon van Waterschoot. "Design and implementation of a least-mean-square adaptive notch filter." Journal of the Acoustical Society of America 153, no. 3_supplement (March 1, 2023): A215. http://dx.doi.org/10.1121/10.0018697.

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The task of removing sinusoidal components from observed signals can be accomplished by using a notch filter with a specific attenuation at a particular frequency. In some applications, however, such as acoustic feedback control, the frequency at which attenuation is required is unknown and possibly time-varying, and hence an adaptive notch filter is a more appropriate solution. Transitioning from a fixed notch filter to an adaptive one is by no means trivial and involves the understanding of a range of digital signal processing (DSP) topics from pole-zero placement techniques for designing infinite impulse response filters to optimal and adaptive filtering algorithms. In the signal processing algorithms and implementation graduate course taught at KU Leuven (Belgium), we study the design of an adaptive notch filter, which is based on a constrained biquadratic IIR representation, andwhose parameters are updated using a least-mean-square algorithm. Students also have to implement the algorithm on a 16-bit DSP TMS320C5515. In this presentation, we will discuss the design and implementation challenges of this adaptive notch filter and how it serves as an illustrative example/homework problem where several aspects of DSP are interwoven.

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45

Kaplun, Dmitry, Denis Butusov, Valerii Ostrovskii, Alexander Veligosha, and Vyacheslav Gulvanskii. "Optimization of the FIR Filter Structure in Finite Residue Field Algebra." Electronics 7, no. 12 (December 2, 2018): 372. http://dx.doi.org/10.3390/electronics7120372.

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This paper introduces a method for optimizing non-recursive filtering algorithms. A mathematical model of a non-recursive digital filter is proposed and a performance estimation is given. A method for optimizing the structural implementation of the modular digital filter is described. The essence of the optimization is that by using the property of the residue ring and the properties of the symmetric impulse response of the filter, it is possible to obtain a filter having almost a half the length of the impulse response compared to the traditional modular filter. A difference equation is given by calculating the output sample of modules p1 … pn in the modified modular digital filter. The performance of the modular filters was compared with the performance of positional non-recursive filters implemented on a digital signal processor. An example of the estimation of the hardware costs is shown to be required for implementing a modular digital filter with a modified structure. This paper substantiates the expediency of applying the natural redundancy of finite field algebra codes on the example of the possibility to reduce hardware costs by a factor of two. It is demonstrated that the accuracy of data processing in the modular digital filter is higher than the accuracy achieved with the implementation of filters on digital processors. The accuracy advantage of the proposed approach is shown experimentally by the construction of the frequency response of the non-recursive low-pass filters.

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46

Erdogan, A. T., and T. Arslan. "A Combined Coefficient Segmentation and Block Processing Algorithm for Low Power Implementation of FIR Digital Filters." VLSI Design 15, no. 2 (January 1, 2002): 529–35. http://dx.doi.org/10.1080/1065514021000012147.

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A combined coefficient segmentation and block processing algorithm for low power implementation of FIR digital filters is described in this paper. The algorithm processes data and coefficients in blocks of fixed sizes. During the manipulation of each block, coefficients are segmented into two primitive components. The accumulative effect of processing a sequence of blocks and segmentation results in up to 80% reduction in power consumption in the multiplier circuit compared to conventional filtering. The paper describes the implementation of the algorithm, its constituent components, and the power evaluation environment developed. Simulations are performed using eight practical digital filter examples with various filter orders and data/coefficient wordlengths. In addition, the algorithm is compared with conventional filtering implementations and those using block processing and coefficient segmentation algorithms alone.

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47

Sac, Maciej, and Marek Blok. "A Nearly Optimal Fractional Delay Filter Design Using an Asymmetric Window." International Journal of Electronics and Telecommunications 57, no. 4 (December 1, 2011): 465–72. http://dx.doi.org/10.2478/v10177-011-0065-0.

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A Nearly Optimal Fractional Delay Filter Design Using an Asymmetric WindowIn this paper a numerically efficient filter design method suitable for variable fractional delay (VFD) filter implementation is investigated. We propose to use a well known window method with an asymmetric window extracted from optimal filter designed beforehand. As we will demonstrate, such an approach, if additional gain correction is applied, allows for nearly optimal VFD filter design. Thus, the proposed approach combines window method simplicity with performance comparable to that of optimal filters. Efficiency of the presented technique makes it suitable for designing filters with varying delay in real time.

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48

LIU, XIAOJIAN, and LEONARD T. BRUTON. "PARALLEL COMPUTING IN MULTIDIMENSIONAL RECURSIVE FILTERING." International Journal of High Speed Electronics and Systems 04, no. 02 (June 1993): 219–43. http://dx.doi.org/10.1142/s0129156493000108.

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This paper introduces and generalizes a number of multidimensional (MD) recursive parallel filter algorithms, which are based on the principles of orthogonal and diagonal computing, respectively. Efficient software and hardware implementation methods for the proposed parallel algorithms are presented. In particular, it is shown that systolic array implementations can be achieved for MD parallel filter structures that are locally interconnected and have a critical path of 1 multiplication plus 1 addition. In this way, the proposed parallel filters are easily able to perform real-time processing at video rates.

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49

Melzer, Alexander, Andreas Pedross, and Manfred Mücke. "Holistic Biquadratic IIR Filter Design for Communication Systems Using Differential Evolution." Journal of Electrical and Computer Engineering 2013 (2013): 1–14. http://dx.doi.org/10.1155/2013/741251.

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Digital IIR filter implementations are important building blocks of most communication systems. The chosen number format (fixed-point, floating-point; precision) has a major impact on achievable performance and implementation cost. Typically, filter design for communication systems is based on filter specifications in the frequency domain. We consider IIR filter design as an integral part of communication system optimisation with implicit filter specification in thetime domain(via symbol/bit error rate). We present a holistic design flow with the system's bit error rate as the main objective. We consider a discrete search space spanned by the quantised filter coefficients.Differential Evolutionis used for efficient sampling of this huge finite design space. We present communication system performance (based on bit-true simulations) and both measured and estimated receiver IIR chip areas. The results show that very small number formats are acceptable for complex filters and that the choice between fixed-point and floating-point number formats is nontrivial if precision is a free parameter.

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50

Khine, Lynn, Lionel Y. L. Wong, Jeffrey B. W. Soon, and Ming Lin Julius Tsai. "FBAR Resonators with Sufficient High Q for RF Filter Implementation." Advanced Materials Research 254 (May 2011): 70–73. http://dx.doi.org/10.4028/www.scientific.net/amr.254.70.

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Film Bulk Acoustic Wave Resonators (FBAR) at 2.6GHz using AlN piezoelectric material have been fabricated and characterized in this work. A stack of Al bottom electrode, AlN layer and top Al electrode is used to excite the thickness extensional (TE) vibration mode. The FBAR resonator has a quality factor of about 400 and the piezoelectric coupling coefficient of 4.25%, which is critical for RF filter implementation. Moreover, FBAR resonator has been designed to suppress spurious modes in order to ensure higher quality factor. Different filter topologies of ladder/lattice architecture are then explored for effective implementation using several FBAR resonators to build band-pass RF filters.

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