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Статті в журналах з теми "Field Programmable Gate Arrays"

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Автор: Grafiati

Опубліковано: 4 червня 2021

Оновлено: 29 липня 2024

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1

Marchal, Pierre. "Field-programmable gate arrays." Communications of the ACM 42, no. 4 (April 1999): 57–59. http://dx.doi.org/10.1145/299157.299594.

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2

Verma, H. "Field programmable gate arrays." IEEE Potentials 18, no. 4 (1999): 34–36. http://dx.doi.org/10.1109/45.796099.

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3

Lombardi, F. "Field Programmable Gate-Arrays." IEEE Design & Test of Computers 15, no. 1 (January 1998): 8–9. http://dx.doi.org/10.1109/mdt.1998.655176.

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4

Bhatia, Dinesh. "Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (January 1, 1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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5

Hurst, S. L. "Field programmable gate arrays." Microelectronics Journal 28, no. 1 (January 1997): 102. http://dx.doi.org/10.1016/s0026-2692(97)87854-8.

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6

Hurst, S. L. "Field-programmable gate arrays." Microelectronics Journal 25, no. 1 (February 1994): 77–78. http://dx.doi.org/10.1016/0026-2692(94)90166-x.

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7

Jay, Christopher. "Field programmable gate arrays." Microprocessors and Microsystems 17, no. 7 (September 1993): 370. http://dx.doi.org/10.1016/0141-9331(93)90058-f.

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8

Greene, J., E. Hamdy, and S. Beal. "Antifuse field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (July 1993): 1042–56. http://dx.doi.org/10.1109/5.231343.

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9

Leon, A. F. "Field programmable gate arrays in space." IEEE Instrumentation & Measurement Magazine 6, no. 4 (December 2003): 42–48. http://dx.doi.org/10.1109/mim.2003.1251482.

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10

Rose, J., A. El Gamal, and A. Sangiovanni-Vincentelli. "Architecture of field-programmable gate arrays." Proceedings of the IEEE 81, no. 7 (July 1993): 1013–29. http://dx.doi.org/10.1109/5.231340.

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11

Leeser, Miriam, Scott Hauck, and Russell Tessier. "Field-Programmable Gate Arrays in Embedded Systems." EURASIP Journal on Embedded Systems 2006, no. 1 (2006): 051312. http://dx.doi.org/10.1186/1687-3963-2006-051312.

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12

Dettmer, R. "Onwards and upwards [field programmable gate arrays]." IEE Review 51, no. 12 (December 1, 2005): 40–43. http://dx.doi.org/10.1049/ir:20051204.

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13

Ting-Ting Hwang, R. M. Owens, M. J. Irwin, and Kuo Hua Wang. "Logic synthesis for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 10 (1994): 1280–87. http://dx.doi.org/10.1109/43.317471.

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14

Dasgupta, S., and D. Cussans. "Field Programmable Gate Arrays—Detecting Cosmic Rays." Journal of Instrumentation 10, no. 07 (July 9, 2015): C07006. http://dx.doi.org/10.1088/1748-0221/10/07/c07006.

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15

Erbagci, Burak, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, and Ken Mai. "Secure hardware-entangled field programmable gate arrays." Journal of Parallel and Distributed Computing 131 (September 2019): 81–96. http://dx.doi.org/10.1016/j.jpdc.2019.04.002.

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16

Mintzer, Les. "FIR filters with field-programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 2 (August 1993): 119–27. http://dx.doi.org/10.1007/bf01607876.

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17

Hurst, S. L. "Logic synthesis for field-programmable gate arrays." Microelectronics Journal 27, no. 8 (November 1996): 803–4. http://dx.doi.org/10.1016/0026-2692(96)82780-7.

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18

Leeser, Miriam, Scott Hauck, and Russell Tessier. "Field-Programmable Gate Arrays in Embedded Systems." EURASIP Journal on Embedded Systems 2006 (2006): 1–2. http://dx.doi.org/10.1155/es/2006/51312.

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19

AHUJA, SUMIT, and S. K. BALASUBRAMANIAN. "Field Programmable Gate Arrays Based Overcurrent Relays." Electric Power Components and Systems 32, no. 3 (March 2004): 247–55. http://dx.doi.org/10.1080/15325000490207769.

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20

Sangiovanni-Vincentelli, A., A. El Gamal, and J. Rose. "Synthesis method for field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (July 1993): 1057–83. http://dx.doi.org/10.1109/5.231344.

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21

Louie, Marianne E., and Milos D. Ercegovac. "Implementing division with field programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 7, no. 3 (October 1994): 271–85. http://dx.doi.org/10.1007/bf02409403.

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22

Sergienko, Anatolij M., Vitalij O. Romankevich, and Pavlo A. Serhiienko. "Image buffering in application specific processors." Applied Aspects of Information Technology 5, no. 3 (October 25, 2022): 228–39. http://dx.doi.org/10.15276/aait.05.2022.16.

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Анотація:

In many digital image-processingapplications, which are implementedin field programmable gate arrays,the currently processed image's frames are stored in external dynamic memory.The performance of such an application dependson the dynamic memoryspeed and the necessaryrequests quantity during algorithm’sruntime. This performance is being optimized through field programmable gate arrays -implemented buffer memory usage.But there is no common method for the formal buffer memory synthesis with preset throughput, input and output data sequenceorderand minimizedhardwarecosts.In this article,the featuresof image input and processing based on Field Programmable Gate Arrayareconsidered.The methods of building buffer circuits in field programmable gate arrays, due to which the intensity of data exchanges with external memory is reduced, are analyzed. Themethod of synthesizing pipeline circuits with specified performance characteristics and the data sequence order is given, which is based on the mapping of the spatial synchronous data flows into the structure implemented in the field programmable gate arrays.A method of designing buffer schemes is proposed, which is based on the mapping of spatial synchronous data flows into local memory in the form of chains of pipeline registers.The method helpsto organize the data flow of at the input of built-in pipeline units of image processing, in which the data follow in a given order, andto minimize the amount of buffer memory.The method ensures the use of dynamically adjustable register delays built into the field programmable gate arrays, which increases the efficiency of buffering.Thismethod was tested during the development of an intelligent video camera. The embedded hardware implements a video image compression algorithm with a wide dynamic range according to the Retinexalgorithm. The same time it selects characteristic points in the image for the further pattern recognition.At the same time, multiple decimation of the frame is performed. Due to themultirate buffering of the image in the field programmable gate arrays,it was possible to avoid using of external dynamic memory

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23

Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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Анотація:

The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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24

Ogurtsov, A. A. "Conducting functional control of field-programmable gate arrays." VESTNIK of Samara University. Aerospace and Mechanical Engineering 16, no. 4 (January 22, 2018): 137. http://dx.doi.org/10.18287/2541-7533-2017-16-4-137-146.

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25

Brown, S., J. Rose, and Z. G. Vranesic. "A detailed router for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11, no. 5 (May 1992): 620–28. http://dx.doi.org/10.1109/43.127623.

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26

Reiss, G., and D. Meyners. "Reliability of field programmable magnetic logic gate arrays." Applied Physics Letters 88, no. 4 (January 23, 2006): 043505. http://dx.doi.org/10.1063/1.2167609.

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27

Lum, G. K., R. J. May, and L. E. Robinette. "Total dose hardness of field programmable gate arrays." IEEE Transactions on Nuclear Science 41, no. 6 (December 1994): 2487–93. http://dx.doi.org/10.1109/23.340606.

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28

Joginipelly, Arjun Kumar, and Dimitrios Charalampidis. "Efficient separable convolution using field programmable gate arrays." Microprocessors and Microsystems 71 (November 2019): 102852. http://dx.doi.org/10.1016/j.micpro.2019.102852.

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29

Bogdan, IstvÁn A., Daniel Coca, and Rob J. Beynon. "Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays." IEEE Transactions on Biomedical Circuits and Systems 3, no. 3 (June 2009): 142–49. http://dx.doi.org/10.1109/tbcas.2008.2010945.

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30

Yazdanshenas, Sadegh, and Vaughn Betz. "Interconnect Solutions for Virtualized Field-Programmable Gate Arrays." IEEE Access 6 (2018): 10497–507. http://dx.doi.org/10.1109/access.2018.2806618.

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31

Howard, N. J., A. M. Tyrrell, and N. M. Allinson. "The yield enhancement of field-programmable gate arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 1 (March 1994): 115–23. http://dx.doi.org/10.1109/92.273147.

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32

Fagin, B., and C. Renard. "Field programmable gate arrays and floating point arithmetic." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2, no. 3 (September 1994): 365–67. http://dx.doi.org/10.1109/92.311646.

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33

Yen-Tai Lai and Ping-Tsung Wang. "Hierarchical interconnection structures for field programmable gate arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5, no. 2 (June 1997): 186–96. http://dx.doi.org/10.1109/92.585219.

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34

Banerjee, P., D. Saha, and S. Sur-Kolay. "Cone-based placement for field programmable gate arrays." IET Computers & Digital Techniques 5, no. 1 (2011): 49. http://dx.doi.org/10.1049/iet-cdt.2009.0058.

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35

McNelles, Phillip, and Lixuan Lu. "ICONE23-1171 DESIGN OF A TRITIUM-IN-AIR-MONITOR USING FIELD PROGRAMMABLE GATE ARRAYS." Proceedings of the International Conference on Nuclear Engineering (ICONE) 2015.23 (2015): _ICONE23–1—_ICONE23–1. http://dx.doi.org/10.1299/jsmeicone.2015.23._icone23-1_93.

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36

VENKATESWARAN, N., S. PATTABIRAMAN, J. DESOUZA, G. SRIRAM, R. SRINIVASAN, R. SANKAR, and G. SURESH. "A DESIGN METHODOLOGY FOR VERY LARGE ARRAY PROCESSORS-PART 2: PACUBE VLSI ARRAYS." International Journal of Pattern Recognition and Artificial Intelligence 09, no. 02 (April 1995): 263–301. http://dx.doi.org/10.1142/s0218001495000134.

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Анотація:

The types of functional VLSI chips needed for general and special purpose (computationally intensive) applications are wide ranging, Hence, to reduce the turn-around time of these VLSI chips, mask/field programmable PLAs, gate arrays SLAs and FPGAs are available. However these VLSI arrays are unsuitable for designing ultrahigh performance special purpose VLSI chips. There is a strong need for developing a suitable mask programmable VLSI structures exclusively for designing ultrahigh performance and cost-effective special purpose systems. For this purpose, a macro cell based mask programmable Pacube (PA3—Programmable Array of Array Adders) VLSI array is proposed in this paper. These arrays can be mask programmed for building cost-effective super computing VLSI functional units. Another important feature is the architecture of the macro-cell, which is designed in such a way that the functional units corresponding to the G-set equations when mapped on the macro-cell arrays possess identical data flow control. This leads to a highly simplified control design for executing complex computations.

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37

Amer Abbas, Yasir, Razali Jidin, Norziana Jamil, Muhammad Reza Z\'aba, and Mohd Ezanee Rusli. "PRINCE IP-core on Field Programmable Gate Arrays (FPGA)." Research Journal of Applied Sciences, Engineering and Technology 10, no. 8 (July 20, 2015): 914–22. http://dx.doi.org/10.19026/rjaset.10.2447.

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38

Rais. "Field Programmable Gate Arrays Based Realization of Truncated Multipliers." American Journal of Applied Sciences 8, no. 7 (July 1, 2011): 681–84. http://dx.doi.org/10.3844/ajassp.2011.681.684.

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39

Ababei, Cristinel, Shaun Duerr, William Joseph Ebel Jr., Russell Marineau, Milad Ghorbani Moghaddam, and Tanzania Sewell. "Open Source Digital Camera on Field Programmable Gate Arrays." International Journal of Handheld Computing Research 7, no. 4 (October 2016): 30–40. http://dx.doi.org/10.4018/ijhcr.2016100103.

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Анотація:

We present an open source digital camera implemented on a field programmable gate array (FPGA). The camera functionality is completely described in VHDL and tested on the DE2-115 educational FPGA board. Some of the current features of the camera include video mode at 30 fps, storage of taken snapshots into SDRAM memories, and grayscale and edge detection filters. The main contributions of this project include 1) the actual system level design of the camera, tested and verified on an actual FPGA chip, and 2) the public release of the entire implementation including source code and documentation. While the proposed camera is far from being able to compete with commercial offerings, it can serve as a framework to test new research ideas related to digital camera systems, image processing, computer vision, etc., as well as an educational platform for advanced digital design with VHDL and FPGAs. As examples of that, we report two spin-off projects developed on top of or starting from the presented digital camera system.

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40

Chan, P. K., M. D. F. Schlag, C. Ebeling, and L. McMurchie. "Distributed-memory parallel routing for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19, no. 8 (2000): 850–62. http://dx.doi.org/10.1109/43.856973.

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41

Fei Li, Y. Lin, Lei He, Deming Chen, and J. Cong. "Power modeling and characteristics of field programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, no. 11 (November 2005): 1712–24. http://dx.doi.org/10.1109/tcad.2005.852293.

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42

Teng, Bill, and J. H. Anderson. "Latch-Based Performance Optimization for Field-Programmable Gate Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, no. 5 (May 2013): 667–80. http://dx.doi.org/10.1109/tcad.2012.2235913.

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43

Poon, Kara K. W., Steven J. E. Wilton, and Andy Yan. "A detailed power model for field-programmable gate arrays." ACM Transactions on Design Automation of Electronic Systems 10, no. 2 (April 2005): 279–302. http://dx.doi.org/10.1145/1059876.1059881.

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44

Lai, Y. T., and C. C. Kao. "Technology mapping algorithm for heterogeneous field programmable gate arrays." IEE Proceedings - Computers and Digital Techniques 149, no. 6 (2002): 249. http://dx.doi.org/10.1049/ip-cdt:20020748.

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45

MacQueen, D. M., D. M. Gingrich, and N. J. Buchanan. "Ionizing radiation effects in XC4036X field programmable gate arrays." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 479, no. 2-3 (March 2002): 603–10. http://dx.doi.org/10.1016/s0168-9002(01)00947-0.

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46

Conti, Vincenzo, Carmelo Militello, Filippo Sorbello, and Salvatore Vitabile. "Biometric sensors rapid prototyping on field-programmable gate arrays." Knowledge Engineering Review 30, no. 2 (March 2015): 201–19. http://dx.doi.org/10.1017/s0269888914000307.

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Анотація:

AbstractBiometric user authentication in large-scale distributed systems involves passive scanners and networked workstations and databases for user data acquisition, processing, and encryption. Unfortunately, traditional biometric authentication systems are prone to several attacks, such as Replay Attacks, Communication Attacks, and Database Attacks. Embedded biometric sensors overcome security limits of conventional software recognition systems, hiding its common attack points. The availability of mature reconfigurable hardware technology, such as field-programmable gate arrays, allows the developers to design and prototype the whole embedded biometric sensors. In this work, two strong and invasive biometric traits, such as fingerprint and iris, have been considered, analyzed, and combined in unimodal and multimodal biometric sensors. Biometric sensor performance has been evaluated using the well-known FVC2002, CASIA, and BATH databases.

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47

López, Aitor, Daniel Pérez, Prometheus DasMahapatra, and José Capmany. "Auto-routing algorithm for field-programmable photonic gate arrays." Optics Express 28, no. 1 (January 3, 2020): 737. http://dx.doi.org/10.1364/oe.382753.

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48

Rose, J., and S. Brown. "Flexibility of interconnection structures for field-programmable gate arrays." IEEE Journal of Solid-State Circuits 26, no. 3 (March 1991): 277–82. http://dx.doi.org/10.1109/4.75006.

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49

Tickle, A. J., J. S. Smith, and Q. H. Wu. "Development of morphological operators for field programmable gate arrays." Journal of Physics: Conference Series 76 (July 1, 2007): 012028. http://dx.doi.org/10.1088/1742-6596/76/1/012028.

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50

Buchanan, N. J., and D. M. Gingrich. "Proton radiation effects in XC4036XLA field programmable gate arrays." IEEE Transactions on Nuclear Science 50, no. 2 (April 2003): 263–71. http://dx.doi.org/10.1109/tns.2003.809468.

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