Дисертації: "Field Programmable Counter Arrays"

1

Карнаушенко, В. П., and А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between Field Programmable Gates Arrays (FPGA) and Application Specified Integrated Circuits (ASICs) for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.

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2

Attarzadeh, Niaki Seyed Hosein. "Design Space Exploration Of Field Programmable Counter Arrays And Their Integration With FPGAs." Thesis, KTH, Elektronik- och datorsystem, ECS, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-46479.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions. The first contribution of this work is a Design Space Exploration (DSE) of the FPCAs and the identification of trade-offs between different parameters which describe them. Methods for analyzing and pruning the design space are proposed to enable a smart exploration. Finally, a set of best performing architectures in terms of area and delay is determined. Secondly, a study of possible integration schemes to build a hybrid FPGA/FPCA chip is performed. The goal is to find a solution with optimal usage of on-chip silicon area. The advantages and disadvantages of each solution are studied and a new integration solution based on properties of FPCAs is suggested. A VLSI implementation proves the applicability of the proposed solutions.

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3

Sven, Engström. "A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction." Thesis, Linköpings universitet, Datorteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171111.

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This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps.

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4

Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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5

Messa, Norman C. "Design implementation into field programmable gate arrays." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

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6

Niu, Jianyong. "Digital control using field programmable gate arrays." Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.

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7

Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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8

Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays." Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.

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As the logic capacity of FPGAs continues to increase with deep submicron technology, performing a full recompilation for small iterative changes in a large design is an extremely time-consuming and costly process. To address this issue, this thesis presents a new incremental placement algorithm for FPGAs named "iPlace" that significantly reduces the time required for recompilation. The iPlace algorithm is based on shifting, compaction, and annealing. Key ideas from the algorithm include a placement super-grid that is larger than the physical size of the FPGA. The super-grid allows insertion of additional CLBs into areas with no free locations by CPU-efficient shifting. This is followed by a compaction scheme to re-legalize CLBs that are shifted to illegal locations outside of the physical size of the FPGA. The algorithm ends with a low-temperature anneal to improve quality. This algorithm is capable of handling multiple design changes across large regions of a FPGA. This is especially useful for hierarchical designs where sub-circuits are re-used multiple times. If one such sub-circuit is modified, iPlace can quickly produce a high quality incremental placement solution. For a single region of design change, we found that iPlace is 34 to 260 times faster than the academic tool Versatile Place and Route (VPR) in default mode. Compared to VPR's reduced-quality "-fast" placement option, iPlace is 3 to 28 times faster with equivalent quality. For multiple regions of design changes, iPlace is still 50-70 times faster compared to VPR in default mode when up to 2/3 of the CLBs are modified; Compared to the "-fast" placement option, iPlace is still 5-8 times faster. We believe that iPlace is the first academically available incremental placement algorithm capable of handling significant changes to a netlist for very large circuits.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate

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9

Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.

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10

Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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11

Hall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.

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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

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12

James, Calvin L. "COMPLEX WAVEFORM GENERATION UTILIZING FIELD PROGRAMMABLE GATE ARRAYS." International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/609692.

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International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada
The basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications. In addition, this self containment property significantly reduces implementation costs by reducing the number of external components required to support many applications. This paper examines the use of FPGA’s in various complex waveform generation applications. In particular, a discussion will ensue examining possible mappings of the time domain response of the complex waveform into memory elements of the FPGA. The analyses and examples contained in the sequel are from existing waveform generation applications, developed for Gauissian Minimum Shift Keying (GMSK) and Unbalanced Quadriphase Shift Keying (UQPSK) modulation formats.

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13

Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.

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14

Dixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.

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15

Mutlu, Baris Ragip. "Real-time Motion Control Using Field Programmable Gate Arrays." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612049/index.pdf.

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In this thesis, novel implementation methods for FPGA based real-time motion control systems are investigated. These methods are examined for conventional and modern controller topologies as well as peripheral device interfaces which are mutually essential pieces of a motion controller. The developed methods are initially tested one by one to assess the performance of the individual design
and finally an assembled solution is developed to test the overall design. Tests of the overall design are realized via hardware-in-the-loop simulation of a real-world control problem, selected as a CNC machining center. The developed methods are discussed in terms of their success, resource consumptions and attainable sampling rates.

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16

Luo, Ji. "Circuit design and routing for field programmable analog arrays." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3167.

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Thesis (Ph. D.) -- University of Maryland, College Park, 2005.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

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17

Källström, Petter. "Direct Digital Frequency Synthesis in Field-Programmable Gate Arrays." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56550.

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This thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).

Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.

Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA).

Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.

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18

Raina, Baljit Singh. "Delay-optimized placement in symmetrical field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31862.pdf.

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19

Tickle, Andrew Jason. "Applications of Morphological Operators on Field Programmable Gate Arrays." Thesis, University of Liverpool, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.507628.

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20

Ambat, Shadab Gopinath. "SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS." UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/511.

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The high-radiation environment in space can lead to anomalies in normal satellite operation. A major cause of concern to spacecraft-designers is the single event upset (SEU). SEUs can result in deviations from expected component behavior and are capable of causing irreversible damage to hardware. In particular, Field Programmable Gate Arrays (FPGAs) are known to be highly susceptible to SEUs. Radiation-hardened versions of such devices are associated with an increase in power consumption and cost in addition to being technologically inferior when compared to contemporary commercial-off-the-shelf (COTS) parts. This thesis consequently aims at exploring the option of using COTS FPGAs in satellite payloads. A framework is developed, allowing the SEU susceptibility of such a device to be studied. SEU testing is carried out in a software-simulated fault environment using a set of Java classes called JBits. A radiation detector module, to measure the radiation backdrop of the device, is also envisioned as part of the final design implementation.

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21

Self, R. P. "Software-orientated system design for field programmable gate arrays." Thesis, University of Essex, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.397736.

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22

Gray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.

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Floating-gate transistors similar to those used in FLASH and EEPROM can be used to build reconfigurable analog arrays. The charge on the floating gate can be modified to pass or block a signal in a cross-bar switch matrix, or it can be finely tuned to eliminate a threshold difference across a chip or set a bias. By using such a compact and versatile reconfigurable analog memory element, the number of analog circuit components included on an integrated circuit that is field-programmable is significantly higher. As a result, large-scale FPAAs can be built with the same impact on analog design that FPGAs have had on digital design. In my research, I investigate the areas floating-gate transistors can be used to impact FPAA design and implementation. An FPAA can be broken up into two basic components, elements of connection and elements of computation. With respect to connection, I show that a floating-gate switch can be used in a cross-bar matrix in place of a transmission gate resulting in less parasitic capacitance and a more linear resistance for the same size transistor. I illuminate the programming issues relating to injecting a floating-gate for use as a switch, including the drain selection circuitry and rogue injection due to gate induced drain leakage. With respect to computation, I explain how a Multiple-Input Translinear Element, or MITE, can be augmented to fit in an FPAA framework. I also discuss two different MITE implementations compatible with CMOS technology, a subthreshold MOS design and a BJT MITE that uses a lateral BJT. Beyond FPAA components, I present two alternative FPAA systems. The first is a general purpose reconfigurable analog system that uses standard analog design components that have been augmented with floating-gates. The second FPAA is built upon MITE circuits, and is focused on supporting direct system synthesis. I conclude with a discussion of a future large-scale MITE FPAA.

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23

Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.

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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.

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24

Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.

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25

MacQueen, Daniel Montgomery. "Total ionizing dose effects on Xilinx field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ59840.pdf.

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26

Sareen, Aman. "Reconfigurable design for pattern recognition using field programmable gate arrays." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175625525.

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27

Royal, Andrew Peter. "Globally asynchronous locally synchronous interconnect for field programmable gate arrays." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.415717.

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28

Gundam, Madhuri. "Implementation of Directional Median Filtering using Field Programmable Gate Arrays." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/111.

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Median filtering is a non-linear filtering technique which is effective in removing impulsive noise from data. In this thesis, directional median filtering has been implemented using cumulative histogram of samples in several directions. Different methods to implement directional median filtering have been proposed. The filtered images are smoothed along the direction of the filtering window. All implementations aimed to generate outputs in the least amount of time, while reducing the resource utilization on hardware. The implementation methods were designed for Xilinx Virtex 5 FPGA devices but were also attempted on Spartan 3E. The proposed methods used less than 30% of the resources on Virtex 5 FPGA but the resource utilization on Spartan 3E exceeded the number of available resources. After an initial delay, methods 1 and 2 generate a new output for every 5 clock cycles while method 3 generates an output for every 1.5 clock cycles.

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29

Davis, James. "Low-overhead fault-tolerant logic for field-programmable gate arrays." Thesis, Imperial College London, 2015. http://hdl.handle.net/10044/1/44382.

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While allowing for the fabrication of increasingly complex and efficient circuitry, transistor shrinkage and count-per-device expansion have major downsides: chiefly increased variation, degradation and fault susceptibility. For this reason, design-time consideration of faults will have to be given to increasing numbers of electronic systems in the future to ensure yields, reliabilities and lifetimes remain acceptably high. Many mathematical operators commonly accelerated in hardware are suited to modification resulting in datapath error detection and correction capabilities with far lower area, performance and/or power consumption overheads than those incurred through the utilisation of more established, general-purpose fault tolerance methods such as modular redundancy. Field-programmable gate arrays are uniquely placed to allow further area savings to be made thanks to their dynamic reconfigurability. The majority of the technical work presented within this thesis is based upon a benchmark hardware accelerator - a matrix multiplier - that underwent several evolutions in order to detect and correct faults manifesting along its datapath at runtime. In the first instance, fault detectability in excess of 99% was achieved in return for 7.87% additional area and 45.5% extra latency. In the second, the ability to correct errors caused by those faults was added at the cost of 4.20% more area, while 50.7% of this - and 46.2% of the previously incurred latency overhead - was removed through the introduction of partial reconfiguration in the third. The fourth demonstrates further reductions in both area and performance overheads - of 16.7% and 8.27%, respectively - through systematic data width reduction by allowing errors of less than ±0.5% of the maximum output value to propagate.

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30

Pereira, Gustavo Vieira. "Teste da rede de interconexões de field programmable analog arrays." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6305.

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Os dispositivos analógicos programáveis (FPAAs, do inglês, Field Programmable Analog Arrays), apesar de ainda não terem a mesma popularidade de seus pares digitais (FPGAs, do inglês, Field Programmable Gate Arrays), possuem uma gama de aplicações bastante ampla, que vai desde o condicionamento de sinais em sistemas de instrumentação, até o processamento de sinais de radiofreqüência (RF) em telecomunicações. Porém, ao mesmo tempo em que os FPAAs trouxeram um impressionante ganho na agilidade de concepção de circuitos analógicos, também trouxeram um conjunto de novos problemas relativos ao teste deste tipo de dispositivo. Os FPAAs podem ser divididos em duas partes fundamentais: seus blocos programáveis básicos (CABs, do inglês, Configurable Analog Blocks) e sua rede de interconexões. A rede de interconexões, por sua vez, pode ser dividida em duas partes: interconexões internas (locais e globais entre CABs) e interconexões externas (envolvendo células de I/O). Todas estas partes apresentam características estruturais e funcionais distintas, de forma que devem ser testadas separadamente, pois necessitam que se considerem modelos de falhas, configurações e estímulos de teste específicos para assegurar uma boa taxa de detecção de defeitos. Como trabalhos anteriores já estudaram o teste dos CABs, o foco desta dissertação está direcionado ao desenvolvimento de metodologias que se propõem a testar a rede de interconexões de FPAAs. Apesar das várias diferenças entre as redes de interconexões de FPGAs e FPAAs, muitas também são as semelhanças entre elas, sendo, portanto, indiscutível que o ponto de partida deste trabalho tenha que ser o estudo das muitas técnicas propostas para o teste de interconexões em FPGAs, para posterior adaptação ao caso dos FPAAs. Além disto, embora o seu foco não recaia sobre o teste de CABs, pretende-se utilizá-los como recursos internos do dispositivo passíveis de gerar sinais e analisar respostas de teste, propondo uma abordagem de auto-teste integrado de interconexões que reduza o custo relativo ao equipamento externo de teste. Eventualmente, estes mesmos recursos poderão também ser utilizados para diagnóstico das partes defeituosas. Neste trabalho, utiliza-se como veículo de experimentação um dispositivo específico (Anadigm AN10E40), mas pretende-se que as metodologias de teste propostas sejam abrangentes e possam ser facilmente adaptadas a outros FPAAs comerciais que apresentem redes de interconexão semelhantes.

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31

Papadonikolakis, Markos. "Mapping of support vector machines on field programmable gate arrays." Thesis, Imperial College London, 2012. http://hdl.handle.net/10044/1/10004.

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Support Vector Machines (SVMs) are a powerful supervised learning method in the field of Machine Learning, which has drawn a lot of attention in the last two decades due to their high effectiveness and demonstrated prediction accuracy for a wide range of classification and regression tasks. Belonging to the class of supervised learning, this method comprises of two distinct phases, the SVM training and classification. When targeting large-scale problems, both SVM training and classification phases suffer from high execution times, due to their superlinear dependencies on the problem’s dimensionality and size. Therefore, that is an urgent need to accelerate these heavy load tasks, especially when the application imposes real-time constraints. The evolution and technology improvements on reconfigurable logic and, more specifically, the Field Programmable Gate Arrays (FPGAs) allow for the dedication of hardware resources to accelerate time consuming tasks. In the SVM case this is highly favorable, due to the potential for parallelization that the SVM training and classification tasks present. Moreover, many real-world classification problems present different and diverse precision and dynamic range requirements among their features. This is a strong motivation for the investigation and proposal of hardware-mapped architectures to accelerate the SVM training and classification. The FPGAs, due to their inherited custom-arithmetic potential and reconfigurability allow for the exploitation of this heterogeneity of different classification problems. This work focuses on the proposal of hardware-oriented architectures which can exploit the FPGA’s parallel processing potential, the reconfigurability and their custom precision-arithmetic in efficient ways, in order to accelerate the computational intensive tasks of SVM training and classification. The objective is to create highly scalable and adaptive FPGA architectures, which are able to maximize the utilized parallelization of the hardware resources, with respect to the problem’s characteristics and the application’s resource constraints. In this context, this work has proposed a heterogeneous FPGA architecture for the SVM training which allows for the exploitation of the targeted problem’s characteristics, such as the dimensionality and the precision requirements. The proposed architecture is a fully scalable solution, which maps the available FPGA resources in efficient ways, in order to increase parallelism and improve the SVM training performance. The scalability of the FPGA architecture is enhanced by the proposal of an algorithmic flow that balances the utilization of the heterogeneous resources allows for designing problem-specific circuits. This proposed FPGA architecture outperforms previous hardware-mapped approaches by more than 3 times in raw computational power. Further highlighting the achievements of this PhD work, this heterogeneous mapping idea is also exploited for the SVM classification, resulting in the proposal of the first cascade FPGA-based classifier, which exploits the FPGA reconfigurability in order to further improve the SVM classification time performance. For instance, this proposed architecture achieves in doubling the front-end system throughput of the SVM classification by a factor of 2 on a popular dataset, without introducing any resource utilization penalty.

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32

Brown, Simon James. "Fault-tolerance of field-programmable gate arrays subjected to radiation." Thesis, University of Salford, 2010. http://usir.salford.ac.uk/26592/.

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This thesis describes a technology and methodology designed and developed for the study of certain aspects of reliability in digital electronics sub-systems, as implemented on field-programmable gate arrays (FPGAs), while being subjected to small-scale sources of radiation. The technology developed is in the form of a platform for the FPGA under investigation, and an associated configuration and test system. The platforms for the devices are exchangeable, so that a range of different generations, manufacturers and models of FPGA, or other processing element, can be investigated. The circuit boards have been designed to fit inside a small volume, in order to be accommodated by a typical laboratory desk-top source of radiation such as neutrons, alpha or beta particles. To maximise it's usefulness, the test system was designed to be used for a wide range of investigations and prototyping projects. In order to prove the applicability of the system developed, an experiment was run. A triple-module redundant (TMR) system is constructed to test the raw susceptibility of the underlying FPGAs to faults, and to test how well the TMR system copes with correcting such errors. This is done while the whole system is subjected to ionizing radiation in the form of neutrons. This reveals the effects of radiation on the ICs, and provides an accelerated test for tolerance to other potential causes of faults. We are looking for - - confirmation of theory and other's measurements on upset rate - confirmation that fault-tolerance works We conclude that: (1) the experimental test system passed the required tests and measurements, and produces results, (2) the SEU rate, as measured in the example experiment, is consistent with expectations, and (3) a conventional commercial FPGA, programmed to perform a function reliably using triple-module redundancy, will indeed continue to perform correctly under the influence of SEU-inducing radiation.

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33

Lee, Kok Kiong. "CAD algorithms for field programmable logic devices /." Digital version:, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p9992847.

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34

Kumar, Akhilesh. "Leakage Power Modeling and Reduction Techniques for Field Programmable Gate Arrays." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/766.

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FPGAs have become quite popular for implementing digital circuits and systems because of reduced costs and fast design cycles. This has led to increased complexity of FPGAs, and with technology scaling, many new challenges have come up for the FPGA industry, leakage power being one of the key challenges. The current generation FPGAs are being implemented in 90nm technology, therefore, managing leakage power in deep-submicron FPGAs has become critical for the FPGA industry to remain competitive in the semiconductor market and to enter the mobile applications domain.

In this work an analytical state dependent leakage power model for FPGAs is developed, followed by dual-Vt based designs of the FPGA architecture for reducing leakage power.

The leakage power model computes subthreshold and gate leakage in FPGAs, since these are the two dominant components of total leakage power in the scaled nanometer technologies. The leakage power model takes into account the dependency of gate and subthreshold leakage on the state of the circuit inputs. The leakage power model has two main components, one which computes the probability of a state for a particular FPGA circuit element, and the other which computes the leakage of the FPGA circuit element for a given input using analytical equations. This FPGA power model is particularly important for rapidly analyzing various FPGA architectures across different technology nodes.

Dual-Vt based designs of the FPGA architecture are proposed, developed, and evaluated, for reducing the leakage power using a CAD framework. The logic and the routing resources of the FPGA are considered for dual-Vt assignment. The number of the logic elements that can be assigned high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework is estimated. Based upon this estimate two kinds of architectures are developed and evaluated, homogeneous and heterogeneous architectures. Results indicate that leakage power savings of up to 50% can be obtained from these architectures. The analytical state dependent leakage power model developed has been used for estimating the leakage power savings from the dual-Vt FPGA architectures. The CAD framework that has been developed can also be used for developing and evaluating different dual-Vt FPGA architectures, other than the ones proposed in this work.

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35

Lamoureux, Julien. "Modeling and reduction of dynamic power in field-programmable gate arrays." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/414.

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Field-Programmable Gate Arrays (FPGAs) are one of the most popular platforms for implementing digital circuits. Their main advantages include the ability to be (re)programmed in the field, a shorter time-to-market, and lower non-recurring engineering costs. This programmability, however, is afforded through a significant amount of additional circuitry, which makes FPGAs significantly slower and less power-efficient compared to Application Specific Integrated Circuits (ASICs). This thesis investigates three aspects of low-power FPGA design: switching activity estimation, switching activity minimization, and low-power FPGA clock network design. In our investigation of switching activity estimation, we compare new and existing techniques to determine which are most appropriate in the context of FPGAs. Specifically, we compare how each technique affects the accuracy of FPGA power models and the ability of power-aware CAD tools to minimize power. We then present a new publicly available activity estimation tool called ACE-2.0 that incorporates the most appropriate techniques. Using activities estimated byACE-2.0, power estimates and power savings were both within 1% of results obtained using simulated activities. Moreover, the new tool was 69 and 7.2 times faster than circuit simulation for combinational and sequential circuits, respectively. In our investigation of switching activity minimization, we propose a technique for reducing power in FPGAs by minimizing unnecessary transitions called glitches. The technique involves adding programmable delay elements at inputs of the logic elements of the FPGA to align the arrival times, thereby preventing new glitches from being generated. On average, the proposed technique eliminates 87% of the glitching, which reduces overall FPGA power by17%. The added circuitry increases the overall FPGA area by 6% and critical-path delay by less than 1%. Finally, in our investigation of low-power FPGA clock networks, we examine the tradeoff between the power consumption of FPGA clock networks and the cost of the constraints they impose on FPGA CAD tools. Specifically, we present a parameterized framework for describing FPGA clock networks, we describe new clock-aware placement techniques, and we perform an empirical study to examine how the clock network parameters affect the overall power consumption of FPGAs. The results show that the techniques used to produce a legal placement can have a significant influence on power and delay. On average, circuits placed using the most effective techniques dissipate 9.9% less energy and were 2.4% faster than circuits placed using the least effective techniques. Moreover, the results show that the architecture of the clock network is also important. On average, FPGAs with an efficient clock network were up to12.5% more energy efficient and 7.2% faster than other FPGAs.

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36

Wilton, Steven J. E. "Architectures and algorithms for field-programmable gate arrays with embedded memory." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ28082.pdf.

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37

Li, Wei. "Routability prediction for field programmable gate arrays with hierarchical interconnection structures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31846.pdf.

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38

Dai, Zhibin. "Routability prediction for Field Programmable Gate Arrays with a routing hierarchy." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ56315.pdf.

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39

Campregher, Nicola. "Interconnect yield analysis and fault tolerance for field programmable gate arrays." Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/11966.

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40

Inuani, Maurice Kilavuka. "Technology mapping of heterogeneous lookup table based field programmable gate arrays." Thesis, University of Oxford, 1998. http://ora.ox.ac.uk/objects/uuid:8ec8745f-c0b2-43c0-994f-bd949d9fdefa.

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A lot of work has been done over the last decade on the logic synthesis and technology mapping of field programmable gate arrays (FPGAs) based on a single size of lookup table (LUT). A significant part of the FPGA market is occupied by devices based on more than one type of lookup tables. Examples of these heterogeneous LUT-based FPGAs are the Xilinx 4000 series devices. The technology mapping for this class of FPGAs has hardly been considered. This thesis covers work on the synthesis for heterogeneous LUT-based FPGAs. The proposed scheme uses the typical steps of graph covering, decomposition, node elimination and Boolean graph simplification. The covering step is based on the concept of flow networks and cut-computation. A theory is devised that reduces the flow network sizes so that a dynamic programming approach can be used to compute the feasible cuts in the network. An iterative selection algorithm can then be used to compute the set cover of the network. For the decomposition, the conventional bin-packing (cube-packing) algorithm has been extended so that it produces two types of bins. It has also been enhanced to explore several packing possibilities and include cube division and cascading of nodes. The classical functional decomposition method is extended to heterogeneous graphs. In particular, variable partitioning is coupled with other decomposition methods and exploits the structure of the functions. Partial collapsing and re-decomposition are used to re-synthesise the graphs. A strategy for eliminating nodes within a heterogeneous graph is developed. A simplification strategy is also derived from logic optimisation techniques. Comparisons of the mapping results on Xilinx devices show an improvement of over 11% over existing mapping tools for the same devices.

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41

Keeley, Jared Matthew. "An Incremental Trace-Based Debug System for Field-Programmable Gate-Arrays." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/3880.

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Modern society increasingly relies upon integrated circuits (ICs). It can be very costly if ICs do not function properly, and large portions of designer effort are spent on their verification. The use of field-programmable gate arrays (FPGAs) for verification and debug of ICs is increasing. FPGAs are faster than simulation and cost less than fabricating an ASIC prototype. However, the major challenge of using FPGAs for verification and debug is observability. Designers must use special techniques to observe the values of FPGA's internal signals. This thesis proposes a new method for increasing the observability of FPGAs and demonstrates its feasibility. The new method incrementally inserts trace buffers controlled by a trigger into already placed-and-routed FPGA designs. Incremental insertion allows several drawbacks of typical trace-based approaches to be avoided such as influencing the placing and routing of the design, large area overheads, and slow turnaround times when changes must be made to the instrumentation. It is shown that it is possible to observe every flip flop in Xilinx Virtex-5 designs using the method, given that enough trace buffer capacity is available. We investigate factors that influence the results of the method. It is shown that making the trace buffers wide may lead to routing failures. Congested areas of the circuit must be avoided when placing the trigger or this may also lead to routing failures. A drawback of the method is that it may increase the minimum period of the design, but we show that pipelining can reduce these effects. The method proves to be a promising way to observe thousands of signals in a design, potentially allowing designers to fully reconstruct the internal values of an FPGA over multiple clock cycles to assist in verification and debug.

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42

Lovell, Jack James. "Development of smart, compact fusion diagnostics using field-programmable gate arrays." Thesis, Durham University, 2017. http://etheses.dur.ac.uk/12401/.

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Fusion research requires high quality diagnostics to understand the complex physical processes involved. Traditional analogue systems are complex, large and expensive, and expansion of diagnostic capabilities is often impossible without building a completely new system at considerable expense. Field-programmable gate array (FPGA) technology can provide a solution to this problem. By implementing complex functionality and digital signal processing on an FPGA chip, diagnostic hardware can be greatly simpliﬁed and compacted. In this thesis we describe the enhancements of two diagnostics for the MAST-Upgrade tokamak using FPGA technology. Firstly, the design of the back end electronics for the new divertor bolometer is described. Results of tests of the new electronics at a number of sites, including lab-based testing and tokamak installations, are also presented. We demonstrate the correct functionality of the electronics and illustrate a number of important eﬀects which must be taken into account when interpreting bolometer data on MAST-U. Secondly, we describe the new control and acquisition electronics developed for the MAST-U divertor Langmuir probe diagnostic. Much of the analogue control circuitry of the previous system has been upgraded to a digital implementation on an FPGA, which results in a signiﬁcantly more compact and cost eﬀective design. Given that MAST-Upgrade will feature around 850 Langmuir probes, these improvements are extremely important to keep the diagnostic manageable. Again, results are presented from the testing of the system at several sites, which both demonstrate the correct functionality of the new system and provide information on the diagnostic behaviour which needs to be accounted for when interpreting the probe data during MAST-U experiments.

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43

Moeller, Tyler J. (Tyler John) 1975. "Field programmable gate arrays for radar front-end digital signal processing." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80555.

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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.
Includes bibliographical references (p. 113-116).
by Tyler J. Moeller.
S.B.and M.Eng.

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44

Honoré, Francis. "Energy-aware architectures, circuits and CAD for field programmable gate arrays." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37911.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 113-117).
Field Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of fine grain configurable power domains. By introducing fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the analysis and implementation of these configurable power domains. A test chip using dual core voltages fabricated in a 0.18 /m CMOS process features these power reduction techniques. The test chip includes an 8x8 array of logic tiles and a 9x9 switch matrix grid. The chip design flow utilizes a mix of synthesized logic and custom cells. 'The layout required a customized approach to overcome some of the challenges of implementing a fine granularity multiple voltage design.
(cont.) A set of benchmark circuits shows a measured average energy-delay improvement of nearly 2X. Additionally, enhancements for the implementation of finite impulse response filters provide a 2.5x improvement in the energy-delay product relative to standard FPGA architectures. This thesis also addresses static: power consumption by reducing sub-threshold leakage through the use of distributed multi-threshold CMOS. A separate test chip using a 0.13 m dual VT process demonstrates the advantages of distributed power gating for sub-threshold leakage reduction by achieving over 10X reduction in static power.
by Francis A. Honoré.
Ph.D.

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45

Potgieter, Juan-Pierre. "Single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12520.

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In the last 50 years microelectronics have advanced at an exponential rate, causing microelectronic devices to shrink, have very low operating voltages and increased complexities; all this has made circuits more sensitive to various kinds of failures. These trends allowed soft errors, which up until recently was just a concern for space application, to become a major source of system failures of electronic products. The aim of this research paper was to investigate different mitigation techniques that prevent these soft errors in a Video Graphics Array (VGA) controller which is commonly used in projecting images captured by cameras. This controller was implemented on a Flash Based Field Programmable Gate array (FPGA). A test set-up was designed and implemented at NRF iThemba LABS, which was used to conduct the experiments necessary to evaluate the effectiveness of different mitigation techniques. The set-up was capable of handling multiple Device Under Tests (DUT) and had the ability to change the angle of incidence of each DUT. The DUTs were radiated with a 66MeV proton beam while the monitoring equipment observed any errors that had occurred. The results obtained indicated that all the implemented mitigation techniques tested on the VGA system improved the system’s capability of mitigating Single Event Upsets (SEU). The most effective mitigation technique was the OR-AND Multiplexer Single Event Transient (SET) filter technique. It was thus shown that mitigation techniques are viable options to prevent SEU in a VGA controller. The permanent SEU testing set-up which was designed and manufactured and was used to conduct the experiments, proved to be a practical option for further microelectronics testing at iThemba LABS.

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46

Ortiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.

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47

Milton, Daniel. "Built-in self test of configurable memory resources in field programmable gate arrays." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Theses/MILTON_DANIEL_9.pdf.

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48

Lin, Yu Colin, and 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.

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Due to their high potential performance and reduced energy and power consumption, field-programmable gate arrays (FPGAs) are widely used as accelerators for today’s computationally intensive applications. These applications use advanced algorithms more sophisticated than ever before. The high design complexity along with fast development process challenges the traditional FPGA design methodology using hardware description languages. High-level synthesis accelerates design implementation by raising the level of design abstraction beyond register transfer level. This dissertation work develops a highly energy-efficient FPGA high-level synthesis tool, ArchSyn, using an application-specific coarse-grain architecture as an intermediate synthesis step. ArchSyn provides rapid and energy-efficient compilation of dataflow graphs (DFGs) on FPGAs by scheduling the dataflow operations on an array of directly connected simple configurable processing elements (CPEs). Each CPE in the array performs primitive compute operations according to a small local sequencer at each cycle. Data are communicated via multi-hop routing within the direct interconnect network. The scheduler schedules each compute operation of the DFG obtained from the high-level design to execute on a particular hardware CPE at a particular cycle. It also determines the communication schedule of the intermediate data among the producing and consuming CPEs, optionally buffering them with distributed memory along the path. As such, the lengthy process of synthesizing a full custom hardware design on FPGA is reduced to a scheduling and mapping process. By restricting the fine-grain programmability into a coarse grain processor network scheduling problem, the compilation time can be improved substantially, thereby improving the overall productivity of the designer. Furthermore, taking advantage of the programmability of FPGAs, the effect of the array interconnect architecture on the energy-efficiency of the resulting system is studied. By altering the array configuration, the data communication scheme among the CPEs must also be changed. This has a net effect on both the energy consumption spent on data movement as well as on the overall compute performance. It is shown that by using array topology that is customized to the input DFG, up to 28% improvement in energy-efficiency could be achieved. An exploratory framework based on a genetic algorithm was developed that allows us to obtain such application-specific connection network. Such degree of customization is possible only with the programmability of FPGAs. Moreover, such topology adaptation can be achieved rapidly as only routings between a fixed set of pre-placed CPEs are required. Implementations using ArchSyn and an existing FPGA compilation tool xPilot were compared. ArchSyn gave a 2X better energy consumption and a 11X better energy-delay product for computation with very regular and simple data dependency. For computation with irregular data dependency, the energy consumption and energy-delay product improvement was 9.6X and 199X.
published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy

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49

Johnson, Steven A. "Implementation of a configurable fault tolerant processor (CFTP)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Mar%5FJohnson.pdf.

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Анотація:

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 2003.
Thesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.

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50

Hauck, Scott. "Multi-FPGA systems /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.

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Дисертації з теми "Field Programmable Counter Arrays"

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