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Статті в журналах з теми "Fault-tolerant multiprocessor systems"

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Автор: Grafiati

Опубліковано: 30 травня 2022

Оновлено: 31 травня 2022

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1

Tafesse, Bisrat, and Venkatesan Muthukumar. "Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration." VLSI Design 2013 (July 11, 2013): 1–16. http://dx.doi.org/10.1155/2013/936181.

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Анотація:

Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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2

Feseniuk, A. P. "Software SERC for Monte Carlo Error analysis of fault-tolerant multiprocessor systems reliability estimation." PROBLEMS IN PROGRAMMING, no. 4 (December 2016): 048–57. http://dx.doi.org/10.15407/pp2016.04.048.

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The article devoted to reliability estimation of fault-tolerant reconfigurable multiprocessor systems. The paper briefly describes implementation of software SERC (Statistical Experiments for Reliability Calculation) which contains known and proposed by author statistical methods for fault tolerant reconfigurable multiprocessor systems reliability estimation and tools for Monte Carlo Error analysis of the estimation.

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3

Alam, M. S., and R. G. Melhem. "Routing in modular fault-tolerant multiprocessor systems." IEEE Transactions on Parallel and Distributed Systems 6, no. 11 (1995): 1206–20. http://dx.doi.org/10.1109/71.476192.

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4

Bruno, John, and E. G. Coffman Jr. "Optimal fault-tolerant computing on multiprocessor systems." Acta Informatica 34, no. 12 (November 1, 1997): 881–904. http://dx.doi.org/10.1007/s002360050110.

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5

ZHU, LINJIE, TONGQUAN WEI, XIAODAO CHEN, YONGHE GUO, and SHIYAN HU. "ADAPTIVE FAULT-TOLERANT TASK SCHEDULING FOR REAL-TIME ENERGY HARVESTING SYSTEMS." Journal of Circuits, Systems and Computers 21, no. 01 (February 2012): 1250004. http://dx.doi.org/10.1142/s0218126612500041.

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Fault tolerance and energy have become important design issues in multiprocessor system-on-chips (SoCs) with the technology scaling and the proliferation of battery-powered multiprocessor SoCs. This paper proposed an energy-efficient fault tolerance task allocation scheme for multiprocessor SoCs in real-time energy harvesting systems. The proposed fault-tolerance scheme is based on the principle of the primiary/backup task scheduling, and can tolerate at most one single transient fault. Extensive simulated experiment shows that the proposed scheme can save up to 30% energy consumption and reduce the miss ratio to about 8% in the presence of faults.

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6

Bertossi, Alan A., and Luigi Mancini. "Fault-tolerant LPT task scheduling in multiprocessor systems." Microprocessors and Microsystems 16, no. 2 (January 1992): 91–99. http://dx.doi.org/10.1016/0141-9331(92)90076-6.

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7

Karavay, M. F. "Methodology of Designing the Fault-Tolerant Distributed Multiprocessor systems." IFAC Proceedings Volumes 21, no. 19 (June 1988): 107–14. http://dx.doi.org/10.1016/s1474-6670(17)54478-x.

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8

Blough, D. M., and H. Y. Wang. "Cooperative Diagnosis and Routing in Fault-Tolerant Multiprocessor Systems." Journal of Parallel and Distributed Computing 27, no. 2 (June 1995): 205–11. http://dx.doi.org/10.1006/jpdc.1995.1083.

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9

Yajnik, S., and N. K. Jha. "Graceful degradation in algorithm-based fault tolerant multiprocessor systems." IEEE Transactions on Parallel and Distributed Systems 8, no. 2 (1997): 137–53. http://dx.doi.org/10.1109/71.577256.

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10

Tabba, Nabil, Reza Entezari-Maleki, and Ali Movaghar. "Reduced Communications Fault Tolerant Task Scheduling Algorithm for Multiprocessor Systems." Procedia Engineering 29 (2012): 3820–25. http://dx.doi.org/10.1016/j.proeng.2012.01.577.

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11

Yuan, Bo, Huanhuan Chen, and Xin Yao. "Toward Efficient Design Space Exploration for Fault-Tolerant Multiprocessor Systems." IEEE Transactions on Evolutionary Computation 24, no. 1 (February 2020): 157–69. http://dx.doi.org/10.1109/tevc.2019.2912726.

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12

Nair, V. S. S., Y. V. Hoskote, and J. A. Abraham. "Probabilistic evaluation of online checks in fault-tolerant multiprocessor systems." IEEE Transactions on Computers 41, no. 5 (May 1992): 532–41. http://dx.doi.org/10.1109/12.142679.

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13

Ghafoor, A., S. Sheikh, and P. Sole. "Bipartite distance-regular interconnection topology for fault-tolerant multiprocessor systems." IEE Proceedings E Computers and Digital Techniques 137, no. 3 (1990): 173. http://dx.doi.org/10.1049/ip-e.1990.0021.

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14

Grandoni, F. "Evaluation of Fault-Tolerant Multiprocessor Systems for High Assurance Applications." Computer Journal 44, no. 6 (June 1, 2001): 544–56. http://dx.doi.org/10.1093/comjnl/44.6.544.

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15

Das, C. R., and L. N. Bhuyan. "Reliability and fault-tolerant issues of multiprocessor and multicomputer systems." Sadhana 11, no. 1-2 (October 1987): 129–54. http://dx.doi.org/10.1007/bf02811315.

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16

Kada, Barkahoum, and Hamoudi Kalla. "An Efficient Fault-Tolerant Scheduling Approach with Energy Minimization for Hard Real-Time Embedded Systems." Cybernetics and Information Technologies 19, no. 4 (November 1, 2019): 45–60. http://dx.doi.org/10.2478/cait-2019-0035.

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Анотація:

Abstract In this paper, we focus on two major problems in hard real-time embedded systems fault tolerance and energy minimization. Fault tolerance is achieved via both checkpointing technique and active replication strategy to tolerate multiple transient faults, whereas energy minimization is achieved by adapting Dynamic Voltage Frequency Scaling (DVFS) technique. First, we introduce an original fault-tolerance approach for hard real-time systems on multiprocessor platforms. Based on this approach, we then propose DVFS_FTS algorithm for energy-efficient fault-tolerant scheduling of precedence-constrained applications. DVFS_FTS is based on a list scheduling heuristics, it satisfies real-time constraints and minimizes energy consumption even in the presence of faults by exploring the multiprocessor architecture. Simulation results reveal that the proposed algorithm can save a significant amount of energy while preserving the required fault-tolerance of the system and outperforms other related approaches in energy savings.

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17

Lala, Jaynarayan H. "Fault detection, isolation, and reconfiguration in the fault tolerant multiprocessor." Journal of Guidance, Control, and Dynamics 9, no. 5 (September 1986): 585–92. http://dx.doi.org/10.2514/3.20150.

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18

Dumitrescu, Mariana. "Fault Tolerant Control Multiprocessor Systems Modelling Using Advanced Stochastic Petri Nets." Procedia Technology 22 (2016): 623–28. http://dx.doi.org/10.1016/j.protcy.2016.01.129.

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19

Nikolaev, A. B., and V. S. Podlazov. "Fault-tolerant expansion of system area networks in multiprocessor computer systems." Automation and Remote Control 69, no. 1 (January 2008): 150–57. http://dx.doi.org/10.1134/s0005117908010141.

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20

Zhang, Jun, Edwin H. M. Sha, Qingfeng Zhuge, Juan Yi, and Kaijie Wu. "Efficient fault-tolerant scheduling on multiprocessor systems via replication and deallocation." International Journal of Embedded Systems 6, no. 2/3 (2014): 216. http://dx.doi.org/10.1504/ijes.2014.063819.

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21

Yang, Fumin, Wei Luo, and Liping Pang. "An efficient real-time fault-tolerant scheduling algorithm based on multiprocessor systems." Wuhan University Journal of Natural Sciences 12, no. 1 (January 2007): 113–16. http://dx.doi.org/10.1007/s11859-006-0231-x.

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22

Vinnakota, B., and N. K. Jha. "Design of algorithm-based fault-tolerant multiprocessor systems for concurrent error detection and fault diagnosis." IEEE Transactions on Parallel and Distributed Systems 5, no. 10 (1994): 1099–106. http://dx.doi.org/10.1109/71.313125.

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23

Hu, Shuo-Cheng, and Chang-Biau Yang. "Fault Tolerance on Star Graphs." International Journal of Foundations of Computer Science 08, no. 02 (June 1997): 127–42. http://dx.doi.org/10.1142/s0129054197000112.

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Анотація:

The capability of fault tolerance is one of the advantages of multiprocessor systems. In this paper, we prove that the fault tolerance of an n-star graph is 2n-5 with restriction to the forbidden faulty set. And we propose an algorithm for examining the connectivity of an n-star graph when there exist at most 2n - 4 faults. The algorithm requires O(n2 log n) time. Besides, we improve the fault-tolerant routing algorithm proposed by Bagherzadeh et al. by calculating the cycle structure of a permutation and the avoidance of routing message to a node without any nonfaulty neighbor. This calculation needs only constant time. And then, we propose an efficient fault-tolerant broadcasting algorithm. When there is no fault, our broadcasting algorithm remains optimal. The penalty is O(n) if there exists only one fault, and the penalty is O(n2) if there exist at most n - 2 faults.

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24

Naseer, Oumair. "Online Adaptive Fault Tolerant Based Feedback Control Scheduling Algorithm for Multiprocessor Embedded Systems." International Journal of Embedded Systems and Applications 2, no. 3 (September 30, 2012): 1–9. http://dx.doi.org/10.5121/ijesa.2012.2301.

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25

Huang, Kai, Xiaowen Jiang, Xiaomeng Zhang, Rongjie Yan, Ke Wang, Dongliang Xiong, and Xiaolang Yan. "Energy-Efficient Fault-Tolerant Mapping and Scheduling on Heterogeneous Multiprocessor Real-Time Systems." IEEE Access 6 (2018): 57614–30. http://dx.doi.org/10.1109/access.2018.2873641.

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26

PARK, JAEHYUN, HYUNSOO YOON, HEUNGKYU LEE, and SEONGBAE EUN. "THE RING-BANYAN NETWORK: A FAULT TOLERANT MULTISTAGE INTERCONNECTION NETWORK FOR MULTIPROCESSOR SYSTEMS." International Journal of High Speed Computing 06, no. 04 (December 1994): 557–77. http://dx.doi.org/10.1142/s0129053394000275.

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27

Hashimoto, Koji, Tatsuhiro Tsuchiya, and Tohru Kikuno. "A new approach to fault-tolerant scheduling using task duplication in multiprocessor systems." Journal of Systems and Software 53, no. 2 (August 2000): 159–71. http://dx.doi.org/10.1016/s0164-1212(99)00105-3.

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28

Baek, Hyeongboo, and Jaewoo Lee. "Task-Level Re-Execution Framework for Improving Fault Tolerance on Symmetry Multiprocessors." Symmetry 11, no. 5 (May 9, 2019): 651. http://dx.doi.org/10.3390/sym11050651.

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Анотація:

Hard real-time systems are employed in military, aeronautics, and astronautics fields where deployed systems are susceptible to software faults that can result in functional errors. Thus, there is a need to use fault-tolerant (FT) real-time scheduling. Among the various fault-tolerant real-time scheduling techniques, re-execution has been applied widely to existing real-time systems owing to its simplicity and applicability. However, re-execution requires multiple executions of every task, and some tasks miss their deadlines owing to the prolonged execution time; therefore, it has been found to be suitable for only soft real-time systems. In this paper, we propose an FT policy that can be incorporated into most (if not all) existing real-time scheduling algorithms on multiprocessor systems, which improves the reliability of the target system without a tradeoff against schedulability. As a case study, we apply the FT policy to existing fixed-priority scheduling and earliest deadline zero-laxity scheduling, and we demonstrate that it enhances reliability without schedulability loss.

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29

Manimaran, G., and C. Siva Ram Murthy. "A new scheduling approach supporting different fault-tolerant techniques for real-time multiprocessor systems." Microprocessors and Microsystems 21, no. 3 (December 1997): 163–73. http://dx.doi.org/10.1016/s0141-9331(97)00030-6.

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30

Park, Seong-Jin, and Kwang-Hyun Cho. "Supervisory control for fault-tolerant scheduling of real-time multiprocessor systems with aperiodic tasks." International Journal of Control 82, no. 2 (January 22, 2009): 217–27. http://dx.doi.org/10.1080/00207170802047425.

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31

Karavay, M. F., and V. S. Podlazov. "An extended generalized hypercube as a fault-tolerant system area network for multiprocessor systems." Automation and Remote Control 76, no. 2 (February 2015): 336–52. http://dx.doi.org/10.1134/s0005117915020137.

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32

Wang, K., and C. K. Wu. "Design and implementation of fault-tolerant and cost effective crossbar switches for multiprocessor systems." IEE Proceedings - Computers and Digital Techniques 146, no. 1 (1999): 50. http://dx.doi.org/10.1049/ip-cdt:19990240.

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33

Sitaraman, R. K., and N. K. Jha. "Optimal design of checks for error detection and location in fault-tolerant multiprocessor systems." IEEE Transactions on Computers 42, no. 7 (July 1993): 780–93. http://dx.doi.org/10.1109/12.237719.

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34

Manimaran, G., and C. S. R. Murthy. "A fault-tolerant dynamic scheduling algorithm for multiprocessor real-time systems and its analysis." IEEE Transactions on Parallel and Distributed Systems 9, no. 11 (1998): 1137–52. http://dx.doi.org/10.1109/71.735960.

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35

Baek, Yunju, Heung-Kyu Lee, and Kiyeol Ryu. "A new hardware-based fault-tolerant clock synchronization scheme for real-time multiprocessor systems." Microelectronics Reliability 34, no. 2 (February 1994): 335–49. http://dx.doi.org/10.1016/0026-2714(94)90115-5.

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36

Yu, Xing-biao, Jun-suo Zhao, Chang-wen Zheng, and Xiao-hui Hu. "A Fault-Tolerant Scheduling Algorithm using Hybrid Overloading Technology for Dynamic Grouping based Multiprocessor Systems." International Journal of Computers Communications & Control 7, no. 5 (September 14, 2014): 990. http://dx.doi.org/10.15837/ijccc.2012.5.1358.

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37

Al-Omari, R., A. K. Somani, and G. Manimaran. "An adaptive scheme for fault-tolerant scheduling of soft real-time tasks in multiprocessor systems." Journal of Parallel and Distributed Computing 65, no. 5 (May 2005): 595–608. http://dx.doi.org/10.1016/j.jpdc.2004.09.021.

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38

Choi, B. R., K. H. Park, and M. Kim. "An improved hardware implementation of the fault-tolerant clock synchronization algorithm for large multiprocessor systems." IEEE Transactions on Computers 39, no. 3 (March 1990): 404–7. http://dx.doi.org/10.1109/12.48872.

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39

Yajnik, S., and N. K. Jha. "Analysis and randomized design of algorithm-based fault tolerant multiprocessor systems under an extended model." IEEE Transactions on Parallel and Distributed Systems 8, no. 7 (July 1997): 757–68. http://dx.doi.org/10.1109/71.598349.

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40

Prakash, Amit, Dilip K. Yadav, and Arvind Choubey. "A Survey of Multistage Interconnection Networks." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 13, no. 2 (April 27, 2020): 165–83. http://dx.doi.org/10.2174/1872212113666190215145815.

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Анотація:

Background: Multistage interconnection networks are being used in computer and communications. Multiprocessor architectures for parallel computing exercise these interconnection networks for connecting various processing elements and transfer data between sub-systems of a digital system. The vast diversity of the field poses an obstacle to realize different kinds of interconnection networks and their relationship. Methods: This paper consists of an extensive survey of multistage interconnection networks. Results: A broad classification of multistage interconnection networks based on network functionality, reliability and fault tolerance is presented in order to emphasize the important principles which differentiate the network architectures. For each class of network, significant results are given and the basic design principles are explained. Conclusion: The various multistage interconnection networks design provide high performance, availability, throughput, lower latency, less power consumption along with improved fault-tolerance and reliability. However, there is a rising demand for new fault-tolerant and reliable multistage interconnection networks.

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41

Baek, Jaemin, Jeonghyun Baek, Jeeheon Yoo, and Hyeongboo Baek. "An N-Modular Redundancy Framework Incorporating Response-Time Analysis on Multiprocessor Platforms." Symmetry 11, no. 8 (July 31, 2019): 960. http://dx.doi.org/10.3390/sym11080960.

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Анотація:

A timing constraint and a high level of reliability are the fundamental requirements for designing hard real-time systems. To support both requirements, the N modular redundancy (NMR) technique as a fault-tolerant real-time scheduling has been proposed, which executes identical copies for each task simultaneously on multiprocessor platforms, and a single correct one is voted on, if any. However, this technique can compromise the schedulability of the target system during improving reliability because it produces N identical copies of each job that execute in parallel on multiprocessor platforms, and some tasks may miss their deadlines due to the enlarged computing power required for completing their executions. In this paper, we propose task-level N modular redundancy (TL-NMR), which improves the system reliability of the target system of which tasks are scheduled by any fixed-priority (FP) scheduling without schedulability loss. Based on experimental results, we demonstrate that TL-NMR maintains the schedulability, while significantly improving average system safety compared to the existing NMR.

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42

Kim, Jin S., Seung Ryoul Maeng, and H. Yoon. "Ring Embedding in Hypercubes with Faculty Nodes." Parallel Processing Letters 07, no. 03 (September 1997): 285–96. http://dx.doi.org/10.1142/s0129626497000309.

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Hypercube is an attractive structure for parellel processing due to its symmetry and regularity. To increase the reliability of hypercube based systems and to allow their use in the presence of faulty nodes, efficient fault-tolerant schemes in hypercubes are necessary. In this paper, we present an algorithm for embedding rings in hypercubes based multiprocessor network in the event of node failures. The algorithm can tolerate up to θ(2n/2) faults, and guarantee that given any f < (n - 2k)2k faulty nodes, it can find a ring of size at least 2n - 2f for k = 0 and 2n - 2k f - 22k for k ≥ 1 in an n-dimensional hypercube. It improves over existing algorithms in the size of ring.

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43

Devaraj, Rajesh, Arnab Sarkar, and Santosh Biswas. "A design fix to supervisory control for fault-tolerant scheduling of real-time multiprocessor systems with aperiodic tasks." International Journal of Control 88, no. 11 (May 8, 2015): 2211–16. http://dx.doi.org/10.1080/00207179.2015.1039592.

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44

Романкевич, Виталий Алексеевич, Алексей Витальевич Романкевич та Дарина Натиговна Ахмедова. "МЕТОД УМЕНЬШЕНИЯ КОЛИЧЕСТВА ВЗАИМОПРОВЕРОК ПРИ САМОТЕСТИРОВАНИИ МНОГОПРОЦЕССОРНЫХ СИСТЕМ". RADIOELECTRONIC AND COMPUTER SYSTEMS, № 4 (20 грудня 2018): 61–66. http://dx.doi.org/10.32620/reks.2018.4.06.

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Анотація:

The subject matter of this article is the testing processes in multiprocessor systems, first of all - fault-tolerant control systems, when the number m of allowed failures from n processors is known in advance and is limited. The topology of interprocessor communications can be represented as a directed graph of the circulant type, where the number of input and output channels between each one processor and the other processors in the system is not less than m. The goal is to minimize the number of mutual checks in the system when performing its self-testing. Tasks: develop an effective method for organizing the mutual testing of processors in multiprocessor systems and algorithm for its implementation, estimate the number of elementary checks and prove its rightness. The following results were obtained. Based on the known method of diagnosis of multiprocessor systems with a regular structure, and m≤4, with parallel and independent testing, the task of organizing of testing process for any m <(n ⁄ 2) was formulated. In this process, only one pair of processors participate in testing in one moment of time, thus it was called sequential. what special about this organization is that the choice of the next pair is based on the analysis of the history of the process. An algorithm for performing the method has been proposed. The Preparata-Metz-Chen model was chosen as the model of faults, as the closest one to reality. Conclusions. The scientific novelty of the results is as follows: The method for organizing of self-testing of multiprocessor systems with a connection topology described by a circulant graph (with at least m input and m output edges) has been proposed, and this method allows reducing the number of mutual tests in the system. It has been proved that the state (serviceable/faulty) of all processors of the system can be determined after performing no more than n + 2m checks. Practical value - the method allows to reduce the time spent by system on self-testing, and, therefore, to increase its performance, since the system performs this task constantly in the process of exploitation. The advantages of the selected topology: it is suitable for any integer values of n

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45

Ruospo, Annachiara, and Ernesto Sanchez. "On the Reliability Assessment of Artificial Neural Networks Running on AI-Oriented MPSoCs." Applied Sciences 11, no. 14 (July 13, 2021): 6455. http://dx.doi.org/10.3390/app11146455.

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Nowadays, the usage of electronic devices running artificial neural networks (ANNs)-based applications is spreading in our everyday life. Due to their outstanding computational capabilities, ANNs have become appealing solutions for safety-critical systems as well. Frequently, they are considered intrinsically robust and fault tolerant for being brain-inspired and redundant computing models. However, when ANNs are deployed on resource-constrained hardware devices, single physical faults may compromise the activity of multiple neurons. Therefore, it is crucial to assess the reliability of the entire neural computing system, including both the software and the hardware components. This article systematically addresses reliability concerns for ANNs running on multiprocessor system-on-a-chips (MPSoCs). It presents a methodology to assign resilience scores to individual neurons and, based on that, schedule the workload of an ANN on the target MPSoC so that critical neurons are neatly distributed among the available processing elements. This reliability-oriented methodology exploits an integer linear programming solver to find the optimal solution. Experimental results are given for three different convolutional neural networks trained on MNIST, SVHN, and CIFAR-10. We carried out a comprehensive assessment on an open-source artificial intelligence-based RISC-V MPSoC. The results show the reliability improvements of the proposed methodology against the traditional scheduling.

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Kukushkin, D. I., and V. A. Antonenko. "SERVERLESS COMPUTATIONS RESOURCE SCHEDULING BASED ON DATA DEPENDENCY." Vestnik komp'iuternykh i informatsionnykh tekhnologii, no. 209 (November 2021): 37–46. http://dx.doi.org/10.14489/vkit.2021.11.pp.037-046.

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The serverless computing model is becoming quite widespread. This model allows developers to create flexible and fault tolerant applications with an attractive billing model. The increasing complexity of serverless functions has led to the necessity to use serverless workflows – serverless functions invoking other serverless functions. However, such concept imposes certain requirements on the serverless functions that make distributed computations. The overhead of transferring data between serverless functions can significantly increase the execution time of a program using this approach. One way to reduce overhead is to improve serverless scheduling techniques. This paper discusses an approach to scheduling serverless computations based on data dependency analysis. We propose to divide the problem of planning of the computation of a composite serverless function into three stages. For each stage we provide a description by a mathematical model. We carried out a review of algorithms used to schedule resources by compilers and in parallel computing in multiprocessor systems to determine the best algorithm to implement in a prototype scheduler. For each algorithm, it was specified how it could be used for resource scheduling in serverless platforms. We provide a description of the developed prototype based on the Fission serverless platform. The prototype implements the critical path heuristic. It is shown that the improvements can significantly reduce the execution time up to two times for some types of serverless functions.

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Shvahirev, P., O. Lopakov, V. Kosmachevskiy, and V. Salii. "METHOD FOR ASSESSING OF RELIABILITY CHARACTERISTICS IN DESIGNING OF FAILURERESISTANT REAL-TIME OPERATING SYSTEMS." Odes’kyi Politechnichnyi Universytet Pratsi 2, no. 61 (2020): 108–18. http://dx.doi.org/10.15276/opu.2.61.2020.13.

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For many years, real-time OS-based applications have been used in embedded special-purpose systems. Recently they have been used everywhere, from on-board control systems for aircraft, to household appliances. The development of multiprocessor computing systems usually aims to increase either the level of reliability or the level of system performance to values that are inaccessible or difficult to implement in traditional computer systems. In the first case, the question of the availability of special means of ensuring the fault tolerance of computer systems arises, the main feature (and advantage) of which is the absence of any single resource, failure of which leads to a fatal failure of the entire system. The use of a real-time operating system is always associated with equipment, with an object and with events occurring at an object. A real-time system, as a hardware-software complex, includes sensors that record events at an object, input / output modules that convert sensor readings into a digital form suitable for processing these readings on a computer, and finally, a computer with a program that responds to events occurring at the facility. The RTOS is focused on processing external events. It is this that leads to fundamental differences (compared with general-purpose OS) in the structure of the system as well as in the functions of the kernel and in the construction of the input-output system. The RTOS can be similar in its user interface to general-purpose operating systems, but it is completely different in its structure. In addition, the use of RTOS is always specific. If users (not developers) usually perceive a general-purpose OS as a ready-made set of applications, then the RTOS serves only as a tool for creating a specific hardware-software complex in real time. Therefore, the widest class of users of RTOS is the developers of real-time complexes, people designing control and data collection systems. When designing and developing a specific real-time system, the programmer always knows exactly what events can occur at the facility, and he knows the critical terms for servicing each of these events. We call a real-time system (SRV) a hardware-software complex that responds in predictable times to an unpredictable stream of external events. The system must have time to respond to the event that occurred at the facility, during the time critical for this event. The critical time for each event is determined by the object and by the event itself, and, of course, it can be different, but the response time of the system must be predicted (calculated) when creating the system. Lack of response at the predicted time is considered an error for real-time systems. The system must have time to respond to simultaneously occurring events. Even if two or more external events occur simultaneously, the system must have time to respond to each of them during time intervals critical for these events. In this study, as part of a network fault-tolerant technology, the RTOS becomes a special type of control software that is used to organize the operation of embedded applications, which are characterized by limited memory resources, low productivity and the requirements of a guaranteed response time (T<4 μs), high level availability and availability of auto-monitoring facilities.

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Malika, Bachir, and Hamoudi Kalla. "A Fault Tolerant Scheduling Heuristics for Distributed Real Time Embedded Systems." Cybernetics and Information Technologies 18, no. 3 (September 1, 2018): 48–61. http://dx.doi.org/10.2478/cait-2018-0038.

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Abstract In this paper, fault tolerant task scheduling algorithms are proposed for mapping task graphs to heterogeneous processing nodes. These scheduling heuristics that we propose are redundancy-based software to tolerate hardware faults. We consider only processor permanent failures with a fail-silent behavior. The proposed heuristics generate automatically a real-time fault distributed schedule of dependent and independent tasks into heterogonous multiprocessors architecture. The heuristics are based on active and passive redundancy.

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Nehnouh, Chakib. "A new architecture for online error detection and isolation in network on chip." Journal of High Speed Networks 26, no. 4 (December 23, 2020): 307–23. http://dx.doi.org/10.3233/jhs-200646.

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The Network-on-Chip (NoC) has become a promising communication infrastructure for Multiprocessors-System-on-Chip (MPSoC). Reliability is a main concern in NoC and performance is degraded when NoC is susceptible to faults. A fault can be determined as a cause of deviation from the desired operation of the system (error). To deal with these reliability challenges, this work propose OFDIM (Online Fault Detection and Isolation Mechanism),a novel combined methodology to tolerate multiple permanent and transient faults. The new router architecture uses two modules to assure highly reliable and low-cost fault-tolerant strategy. In contrast to existing works, our architecture presents less area, more fault tolerance, and high reliability. The reliability comparison using Silicon Protection Factor (SPF), shows 22-time improvement and that additional circuitry incurs an area overhead of 27%, which is better than state-of-the-art reliable router architectures. Also, the results show that the throughput decreases only by 5.19% and minor increase in average latency 2.40% while providing high reliability.

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Pransky, Joanne. "The Pransky interview: Gianmarco Veruggio, Director of Research, CNR-IEIIT, Genoa Branch; Robotics Pioneer and Inventor." Industrial Robot: An International Journal 44, no. 1 (January 16, 2017): 6–10. http://dx.doi.org/10.1108/ir-10-2016-0271.

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Purpose The following paper is a “Q&A interview” conducted by Joanne Pransky of Industrial Robot journal as a method to impart the combined technological, business and personal experience of a prominent, robotic industry engineer-turned successful innovator and leader, regarding the challenges of bringing technological discoveries to fruition. The paper aims to discuss these issues. Design/methodology/approach The interviewee is Gianmarco Veruggio who is responsible for the Operational Unit of Genoa of the Italian National Research Council Institute of Electronics, Computer and Telecommunication Engineering (CNR-IEIIT). Veruggio is an early pioneer of telerobotics in extreme environments. Veruggio founded the new applicative field of Roboethics. In this interview, Veruggio shares some of his 30-year robotic journey along with his thoughts and concerns on robotics and society. Findings Gianmarco Veruggio received a master’s degree in electronic engineering, computer science, control and automation from Genoa University in 1980. From 1980 to 1983 he worked in the Automation Division of Ansaldo as a Designer of fault-tolerant multiprocessor architectures for fail-safe control systems and was part of the development team for the new automation of the Italian Railway Stations. In 1984, he joined the CNR-Institute of Naval Automation (IAN) in Genoa as a Research Scientist. There, he worked on real-time computer graphics for simulation, control techniques and naval and marine data-collection systems. In 1989, he founded the CNR-IAN Robotics Department (Robotlab), which he headed until 2003, to develop missions on experimental robotics in extreme environments. His approach utilized working prototypes in a virtual lab environment and focused on robot mission control, real-time human-machine interfaces, networked control system architectures for tele-robotics and Internet Robotics. In 2000, he founded the association “Scuola di Robotica” (School of Robotics) to promote this new science among young people and society at large by means of educational robotics. He joined the CNR-IEIIT in 2007 to continue his research in robotics and to also develop studies on the philosophical, social and ethical implications of Robotics. Originality/value Veruggio led the first Italian underwater robotics campaigns in Antarctica during the Italian expeditions in 1993, 1997 and 2001, and in the Arctic during 2002. During the 2001-2002 Antarctic expedition, he carried out the E-Robot Project, the first experiment of internet robotics via satellite in the Antarctica. In 2002, he designed and developed the Project E-Robot2, the first experiment of worldwide internet robotics ever carried out in the Arctic. During these projects, he organized a series of “live-science” sessions in collaboration with students and teachers of Italian schools. Beginning with his new “School of Robotics”, Veruggio continued to disseminate and educate young people on the complex relationship between robotics and society. This led him to coin the term and propose the concept of Roboethics in 2002, and he has since made worldwide efforts at dedicating resources to the development of this new field. He was the General Chair of the “First International Symposium on Roboethics” in 2004 and of the “EURON Roboethics Atelier” in 2006 that produced the Roboethics Roadmap. Veruggio is the author of more than 150 scientific publications. In 2006, he was presented with the Ligurian Region Award for Innovation, and in 2009, for his merits in the field of science and society, he was awarded the title of Commander of the Order of Merit of the Italian Republic, one of Italy’s highest civilian honors.

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