Статті в журналах: "Error-resilient application"

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Kumar, Vinay, Ankit Singh, Shubham Upadhyay, and Binod Kumar. "Power–Delay-Error-Efficient Approximate Adder for Error-Resilient Applications." Journal of Circuits, Systems and Computers 28, no. 10 (September 2019): 1950171. http://dx.doi.org/10.1142/s0218126619501718.

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Power dissipation has been the prime concern for CMOS circuits. Approximate computing is a potential solution for addressing this concern as it reduces power consumption resulting in improved performance in terms of power–delay product (PDP). Decrease of power consumption in approximate computing is achieved by approximating the demand of accuracy as per the error tolerance of the system. This paper presents a new approach for designing approximate adder by introducing inexactness in the existing logic gate(s). Approximated logic gates provide flexibility in designing low power error-resilient systems depending on the error tolerance of the applications such as image processing and data mining. The proposed approximate adder (PAA) has higher accuracy than existing approximate adders with normalized mean error distance of 0.123 and 0.1256 for 16-bit and 32-bit adder, respectively, and lower PDP of 1.924E[Formula: see text]18[Formula: see text]J for 16-bit adder and 5.808E[Formula: see text]18[Formula: see text]J for 32-bit adder. The PAA also performs better than some of the recent approximate adders reported in literature in terms of layout area and delay. Performance of PAA has also been evaluated with an image processing application.

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Joshi, Viraj, Pravin Mane, and Bits Pilani. "Approximate Arithmetic Circuit Design for Error Resilient Applications." International Journal of VLSI Design & Communication Systems 13, no. 1/2/3/4/5/6 (December 30, 2022): 01–16. http://dx.doi.org/10.5121/vlsic.2022.13601.

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When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on performance are rapidly getting replaced by approximate arithmetic circuits which are the need of the hour, and so on about their design.

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Kumar, G. Vijay, and Y. Anjani. "Application of Error-resilient Transmission of Sleep Apnea Patient Video with Sound over Mobile Network." International Journal of Emerging Research in Management and Technology 6, no. 11 (June 13, 2018): 81. http://dx.doi.org/10.23956/ijermt.v6i11.50.

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Mobile video-audio transmission systems have delivered patient video with relevant snoring sound to quantify the severity of the sleep apnea patient over wireless networks, but few have optimized video-audio transmission in combination with transmission protocol over error-prone environments using wireless links. In this paper, the performance of the MPEG (Motion Picture Expert Group)-4 error resilient tools with UDP(User Datagram Protocol) protocol were evaluated over a wireless network to suggest the optimum combination of MPEG-4 error resilient tools and UDP packet size suitable for real-time transmission of video-audio transmission over error-prone mobile networks. Through experimentation, it was found that the packet size should correspond to IP(Internet Protocol) datagram size minus UDP and IP header for optimal video-audio quality. Also, for error resilient tool selection, the combination of resynchronization marker and data partitioning showed the best performance.

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Yang Hu, W. A. Pearlman, and Xin Li. "Progressive Significance Map and Its Application to Error-Resilient Image Transmission." IEEE Transactions on Image Processing 21, no. 7 (July 2012): 3229–38. http://dx.doi.org/10.1109/tip.2012.2190084.

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Mehrabani, Yavar Safaei, Mona Parsapour, Mona Moradi, and Mehdi Bagherizadeh. "A Novel Efficient CNFET-Based Inexact Full Adder Design for Image Processing Applications." International Journal of Nanoscience 20, no. 02 (January 22, 2021): 2150016. http://dx.doi.org/10.1142/s0219581x21500162.

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Employing inexact arithmetic circuits in error-resilient applications results in reduction of hardware-level metrics such as power consumption, delay and occupied area. These criteria are very important in portable applications because they are battery limited. Full Adder cell is as a building block of many arithmetic circuits. Therefore, it can influence the performance of the entire digital system. This paper presents a novel low-power and high-speed design of one-bit inexact full adder cell based on 32-nm (CNFET) technology for error resilient applications. This design technique can be utilized in various applications particularly in image processing. The presented design employs capacitive threshold logic (CTL) approach which significantly reduces the number of transistors. The peak signal-to-noise ratio (PSNR) is considered to evaluate accuracy of circuits at application level. Then extensive simulations regarding various power supplies, temperatures and loads at transistor level are performed to measure power consumption and propagation delay criteria. Moreover, some new metrics are introduced to trade-off between application and hardware level parameters. Comprehensive simulations demonstrate the supremacy of the proposed cell than others.

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Yen-Chi Lee, Y. Altunbasak, and R. M. Mersereau. "Coordinated application of multiple description scalar quantization and error concealment for error-resilient MPEG video streaming." IEEE Transactions on Circuits and Systems for Video Technology 15, no. 4 (April 2005): 457–68. http://dx.doi.org/10.1109/tcsvt.2005.844446.

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Lee, Yen-Chi, Yucel Altunbasak, and Russell M. Mersereau. "An integrated application of multiple description transform coding and error concealment for error-resilient video streaming." Signal Processing: Image Communication 18, no. 10 (November 2003): 957–70. http://dx.doi.org/10.1016/j.image.2003.08.011.

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Huo, Mingxia, and Ying Li. "Error-resilient Monte Carlo quantum simulation of imaginary time." Quantum 7 (February 9, 2023): 916. http://dx.doi.org/10.22331/q-2023-02-09-916.

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Computing the ground-state properties of quantum many-body systems is a promising application of near-term quantum hardware with a potential impact in many fields. The conventional algorithm quantum phase estimation uses deep circuits and requires fault-tolerant technologies. Many quantum simulation algorithms developed recently work in an inexact and variational manner to exploit shallow circuits. In this work, we combine quantum Monte Carlo with quantum computing and propose an algorithm for simulating the imaginary-time evolution and solving the ground-state problem. By sampling the real-time evolution operator with a random evolution time according to a modified Cauchy-Lorentz distribution, we can compute the expected value of an observable in imaginary-time evolution. Our algorithm approaches the exact solution given a circuit depth increasing polylogarithmically with the desired accuracy. Compared with quantum phase estimation, the Trotter step number, i.e. the circuit depth, can be thousands of times smaller to achieve the same accuracy in the ground-state energy. We verify the resilience to Trotterisation errors caused by the finite circuit depth in the numerical simulation of various models. The results show that Monte Carlo quantum simulation is promising even without a fully fault-tolerant quantum computer.

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Reina, Salvatore, Robert Arcos, Arnau Clot, and Jordi Romeu. "An Efficient Experimental Methodology for the Assessment of the Dynamic Behaviour of Resilient Elements." Materials 13, no. 13 (June 27, 2020): 2889. http://dx.doi.org/10.3390/ma13132889.

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The assessment of the dynamic behaviour of resilient elements can be performed using the indirect method as described in the standard ISO 10846-3. This paper presents a methodology for control the error on the estimation of the frequency response functions (FRF) required for the application of the indirect method when sweep sine excitation is used. Based on a simulation process, this methodology allows for the design of the sweep sine excitation parameters, i.e., the sweep rate and the force amplitude, to control three types of errors associated to the experimentally obtained FRF in the presence of background noise: a general error of the FRF in a selected frequency range, and the errors associated to the amplitude and the frequency of the FRF resonance peak. The signal processing method used can be also tested with this methodology. The methodology has been tested in the characterisation of two different resilient elements: an elastomer and a coil spring. The simulated error estimations has been found to be in good agreement with the errors found in the measured FRF. Furthermore, it is found that for large signal-to-noise ratios, both sweep rate and force amplitude significantly affect the FRF estimation error, while, for small signal-to-noise ratios, only the force amplitude can control the error efficiently. The current methodology is specially interesting for laboratory test rigs highly used for the dynamic characterisation of resilient elements which are required to operate efficiently, since it can be used for minimising test times and providing quality assurance. Moreover, the application of this methodology would be specially relevant when characterisation is done in noisy environments.

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Shirani, Shahram, and Ali Jerbi. "Application of nonlinear pre- and post-processing in low bit rate, error resilient image communication." Signal Processing: Image Communication 18, no. 9 (October 2003): 823–35. http://dx.doi.org/10.1016/j.image.2003.06.002.

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Lin, Mingjie, Yu Bai, and John Wawrzynek. "Selectively Fortifying Reconfigurable Computing Device to Achieve Higher Error Resilience." Journal of Electrical and Computer Engineering 2012 (2012): 1–12. http://dx.doi.org/10.1155/2012/593532.

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With the advent of 10 nm CMOS devices and “exotic” nanodevices, the location and occurrence time of hardware defects and design faults become increasingly unpredictable, therefore posing severe challenges to existing techniques for error-resilient computing because most of them statically assign hardware redundancy and do not account for the error tolerance inherently existing in many mission-critical applications. This work proposes a novel approach to selectively fortifying a target reconfigurable computing device in order to achieve hardware-efficient error resilience for a specific target application. We intend to demonstrate that such error resilience can be significantly improved with effective hardware support. The major contributions of this work include (1) the development of a complete methodology to perform sensitivity and criticality analysis of hardware redundancy, (2) a novel problem formulation and an efficient heuristic methodology to selectively allocate hardware redundancy among a target design’s key components in order to maximize its overall error resilience, and (3) an academic prototype of SFC computing device that illustrates a 4 times improvement of error resilience for a H.264 encoder implemented with an FPGA device.

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Petracca, Matteo, Claudio Salvadori, Stefano Bocchino, and Paolo Pagano. "Error Resilient Video Streaming with BCH Code Protection in Wireless Sensor Networks." Journal of Communications Software and Systems 10, no. 1 (March 21, 2014): 41. http://dx.doi.org/10.24138/jcomss.v10i1.139.

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Video streaming in Wireless Sensor Networks (WSNs) is a promising and challenging application for enabling high-value services. In such a context, the reduced amount ofavailable bandwidth, as well as the low-computational power available for acquiring and processing video frames, imposes the transmission of low resolution images at a low frame rate. Considering the aforementioned limitations, the amount of information carried by each video frame must be considered of utmost importance and preserved, as much as possible, against network losses that could introduce possible artifacts in the reconstructed dynamics of the scene.In this paper we first evaluate the impact of the bit error rate on the quality of the received video stream in a real scenario, then we propose a forward error correction technique based on the use of BCH codes with the aim of preserving the video quality. The proposed technique, against already proposed techniques in the WSN research field, has been specially designed to maintain a full back-compatibility with the IEEE802.15.4 standard in order to create a suitable solution aiming at accomplishing the Internet of Things (IoT) vision. Performance results evaluated in terms of Peak Signal-to-Noise Ratio (PSNR) show that the proposed solution reaches a PSNR improvement of 4.16 dB with respect to an unprotected transmission, while requiring an additional overhead equal to 22.51% in number of transmitted bits, and minimal impact on frame rate reduction and energy consumption. When higher protection levels have been imposed, bigger PSNR values have been experienced at the cost of an increased additional overhead, lower frame rates, and bigger energy consumption values.

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Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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Liu, Yuntao, Michael Zuzak, Yang Xie, Abhishek Chakraborty, and Ankur Srivastava. "Robust and Attack Resilient Logic Locking with a High Application-Level Impact." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (May 11, 2021): 1–22. http://dx.doi.org/10.1145/3446215.

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Logic locking is a hardware security technique aimed at protecting intellectual property against security threats in the IC supply chain, especially those posed by untrusted fabrication facilities. Such techniques incorporate additional locking circuitry within an integrated circuit (IC) that induces incorrect digital functionality when an incorrect verification key is provided by a user. The amount of error induced by an incorrect key is known as the effectiveness of the locking technique. A family of attacks known as “SAT attacks” provide a strong mathematical formulation to find the correct key of locked circuits. To achieve high SAT resilience (i.e., complexity of SAT attacks), many conventional logic locking schemes fail to inject sufficient error into the circuit when the key is incorrect. For example, in the case of SARLock and Anti-SAT, there are usually very few (or only one) input minterms that cause any error at the circuit output. The state-of-the-art s tripped functionality logic locking (SFLL) technique provides a wide spectrum of configurations that introduced a tradeoff between SAT resilience and effectiveness. In this work, we prove that such a tradeoff is universal among all logic locking techniques. To attain high effectiveness of locking without compromising SAT resilience, we propose a novel logic locking scheme, called Strong Anti-SAT (SAS). In addition to SAT attacks, removal-based attacks are another popular kind of attack formulation against logic locking where the attacker tries to identify and remove the locking structure. Based on SAS, we also propose Robust SAS (RSAS) that is resilient to removal attacks and maintains the same SAT resilience and effectiveness as SAS. SAS and RSAS have the following significant improvements over existing techniques. (1) We prove that the SAT resilience of SAS and RSAS against SAT attack is not compromised by increase in effectiveness . (2) In contrast to prior work that focused solely on the circuit-level locking impact, we integrate SAS-locked modules into an 80386 processor and show that SAS has a high application-level impact. (3) Our experiments show that SAS and RSAS exhibit better SAT resilience than SFLL and their effectiveness is similar to SFLL.

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Arifuzzaman, Md, Muhammad Aniq Gul, Kaffayatullah Khan, and S. M. Zakir Hossain. "Application of Artificial Intelligence (AI) for Sustainable Highway and Road System." Symmetry 13, no. 1 (December 31, 2020): 60. http://dx.doi.org/10.3390/sym13010060.

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There are several environmental factors such as temperature differential, moisture, oxidation, etc. that affect the extended life of the modified asphalt influencing its desired adhesive properties. Knowledge of the properties of asphalt adhesives can help to provide a more resilient and durable asphalt surface. In this study, a hybrid of Bayesian optimization algorithm and support vector regression approach is recommended to predict the adhesion force of asphalt. The effects of three important variables viz., conditions (fresh, wet and aged), binder types (base, 4% SB, 5% SB, 4% SBS and 5% SBS), and Carbon Nano Tube doses (0.5%, 1.0% and 1.5%) on adhesive force are taken into consideration. Real-life experimental data (405 specimens) are considered for model development. Using atomic force microscopy, the adhesive strength of nanoscales of test specimens is determined according to functional groups on the asphalt. It is found that the model predictions overlap with the experimental data with a high R2 of 90.5% and relative deviation are scattered around zero line. Besides, the mean, median and standard deviations of experimental and the predicted values are very close. In addition, the mean absolute Error, root mean square error and fractional bias values were found to be low, indicating the high performance of the developed model.

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Masadeh, Mahmoud, Yassmeen Elderhalli, Osman Hasan, and Sofiene Tahar. "A Quality-assured Approximate Hardware Accelerators–based on Machine Learning and Dynamic Partial Reconfiguration." ACM Journal on Emerging Technologies in Computing Systems 17, no. 4 (October 31, 2021): 1–19. http://dx.doi.org/10.1145/3462329.

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Machine learning is widely used these days to extract meaningful information out of the Zettabytes of sensors data collected daily. All applications require analyzing and understanding the data to identify trends, e.g., surveillance, exhibit some error tolerance. Approximate computing has emerged as an energy-efficient design paradigm aiming to take advantage of the intrinsic error resilience in a wide set of error-tolerant applications. Thus, inexact results could reduce power consumption, delay, area, and execution time. To increase the energy-efficiency of machine learning on FPGA, we consider approximation at the hardware level, e.g., approximate multipliers. However, errors in approximate computing heavily depend on the application, the applied inputs, and user preferences. However, dynamic partial reconfiguration has been introduced, as a key differentiating capability in recent FPGAs, to significantly reduce design area, power consumption, and reconfiguration time by adaptively changing a selective part of the FPGA design without interrupting the remaining system. Thus, integrating “Dynamic Partial Reconfiguration” (DPR) with “Approximate Computing” (AC) will significantly ameliorate the efficiency of FPGA-based design approximation. In this article, we propose hardware-efficient quality-controlled approximate accelerators, which are suitable to be implemented in FPGA-based machine learning algorithms as well as any error-resilient applications. Experimental results using three case studies of image blending, audio blending, and image filtering applications demonstrate that the proposed adaptive approximate accelerator satisfies the required quality with an accuracy of 81.82%, 80.4%, and 89.4%, respectively. On average, the partial bitstream was found to be 28.6 smaller than the full bitstream .

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Arya, Mukesh Kumar, and Namit Gupta. "Adoptive Cloud Application in Semantic Web." International Journal of Advance Research and Innovation 2, no. 2 (2014): 48–51. http://dx.doi.org/10.51976/ijari.221407.

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Cloud computing has been envisioned as the next-generation architecture of IT enterprise. In contrast to traditional solutions, where the IT services are under proper physical, logical and personnel controls, cloud computing moves the application software and databases to the large data centers, where the management of the data and services may not be fully trustworthy. This unique attribute, however, poses many new security challenges which have not been well understood. In this article, we focus on cloud data storage security, which has always been an important aspect of quality of service. To ensure the correctness of users' data in the cloud, we propose an effective and flexible distributed scheme with two salient features, opposing to its predecessors. By utilizing the homomorphic token with distributed verification of erasure-coded data, our scheme achieves the integration of storage correctness insurance and data error localization, i.e., the identification of misbehaving server (s). Unlike most prior works, the new scheme further supports secure and efficient dynamic operations on data blocks, including: data update, delete and append. Extensive security and performance analysis shows that the proposed scheme is highly efficient and resilient against Byzantine failure, malicious data modification attack, and even server colluding attacks.

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18

Jardak, Nabil, and Quentin Jault. "The Potential of LEO Satellite-Based Opportunistic Navigation for High Dynamic Applications." Sensors 22, no. 7 (March 25, 2022): 2541. http://dx.doi.org/10.3390/s22072541.

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Resilient navigation in Global Navigation Satellite System (GNSS)-degraded and -denied environments is becoming more and more required for many applications. It can typically be based on multi-sensor data fusion that relies on alternative technologies to GNSS. In this work, we studied the potential of a low earth orbit (LEO) satellite communication system for a high-dynamic application, when it is integrated with an inertial measurement unit (IMU) and magnetometers. We derived the influence of the main error sources that affect the LEO space vehicle (SV) Doppler-based navigation on both positioning and attitude estimations. This allowed us to determine the best, intermediate and worst cases of navigation performances. We show that while the positioning error is large due to large orbit errors or high SV clock drifts, it becomes competitive with that of an inertial navigation system (INS) based on a better quality IMU if precise satellite orbits are available. On the other hand, the attitude estimation tolerates large orbit errors and high SV clock drifts. The obtained results suggest that LEO SV signals, used as signals of opportunity for navigation, are an attractive alternative in GNSS-denied environments for high dynamic vehicles.

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SINEGLAZOV, Victor, Olena CHUMACHENKO, and Vladyslav GORBATIUK. "FORECASTING AIRCRAFT MILES FLOWN TIME SERIES USING A DEEP LEARNING-BASED HYBRID APPROACH." Aviation 22, no. 1 (May 30, 2018): 6–12. http://dx.doi.org/10.3846/aviation.2018.2048.

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Neural network-based methods such as deep neural networks show great efficiency for a wide range of applications. In this paper, a deep learning-based hybrid approach to forecast the yearly revenue passenger kilometers time series of Australia’s major domestic airlines is proposed. The essence of the approach is to use a resilient error backpropagation algorithm with dropout for “tuning” the polynomial neural network, obtained as a result of a multi-layered GMDH algorithm. The article compares the performance of the suggested algorithm on the time series with other popular forecasting methods: deep belief network, multi-layered GMDH algorithm, Box-Jenkins method and the ANFIS model. The minimum reached MAE of the proposed algorithm was approximately 25% lower than the minimum MAE of the next best method – GMDH, thus indicating that the practical application of the algorithm can give good results compared with other well-known methods.

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Nagarajan, Manikandan, A. Sasikumar, D. Muralidharan, and Muthaiah Rajappa. "Fixed point multi-bit approximate adder based convolutional neural network accelerator for digit classification inference." Journal of Intelligent & Fuzzy Systems 39, no. 6 (December 4, 2020): 8521–28. http://dx.doi.org/10.3233/jifs-189169.

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Approximate computing is a rapidly growing technique to speed up applications with less computational effort while maintaining the accuracy of error-resilient applications such as machine learning and deep learning. Inheritance properties of the machine and deep learning process give freedom for the designer to simplify the circuitry to speed up the computation process at the expense of accuracy of computational results. Fundamental blocks of any computation are adders. In order to optimize it for better performance, 2-bit multi-bit approximate adders (MAPX) are proposed in this work which breaks the lengthy carry chain. In contrast with other approximate larger width adders, instead of using accurate adders for the most significant part, here proposed 2-bit MAPX-1 and MAPX-2 adders are arranged in various ways to compose most and least significant parts. Designed 8-bit and 16-bit adders are evaluated for their performance and error characteristics. Proposed 2-bit MAPX-2 shows better error characteristics whose MED is 0.250 while occupying less area and MAPX-1 consumes less power and delay at the cost of accuracy. Among the extended adders, MAPX 8-bit adder design1 outperforms the best performing APX based 8-bit adder design1. The error performance of it is improved by 14%, 42.1% and 50.4% compared to the existing well-performing APX 8-bit Design1, Design2 and Design3 respectively. Similarly, proposed MAPX 16-bit Design1 exhibits overwhelming performance compared to best performing APX 16-bit Design1, and its error performance is improved by 24.3%, 34.9% and 50.3% compared to APX 16-bit Design1, Design2 and Design3 respectively. In order to evaluate the proposed adder for a real application, extended MAPX 16-bit Design1 is fit in the convolution layer of Low Weights Digit Detector (LWDD) convolutional neural network-based digit classification system. Our modified system accelerates the computation process by 1.25 factors while exhibiting the accuracy of 91% and it best fits error-tolerant real applications. All the adders are synthesized and implemented in the Intel Cyclone IV EP4CE22F17C6N FPGA.

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Perri, Stefania, Fanny Spagnolo, Fabio Frustaci, and Pasquale Corsonello. "Efficient Approximate Adders for FPGA-Based Data-Paths." Electronics 9, no. 9 (September 18, 2020): 1529. http://dx.doi.org/10.3390/electronics9091529.

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Approximate computing represents a powerful technique to reduce energy consumption and computational delay in error-resilient applications, such as multimedia processing, machine learning, and many others. In these contexts, designing efficient digital data-paths is a crucial concern. For this reason, the addition operation has received a great deal of attention. However, most of the approximate adders proposed in the literature are oriented to Application Specific Integrated Circuits (ASICs), and their deployment on different devices, such as Field Programmable Gate Arrays (FPGAs), appears to be unfeasible (or at least ineffective). This paper presents a novel approximate addition technique thought to efficiently exploit the configurable resources available within an FPGA device. The proposed approximation strategy sums the k least significant bits two-by-two by using 4-input Look-up-Tables (LUTs), each performing a precise 2-bit addition with the zeroed carry-in. In comparison with several FPGA-based approximate adders in the existing literature, the novel adder achieves markedly improved error characteristics without compromising either the power consumption or the delay. As an example, when implemented within the Artix-7 xc7a100tcsg324-3 chip, the 32-bit adder designed as proposed here with k = 8 performs as fast as its competitors and reduces the Mean Error Distance (MED) by up to 72% over the state-of-the-art approximate adders, with an energy penalty of just 8% in the worst scenario. The integration of the new approximate adder within a more complex application, such as the 2D digital image filtering, has shown even better results. In such a case, the MED is reduced by up to 97% with respect to the FPGA-based counterparts proposed in the literature.

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Taheri, MohammadReza, Fazel Sharifi, MohammadAli Shafiabadi, Hamid Mahmoodi, and Keivan Navi. "Spin-Based Imprecise 4-2 Compressor for Energy-Efficient Multipliers." SPIN 09, no. 03 (September 2019): 1950011. http://dx.doi.org/10.1142/s2010324719500115.

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The 4-2 compressor has been widely employed in the design of multipliers. The considerable impact of 4-2 compressors on the efficiency of multipliers has created significant research interests in design of new compressor structures. In the vast range of error resilient applications, multiplication plays an important role in performing computation. Imprecise (approximate) realization of multiplication results in considerable area, power and delay efficiency at the cost of negligible computational errors. In this paper, an imprecise 4-2 compressor is presented. Spintronic devices as promising alternative technologies for silicon-based FET are considered for implementation of the proposed design. All designs are simulated exhaustively at the circuit level and application level. The conducted simulations indicate the superiority of the proposed design compared with the related state-of-the-art in all aspects. The proposed design has more than two and three times lower power and power delay product, respectively, compared to the best previous design.

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Lee, Chanhwa. "Observability Decomposition-Based Decentralized Kalman Filter and Its Application to Resilient State Estimation under Sensor Attacks." Sensors 22, no. 18 (September 13, 2022): 6909. http://dx.doi.org/10.3390/s22186909.

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This paper considers a discrete-time linear time invariant system in the presence of Gaussian disturbances/noises and sparse sensor attacks. First, we propose an optimal decentralized multi-sensor information fusion Kalman filter based on the observability decomposition when there is no sensor attack. The proposed decentralized Kalman filter deploys a bank of local observers who utilize their own single sensor information and generate the state estimate for the observable subspace. In the absence of an attack, the state estimate achieves the minimum variance, and the computational process does not suffer from the divergent error covariance matrix. Second, the decentralized Kalman filter method is applied in the presence of sparse sensor attacks as well as Gaussian disturbances/noises. Based on the redundant observability, an attack detection scheme by the χ2 test and a resilient state estimation algorithm by the maximum likelihood decision rule among multiple hypotheses, are presented. The secure state estimation algorithm finally produces a state estimate that is most likely to have minimum variance with an unbiased mean. Simulation results on a motor controlled multiple torsion system are provided to validate the effectiveness of the proposed algorithm.

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Huang, Lvwen, Lianliang Chen, Qin Wang, Siwen Yan, Xunbing Gao, and Jiangjiang Luan. "Regional Short-term Micro-climate Air Temperature Prediction with CBPNN." E3S Web of Conferences 53 (2018): 03009. http://dx.doi.org/10.1051/e3sconf/20185303009.

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This paper proposes a novel short-term air temperature prediction with three-layer Back Propagation Neural Network (BPNN) for the regional application of next 1-12 hours. With the continuous collection of eight real-time micro-climate parameters in the experimentation and demonstration stations in our university, the Multiple Stepwise Regression (MSR) is employed to screen the original historical data to find the parameter factors with greater contribution rate. On the basis of the Root Mean Square Error (RMSE) value evaluating the optimal fitting degree of the stepwise regression, the Levenberg-Marquardt (LM) and the Resilient Propagation (R-Prop) training algorithm are employed to construct a Combined BPNN (CBPNN) with two MSR inputs. Compared with the known micro-climate data sets, the Mean Absolute Error (MAE) is to evaluate the applicability of CBPNN prediction model. The experimentation shows that the MAE is within 4°C in the next 12 hours. This proposal will be deployed in stations in our university for extreme weather warnings, and could be applied to some regional short-term parameter prediction for the future agricultural production service.

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Ebrahimi, Zahra, Dennis Klar, Mohammad Aasim Ekhtiyar, and Akash Kumar. "Plasticine: A Cross-layer Approximation Methodology for Multi-kernel Applications through Minimally Biased, High-throughput, and Energy-efficient SIMD Soft Multiplier-divider." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (March 31, 2022): 1–33. http://dx.doi.org/10.1145/3486616.

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The rapid evolution of error-resilient programs intertwined with their quest for high throughput has motivated the use of Single Instruction, Multiple Data (SIMD) components in Field-Programmable Gate Arrays (FPGAs). Particularly, to exploit the error-resiliency of such applications, Cross-layer approximation paradigm has recently gained traction, the ultimate goal of which is to efficiently exploit approximation potentials across layers of abstraction. From circuit- to application-level, valuable studies have proposed various approximation techniques, albeit linked to four drawbacks: First, most of approximate multipliers and dividers operate only in SISD mode. Second, imprecise units are often substituted, merely in a single kernel of a multi-kernel application, with an end-to-end analysis in Quality of Results (QoR) and not in the gained performance. Third, state-of-the-art (SoA) strategies neglect the fact that each kernel contributes differently to the end-to-end QoR and performance metrics. Therefore, they lack in adopting a generic methodology for adjusting the approximation knobs to maximize performance gains for a user-defined quality constraint. Finally, multi-level techniques lack in being efficiently supported, from application-, to architecture-, to circuit-level, in a cohesive cross-layer hierarchy. In this article, we propose Plasticine , a cross-layer methodology for multi-kernel applications, which addresses the aforementioned challenges by efficiently utilizing the synergistic effects of a chain of techniques across layers of abstraction. To this end, we propose an application sensitivity analysis and a heuristic that tailor the precision at constituent kernels of the application by finding the most tolerable degree of approximations for each of consecutive kernels, while also satisfying the ultimate user-defined QoR. The chain of approximations is also effectively enabled in a cross-layer hierarchy, from application- to architecture- to circuit-level, through the plasticity of SIMD multiplier-dividers, each supporting dynamic precision variability along with hybrid functionality. The end-to-end evaluations of Plasticine on three multi-kernel applications employed in bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) demonstrate 41%–64%, 39%–62%, and 70%–86% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over 32-bit fixed precision, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https://cfaed.tu-dresden.de/pd-downloads.

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Korotkiy, Viktor, and Igor' Vitovtov. "Approximation of Physical Spline with Large Deflections." Geometry & Graphics 9, no. 1 (July 22, 2021): 3–19. http://dx.doi.org/10.12737/2308-4898-2021-9-1-3-19.

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Physical spline is a resilient element whose cross-sectional dimensions are very small compared to its axis’s length and radius of curvature. Such a resilient element, passing through given points, acquires a "nature-like" form, having a minimum energy of internal stresses, and, as a consequence, a minimum of average curvature. For example, a flexible metal ruler, previously used to construct smooth curves passing through given coplanar points, can be considered as a physical spline. The theoretical search for the equation of physical spline’s axis is a complex mathematical problem with no elementary solution. However, the form of a physical spline passing through given points can be obtained experimentally without much difficulty. In this paper polynomial and parametric methods for approximation of experimentally produced physical spline with large deflections are considered. As known, in the case of small deflections it is possible to obtain a good approximation to a real elastic line by a set of cubic polynomials ("cubic spline"). But as deflections increase, the polynomial model begins to differ markedly from the experimental physical spline, that limits the application of polynomial approximation. High precision approximation of an elastic line with large deflections is achieved by using a parameterized description based on Ferguson or Bézier curves. At the same time, not only the basic points, but also the tangents to the elastic line of the real physical spline should be given as boundary conditions. In such a case it has been shown that standard cubic Bézier curves have a significant computational advantage over Ferguson ones. Examples for modelling of physical splines with free and clamped ends have been considered. For a free spline an error of parametric approximation is equal to 0.4 %. For a spline with clamped ends an error of less than 1.5 % has been obtained. The calculations have been performed with SMath Studio computer graphics system.

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Cevher, Elçin Yeşiloğlu, and Demet Yıldırım. "Using Artificial Neural Network Application in Modeling the Mechanical Properties of Loading Position and Storage Duration of Pear Fruit." Processes 10, no. 11 (November 1, 2022): 2245. http://dx.doi.org/10.3390/pr10112245.

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In the study, rupture energy values of Deveci and Abate Fetel pear fruits were predicted using artificial neural network (ANN). This research aimed to develop a simple, accurate, rapid, and economic model for harvest/post-harvest loss of efficiently predicting rupture energy values of Deveci and Abate Fetel pear fruits. The breaking energy of the pears was examined in terms of storage time and loading position. The experiments were carried out in two stages, with samples kept in cold storage immediately after harvest and 30 days later. Rupture energy values were estimated using four different single and multi-layer ANN models. Four different model results obtained using Levenberg–Marquardt, Scaled Conjugate Gradient, and resilient backpropagation training algorithms were compared with the calculated values. Statistical parameters such as R2, RMSE, MAE, and MSE were used to evaluate the performance of the methods. The best-performing model was obtained in network structure 5-1 that used three inputs: the highest R2 value (0.90) and the lowest square of the root error (0.018), and the MAE (0.093).

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Jeong, Jonghyun, and Youngmin Kim. "ASAD-RD: Accuracy Scalable Approximate Divider Based on Restoring Division for Energy Efficiency." Electronics 10, no. 1 (December 28, 2020): 31. http://dx.doi.org/10.3390/electronics10010031.

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Approximate computing can considerably improve energy efficiency by mitigating the accuracy requirements of calculations in error resilient application programming, such as machine learning, audio–video signal processing, data mining, and search engines. In this study, we propose an approximate divider for dynamic energy-quality scaling, which involves a trade-off between accuracy and latency. Previous approximate dividers for dynamic energy-quality scaling are well-configured, but lack energy-quality scalability. The key is to create a more accurate dynamic approximate divider while extending the limits of accuracy to maximize energy efficiency and meet various accuracy requirements. The proposed divider, called the accuracy scalable approximate divider based on restoring division (ASAD-RD), uses restoring division to significantly improve the error of the approximate divider and to use less latency. For the 8-bit division, SAADI, the previous design, has an average accuracy of 90.78% to 98.77%; however, ASAD-RD can improve the accuracy between 95.2% and 99.23% and hardly requires additional power consumption. Furthermore, for the same target accuracy, ASAD-RD requires fewer cycle iterations than SAADI. Thus, ASAD-RD requires lower energy than SAADI and can operate as an energy-efficient approximate divider.

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Ramya, K. P., R. Chithra Devi, M. K. Revathi, and P. Annapandi. "Sensor Data Hiding Based on Image Watermarking Using Interpolation Technique over Inter-Packet Delays." Applied Mechanics and Materials 573 (June 2014): 543–48. http://dx.doi.org/10.4028/www.scientific.net/amm.573.543.

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Large number of application areas, like location-based services, transaction logs, sensor networks are qualified by uninterrupted data stream from many. Sensor data handling of continuous data needs to cover various issues, admitting the storage efficiency, processing throughput, bandwidth conception and secure transmission. This paper addresses the challenges by providing secure and efficient transmission of sensor data by embedding it over the inter-packet delays (IPDs). The embedding of sensor data within a host medium makes this technique reminiscent of watermarking. Interpolation technique is used to hide the sensor data into an image which is send to another node. By enforcing linear enlargement to interpolation-errors, a extremely effective reversible watermarking scheme is achieved, which can ensure high image quality without sacrificing embedding capacity. Time-Based flow watermarking technique is proposed, that avoids data degradation due to traditional watermarking. Sensor data is extracted effectively based on the inter-packet delays that minimizes the probability of decoding error. The outcome of the observation depicts that this system is scalable and highly resilient in sensor data.

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Ait Said, Noureddine, Mounir Benabdenbi, and Katell Morin-Allory. "Self-Adaptive Run-Time Variable Floating-Point Precision for Iterative Algorithms: A Joint HW/SW Approach." Electronics 10, no. 18 (September 9, 2021): 2209. http://dx.doi.org/10.3390/electronics10182209.

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Using standard Floating-Point (FP) formats for computation leads to significant hardware overhead since these formats are over-designed for error-resilient workloads such as iterative algorithms. Hence, hardware FP Unit (FPU) architectures need run-time variable precision capabilities. In this work, we propose a new method and an FPU architecture that enable designers to dynamically tune FP computations’ precision automatically at run-time called Variable Precision in Time (VPT), leading to significant power consumption, execution time, and energy savings. In spite of its circuit area overhead, the proposed approach simplifies the integration of variable precision in existing software workloads at any level of the software stack (OS, RTOS, or application-level): it only requires lightweight software support and solely relies on traditional assembly instructions, without the need for a specialized compiler or custom instructions. We apply the technique on the Jacobi and the Gauss–Seidel iterative methods taking full advantage of the suggested FPU. For each algorithm, two modified versions are proposed: a conservative version and a relaxed one. Both algorithms are analyzed and compared statistically to understand the effects of VPT on iterative applications. The implementations demonstrate up to 70.67% power consumption saving, up to 59.80% execution time saving, and up to 88.20% total energy saving w.r.t the reference double precision implementation, and with no accuracy loss.

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Bonilla-Granados, C. A., N. J. Cely-Calixto, and G. A. Carrillo Soto. "Hydraulic optimization of the physical parameters of a drinking water distribution system." Journal of Physics: Conference Series 2139, no. 1 (December 1, 2021): 012013. http://dx.doi.org/10.1088/1742-6596/2139/1/012013.

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Abstract Drinking-water distribution systems are generally designed with methodologies based on trial-and-error tests, which generate feasible results. However, these trials are not the most economical and reliable solution since they do not consider the optimization of the network. For the present work, the hydraulic model of the drinking water distribution network of San José de Cúcuta, Colombia, was optimized by applying the concept of resilience rate and minimum cost. The development of the work consisted of the hydraulic modeling of the physical components of the network in EPANET software, as well as the application of calculations of the connectivity coefficient and the unitary power of each section. With the data obtained from the modeling and calculations, the physical parameters were optimized, and the cost-benefit ratio was estimated. It was found that the current drinking water distribution system does not have a power surplus to overcome a system failure. The optimization increased the total energy surplus of the network (261%) and the resilience rate (585%). Also, the connectivity coefficient was improved with an average value of 0.95. The hydraulic optimization methodology applied resulted in a network resilient to system failures.

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32

Jagdish, Mukta, Amelec Viloria, Jesus Vargas, Omar Bonerge Pineda Lezama, and David Ovallos-Gazabon. "Modeling software architecture design on data storage security in cloud computing environments." Journal of Intelligent & Fuzzy Systems 39, no. 6 (December 4, 2020): 8557–64. http://dx.doi.org/10.3233/jifs-189172.

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Cloud-based computation is known as the source architecture of the upcoming generation of IT enterprise. In context to up-coming trade solutions, the Information Technology sections are established under logical, personnel, and physical control, it transfers application software and large database to appropriate data centers, where security and management of database with services are not trustworthy fully. So this process may face many challenges towards society and organizations and that not been well understood over a while duration. This becomes one of the major challenges days today. So in this research, it focuses on security-based data storage using cloud, which plays one of the important aspects bases on qualities of services. To assure user data correctness in the cloud system, a flexible and effective distributed technique with two different salient features was examined by utilizing the token called homomorphic with erasure-coded data for distributed verification, based on this technique it achieved error data localization and integration of storage correctness. Also, it identifies server misbehaving, efficient, and security-based dynamic operations on data blocking such as data append, delete, and update methods. Performance analysis and security show the proposed method is more effective resilient and efficient against Byzantine failure, even server colluding attacks and malicious data modification attacks.

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Agullo, Emmanuel, Mirco Altenbernd, Hartwig Anzt, Leonardo Bautista-Gomez, Tommaso Benacchio, Luca Bonaventura, Hans-Joachim Bungartz, et al. "Resiliency in numerical algorithm design for extreme scale simulations." International Journal of High Performance Computing Applications 36, no. 2 (December 10, 2021): 251–85. http://dx.doi.org/10.1177/10943420211055188.

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This work is based on the seminar titled ‘Resiliency in Numerical Algorithm Design for Extreme Scale Simulations’ held March 1–6, 2020, at Schloss Dagstuhl, that was attended by all the authors. Advanced supercomputing is characterized by very high computation speeds at the cost of involving an enormous amount of resources and costs. A typical large-scale computation running for 48 h on a system consuming 20 MW, as predicted for exascale systems, would consume a million kWh, corresponding to about 100k Euro in energy cost for executing 1023 floating-point operations. It is clearly unacceptable to lose the whole computation if any of the several million parallel processes fails during the execution. Moreover, if a single operation suffers from a bit-flip error, should the whole computation be declared invalid? What about the notion of reproducibility itself: should this core paradigm of science be revised and refined for results that are obtained by large-scale simulation? Naive versions of conventional resilience techniques will not scale to the exascale regime: with a main memory footprint of tens of Petabytes, synchronously writing checkpoint data all the way to background storage at frequent intervals will create intolerable overheads in runtime and energy consumption. Forecasts show that the mean time between failures could be lower than the time to recover from such a checkpoint, so that large calculations at scale might not make any progress if robust alternatives are not investigated. More advanced resilience techniques must be devised. The key may lie in exploiting both advanced system features as well as specific application knowledge. Research will face two essential questions: (1) what are the reliability requirements for a particular computation and (2) how do we best design the algorithms and software to meet these requirements? While the analysis of use cases can help understand the particular reliability requirements, the construction of remedies is currently wide open. One avenue would be to refine and improve on system- or application-level checkpointing and rollback strategies in the case an error is detected. Developers might use fault notification interfaces and flexible runtime systems to respond to node failures in an application-dependent fashion. Novel numerical algorithms or more stochastic computational approaches may be required to meet accuracy requirements in the face of undetectable soft errors. These ideas constituted an essential topic of the seminar. The goal of this Dagstuhl Seminar was to bring together a diverse group of scientists with expertise in exascale computing to discuss novel ways to make applications resilient against detected and undetected faults. In particular, participants explored the role that algorithms and applications play in the holistic approach needed to tackle this challenge. This article gathers a broad range of perspectives on the role of algorithms, applications and systems in achieving resilience for extreme scale simulations. The ultimate goal is to spark novel ideas and encourage the development of concrete solutions for achieving such resilience holistically.

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Jain, Riya, and Neeta Pandey. "Approximate Karatsuba multiplier for error-resilient applications." AEU - International Journal of Electronics and Communications 130 (February 2021): 153579. http://dx.doi.org/10.1016/j.aeue.2020.153579.

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F. M. AKINSEYE, A. H. FOLORUNSHO, AJEIGBE, A. HAKEEM, and S. O. AGELE. "Impacts of rainfall and temperature on photoperiod insensitive sorghum cultivar : model evaluation and sensitivity analysis." Journal of Agrometeorology 21, no. 3 (November 10, 2021): 262–69. http://dx.doi.org/10.54386/jam.v21i3.248.

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A combination of local-scale climate and crop simulation model were used to investigate the impacts of change in temperature and rainfall on photoperiod insensitive sorghum in the Sudanian zone of Mali. In this study, the response of temperature and rainfall to yield patterns of photoperiod insensitive sorghum (Sorghum bicolor L. Moench) using the Agricultural Production Systems Simulator (APSIM) model was evaluated. Following model calibration of the cultivar at varying sowing dates over two growing seasons (2013 and 2014), a long-term simulation was run using historical weather data (1981-2010) to determine the impacts of temperature and rainfall on grain yield, total biomass and water use efficiency at varying nitrogen fertilizer applications. The results showed that model performance was excellent with the lowest mean bias error (MBE) of -2.2 days for flowering and 1.4 days for physiological maturity. Total biomass and grain yield were satisfactorily reproduced, indicating fairly low RMSE values of 21.3% for total biomass and very low RMSE of 11.2 % for grain yield of the observed mean. Simulations at varying Nfertilizer application rate with increased temperature of 2 °C, 4 °C and 6 °C and decreased rainfall by 25 and 50 % (W-25% and W-50%) posed a highly significant risk to low yield compared to increase in rainfall. However, the magnitude of temperature changes showed a decline in grain yield by 10%, while a decrease in rainfall by W-25% and W-50% resulted in yield decline between 5% and 37%, respectively. Thus, climate-smart site-specific utilization of the photoperiod insensitive sorghum cultivar suggests more resilient and productive farming systems for sorghum in semi-arid regions of Mali.

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Cho, Hyungmin, Larkhoon Leem, and Subhasish Mitra. "ERSA: Error Resilient System Architecture for Probabilistic Applications." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 4 (April 2012): 546–58. http://dx.doi.org/10.1109/tcad.2011.2179038.

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37

Gowtham, P., P. Sasipriya, and A. Anita Angeline. "Design of Approximate Restoring Dividers for Error Resilient Applications." ECS Transactions 107, no. 1 (April 24, 2022): 13675–86. http://dx.doi.org/10.1149/10701.13675ecst.

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In this paper, a low-power and high-speed approximate divider using restoring array architecture has been proposed. Approximation is realized by replacing the subtractor/divider cells with the approximate subtractor/divider cells through the use of reduced gate level complexity. Four approximate divider architectures, namely, AD1, AD2, AD3, and AD4, have been proposed. The amount of approximation can be scaled by introducing the approximation factor and the proposed dividers have been analyzed for different values of approximation factor. The simulation results show that the proposed dividers AD1, AD2, AD3, and AD4, with approximation factor of 10 have achieved power reduction of 17%, 30%, 23%, and 37% respectively, when compared to the exact restoring divider. The proposed dividers have also been compared with the existing approximate restoring divider and shows signification reduction in power and delay. All the simulations are carried out using 180nm CMOS technology. The image processing applications, such as change detection and background removal, have been implemented using the proposed divider to show the feasibility of employing the approximate divider for real time applications. The simulation results prove that the approximate dividers have realized a feasible PSNR for the resultant images.

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Arya, Neelam, Manisha Pattanaik, and G. K. Sharma. "Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29, no. 11 (November 2021): 1994–97. http://dx.doi.org/10.1109/tvlsi.2021.3114616.

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39

Davidson, R. L., and C. P. Bridges. "Error Resilient GPU Accelerated Image Processing for Space Applications." IEEE Transactions on Parallel and Distributed Systems 29, no. 9 (September 1, 2018): 1990–2003. http://dx.doi.org/10.1109/tpds.2018.2812853.

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Park, S. B., C. S. Kim, and S. U. Lee. "Error Resilient 3-D Mesh Compression." IEEE Transactions on Multimedia 8, no. 5 (October 2006): 885–95. http://dx.doi.org/10.1109/tmm.2006.879914.

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Ho, Long, Cassia Pompeu, Wout Van Echelpoel, Olivier Thas, and Peter Goethals. "Model-Based Analysis of Increased Loads on the Performance of Activated Sludge and Waste Stabilization Ponds." Water 10, no. 10 (October 10, 2018): 1410. http://dx.doi.org/10.3390/w10101410.

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In a way to counter criticism on low cost-effective conventional activated sludge (AS) technology, waste stabilization ponds (WSPs) offer a valid alternative for wastewater treatment due to their simple and inexpensive operation. To evaluate this alternative with respect to its robustness and resilience capacity, we perform in silico experiments of different peak-load scenarios in two mathematical models representing the two systems. A systematic process of quality assurance for these virtual experiments is implemented, including sensitivity and identifiability analysis, with non-linear error propagation. Moreover, model calibration of a 210-day real experiment with 31 days of increased load was added to the evaluation. Generally speaking, increased-load scenarios run in silico showed that WSP systems are more resilient towards intermediate disturbances, hence, are suitable to treat not only municipal wastewater, but also industrial wastewater, such as poultry wastewater, and paperboard wastewater. However, when disturbances are extreme (over 7000 mg COD·L−1), the common design of the natural system fails to perform better than AS. Besides, the application of sensitivity analysis reveals the most influential parameters on the performance of the two systems. In the AS system, parameters related to autotrophic bacteria have the highest influence on the dynamics of particulate organic matter, while nitrogen removal is largely driven by nitrification and denitrification. Conversely, with an insignificant contribution of heterotrophs, the nutrient removal in the pond system is mostly done by algal assimilation. Furthermore, this systematic model-based analysis proved to be a suitable means for investigating the maximum load of wastewater treatment systems, and from that avoiding environmental problems and high economic costs for cleaning surface waters after severe overload events.

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S., Skandha Deepsita, and Noor Mahammad Sk. "Low power, high speed approximate multiplier for error resilient applications." Integration 84 (May 2022): 37–46. http://dx.doi.org/10.1016/j.vlsi.2022.01.001.

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43

Raha, Arnab, and Vijay Raghunathan. "Synergistic Approximation of Computation and Memory Subsystems for Error-Resilient Applications." IEEE Embedded Systems Letters 9, no. 1 (March 2017): 21–24. http://dx.doi.org/10.1109/les.2017.2658566.

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44

Agarwal, Rachit, Emanuel Popovici, Massimiliano Sala, and Brendan O'Flynn. "Error resilient data transport in sensor network applications: A generic perspective." International Journal of Circuit Theory and Applications 37, no. 2 (March 2009): 377–96. http://dx.doi.org/10.1002/cta.550.

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45

Garg, Bharat, and G. K. Sharma. "ACM: An Energy-Efficient Accuracy Configurable Multiplier for Error-Resilient Applications." Journal of Electronic Testing 33, no. 4 (June 24, 2017): 479–89. http://dx.doi.org/10.1007/s10836-017-5667-8.

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46

Piñol, Pablo, Miguel Martinez-Rach, Pablo Garrido, Otoniel Lopez-Granado, and Manuel Malumbres. "Error Resilient Coding Techniques for Video Delivery over Vehicular Networks." Sensors 18, no. 10 (October 17, 2018): 3495. http://dx.doi.org/10.3390/s18103495.

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Nowadays, more and more vehicles are equipped with communication capabilities, not only providing connectivity with onboard devices, but also with off-board communication infrastructures. From road safety (i.e., multimedia e-call) to infotainment (i.e., video on demand services), there are a lot of applications and services that may be deployed in vehicular networks, where video streaming is the key factor. As it is well known, these networks suffer from high interference levels and low available network resources, and it is a great challenge to deploy video delivery applications which provide good quality video services. We focus our work on supplying error resilience capabilities to video streams in order to fight against the high packet loss rates found in vehicular networks. So, we propose the combination of source coding and channel coding techniques. The former ones are applied in the video encoding process by means of intra-refresh coding modes and tile-based frame partitioning techniques. The latter one is based on the use of forward error correction mechanisms in order to recover as many lost packets as possible. We have carried out an extensive evaluation process to measure the error resilience capabilities of both approaches in both (a) a simple packet error probabilistic model, and (b) a realistic vehicular network simulation framework. Results show that forward error correction mechanisms are mandatory to guarantee video delivery with an acceptable quality level , and we highly recommend the use of the proposed mechanisms to increase even more the final video quality.

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47

Jha, Chandan Kumar, Shreyas Singh, Riddhi Thakker, Manu Awasthi, and Joycee Mekie. "Zero Aware Configurable Data Encoding by Skipping Transfer for Error Resilient Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 68, no. 8 (August 2021): 3337–50. http://dx.doi.org/10.1109/tcsi.2021.3081623.

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48

Van Toan, Nguyen, and Jeong-Gun Lee. "FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications." IEEE Access 8 (2020): 25481–97. http://dx.doi.org/10.1109/access.2020.2970968.

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Kanduri, Anil, Mohammad-Hashem Haghbayan, Amir M. Rahmani, Pasi Liljeberg, Axel Jantsch, Hannu Tenhunen, and Nikil Dutt. "Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 10 (October 2017): 2749–62. http://dx.doi.org/10.1109/tvlsi.2017.2694388.

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Tao Fang and Lap-Pui Chau. "An error-resilient GOP structure for robust video transmission." IEEE Transactions on Multimedia 7, no. 6 (December 2005): 1131–38. http://dx.doi.org/10.1109/tmm.2005.858399.

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