Дисертації з теми "Energy chirp"
Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями
Ознайомтеся з топ-50 дисертацій для дослідження на тему "Energy chirp".
Біля кожної праці в переліку літератури доступна кнопка «Додати до бібліографії». Скористайтеся нею – і ми автоматично оформимо бібліографічне посилання на обрану працю в потрібному вам стилі цитування: APA, MLA, «Гарвард», «Чикаго», «Ванкувер» тощо.
Також ви можете завантажити повний текст наукової публікації у форматі «.pdf» та прочитати онлайн анотацію до роботи, якщо відповідні параметри наявні в метаданих.
Переглядайте дисертації для різних дисциплін та оформлюйте правильно вашу бібліографію.
Lutman, Alberto. "Impact of the wakefields and of an initial energy curvature on a Free Electron Laser." Doctoral thesis, Università degli studi di Trieste, 2010. http://hdl.handle.net/10077/3678.
Повний текст джерелаFor an X-ray free electron laser (FEL), a high-quality electron bunch with low emittance, high peak current and energy is needed. During the phases of acceleration, bunch compression and transportation, the electron beam is subject to radio frequency curvature and to wakefields effects. Thus, the energy profile of the electron beam can present a parabolic profile, which has important electromagnetic effects on the FEL process. The quality of the electron beam is also degraded by the interaction with the low-gap undulator vacuum chamber. In our work we first analyze this interaction, deriving a formula to evaluate the longitudinal and the transversal wakefields for an elliptical cross section vacuum chamber, obtaining accurate results in the short range. Subsequently within the Vlasov-Maxwell one-dimensional model, we derive the Green functions necessary to evaluate the radiation envelope, having as initial conditions both an energy chirp and curvature on the electrons and eventually an initial bunching, which is useful to treat the harmonic generation FEL cascade configuration. This allows to study the impact of the elecron beam energy profile on the FEL performance. Using the derived Green functions we discuss FEL radiation properties such as bandwidth, frequency shift, frequency chirp and velocity of propagation. Finally, we propose a method to achieve ultra-short FEL pulses using a frequency chirp on the seed laser and a suitable electron energy profile.
XXII Ciclo
1980
Konstantakopoulos, Theodoros K. 1977. "Energy scalability of on-chip interconnection networks." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40315.
Повний текст джерелаThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Page 198 blank.
Includes bibliographical references (p. 191-197).
On-chip interconnection networks (OCN) such as point-to-point networks and buses form the communication backbone in multiprocessor systems-on-a-chip, multicore processors, and tiled processors. OCNs consume significant portions of a chip's energy budget, so their energy analysis early in the design cycle becomes important for architectural design decisions. Although innumerable studies have examined OCN implementation and performance, there have been few energy analysis studies. This thesis develops an analytical framework for energy estimation in OCNs, for any given topology and arbitrary communication patterns, and presents OCN energy results based on both analytical communication models and real network traces from applications running on a tiled multicore processor. This thesis is the first work to address communication locality in analyzing multicore interconnect energy and to use real multicore interconnect traces extensively. The thesis compares the energy performance of point-to-point networks with buses for varying degrees of communication locality. The model accounts for wire length, switch energy, and network contention. This work is the first to examine network contention from the energy standpoint.
(cont.) The thesis presents a detailed analysis of the energy costs of a switch and shows that the estimated values for channel energy, switch control logic energy, and switch queue buffer energy are 34.5pJ, 17pJ, and 12pJ, respectively. The results suggest that a one-dimensional point-to-point network results in approximately 66% energy savings over a bus for 16 or more processors, while a two-dimensional network saves over 82%, when the processors communicate with each other with equal likelihood. The savings increase with locality. Analysis of the effect of contention on OCNs for the Raw tiled microprocessor reports a maximum energy overhead of 23% due to resource contention in the interconnection network.
by Theodoros K. Konstantakopoulos.
Ph.D.
Chan, Jeremy Computer Science & Engineering Faculty of Engineering UNSW. "Energy-aware synthesis for networks on chip architectures." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2007. http://handle.unsw.edu.au/1959.4/35313.
Повний текст джерелаVangal, Sriram. "Performance and Energy Efficient Network-on-Chip Architectures." Doctoral thesis, Linköpings universitet, Institutionen för systemteknik, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11439.
Повний текст джерелаMuhic, Dino. "Improved energy efficiency in double disc chip refining." Licentiate thesis, Mittuniversitetet, Institutionen för naturvetenskap, teknik och matematik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-12979.
Повний текст джерелаDen höga elenergiförbrukningen vid produktion av mekanisk massa har ställtkrav på mer forskning för att elenergieffektivisera raffineringsprocessen. Som ettsteg mot en mer energi‐ och kostnadseffektiv raffineringsprocess, har HolmenPaper AB investerat i en ny tillverkning av termomekanisk (TMP) massa vidBravikens pappersbruk. Dubbeldiskraffinörerna i den nya massalinjens primäraraffineringssteget studerades i detta projekt. Det finns goda indikationer på att enminskning av energiförbrukningen är möjlig genom att studerar och optimeraraffineringparametrar såsom intensitet och temperatur. Projektets huvudmål varatt energieffektivisera det primära dubbeldiskraffineringssteget med 150 kWh/adttill motsvarande massaegenskaper, så som dragstyrka, mätt på massa efterraffinör. Tillfälle gavs också till att studera morfologiska förändringar på fibrer föratt ytterligare förstå hur massa och fibrerna påverkas av dubbeldiskraffinering ochförändringar i raffineringssystemet.Detta licentiatprojekt är en del av ett större projekt där olika tekniker för attförbättra energieffektiviteten har utvärderats i industriell skala på Holmen PaperBravikens pappersbruk. Licentiatprojektet är finansierat av KK‐stiftelsen, MetsoPaper och Holmen Paper, i samarbete med Mittuniversitetet.Fullskaleförsök gjordes på en av TMP linjerna vid Bravikens pappersbruk, därgran används som råvara. Studien utfördes på dubbeldiskraffinörerna i detprimära raffineringssteget. Malkurvor, med ökande specifik raffineringsenergi,gjordes vid olika raffineringstemperaturer, intensitet, massakoncentration ochproduktion. Resultat som erhållits från malkurvorna bekräftades med längrestudier på raffinörerna. Intensitetsmodeller och simuleringar utfördes av Juha‐Pekka Huhtanen från Tampere University of Technology.De erhållna resultaten visar på att energiförbrukningen till ett visst dragindexkan minskas genom att öka raffineringstrycket/temperaturen. Medraffineringstryck menas inlopp och hustryck i raffinören. Energibesparingen är iintervallet 80‐150 kWh/adt. Den största förbättringen kan uppnås vid lågaenergiinsatser. Massor producerade med högt tryck och temperatur och lägrespecifik energiförbrukning uppvisar liknande ultrastrukturella ytegenskaper sommassor producerade med lågt tryck och temperatur och hög specifik energi. Högttryck och temperaturer med hög specifik energiinsats gav en signifikant förbättringav delaminering/intern fibrillering av massafibrer. Dessa fibrer uppvisadebildningar av långa band‐liknande fibriller från fibrernas S2 skikt, i jämförelse medmassor tillverkade med lägre tryck och temperatur och lägre specifik energi.5Om raffineringen genomförs vid högt tryck/temperatur bevaras dragindexunder hela segmentlivslängden.Den specifika ljusspridningskoefficienten påverkades positivt av ökat tryck ochtemperatur. En orsak till detta kan vara högre intensitet som orsakas av minskadmalspalt.Ökad intensitet genom förändrad segmentdesign leder till stora ökningar i denspecifika ljusspridningskoefficienten. Samtidigt uppnås samma dragindex, lägrespethalt, lägre genomsnittlig fiberlängd och CSF vid samma specifikaenergiförbrukning.Förbrukningen av färskångan sänktes vid tillämning av högre tryck ochtemperatur i raffinören.
Rahmat, Meysam. "Geometric optimization for a thermal microfluidic chip." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=18408.
Повний текст джерелаAu cours des deux dernières décades, les puces thermiques micro-fluidiques ont été considérablement examinées. Du fait de leur haute capacité pour le transport de chaleur, de nombreuses études ont été réalisées sur différents aspects de leurs propriétés. Cependant, une étude de la géométrie des puces micro-fluidiques utilisant un logiciel d'analyse par éléments finis est absente de la littérature. Dans cette thèse, des paramètres géométriques des puces thermiques micro-fluidiques ont été optimisés en utilisant un logiciel d'analyse par éléments finis. Ainsi, les phénomènes micro et macro ont été étudiés dans différents modèles. L'approche micro a consisté à étudier les micro-canaux seuls, et à optimiser la géométrie de leur section transverse. De plus, deux phases d'écoulement ont été modélisées en utilisant le logiciel d'élément fini ANSYS CFX. L'accumulation de liquide dans les coins saillants a été saisie par le modèle et le phénomène de changement de phase a pu être également observé. Les résultats de l'analyse par élément finis ont été comparés à ceux trouvés dans la littérature, et une bonne corrélation a été observée. La configuration des micro-canaux dans la puce micro-fluidique a été étudiée par l'approche macro. Des graphes adimensionnels ont été présentés dans cette section afin d'être employés pour toutes sortes de puces ayant différentes conditions aux frontières. En se basant sur la validité du modèle micro, élaboré par élément finis, l'écoulement des deux phases dans un réseau tridimensionnel de micro-canaux avec une géométrie optimisée a été modélisé. Les résultats montrent une circulation des deux phases dans les micro-canaux et démontrent le bon fonctionnement des puces thermiques micro fluidiques.
Al-Tarawneh, Mutaz. "Improving the Off-chip Bandwidth Utilization and Energy Efficiency in Chip Multiprocessor (CMP) Architectures." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/dissertations/216.
Повний текст джерелаPark, Sunghyun Ph D. Massachusetts Institute of Technology. "Low-swing signaling for energy efficient on-chip networks." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66474.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (p. 65-69).
On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several contributions to low-swing signaling circuit design for the energy efficient on-chip networks in two separate projects: on-chip networks optimized for one-to-many multicasts and broadcasts, and link designs that allow on-chip networks to approach an ideal interconnection fabric. A low-swing crossbar switch, which is based on tri-state Reduced-Swing Drivers (RSDs), is presented for the first project. Measurement results of its test chip fabricated in 45nm SOI CMOS show that the tri-state RSD-based crossbar enables 55% power savings as compared to an equivalent full-swing crossbar and link. Also, the measurement results show that the proposed crossbar allows the broadcast-optimized on-chip networks using a single pipeline stage for physical data transmission to operate at 21% higher data rate, when compared with the full-swing networks. For the second project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such digital-intensive properties enable them to approach energy and delay performance of a point-to-point interconnect of variable lengths. Simulated in 45nm SOI CMOS, the 10mm SRLR featured with high energy efficiency consumes 338fJ/b at 5.4Gb/s/ch while the 10mm VLR raises its data rate up to 16.OGb/s/ch with 427fJ/b.
by Sunghyun Park.
S.M.
Li, Hui. "Design methods for energy-efficient silicon photonic interconnects on chip." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEC059/document.
Повний текст джерелаSilicon photonics is an emerging technology considered as one of the key solutions for future generation on-chip interconnects, providing several prospective advantages such as low transmission latency and high bandwidth. However, it still encounters challenges in energy efficiency. Different topologies, physical layouts, and architectures provide various interconnect options for on-chip communication. This leads to a large variation in optical losses, which is one of the predominant factors in power consumption. In addition, silicon photonic devices are highly sensitive to temperature variation. Under a given chip activity, this leads to a lower laser efficiency and a drift of wavelengths of optical devices (on-chip lasers and microring resonators (MRs)), which in turn results in a higher Bit Error Ratio (BER) and consequently reduces the energy efficiency of optical interconnects. In this thesis, we work on design methodologies for energy-efficient silicon photonic interconnects on chip related to topology/layout, thermal variation, and architecture
Celik, Coskun. "Energy And Buffer Aware Application Mapping For Networks On Chip." Phd thesis, METU, 2013. http://etd.lib.metu.edu.tr/upload/12615753/index.pdf.
Повний текст джерелаHammer, Jakob. "A microwave chip-based beamsplitter for guided low-energy electrons." Diss., Ludwig-Maximilians-Universität München, 2014. http://nbn-resolving.de/urn:nbn:de:bvb:19-179750.
Повний текст джерелаThis work reports on the manipulation of slow electrons in free space using a microwave quadrupole guide. The generation of the electric fields by means of a planar microwave chip provides an entirely new electron toolkit that allows the guidance and steerage of electrons with kinetic energies below 10 eV. As a key feature, this chip-based technology combines the flexibility to engineer microstructured guiding potentials in the near-field of the microwave excitation with tight transverse confinement of the guided electrons. This renders planar guiding structures ideally suited for the implementation of electron beam splitters or resonators with prospects for novel quantum optics experiments with guided electrons. We present an experiment that demonstrates, for the first time, the realization of a chip-based beam splitter for low-energy electrons. Crucial for the success of the experiment is the generation of a finely structured beam splitter potential and the operation at drive frequencies in the gigahertz range. We report on the design of an optimized microwave chip that generates a beam splitter guiding potential by gradually transforming from a single-well harmonic confinement into a double well along the chip. In the experiment we observe an electron signal with two symmetrically split up output beams. Furthermore we find that with increasing electron kinetic energy, electron loss starts to dominate the electron signal for energies above 3 eV. To this end, we present results of wave-optical simulations that further optimize the guiding potential to reduce excitations in the electron motion as an adverse effect of the splitting process. A second main result of this thesis is the construction and experimental characterization of an electron gun that is based on a nanotip electron emitter. It is specifically designed to provide a pulsed, diffraction-limited electron beam for injection into the guide. We prove that photoemitted electron beams from a laser-triggered nanotip are spatially highly coherent using an electron interference setup. This finding is of importance for all time-resolved applications that employ coherent electron beams from a laser-triggered nanotip. Unprecedented spatial and temporal control over guided electrons can be achieved when combining this coherent laser-triggered electron source with a microwave electron guide. The transverse guiding potential naturally provides discretized motional quantum states that govern the dynamics of guided electrons. Ultimately, it should be possible to directly inject electrons into low-lying motional quantum states of the guiding potential. As prerequisites, this necessitates a diffraction-limited electron gun and a guiding potential that provides electrons a smooth passage into the guide. Therefore, we employ an optimized coupling electrode structure as well as a pulsed electron source to demonstrate experimentally that electron excitations at the guide entrance can be greatly reduced. This paves the way towards the direct injection of electrons into motional quantum states of the guide.
Bacha, Anys. "Harnessing On-chip Error Correction for Energy Efficiency and Security." The Ohio State University, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=osu1462789967.
Повний текст джерелаBai, Yun. "High-speed energy-efficient on-chip interconnect driver and receiver /." May be available electronically:, 2008. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
Повний текст джерелаAslam, Junaid. "Study and Comparison of On-Chip LC Oscillators for Energy Recovery Clocking." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2779.
Повний текст джерелаThis thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.
Perelman, Jenna. "Increasing Energy Efficiency in Existing Residential Buildings: A Case Study of the Community Home Energy Retrofit Project (CHERP)." Scholarship @ Claremont, 2016. http://scholarship.claremont.edu/scripps_theses/793.
Повний текст джерелаNikitovic, Mladen. "Reducing Energy Consumption through Adaptive Shutdown Scheduling on a Chip-Multiprocessor." Licentiate thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-1774.
Повний текст джерелаThere is seemingly a never-ending consumer demand for mobileterminals such as cellular phones and personal digitalassistants (PDAs). Each new generation of terminals comes withmore elaborate functions than in the previous generation. Thistrend results in a higher performance demand on the computerarchitecture that performs the required computations within theterminal. To satisfy the projected requirements on cominggenerations of mobile terminals, we propose an architecturethat when intelligently managed can provide the necessaryperformance at low power and energy consumption. Thisarchitecture, a chip-multiprocessor (CMP), thus amulti-processor implemented on a single chip, has incombination with adaptive scheduling strategies the potentialto efficiently fullfill future requirements.
This licentiate thesis spans over several studies done onthe effectiveness of the adaptive CMP. In our studies, we haveshown that an adaptive CMP can satisfy the same performancerequirements as a comparable uni-processor, still consumingless power and energy. Furthermore, we have made an effort toaccurately model the workload behaviour of mobile terminals,which is of paramount importance when comparing candidatearchitectures. In the future, apart from proposing moreadaptive scheduling techniques, we expect to do more thoroughstudies on workload modeling as well as on the operating systeminfluence on the overall performance and power consumption.
Allu, Veera Bramhanandha Rao. "Compiler-directed leakage energy reduction for large on-chip array structures /." Available to subscribers only, 2005. http://proquest.umi.com/pqdweb?did=1083541611&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.
Повний текст джерелаVangal, Sriram R. "Performance and Energy Efficient Building Blocks for Network-on-Chip Architectures." Licentiate thesis, Linköping : Linköpings universitet, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7845.
Повний текст джерелаHildingsson, Kristian. "Energy-aware design and evaluation of heterogeneous system-on-chip devices." Thesis, University of Glasgow, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.412932.
Повний текст джерелаZhu, Jun. "Energy and Design Cost Efficiency for Streaming Applications on Systems-on-Chip." Licentiate thesis, Stockholm : Skolan för informations- och kommunikationsteknik, Kungliga Tekniska högskolan, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-10591.
Повний текст джерелаZhou, Yuan. "Magnetoelectric Composites for On-Chip Near-Resonance Applications." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/50488.
Повний текст джерелаPh. D.
Li, Jiayin. "ENERGY-AWARE OPTIMIZATION FOR EMBEDDED SYSTEMS WITH CHIP MULTIPROCESSOR AND PHASE-CHANGE MEMORY." UKnowledge, 2012. http://uknowledge.uky.edu/ece_etds/7.
Повний текст джерелаPham, Van Dung. "Architectural exploration of network Interface for energy efficient 3D optical network-on-chip." Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S076/document.
Повний текст джерелаElectrical Network-on-Chip (ENoC) has long been considered as the de facto technology for interconnects in multiprocessor systems-on-chip (MPSoCs). However, with the increase of the number of cores integrated on a single chip, ENoCs are less and less suitable to adapt the bandwidth and latency requirements of nowadays complex and highly-parallel applications. In recent years, due to power consumption constraint, low latency, and high data bandwidth requirements, optical interconnects became an interesting solution to overcome these limitations. Indeed, Optical Networks on Chip (ONoC) are based on waveguides which drive optical signals from source to destination with very low latency. Unfortunately, the optical devices used to built ONoCs suffer from some imperfections which introduce losses during communications. These losses (crosstalk noises and optical losses) are very important factors which impact the energy efficiency and the performance of the system. Furthermore, Wavelength Division Multiplexing (WDM) technology can help the designer to improve ONoC performance, especially the bandwidth and the latency. However, using the WDM technology leads to introduce new losses and crosstalk noises which negatively impact the Signal to Noise Ratio (SNR) and Bit Error Rate (BER). In detail, this results in higher BER and increases power consumption, which therefore reduces the energy efficiency of the optical interconnects. The contributions presented in this manuscript address these issues. For that, we first model and analyze the optical losses and crosstalk in WDM based ONoC. The model can provide an analytical evaluation of the worst case of loss and crosstalk with different parameters for optical ring network-on-chip. Based on this model, we propose a methodology to improve the performance and then to reduce the power consumption of optical interconnects relying on the use of forward error correction (FEC). We present two case studies of lightweight FEC with low implementation complexity and high error-correction performance under 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology. The results demonstrate the advantages of using FEC on the optical interconnect in the context of the CHAMELEON ONoC. Secondly, we propose a complete design of Optical Network Interface (ONI) which is composed of data flow allocation, integrated FECs, data serialization/deserialization, and control of the laser driver. The details of these different elements are presented in this manuscript. Relying on this network interface, an allocation management to improve energy efficiency can be supported at runtime depending on the application demands. This runtime management of energy vs. performance can be integrated into the ONI manager through configuration manager located in each ONI. Finally, the design of an ONoC configuration sequencer (OCS), located at the center of the optical layer, is presented. By using the ONI manager, the OCS can configure ONoC at runtime according to the application performance and energy requirements
Eriksson, Anders. "Energy efficient storage of biomass at Vattenfall heat and power plant." Thesis, Institutionen för energi och teknik, SLU, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-153326.
Повний текст джерелаShalf, John Marshall. "Advanced System-Scale and Chip-Scale Interconnection Networks for Ultrascale Systems." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36134.
Повний текст джерелаMaster of Science
Alimadadi, Mehdi. "Recycling clock network energy in high-performance digital designs using on-chip DC-DC converters." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/1447.
Повний текст джерелаPenolazzi, Sandro. "A System-Level Framework for Energy and Performance Estimation in System-on-Chip Architectures." Doctoral thesis, KTH, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-31425.
Повний текст джерелаQC 20110315
Hammer, Jakob [Verfasser], and Peter [Akademischer Betreuer] Hommelhoff. "A microwave chip-based beamsplitter for guided low-energy electrons / Jakob Hammer. Betreuer: Peter Hommelhoff." München : Universitätsbibliothek der Ludwig-Maximilians-Universität, 2014. http://d-nb.info/106775251X/34.
Повний текст джерелаHung, Wei-Chen. "On-line Thermal Aware Energy Optimization via Dynamic Voltage Selection for Multiprocessor System-On-Chip." Thesis, Linköpings universitet, ESLAB - Laboratoriet för inbyggda system, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-65742.
Повний текст джерелаBhamidipati, Padmaja. "RETUNES: Reliable and Energy-Ecient Network-on-Chip Architecture using Adaptive Routing and Approximate Communication." Ohio University / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1554914045111913.
Повний текст джерелаFerreras, Jorge. "One-dimensional Bose gases on an atom chip." Thesis, University of Nottingham, 2018. http://eprints.nottingham.ac.uk/53074/.
Повний текст джерелаSundaresan, Krishnan. "Activity-aware modeling and design optimization of on-chip signal interconnects." Diss., Connect to online resource - MSU authorized users, 2006.
Знайти повний текст джерелаTitle from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.
Basu, Prabal. "Toward Reliable, Secure, and Energy-Efficient Multi-Core System Design." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7517.
Повний текст джерелаChen, Caipeng. "Design, fabrication and testing of a microfluidic channel platform for sensor chip manipulation and data retreival." Thesis, Boston University, 2013. https://hdl.handle.net/2144/21134.
Повний текст джерелаThe exploration and production of oil and gas resources require innovative information acquisition strategies for wellbore environments to improve reservoir management. In this study, a microfluidic channel data retrieval platform was proposed for multiple sensor chip manipulation, wireless charging and information extraction in fluidic mediums. The working principle of near-field magneto inductive coupling was investigated and a prototype of a microfluidic channel integrated with a spiral reader antenna was designed and fabricated. Sensor chip manipulations and dynamic couplings between readers and sensors were demonstrated inside the proposed microfluidic channel. Furthermore, solid fluidic interaction between sensors and flows was analyzed. Comsol simulation was conducted to quantitatively characterize flow drag forces inside the channel. To prevent communication interference between sensors in the proposed coupling region, sensor separation strategies based on side channel and meander channel design were proposed and realized to separate sensors one by one by the desired distance. To enhance the efficiency of the sensor separation process, a new channel design based on a spinning blade with real-time image processing was also developed for feedback control of separation. Additionally, a 500-micron cubic sensor antenna was cut by a dicing saw and assembled into an 800-micron cubic package. Magneto inductive couplings between readers and the assembly package were conducted out of the channel. The results show that the coupling effect is strongly related with the orientation between the reader and the assembly package. Finally, the assembly package control with desired velocity and direction in oil mediums was successfully realized inside the channel.
2031-01-01
Mahfuzul, Islam A. K. M. "Modeling, Characterization and Compensation of Performance Variability using On-chip Monitor Circuits for Energy-efficient LSI." 京都大学 (Kyoto University), 2014. http://hdl.handle.net/2433/185201.
Повний текст джерелаDe, Gaspari Massimiliano [Verfasser], and Johanna [Akademischer Betreuer] Stachel. "Systems-on-Chip (SoC) for applications in High-Energy Physics / Massimiliano De Gaspari ; Betreuer: Johanna Stachel." Heidelberg : Universitätsbibliothek Heidelberg, 2012. http://d-nb.info/1179786289/34.
Повний текст джерелаShiomi, Jun. "Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits." Kyoto University, 2017. http://hdl.handle.net/2433/228252.
Повний текст джерелаPainkras, Eustace. "A chip multiprocessor for a large-scale neural simulator." Thesis, University of Manchester, 2013. https://www.research.manchester.ac.uk/portal/en/theses/a-chip-multiprocessor-for-a-largescale-neural-simulator(d3637073-2669-4a81-985a-2da9eec46480).html.
Повний текст джерелаXu, Hongjie. "Energy-Efficient On-Chip Cache Architectures and Deep Neural Network Accelerators Considering the Cost of Data Movement." Doctoral thesis, Kyoto University, 2021. http://hdl.handle.net/2433/263786.
Повний текст джерела京都大学
新制・課程博士
博士(情報学)
甲第23325号
情博第761号
京都大学大学院情報学研究科通信情報システム専攻
(主査)教授 小野寺 秀俊, 教授 大木 英司, 教授 佐藤 高史
学位規則第4条第1項該当
Doctor of Informatics
Kyoto University
DFAM
Ferdeen, Mats. "Reducing Energy Consumption Through Image Compression." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-134335.
Повний текст джерелаEnergikonsumtionen för att skriva och läsa till off-chip minne är ett känt problem. Inombildbehandlingsområdet struktur från rörelse kan enklare kompressionstekniker användasför att spara energi. En avvägning mellan detekterade features såsom hörn, kanter, etc.och grad av kompression blir då en fråga att utreda. I detta examensarbete har en djuparestudie av denna avvägning utförts. Ett antal mer avancerade kompressionsalgoritmer förbearbetning av stillbilder som tex. JPEG används för jämförelse med ett antal utvaldaenklare kompressionsalgoritmer. De enklare algoritmerna kan delas in i två kategorier:individuell blockvis kompression av vardera bilden och kompression med hänsyn tillsamtliga pixlar i vardera bilden. I studien är bildsekvenserna i gråskala och tillhandahållnafrån en tidigare studie om rullande slutare. Syntetiska data set från ytterligare en studie om’optical flow’ ingår även för att se hur pass tillförlitliga de andra dataseten är.
Fettweis, Gerhard P., Hassan Najeeb ul, Lukas Landau, and Erik Fischer. "Wireless Interconnect for Board and Chip Level." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-118302.
Повний текст джерелаKadeed, Thawra Mohamad Verfasser], Rolf [Akademischer Betreuer] [Ernst, and Andreas [Akademischer Betreuer] Herkersdorf. "Dependable and Energy-Efficient Mixed-Critical Real-Time Systems-on-Chip / Thawra Mohamad Kadeed ; Rolf Ernst, Andreas Herkersdorf." Braunschweig : Technische Universität Braunschweig, 2021. http://d-nb.info/1235138720/34.
Повний текст джерелаLiang, Jie. "Exploration of carbon nanotube and copper-carbon nanotube composite for next generation on-chip energy efficient interconnect applications." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS022/document.
Повний текст джерелаImproving only the performance and energy efficiency of transistors is not sufficient for future systems-on-chip. On-chip interconnects have become equally critical to transistors and can detriment the system’s performance and energy efficiency. Copper (Cu) is the state-of-the-art interconnect material and is reaching its physical limitations due to scaling. Barrier and scattering effects induce high resistivity and electromigration exacerbates interconnect reliability. Carbon Nanotubes (CNTs) and Copper-Carbon Nanotube (Cu-CNT) composite materials are of interest due to ballistic transport, high scalability, high thermal conductivity, and high current density. We investigate from fundamental atomistic level to macroscopic level the physical understanding and electrical compact modeling on CNT and Cu-CNT composite for on-chip local and global interconnect applications. We evaluate and assess the different sources of variations and their impacts on CNT interconnect performance and energy efficiency. Charge transfer based doping of CNT is also investigated as an alternative method to further reduce its resistivity, mitigate CNT chirality variations and contact resistance drawbacks. Experimental measurement results are used to demonstrate the validity and accuracy of our established models. The interconnect models are finally applied to the gate- and circuit- level studies as local and global interconnects to evaluate their performance
DiTomaso, Dominic F. "Improving Energy Efficiency of Network-on-Chips Using Emerging Wireless Technology and Router Optimizations." Ohio University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1337627400.
Повний текст джерелаSampaio, Felipe Martin. "Energy-efficient memory architecture design and management for parallel video coding." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179534.
Повний текст джерелаThis Thesis presents the design of an energy-efficient hybrid scratchpad video memory architecture (called Hy-SVM) for parallel High-Efficiency Video Coding. Video coding stands out as a high complex part in the video processing applications. HEVC standard brought innovations that increase the memory requirements, mainly due to: (a) the novel coding structures, which aggravates the computational complexity by providing a wider range of possibilities to be analyzed; and (b) the high-level parallelism features provided by the Tiles partitioning, which provides performance acceleration, but, at the same time, strongly adds hard challenges to the memory infrastructure. The main bottleneck in terms of external memory transmission and on-chip storage is the reference frames data: which consists of already coded (and reconstructed) entire frames that must be stored and intensively accessed during the encoding process of future frames. Due to the large volume of data required to represent the reference frames, they are typically stored in the external memory (especially when highdefinition videos are targeted). The proposed Hy-SVM architecture is inserted in a video coding system, which is based on multiple Tiles partitioning to enable parallel HEVC encoding: each Tile is assigned to a specific processing unit. The key ideas of Hy-SVM include: applicationspecific design and management; combined multiple levels of private and shared memories that jointly exploit intra-Tile and inter-Tiles data reuse; scratchpad memories (SPMs) as energyefficient on-chip data storage; combined SRAM and STT-RAM hybrid memory (HyM) design We propose a design methodology for Hy-SVM that leverages application-specific properties to properly define the HyMs parameters. In order to provide run-time adaptation (for both offand on-chip parts), Hy-SVM integrates a memory management layer composed of: (1) overlap prediction, which has the goal of identifying the redundant memory access behavior by analyzing monitored past frames encoding to increase inter-Tiles data reuse exploitation; (2) memory pressure management, which aims on balancing the Tiles-accumulated memory pressure targeting on improving external memory communication channel usage; and (3) lifetime-aware data management scheme that alleviates STT-RAM SPMs of high bit-toggling write accesses to increase the their cells lifetime, as well as to reduce overhead issues related to poor write characteristics of STT-RAM. Application-specific knowledge was exploited by inheriting HEVC properties and performing run-time monitoring of memory accesses. Such information is used to properly design the on-chip video memories, as well as being utilized as input parameters of the run-time memory management layer. Based on the run-time decisions from the proposed Hy-SVM management strategies, Hy-SVM integrates distributed memory access management units (MAMUs) to control the access dynamics of private and shared SPMs. Additionally, adaptive power management units (APMUs) are able to strongly reduce on-chip energy consumption due to an accurate overlap prediction The experimental results demonstrate Hy-SVM overall energy savings over related works under various HEVC encoding scenarios. Compared to traditional data reuse schemes, like Level-C, the combined intra-Tile and inter-Tiles data reuse provides 69%-79% of energy reduction. Regarding related HEVC video memory architectures, the savings varied from 2.8% (worst case) to 67% (best case). From the external memory perspective, Hy-SVM can improve data reuse (by also exploiting inter-Tiles data redundancy), resulting on 11%-71%% of reduced off-chip energy consumption. Additionally, our APMUs contribute by reducing on-chip energy consumption of Hy-SVM by 56%-95%, for the evaluated HEVC scenarios. Thus, compared to related works, Hy-SVM presents the lowest on-chip energy consumption. The memory pressure management scheme can reduce the variations in the memory bandwidth by 37%-83% when compared to the traditional raster scan processing for 4- and 16-core parallelized HEVC encoder. The lifetime-aware data management significantly extends the STT-RAM lifetime, achieving 0.83 of normalized lifetime (near to the optimal case). Moreover, the overhead of implementing our management units insignificantly affects the performance and energyefficiency of Hy-SVM.
Wong, Winnie. "A Hybrid Pixel Detector ASIC with Energy Binning for Real-Time, Spectroscopic Dose Measurements." Doctoral thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-16171.
Повний текст джерелаSi, Wenping. "Designing Electrochemical Energy Storage Microdevices: Li-Ion Batteries and Flexible Supercapacitors." Doctoral thesis, Universitätsbibliothek Chemnitz, 2015. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-160049.
Повний текст джерелаHuman beings are facing the grand energy challenge in the 21st century. Nowhere has this become more urgent than in the area of energy storage and conversion. Conventional energy is based on fossil fuels which are limited on the earth, and has caused extensive environmental pollutions. Additionally, the consumptions of energy are still increasing, especially with the rapid proliferation of vehicles and various consumer electronics like PCs and cell phones. We cannot rely on the earth’s limited legacy forever. Alternative energy resources should be developed before an energy crisis. The developments of renewable conversion energy from solar and wind are very important but these energies are often not even and continuous. Therefore, energy storage devices are of significant importance since they are the one stabilizing the converted energy. In addition, it is a disappointing fact that nowadays a smart phone, no matter of which brand, runs out of power in one day, and users have to carry an extra mobile power pack. Portable electronics demands urgently high-performance energy storage devices with higher energy density. The first part of this work involves lithium-ion micro-batteries utilizing single silicon rolled-up tubes as anodes, which are fabricated by the rolled-up nanotechnology approach. A lab-on-chip electrochemical device platform is presented for probing the electrochemical kinetics, electrical properties and lithium-driven structural changes of a single silicon rolled-up tube as an anode in lithium ion batteries. The second part introduces the new design and fabrication of on chip, all solid-state and flexible micro-supercapacitors based on MnOx/Au multilayers, which are compatible with current microelectronics. The micro-supercapacitor exhibits a maximum energy density of 1.75 mW h cm-3 and a maximum power density of 3.44 W cm-3. Furthermore, a flexible and weavable fiber-like supercapacitor is also demonstrated using Cu wire as substrate. This dissertation was written based on the research project supported by the International Research Training Group (IRTG) GRK 1215 "Rolled-up nanotech for on-chip energy storage" from the year 2010 to 2013 and PAKT project "Electrochemical energy storage in autonomous systems, no. 49004401" from 2013 to 2014. The aim of the projects was to design advanced energy storage materials for next-generation rechargeable batteries and flexible supercapacitors in order to address the energy issue. Here, I am deeply indebted to IRTG for giving me an opportunity to carry out the research project in Germany. September 2014, IFW Dresden, Germany Wenping Si
Sampaio, Felipe Martin. "Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2013. http://hdl.handle.net/10183/71292.
Повний текст джерелаThis Master Thesis proposes a memory hierarchy for the Motion and Disparity Estimation (ME/DE) centered on the encoding references, called Reference-Centered Data Reuse (RCDR), focusing on energy reduction in the Multiview Video Coding (MVC). In the MVC encoders the ME/DE represents more than 98% of the overall energy consumption. Moreover, in the overall ME/DE energy, up to 90% is related to the memory issues, and only 10% is related to effective computation. The two items to be concerned with: (1) off-chip memory communication to fetch the reference samples (45%) and (2) on-chip memory to keep stored the search window samples and to send them to the ME/DE processing core (45%). The main goal of this work is to jointly minimize the on-chip and off-chip energy consumption in order to reduce the overall energy related to the ME/DE on MVC. The memory hierarchy is composed of an onchip video memory (which stores the entire search window), an on-chip memory gating control, and a partial results compressor. A search control unit is also proposed to exploit the search behavior to achieve further energy reduction. This work also aggregates to the memory hierarchy a low-complexity reference frame compressor. The experimental results proved that the proposed system accomplished the goal of the work of jointly minimizing the on-chip and off-chip energies. The RCDR provides off-chip energy savings of up to 68% when compared to state-of-the-art. the traditional MBcentered approach. The partial results compressor is able to reduce by 52% the off-chip memory communication to handle this RCDR penalty. When compared to techniques that do not access the entire search window, the proposed RCDR also achieve the best results in off-chip energy consumption due to the regular access pattern that allows lots of DDR burst reads (30% less off-chip energy consumption). Besides, the reference frame compressor is capable to improve by 2.6x the off-chip memory communication savings, along with negligible losses on MVC encoding performance. The on-chip video memory size required for the RCDR is up to 74% smaller than the MB-centered Level C approaches. On top of that, the power-gating control is capable to save 82% of leakage energy. The dynamic energy is treated due to the candidate merging technique, with savings of more than 65%. Due to the jointly off-chip communication and on-chip storage energy savings, the proposed memory hierarchy system is able to meet the MVC constraints for the ME/DE processing.
Rangel, Edylara Ribeiro. "Estudo sobre o consumo de energia em redes-em-chip baseadas em dispositivos nanoeletrônicos." reponame:Repositório Institucional da UnB, 2017. http://repositorio.unb.br/handle/10482/31306.
Повний текст джерелаSubmitted by Raquel Almeida (raquel.df13@gmail.com) on 2018-02-21T16:44:37Z No. of bitstreams: 1 2017_EdylaraRibeiroRangel.pdf: 3128190 bytes, checksum: e2eee5ac868a08d0fc6370ae8cdd3282 (MD5)
Approved for entry into archive by Raquel Viana (raquelviana@bce.unb.br) on 2018-02-27T16:48:02Z (GMT) No. of bitstreams: 1 2017_EdylaraRibeiroRangel.pdf: 3128190 bytes, checksum: e2eee5ac868a08d0fc6370ae8cdd3282 (MD5)
Made available in DSpace on 2018-02-27T16:48:02Z (GMT). No. of bitstreams: 1 2017_EdylaraRibeiroRangel.pdf: 3128190 bytes, checksum: e2eee5ac868a08d0fc6370ae8cdd3282 (MD5) Previous issue date: 2018-02-27
A evolução da indústria eletrônica que permitiu a implementação de arquiteturas de múltiplos núcleos foi motivada principalmente pelo consumo de energia, pois elas oferecem melhor desempenho e menor dissipação de potência do que os sistemas de processamento único. Com o aumento do número de núcleos em um único chip, a arquitetura de comunicação que interliga esses núcleos começou a ganhar importância. Assim, para resolver os problemas de interconectividade e comunicação dos sistemas em chip, a arquitetura de comunicação do tipo redes-em-chip (NoC - Network-on-Chip) tem sido proposta como uma solução altamente estruturada pela comunidade científica. Estimativas do consumo de energia das arquiteturas de comunicação devem ser realizadas no início do projeto, pois a comunicação do chip representa uma porção significante do total de energia e área consumida pelo chip. Neste contexto, este trabalho objetiva estudar sobre o consumo de energia em NoCs baseadas em dispositivos nanoeletrônicos, por meio de um modelo analítico previamente apresentado. Para obter o consumo total de energia da comunicação do chip, esse modelo utiliza como base alguns parâmetros, tais como, a energia das interconexões e dos roteadores, e a distribuição de probabilidade de comunicação. O objetivo principal deste trabalho é verificar quantitativamente qual a contribuição da nanoeletrônica na redução do consumo de energia, na arquitetura de comunicação do tipo NoC, com ênfase no estudo das interconexões. Desta forma, são feitas simulações para verificar o comportamento da latência e da energia das interconexões que conectam os roteadores da rede, em função dos nós de tecnologia, bem como, é realizada a comparação do consumo de energia entre redes com roteadores nanoeletrônicos e redes com roteadores CMOS. Por fim, é realizada uma análise comparativa entre o consumo de energia de redes com interconexões de cobre e nanotubo de carbono, utilizando roteadores nanoeletrônicos. Os resultados obtidos neste trabalho mostram que a nanoeletrônica é uma tecnologia que aparenta ser uma solução promissora na redução do consumo de energia dos futuros chips e dispositivos.
The evolution of the electronic industry that allowed the implementation of multi-core architectures was motivated mainly by the energy consumption, since they offer better performance and less power dissipation than the single processing systems. With the increase in the number of cores on a single chip, the communication architecture that interconnects these cores began to gain importance. Thus, to solve the problems of interconnectivity and communication of the systems in chip, Networks-on-Chip (NoC) communication architecture has been proposed as a solution highly structured by the scientific community. Estimates of the energy consumption of communication architectures should be carried out at the beginning of the project because the communication of the chip represents a significant portion of the total energy and area consumed by the chip. In this context, this work aims to study energy consumption in NoCs based on nanoelectronic devices, through an analytical model previously presented. To obtain the total energy consumption of the chip communication, this model uses as base some parameters, such as the energy of the interconnections and the routers, and the Communication Probability Distribution. The main objective of this work is to verify quantitatively the contribution of nanoelectronics in the reduction of energy consumption in NoC communication architecture, with emphasis on the study of interconnections. In this way, simulations are performed to verify the latency and energy behavior of the interconnections that connect the routers of the network, as a function of the technology nodes, as well as, the comparison of the energy consumption between networks with nanoelectronic routers and networks with CMOS routers is made. Finally, a comparative analysis was performed between the energy consumption of networks with copper and carbon nanotube interconnections using nanoelectronic routers. The results obtained in this work show that nanoelectronics is a technology that appears to be a promising solution in reducing the energy consumption of future chips and devices.
Wang, Jia. "Design of a low noise, limited area and full on-chip power management for CMOS pixel sensors in high energy physics experiments." Phd thesis, Université de Strasbourg, 2012. http://tel.archives-ouvertes.fr/tel-00758209.
Повний текст джерела