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1
Camp, B. H. "Electronic Design Automation (EDA '84)." Electronics and Power 31, no. 4 (1985): 327. http://dx.doi.org/10.1049/ep.1985.0202.
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Huang, Guyue, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, et al. "Machine Learning for Electronic Design Automation: A Survey." ACM Transactions on Design Automation of Electronic Systems 26, no. 5 (June 5, 2021): 1–46. http://dx.doi.org/10.1145/3451179.
Повний текст джерелаАнотація:
With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.
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Henkel, Jorg. "Open-Source Electronic Design Automation (EDA) Tools." IEEE Design & Test 38, no. 2 (April 2021): 4. http://dx.doi.org/10.1109/mdat.2021.3066119.
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Tian, Zeyu. "Introduction to machine leaning in electronic design automation (EDA)." Applied and Computational Engineering 6, no. 1 (June 14, 2023): 520–26. http://dx.doi.org/10.54254/2755-2721/6/20230849.
Повний текст джерелаАнотація:
The rapid growth of the intergraded circuit industry as predicted by Moores law has significantly increased the importance of efficient design processes. In addition, due to physical constraint, we will soon reach the limit of how small the size of the transistor can become, and the design processes will become more complex than ever. In order to cope with those challenges and introduce the product to the market within the time to market, the industry has been developing ways to apply machine learning to concurrent EDA tools. This paper will aim to introduce how machine learning is applied to varies processes of electronic design and how they improve the current EDA tools. We will also show the limitations and opportunities of ML based EDA tools and provide a rough idea of the potential future to those who are looking into this area.
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Kim, TaeWoong, and SoYoung Kim. "Electronic design automation requirements for R2R printing foundry." Flexible and Printed Electronics 7, no. 1 (February 4, 2022): 013001. http://dx.doi.org/10.1088/2058-8585/ac4d3d.
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Abstract Roll-to-roll (R2R) printed electronic devices have been in the spotlight over the decades as a potential replacement for Si-based semiconductors, research into this technology is still being actively conducted over the world. These printed electronic devices can be used in a variety of applications, so the demand for them is expected to reach over USD 20.7 billion in 2025 given a compound annual growth rate (CAGR) of 21.5%. As the new ink materials and printing technologies being researched are commercialized, foundry companies that produce printed electronics need to provide appropriate work flow that will allow engineers to design these kind of circuits using commercial electronic design automation (EDA) tools. This review paper describes the key parameters that should be found process design kit (PDK), including the contained design rules and the simulation program with integrated circuit emphasis model. We cover the factors that need to be considered when a fabless company develops circuits for the R2R process, including the design methodology from the beginning of the design to the final graphic data stream (GDS) completion stage, we also discuss other essential technological hurdles that must be overcome in this process. The overall process of design and analysis for printed electronic technique is based on the silicon design flow. We describe the full custom design flow for analog integrated circuits (ICs) and explain how the automatic placement and routing based design of digital integrated circuits can be carried out. In addition, the necessity of sign-off verification using post-simulation, electromagnetic (EM) simulation and bias check simulation required for commercial product development will be explained. The development of PDKs and EDA tools for circuit design in the R2R printed electronics foundry industry will have a potentially tremendous impact on the semiconductor ecosystem by lowering the barriers to producing these devices.
6
Patterson, E. B., P. G. Holmes, and D. Morley. "Electronic design automation (EDA) techniques for the design of power electronic control systems." IEE Proceedings G Circuits, Devices and Systems 139, no. 2 (1992): 191. http://dx.doi.org/10.1049/ip-g-2.1992.0033.
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7
Liu, Yong Qin, Guo Qiang Li, Zhi Ping Zhu, and Bao Hui Guo. "Design and Implementation of Automatic Schematics Verification Platform." Advanced Materials Research 529 (June 2012): 343–46. http://dx.doi.org/10.4028/www.scientific.net/amr.529.343.
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Design and implementation of Automatic Schematics Verification Platform based on open EDA (Electronic Design Automation) tools has been discussed. This platform adopts client/server pattern and provides an environment of design Verification and sharing data for designers separately, and at the same time, this platform has strong transplantable ability because of it’s strong cohesion and weak coupling with the open EDA tool, therefore we can transplant this platform to other open EDA tools expediently.
8
Chu, Hong-Son, Oka Kurniawan, Wenzu Zhang, Dongying Li, and Er-Ping Li. "Integrated System-Level Electronic Design Automation (EDA) for Designing Plasmonic Nanocircuits." IEEE Transactions on Nanotechnology 11, no. 4 (July 2012): 731–38. http://dx.doi.org/10.1109/tnano.2012.2194507.
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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.
Повний текст джерелаАнотація:
In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.
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Mirkovic, Dejan, та Predrag Petkovic. "Design automation of ΔΣ switched capacitor modulators using spice and MATLAB". Serbian Journal of Electrical Engineering 11, № 1 (2014): 47–59. http://dx.doi.org/10.2298/sjee131017005m.
Повний текст джерелаАнотація:
Concerning the fact that the design of contemporary integrated circuits (IC) is practically impossible without using sophisticated Electronic Design Automation (EDA) software, this paper gives some interesting thoughts and considerations about that issue. As technology processes advances on year basis consequently EDA industry is forced to follow this trend as well. This, on the other hand, requires IC designer to frequently and efficiently accommodate to new working environments. Authors of this paper suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks. The paper demonstrates the proposed EDA procedure on an example of second order ?? modulator design. It illustrates considerable simulation time saving which is more than welcome in a world of analogue and mixed-signal design.
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Li, Weihui, Haoyu Wen, and Peiji Duan. "Key technologies and international trends in EDA field of digital IC design: a patent analysis." SHS Web of Conferences 140 (2022): 01020. http://dx.doi.org/10.1051/shsconf/202214001020.
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Currently, Electronics Design Automation (EDA) software tools are highly monopolized internationally. In China, EDA suffers from the pain of “stuck neck”. This paper will find out the key technologies in the EDA field through 3D sand table clustering algorithm, and analyze a series of patent data of monopoly three companies (Synopsys, Cadence, Mentor Graphic), in order to help local EDA enterprises perceive the technology status and development trend of the international EDA field.
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Pereira Bitencourt, Tulio, Fábio Luís Livi Ramos, and Sergio Bampi. "AV1 Arithmetic Encoder Design on Open-Source EDA." Journal of Integrated Circuits and Systems 17, no. 2 (September 17, 2022): 1–9. http://dx.doi.org/10.29292/jics.v17i2.564.
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With the increasing demand for video transmission through the Internet, video coding has become a key technology to allow this market's growth at a reduced cost. Moreover, with the inception of higher video resolutions (e.g., 4K, 8K) and their impact on video size, new video coding standards must tackle this issue to reduce video traffic demand on the global internet infrastructure. The AV1, a recently released royalties-free video coding format created by the Alliance for Open Media (AOMedia), reaches great compression rates but cannot accomplish real-time execution on software-only implementations due to its high complexity. This paper presents and analyzes AE-AV1, a high-performance 4-stage pipelined architecture to accelerate the AV1 arithmetic encoding process (part of the entropy encoder block) and make it capable of real-time execution. For the analysis, this work aims to rely on fully open-source Electronic Design Automation (EDA) tools and Package Design Kits (PDKs).
13
Li, Xue Mei, and Li Li. "Implementation of the DES Algorithm on EDA Box." Applied Mechanics and Materials 325-326 (June 2013): 1702–5. http://dx.doi.org/10.4028/www.scientific.net/amm.325-326.1702.
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The EDA (Electronic Design Automation) technique which provides us an alternative method of circuit system based on the PC and information technology is a novel technique in modern electronic engineering field. Research on implementation of the DES (data encryption standard) has been paid much attention. In this paper, a description of the DES implementation on EDA box is presented in an alternative method which is suitable for EDA experimental teaching. The DES is set to different parts according to EDA experimental content. We introduce in detail the sub-circuits which consist of the circuits of the DES from simple units to large scale parts, which is easy for students or beginners to learn hardware implementation of cipher algorithm.
14
Joyner, William H. "The Design Automation Conference and the Early Days of EDA." IEEE Design & Test 31, no. 2 (April 2014): 28–31. http://dx.doi.org/10.1109/mdat.2014.2312091.
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Jin, Lin, and Qiang Liu. "Study on Mechanical and Electrical Automation with System Design of Frequency Meter Based on EDA Technology." Applied Mechanics and Materials 387 (August 2013): 356–59. http://dx.doi.org/10.4028/www.scientific.net/amm.387.356.
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Frequency meter as a kind of electronic measuring instruments, have been widely applied in the field of Mechanical and Electrical automation. The design of a frequency meter based on EDA technology, is implemented in EDA software platform of Quartus II, using hardware description language (HDL) editor can also be seasonal schematic, design, system hardware circuit compiler, simulation, system is divided into five modules: frequency module, control module, counting module, range switching module and display module, the hardware design requires a download chip EPM7128S and input and output circuit.
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Evans, Tristan M., Quang Le, Balaji Narayanasamy, Yarui Peng, Fang Luo, and H. Alan Mantooth. "Development of EDA Techniques for Power Module EMI Modeling and Layout Optimization." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000193–98. http://dx.doi.org/10.4071/2380-4505-2019.1.000193.
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Abstract The design of power electronics modules is undergoing renewed interest as new challenges and technologies emerge in the realm of wide bandgap (WBG) power device packaging. In order to meet the demands of these high-speed transistors, novel techniques are required to produce modules with reduced parasitics and noise generation without exceeding the operating temperature of the devices or their packaging materials. Traditionally, power module design has been a highly iterative process—repeatedly reworking and simulating designs using finite element analysis (FEA) tools that require considerable time in terms of both labor and computation. To overcome these issues, an electronic design automation tool (EDA) known as PowerSynth is ongoing in its development toward power module layout synthesis and optimization based on electrical and thermal criteria. In this paper, work to extend the capabilities of PowerSynth to optimize layouts with reduced electromagnetic interference (EMI) is presented. Optimization strategies based on the transfer functions of noise propagation paths are introduced and results showing layouts with reduced noise generation are compared with FEA simulations.
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Zhang, Zi Sheng, Yi Wang, Chun Sheng Wang, Jin Cui, and Zhi Qiang Liu. "The Control of High Voltage Electrostatic Precipitator Based on EDA." Advanced Materials Research 910 (March 2014): 336–39. http://dx.doi.org/10.4028/www.scientific.net/amr.910.336.
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In order to achieve the automatic control of electrostatic precipitator (ESP) more efficiently and accurately, an ESP system combining hardware and software is designed. According to the requirement of the ESP system,the Electronic Design Automation (EDA) is introduced to the ESP control system and the system is divided into four modules.These sub-modules are designed and the simulation waveform of the system is ananalyzed,based on the Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language and Quartus software.The results show that the security, flexibility and reliabity of the system is improved by using EDA as the control ,which is a great value for generalization.
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Ammes, Gabriel, Paulo Francisco Butzen, André Inácio Reis, and Renato Ribas. "Two-Level and Multilevel Approximate Logic Synthesis." Journal of Integrated Circuits and Systems 17, no. 3 (January 25, 2023): 1–14. http://dx.doi.org/10.29292/jics.v17i3.661.
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Approximate computing represents a modern design paradigm that allows systems to have imprecise or inexact execution, aiming to optimize circuit area, performance, and power dissipation. The automatic construction of approximate integrated circuits (IC) is performed through computer-aided design (CAD) tools available in electronic design automation (EDA) frameworks. Approximate logic synthesis (ALS), in particular, treats two-level and multilevel topologies of combinational blocks in the development of digital IC design. This work provides a survey of ALS methods presented in the literature, from the pioneers until the state-of-the-art approaches.
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ACITO, Bill. "“A Cross-Domain, System Planning Methodology”." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000005–12. http://dx.doi.org/10.4071/2380-4505-2018.1.000005.
Повний текст джерелаАнотація:
Abstract Through several decades of electronic product design, three high-level design domains have emerged; IC (SoC) design, package (SiP) design and board (PCB/PWB) design. These three domains are separated and somewhat isolated, based on the EDA tools they use and by domain expertise. In many cases, the design tools come from 2 or 3 different EDA companies, leading to limited or no methods of sharing design data across the three domains. This typically leads to an “over-the-wall” design approach, resulting in downstream layout complexities for the package and board design teams, requiring domain expertise (human in the loop) in these design domains. Typically, this high-level of complexity occurs because the package substrate and board form-factor are not planned and optimized in context of the IC(s). Thus, the automation of these layouts becomes nearly impossible and tremendous human interaction (domain expertise) is the only way to complete the designs cost-effectively. Moreover, this methodology directly impacts time-to-market and results in products that do not live up to cost or performance expectations.
20
Thanh, Toi Le, Lac Truong Tri, and Trang Hoang. "A Methodology to Design Static NCL Libraries." Journal of Low Power Electronics and Applications 12, no. 2 (June 6, 2022): 31. http://dx.doi.org/10.3390/jlpea12020031.
Повний текст джерелаАнотація:
The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.
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Tri, Lac Truong, Toi Le Thanh, and Trang Hoang. "A Solution to Design Semi-static Null Convention Logic Cell Libraries." International Journal of Circuits, Systems and Signal Processing 15 (November 18, 2021): 1666–75. http://dx.doi.org/10.46300/9106.2021.15.180.
Повний текст джерелаАнотація:
The Null Convention Logic (NCL) based asynchronous circuits have eliminated the disadvantages of the synchronous circuits, including noise, glitches, clock skew, power, and electromagnetic interference. However, using NCL based asynchronous designs was not easy for students and researchers because of the lack of standard NCL cell libraries. This paper proposes a solution to design a semi-static NCL cell library used to synthesize NCL based asynchronous designs. This solution will help researchers save time and effort to approach a new method. In this work, NCL cells are designed based on the Process Design Kit 45nm technology. They are simulated at the different corners with the Ocean script and Electronic Design Automation (EDA) environment to extract the timing models and the power models. These models are used to generate a *.lib file, which is converted to a *.db file by the Design Compiler tool to form a complete library of 27 cells. In addition, we synthesize the NCL based full adders to illustrate the success of the proposed library and compare our synthesis results with the results of the other authors. The comparison results indicate that power and delay are improved significantly.
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Yoshikawa, Masaya, and Hidekazu Terai. "Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption." Journal of Advanced Computational Intelligence and Intelligent Informatics 11, no. 2 (February 20, 2007): 168–75. http://dx.doi.org/10.20965/jaciii.2007.p0168.
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With portable information devices now widely disseminated, low power consumption LSIs are increasingly needed in battery, implementation, and heat generation applications. We propose parallel placement to realize low power consumption and confirm its effectiveness in experiments with a commercial electronic design automation (EDA) tool for designing LSIs. Our proposal hierarchically combines outline and detail placement based on genetic algorithm. In selection operators, new evaluation functions are introduced for realizing the reduction of power consumption focusing on the signal transition probability. Considering a parallel processing, in which a processing speed has a scalable relation with the number of processors, and by implementing it in a parallel computer, its effect is demonstrated.
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Chen, Chuandong, Rongshan Wei, Shaohao Wang, and Wei Hu. "Novel Verification Method for Timing Optimization Based on DPSO." VLSI Design 2018 (March 21, 2018): 1–8. http://dx.doi.org/10.1155/2018/8258397.
Повний текст джерелаАнотація:
Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.
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Thakral, Shaveta, and Dipali Bansal. "High functionality reversible arithmetic logic unit." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 3 (June 1, 2020): 2329. http://dx.doi.org/10.11591/ijece.v10i3.pp2329-2335.
Повний текст джерелаАнотація:
Energy loss is a big challenge in digital logic design primarily due to impending end of Moore’s Law. Increase in power dissipation not only affects portability but also overall life span of a device. Many applications cannot afford this loss. Therefore, future computing will rely on reversible logic for implementation of power efficient and compact circuits. Arithmetic and logic unit (ALU) is a fundamental component of all processors and designing it with reversible logic is tedious. The various ALU designs using reversible logic gates exist in literature but operations performed by them are limited. The main aim of this paper is to propose a new design of reversible ALU and enhance number of operations in it. This paper critically analyzes proposed ALU with existing designs and demonstrates increase in functionality with 56% reduction in gates, 17 % reduction in garbage lines, 92 % reduction in ancillary lines and 53 % reduction in quantum cost. The proposed ALU design is coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. RCViewer+ tool has been used to validate quantum cost of proposed design.
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Малышев, Н. М., та С. В. Рыбкин. "ОСОБЕННОСТЬ РАЗРАБОТКИ САПР ДЛЯ ПРОЕКТИРОВАНИЯ И ВЕРИФИКАЦИИ КОНФИГУРАЦИИ ПЛИС". NANOINDUSTRY Russia 96, № 3s (15 червня 2020): 270–76. http://dx.doi.org/10.22184/1993-8578.2020.13.3s.270.276.
Повний текст джерелаАнотація:
Создан модуль САПР сквозного проектирования с возможностью отладки и верификации проектов для программируемых логических интегральных схем (ПЛИС). На основе модуля создан синтаксический анализатор HDL-кода с формированием на его основе дерева разбора с дальнейшей компиляцией во внутренние объекты. Кроме этого, в работе освещаются вопросы разработки синтеза HDL-абстракций в библиотечные компоненты устройств производителя. Освещаются методы создания синтезатора. The paper deals with EDA (Electronic Design Automation) for designing, verifying and modeling FPGA configuration file. Based on that module HDL syntax analyzer has been created which helps to parse and compile code in internal objects. Besides, the paper presents solutions for HDL synthesis in library-typed component of vendor’s devices, as well as highlights methods of developing a synthesizer.
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Chen, Xinyu, Renjie Li, Yueyao Yu, Yuanwen Shen, Wenye Li, Yin Zhang, and Zhaoyu Zhang. "POViT: Vision Transformer for Multi-Objective Design and Characterization of Photonic Crystal Nanocavities." Nanomaterials 12, no. 24 (December 9, 2022): 4401. http://dx.doi.org/10.3390/nano12244401.
Повний текст джерелаАнотація:
We study a new technique for solving the fundamental challenge in nanophotonic design: fast and accurate characterization of nanoscale photonic devices with minimal human intervention. Much like the fusion between Artificial Intelligence and Electronic Design Automation (EDA), many efforts have been made to apply deep neural networks (DNN) such as convolutional neural networks to prototype and characterize next-gen optoelectronic devices commonly found in Photonic Integrated Circuits. However, state-of-the-art DNN models are still far from being directly applicable in the real world: e.g., DNN-produced correlation coefficients between target and predicted physical quantities are about 80%, which is much lower than what it takes to generate reliable and reproducible nanophotonic designs. Recently, attention-based transformer models have attracted extensive interests and been widely used in Computer Vision and Natural Language Processing. In this work, we for the first time propose a Transformer model (POViT) to efficiently design and simulate photonic crystal nanocavities with multiple objectives under consideration. Unlike the standard Vision Transformer, our model takes photonic crystals as input data and changes the activation layer from GELU to an absolute-value function. Extensive experiments show that POViT significantly improves results reported by previous models: correlation coefficients are increased by over 12% (i.e., to 92.0%) and prediction errors are reduced by an order of magnitude, among several key metric improvements. Our work has the potential to drive the expansion of EDA to fully automated photonic design (i.e., PDA). The complete dataset and code will be released to promote research in the interdisciplinary field of materials science/physics and computer science.
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Saif, Sherif M., Mohamed Dessouky, M. Watheq El-Kharashi, Hazem Abbas, and Salwa Nassar. "A Platform for Placement of Analog Integrated Circuits Using Satisfiability Modulo Theories." Journal of Circuits, Systems and Computers 25, no. 05 (February 25, 2016): 1650047. http://dx.doi.org/10.1142/s021812661650047x.
Повний текст джерелаАнотація:
Satisfiability modulo theories (SMT) is an area concerned with checking the satisfiability of logical formulas over one or more theories. SMT can be well tuned to solve several of the most intriguing problems in electronic design automation (EDA). Analog placers use physical constraints to automatically generate small sections of layout. The work presented in this paper shows that SMT solvers can be used for the automation of analog placement, given some physical constraints. We propose a tool that uses Microsoft Z3 SMT solver to find valid placement solutions for the given analog blocks. Accordingly, it generates multiple layouts that fulfill some given constraints and provides a variety of alternative layouts. The user has the option to choose one of the feasible solutions. The proposed system uses the quantifier-free linear real arithmetic (QFLRA), which makes the problem decidable. The proposed system is able to generate valid placement solutions for benchmarks. For benchmarks that have many constraints and few geometries, the proposed system achieves a speedup that is 10 times faster than other recently used approaches.
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Muthukrishnan, Prathiba, and Sivanantham Sathasivam. "A Technical Survey on Delay Defects in Nanoscale Digital VLSI Circuits." Applied Sciences 12, no. 18 (September 10, 2022): 9103. http://dx.doi.org/10.3390/app12189103.
Повний текст джерелаАнотація:
As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defects may result in functional and delay-related circuit failures. The number of test escapes grows when technology is downscaled. Small delay defects (SDDs) and hidden delay defects (HDDs) are of critical importance in industries today since they are the source of most test escapes and reliability problems. Improving test quality and creating new test methods, algorithms, and test designs requires a comprehensive study of these delay defects. This article reviews the effect and impact of SDD and HDD in logic circuits. It also analyzes the relevant fault models, automatic test pattern generation (ATPG) methods, faster-than-at-speed testing (FAST), cell-aware (CA) based delay tests, test quality metrics, diagnosis of SDDs and HDDs, and commercially available Electronic Design Automation (EDA) tools. Based on the analysis, the benefits and drawbacks of several accessible approaches are addressed.
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Chen, Yonghao, Tianrui Li, Xiaojie Chen, ZhiGang Cai, and Tao Su. "High-Frequency Systolic Array-Based Transformer Accelerator on Field Programmable Gate Arrays." Electronics 12, no. 4 (February 6, 2023): 822. http://dx.doi.org/10.3390/electronics12040822.
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The systolic array is frequently used in accelerators for neural networks, including Transformer models that have recently achieved remarkable progress in natural language processing (NLP) and machine translation. Due to the constraints of FPGA EDA (Field Programmable Gate Array Electronic Design Automation) tools and the limitations of design methodology, existing systolic array accelerators for FPGA deployment often cannot achieve high frequency. In this work, we propose a well-designed high-frequency systolic array for an FPGA-based Transformer accelerator, which is capable of performing the Multi-Head Attention (MHA) block and the position-wise Feed-Forward Network (FFN) block, reaching 588 MHz and 474 MHz for different array size, achieving a frequency improvement of 1.8× and 1.5× on a Xilinx ZCU102 board, while drastically saving resources compared to similar recent works and pushing the utilization of each DSP slice to a higher level. We also propose a semi-automatic design flow with constraint-generating tools as a general solution for FPGA-based high-frequency systolic array deployment.
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Curiac, Christian-Daniel, Alex Doboli, and Daniel-Ioan Curiac. "Co-Occurrence-Based Double Thresholding Method for Research Topic Identification." Mathematics 10, no. 17 (August 30, 2022): 3115. http://dx.doi.org/10.3390/math10173115.
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Identifying possible research gaps is a main step in problem framing, however it is increasingly tedious and expensive considering the continuously growing amount of published material. This situation suggests the critical need for methodologies and tools that can assist researchers in their selection of future research topics. Related work mostly focuses on trend analysis and impact prediction but less on research gap identification. This paper presents our first approach in automated identification of feasible research gaps by using a double-threshold procedure to eliminate the research gaps that are currently difficult to study or offer little novelty. Gaps are then found by extracting subgraphs for the less-frequent co-occurrences and correlations of key terms describing domains. A case study applying the methodology for electronic design automation (EDA) domain is also discussed in the paper.
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Nieto Ramírez, Nathaly, and Rubén Darío Nieto Londoño. "DISEÑO ASÍNCRONO DE LAS FUNCIONES DE TRANSFORMACIÓN DEL ALGORITMO THREEFISH-256." Revista de Investigaciones Universidad del Quindío 25, no. 1 (March 28, 2014): 134–40. http://dx.doi.org/10.33975/riuq.vol25n1.164.
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Los sistemas digitales han crecido en complejidad y la velocidad del reloj aumenta continuamente, incrementando de la misma manera algunos problemas como el retraso de la señal de reloj, el rendimiento total del sistema y el consumo de potencia. Debido a esto se está experimentando un interés en el diseño de circuitos asíncronos, los cuales no manifiestan este tipo de problemas. Este trabajo presenta los resultados de la implementación asíncrona en hardware de las funciones de transformación del algoritmo criptográfico Threefish en su proceso de cifrado, con el fin de utilizar las bondades de los diseños asíncronos en criptografía. Para la especificación, síntesis y simulación asíncrona de los módulos de Threefish se usó una herramienta EDA (Electronic Design Automation) de distribución libre conocida como Balsa. Esta plataforma define su propio lenguaje de descripción de hardware, mientras la implementación se realizó sobre hardware reconfigurable a través de la plataforma ISE Design Suite de Xilinx Inc.
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Ali, Md Liakot, Md Shazzatur Rahman, and Fakir Sharif Hossain. "Design of a BIST implemented AES crypto-processor ASIC." PLOS ONE 16, no. 11 (November 16, 2021): e0259956. http://dx.doi.org/10.1371/journal.pone.0259956.
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This paper presents the design of a Built-in-self-Test (BIST) implemented Advanced Encryption Standard (AES) cryptoprocessor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. Its hardware implementation offers much higher speed and physical security than that of its software implementation. Due to this reason, a number of AES cryptoprocessor ASIC have been presented in the literature, but the problem of testability in the complex AES chip is not addressed yet. This research introduces a solution to the problem for the AES cryptoprocessor ASIC implementing mixed-mode BIST technique, a hybrid of pseudo-random and deterministic techniques. The BIST implemented ASIC is designed using IEEE industry standard Hardware Description Language(HDL). It has been simulated using Electronic Design Automation (EDA)tools for verification and validation using the input-output data from the National Institute of Standard and Technology (NIST) of the USA Govt. The simulation results show that the design is working as per desired functionalities in different modes of operation of the ASIC. The current research is compared with those of other researchers, and it shows that it is unique in terms of BIST implementation into the ASIC chip.
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Ibrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard." Journal of Communications Technology, Electronics and Computer Science 1 (October 22, 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.
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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.
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Hussain, Inamul, and Saurabh Chaudhury. "Design of energy-efficient multiplier based on 3:2 compressor." IAES International Journal of Robotics and Automation (IJRA) 10, no. 1 (March 1, 2021): 51. http://dx.doi.org/10.11591/ijra.v10i1.pp51-58.
Повний текст джерелаАнотація:
<span>A multiplier circuit is one of the most important functional blocks of many nano-electronic, control and automation applications. In this work, an energy-efficient multiplier is reported based on a 3:2 compressor. The multiplier has been designed in three different parts. In the first part, a partial product (PP) generator is used. In the second part, the partial products are reduced which is termed as PPP (partial product processing). Whereas in the third step final addition is performed. PPs are produced by using AND gates. The PPP is designed in two-phase. In the first phase, the Wallace tree logarithm has been used to reduce the PPs. Whereas, in the second phase the PPs are reduced by using energy-efficient half adder and 3:2 compressor. At last, in the third step, by using a carry-save adder final addition has been computed. The performance analysis of the designed multiplier is evaluated and compared with other multiplier circuits. The multiplier shows performance improvements by 20.55%-46% for the power supply variation from 1.2 V to 0.6 V. All the simulations and analyses have been carried out by using the Synopsys EDA tool.</span>
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Wei Kai, Woo, Nabihah Ahmad, and Mohamad Hairol Jabbar. "Design of low power 8-bit gate-diffusion input (GDI) full adder using variable body bias (VBB) technique in 90nm technology." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 912. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp912-920.
Повний текст джерелаАнотація:
In digital system, the full adders are fundamental circuits that are used for arithmetic operations. Adder operation can be used to implement and perform calculation of the multipliers, subtraction, comparators, and address operation in an Arithmetic Logic Unit (ALU). The subthreshold leakage current increasing as proportional with the scaling down of oxide thickness and transistor in short channel sizes. In this paper, a Gate-diffusion Input (GDI) circuit design technique allow minimization the number of transistor while maintaining low complexity of logic design and low power realization of Variable Body Biasing (VBB) technique to reduce the static power consumption. The Silterra 90nm process design kit (PDK) was used to design 8-bit full adder with VBB technique in full custom methodology by using Synopsys Electronic Design Automation (EDA) tools. The simulation of 8-bit full adder was compared within a conventional bias technique and VBB technique with operating voltage of supply. The result showed the reduction of VBB technique in term of peak power, and average power, compare with conventional bias technique. Moreover, the Power Delay Product (PDP) showed 1.29pJ in VBB technique compare with conventional bias mode 1.67pJ. The area size of 8-Bit full adder was 10μm×23μm.
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Dossis, M., and G. Dimitriou. "Are HLS Tools Healthy? The C-Cubed Project." Engineering, Technology & Applied Science Research 5, no. 2 (April 20, 2015): 790–94. http://dx.doi.org/10.48084/etasr.557.
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The increasing complexity of Application Specific Integrated Circuits (ASICs) and Systems-on-Chip (SoCs) that incorporate custom and standard embedded core IP blocks dictates the need for a new generation of automated and formal system EDA tools and methodologies. High-Level Synthesis (HLS) plays a critical role in the required Electronic System Level (ESL) methodologies. However, most of the available academic and commercial High-Level Synthesis (HLS) tools still do not play an established role in the system and hardware engineering teams. This is true for a number of practical reasons, analyzed and discussed in this work. The present article is a practical perspective of the required fully automated and formal tools, which are needed to constitute integral parts in Electronic Design Automation (EDA) flows. In addition, this article is a useful guide to the system engineer who wants to familiarize with HLS tools and to select the appropriate tool for the everyday engineering practice. The advanced HLS toolset that is analyzed in this paper is developed by the first author, its C-frontend by the second author, and they are both based on formal methods and fully automated techniques, thus they guarantee the correctness of the synthesized hardware implementations. This paper completes with a number of experiments that were executed using the author’s methodology and they are used to evaluate the specific HLS tools. Consequently, a number of conclusions are drawn as well as suggestions for the future directions of HLS technology. In this way, what is practically needed by the hardware systems engineering community is outlined at the end of the paper.
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Luo, Xiaoting, Zhiheng Huang, Shuanjin Wang, Min Xiao, Yuezhong Meng, Hui Yan, Qizhuo Li, and Gang Wang. "Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model." Electronics 11, no. 2 (January 11, 2022): 221. http://dx.doi.org/10.3390/electronics11020221.
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As thermal management in 3DIC integration becomes increasingly important in advanced semiconductor node processes, novel experimental and modeling approaches are in great demand to reveal the critical material issues involving multiscale microstructures that govern the behavior of through-silicon-via (TSV) protrusion. Here, a coarse-grained phase-field crystal model properly coupled with mechanics through the atomic density field is used to simulate the formation of polycrystalline structures and protrusion of nano-TSVs from the atomic scale. TSVs with different grain structures are directly loaded, and protrusion/intrusion profiles are obtained along with displacement, stress, and strain fields. Thermodynamic driving forces from external loadings and the mismatch of Young’s modulus between adjoining grains as well as detailed displacement and strain distributions are ascribed to control the complex deformation in TSVs. TSVs with sizes up to around 30 nm and an aspect ratio of 4 are successfully investigated, and a further increase in the size and aspect ratio to cover the micrometer range is feasible, which lays down a solid basis toward a multiscale material database for simulation inputs to the design of TSV-based 3DIC integration and relevant electronic design automation (EDA) tools.
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Markov, Igor L. "EDA: Synergy or sum of the parts? [review of "Electronic Design Automation: Synthesis, Verification and Test (Systems on Silicon" (Wang, L.-T., Eds., et al; 2009)]." IEEE Design & Test of Computers 28, no. 1 (January 2011): 78–79. http://dx.doi.org/10.1109/mdt.2011.13.
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Ahmad, Afaq, Sabir Hussain, M. A. Raheem, Ahmed Al Maashri, Sayyid Samir Al Busaidi, and Medhat Awadalla. "ASIC vs FPGA based Implementations of Built-In Self-Test." International Journal of Advanced Natural Sciences and Engineering Researches 7, no. 6 (July 13, 2023): 14–20. http://dx.doi.org/10.59287/ijanser.942.
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Linear Feedback Shift Registers (LFSRs) are play key role in testing of for Very Large Scale Integration (VLSI) Integrated Circuits (ICs) testing. Due to tremendous IC complex growth, testing of recent VLSI ICs technology have become more complicated. This led to develop a popular alternate viable solution in the form of Built-In Self-Test (BIST) technology as compared to Automatic Test Equipment (ATE). However, the challenges of BIST technology remain the subject of research. Furthermore, implementation of BIST’s LFSR on Application Specific Integrated Circuit (ASIC) versus Field Programmable Gate Array on (FPGA) platform is current area of research especially in context to power consumption. Hence, to make an informed choice between ASIC and FPGA for implementing BIST’s LFSR we focus on study of design of reconfigurable LFSR on ASIC versus FPGA platform. The Electronic Design Automation (EDA) tool, Cadence is used for implementing BIST’s LFSR on ASIC platform. Whereas, Hardware Description Language (HDL), Verilog is used to implement BIST’s LFSR on FPGA platform. During experimental methodology, maximum frequency, the critical path delay is investigated to assess the power dissipation. The functional and timing simulation models are used to verify the implemented reconfigurable BIST’s LFSR designs. The obtained results show that the performance, in terms of speed and power, of ASIC implementation is far better than traditional FPGA implementation.
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Shylashree, N., Yatish D. Vahvale, N. Praveena, and A. S. Mamatha. "Design and Implementation of 64-bit SRAM and CAM on Cadence and Open-source environment." International Journal of Circuits, Systems and Signal Processing 15 (July 14, 2021): 586–94. http://dx.doi.org/10.46300/9106.2021.15.65.
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Low-power IC design has become a priority in recent years because of the growing proliferation of portable battery-operated devices, bringing Static Random-Access Memory (SRAM) and Content Addressable Memory (CAM) into play. In today's SoCs, embedded SRAM units have become a necessary component. There is a lack of chips in the current world and to manufacture chips there is the requirement of Electronic Design Automation(EDA) tools that can perform better. In this paper, the main motive is to showcase the performance of open-source tools available currently which can still generate the required output with no cost. In this new era of fast mobile computing, traditional SRAM cell designs are power-demanding and underperforming. Rather than lowering manufacturing costs through high-volume production, specialty memory give cost-effective alternatives through architecture. Specialty memory devices enable the designer to address issues like board area, important timing, data flow bottlenecks, and so on in ways that high-volume regular memory devices cannot. Implementation of memory devices on Cadence environment and open-source environment to check the compatibility and compare the power, area, and delay of both 64-bit SRAM and CAM also analysing and validating the results of both the memory devices in this paper. For SRAM in a cadence environment, the calculated power, area, and slack have improved values, namely 0.145mW, 1104.3um2, and positive slack of 6636. Furthermore, the power for 64-bit CAM in a cadence context is nearly identical to those for an open-source environment ~0.8mW. In an open-source environment, the calculated slack for CAM is 4.74.
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Su, Hao, Shubin Yan, Xiaoyu Yang, Jing Guo, Jinxi Wang, and Ertian Hua. "Sensing Features of the Fano Resonance in an MIM Waveguide Coupled with an Elliptical Ring Resonant Cavity." Applied Sciences 10, no. 15 (July 24, 2020): 5096. http://dx.doi.org/10.3390/app10155096.
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In this article, a novel refractive index sensor composed of a metal–insulator–metal (MIM) waveguide with two rectangular stubs coupled with an elliptical ring resonator is proposed, the geometric parameters of which are controlled at a few hundreds of nanometer size. The transmission feature of the structure was studied by the finite element method based on electronic design automation (EDA) software COMSOL Multiphysics 5.4 (Stockholm, Sweden). The rectangular stub resonator can be thought of as a Fabry–Perot (FP) cavity, which can facilitate the Fano resonance. The simulation results reveal that the structure has a symmetric Lorentzian resonance, as well as an ultrasharp and asymmetrical Fano resonance. By adjusting the geometrical parameters, the sensitivity and figure of merit (FOM) of the structure can be optimized flexibly. After adjustments and optimization, the maximum sensitivity can reach up to 1550 nm/RIU (nanometer/Refractive Index Unit) and its FOM is 43.05. This structure presented in this article also has a promising application in highly integrated medical optical sensors to detect the concentration of hemoglobin and monitor body health.
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Quynh, Nguyen Vu. "Using radial basis function neural network for PMSM to overcome the changing load." Vietnam Journal of Science and Technology 59, no. 2 (March 16, 2021): 234–48. http://dx.doi.org/10.15625/2525-2518/59/2/14921.
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This paper presents a using Radial Basis Function Neural Network (RBFNN) for PMSM to overcome the changing load. Firstly, a mathematic model of the PMSM drive is derived; then, to increase the performance of the PMSM drive system, a Fuzzy PI controller in which an RBFNN adjusts its parameters is applied to the speed controller for coping with the effect of the system dynamic uncertainty and the external load. Secondly, the Very high-speed integrated circuit Hardware Description Language (VHDL) is adopted to describe the behaviour of the speed control IC which includes the circuits of space vector pulse width modulation (SVPWM), coordinate transformation, RBFNN, and Fuzzy PI. Thirdly, the simulation work is performed by MATLAB/Simulink and ModelSim co-simulation mode, provided by Electronic Design Automation (EDA) Simulator Link. The PMSM, inverter, and speed command are performed in Simulink, and the speed controller of the PMSM drive is executed in ModelSim. Finally, the co-simulation results validate the effectiveness of the proposed algorithm based speed control system
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Lillo, Paolo, Luca Mainetti, Vincenzo Mighali, Luigi Patrono, and Piercosimo Rametta. "An ECA-based Semantic Architecture for IoT Building Automation Systems." Journal of Communications Software and Systems 12, no. 1 (March 22, 2016): 24. http://dx.doi.org/10.24138/jcomss.v12i1.88.
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The Internet of Things (IoT), with its plethora of smart objects and technologies, allows to realize smart environments in several scenarios. However, the existing solutions are strictly intended for specific applications and their customization is often limited to what developers have considered at the design and implementation time. So, the integration of new functionalities requires significant changes by developers, while common users cannot make personalizations by themselves. For these reasons, this work deals with the definition of a novel rule-based semantic architecture for the easy implementation of building automation applications in an IoT context. Applications are structured as an Event-Condition-Action (ECA) rule and the layered architecture separates high-level semantic reasoning aspects from low-level execution details. The proposed architecture is also compared with main state-of-the-art solutions and a standard-based implementation framework is suggested. The last aspect is treated by referring to standardized guidelines and widely-accepted platforms, in order to make the proposal more attractive and robust.
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Ramadan, Tarek. "SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000856–77. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_015.
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INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of proven and qualified electronic design automation (EDA) tools and flows that can be used by the design houses to build HDAPs with the confidence that they are compliant with the foundry/OSAT requirements and recommendations. The need for and general concept of assembly design kits (ADKs) that provide proven, qualified flows for HDAPs has been previously discussed in multiple white papers. In addition, there have been analyses of the need for assembly-level layout vs. schematic (LVS) verification for HDAPs. Best practices for an assembly-level LVS process have been proposed, including the required inputs (data, formats, etc.), and likely hurdles and potential errors have been highlighted. There has even been discussion of how parasitic extraction could be achieved for packages. However, as HDAP technologies and flows mature, system-level designers want to know if package design rule checking (DRC), assembly-level LVS, and layout vs. layout (LVL) verification (die-to-package alignment, scaling, orientation, etc.) are sufficient to guarantee correct functionality and successful manufacturing of the HDAP. While this question may depend on how complicated the HDAP is, in general, the answer (for now) is no. As HDAP technologies become more and more similar to IC technologies, it is clear that, although the physical verification steps for HDAP may be considered good progress, they are only part of a much more comprehensive flow, one that must account for a more in-depth, system-level electrical analysis. Of course, at the same time, expanded EDA tool support is required to ensure fast, accurate, automated flows that ensure package designers can meet their market schedules and expectations. HDAP POST-LAYOUT ELECTRICAL ANALYSIS In the case of an HDAP design, the foundry/OSAT expects that each component is designed and validated to meet the required HDAP constraints and specifications. For an analog-based flow, the designer must simulate the HDAP system circuitry, including parasitics, to ensure it meets the intended performance specifications. For a digital-based flow, the designer must run static timing analysis (STA) on the complete HDAP system, including parasitics, to ensure it meets the overall system timing budget. From an EDA perspective, building an automated flow to support these checks/analyses provides assurance that these processes can occur in a consistent, repeatable manner while ensuring accuracy and minimizing runtime. In general, EDA approaches take one of two paths. SINGLE COCKPIT In the cockpit approach, an EDA supplier builds a single simulator infrastructure to support HDAP circuit simulation, parasitic extraction (PEX), and static timing analysis (STA). Although a single interface seems convenient, it forces the designer to use the same design tool for all components at all levels (die and package). This approach may be too restrictive, given that HDAP design and verification typically require the involvement of multiple groups with varying backgrounds and tool preferences. Although this approach would be useful when building “fully live” heterogeneous HDAPs (i.e., both die and package are under development simultaneously, and can both be edited for performance), this is rarely the case. More commonly, known good dies (which have already been taped out) are used to build an HDAP. TOOL-AGNOSTIC In the tool-agnostic approach, an EDA supplier enables the user to construct the needed system-level connectivity of the HDAP (including parasitics), regardless of which design tools are used to build any one die or the package. Once the system-level connectivity is available, it can be exported in the required format to any circuit simulation/STA tool to simulate or analyze the entire HDAP system. This approach introduces minimum disruption to existing tools/methodologies used for die and package design. This paper discusses the implementation of a system-level parasitic netlist process for the HDAP using the tool-agnostic approach.
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Boukorca, Ahcene, Ladjel Bellatreche, Sid-Ahmed Benali Senouci, and Zoé Faget. "Coupling Materialized View Selection to Multi Query Optimization." International Journal of Data Warehousing and Mining 11, no. 2 (April 2015): 62–84. http://dx.doi.org/10.4018/ijdwm.2015040104.
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Materialized views are queries whose results are stored and maintained in order to facilitate access to data in their underlying base tables of extremely large databases. Selecting the best materialized views for a given query workload is a hard problem. Studies on view selection have considered sharing common sub expressions and other multi-query optimization techniques. Multi-Query Optimization is a well-studied domain in traditional and advanced databases. It aims at optimizing a workload of queries by finding and reusing common sub-expression between queries. Finding the best shared expression is known as a NP-hard problem. The shared expressions usually identified by graph structure have been used to be candidate for materialized views. This shows the strong interdependency between the problems of materialized view selection (PVS) and multi query optimization (PMQO), since the PVS uses the graph structure of the PMQO. Exploring the existing works on PVS considering the interaction between PVS and PMQO figures two main categories of studies: (i) those considering the PMQO as a black box where the output is the graph and (ii) those preparing the graph to guide the materialized view selection process. In this category, the graph generation is based on individual query plans, an approach that does not scale, especially with the explosion of Big Data applications requiring large number of complex queries with high interaction. To ensure a scalable solution, this work proposes a new technique to generate a global processing plan without using individual plans by borrowing techniques used in the electronic design automation (EDA) domain. This paper first presents a rich state of art regarding the PVS and a classification of the most important existing work. Secondly, an analogy between the MQO problem and the EDA domain, in which large circuits are manipulated, is established. Thirdly, it proposes to model the problem with hypergraphs which are massively used to design and test integrated circuits. Fourthly, it proposes a deterministic algorithm to select materialized views using the global processing plan. Finally, experiments are conducted to show the scalability of our approach.
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Saxena, Rimjhim, and Kiran Sharma. "Delay Optimization and Power Optimization of 4-Bit ALU Designed in FS-GDI Technique." SMART MOVES JOURNAL IJOSCIENCE 6, no. 2 (February 1, 2020): 1–12. http://dx.doi.org/10.24113/ijoscience.v6i2.264.
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In this thesis proposed a reduction of delay, leakage current, leakage power. First find out the leakage current and leakage power. This thesis uses a gate diffusion input technique. By using this no of transistor is reduced. If number of transistor is reduced, area is also reduced, leakage current also affected. To study all parameter in this thesis uses a 2x1 MUX, 4x1MUX,16x1 MUX and ALU. Applying a GDI technique and also implemented by using a CMOS technique. Then do comparisons on GDI and CMOS technique and do a capacitance calculation. To implement all those things use a microwind 3.1 and DSCH 2.0. It is an Electronic Design Automation (EDA) environment that allows implementing a integrating in a single framework different applications and tools, allowing supporting all the stages of IC design and verification from a single environment. The resulting layout must verify some geometric rules dependent on the technology (design rules). Now checked with a Design Rule Checker (DRC) to find any error in the layout diagram and them simulation is performed. In implementing and do a comparisons of GDI and CMOS technique we get a 75% advantage in 2x1 MUX in counting the number of transistor. In 4x1 MUX we get again a 75% gain in the number of transistor. In 8x1 MUX, give a 78% benefits in the number of transistor. In 16x1 MUX, give a 81% benefits in the number of transistor. In 1 bit ALU give a 54% benefits in the number of transistor. If related power consumption, get a 74% benefits in comparisons of GDI and CMOS technique in 2x1 MUX. In 4x1mux give the advantage of 79% in the power consumption in comparisons of GDI and CMOS technique. In 8x1mux give the advantage of 78% in the power consumption in comparisons of GDI and CMOS technique. In 16x1mux give the advantage of 79% in the power consumption comparisons of GDI and CMOS technique. In bit ALU give the advantage of 64% in the power consumption in comparisons of GDI and CMOS technique.
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Naik Dessai, Sanket Suresh. "Design and Implementation of an Ethernet MAC IP Core for Embedded Applications." International Journal of Reconfigurable and Embedded Systems (IJRES) 3, no. 3 (November 1, 2014): 85. http://dx.doi.org/10.11591/ijres.v3.i3.pp85-97.
Повний текст джерелаАнотація:
<!--[if gte mso 9]><xml> <o:OfficeDocumentSettings> <o:RelyOnVML /> <o:AllowPNG /> </o:OfficeDocumentSettings> </xml><![endif]--> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">An IP (intellectual property) core is a block of logic or data that is used in making a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) for a product. As essential elements of design reuse, IP cores are part of the growing electronic design automation (EDA) industry trend towards repeated use of previously designed components. Ethernet continues to be one of the most popular LAN technologies. Due to the robustness resulting from its wide acceptance and deployment, there has been an attempt to build Ethernet-based real-time control networks for manufacturing automation. There is a growing demand for low cost, power efficient MAC IP Core for various embedded applications.<span style="mso-spacerun: yes;"> </span></span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt; mso-bidi-font-size: 10.0pt; color: black; mso-bidi-font-weight: bold; mso-no-proof: yes;"><span style="mso-spacerun: yes;"> </span>In this paper a</span><span style="font-size: 9.0pt;"> project is discussed to design an Ethernet MAC IP Core solution for such embedded applications. The proposed 10_100_1000 Mbps tri-mode Ethernet MAC implements a MAC controller conforming to IEEE 802.3 specification. It is designed to use less than 2000 LCs/LEs to implement full function. It will use inferred RAMs and PADs to reduce technology dependence. To increase the flexibility, three optional modules can be added to or removed from the project. A GUI configuration interface, created by Tcl/tk script language, is convenient for configuring optional modules, FIFO depth and verification parameters. Furthermore, a verification system was designed with Tcl/tk user interface, by which the stimulus can be generated automatically and the output packets can be verified with CRC-32 checksum.</span></p> <p class="MsoNormal" style="text-align: justify; text-justify: inter-ideograph; text-indent: 36.0pt;"><span style="font-size: 9.0pt;">A solution which would consume a smaller part of the targeted FPGA, and thus giving room for other on-chip peripherals or enable the use of a smaller sized FPGA. To employ a smaller FPGA is desirable since it would reduce power consumption and device price. </span></p> <!--[if gte mso 9]><xml> <w:WordDocument> <w:View>Normal</w:View> <w:Zoom>0</w:Zoom> <w:Compatibility> <w:BreakWrappedTables /> <w:SnapToGridInCell /> <w:WrapTextWithPunct /> <w:UseAsianBreakRules /> <w:UseFELayout /> </w:Compatibility> </w:WordDocument> </xml><![endif]--><!--[if gte mso 10]> <style>
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Zhu, Qing. "Data Mining Software Tools and Methodologies for VLSI Design." WSEAS TRANSACTIONS ON ELECTRONICS 13 (March 1, 2022): 1–10. http://dx.doi.org/10.37394/232017.2022.13.1.
Повний текст джерелаАнотація:
Modern VLSI design process employs numerous EDA tools to produce large-size report files. It is time consuming as well as the possibility to miss some violations from EDA report files. We developed two data mining software tools targeting for the timing, noise and power grid analysis report files in one high-performance SOC design project. The software extracts, sorts and displays the key information from EDA report files into HTML forms, which can be viewed by designers using the web browser. Organization of EDA report files, configure files, program execution flows and output HTML forms are described for the developed data mining software tools.
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Sun, Si Tong, An Gang Tian, and De Cai Zhuang. "The Design of Electronic Code Lock." Advanced Materials Research 267 (June 2011): 1001–4. http://dx.doi.org/10.4028/www.scientific.net/amr.267.1001.
Повний текст джерелаАнотація:
In this paper, by using EDA technology, Quartus II6.0 working platform and VHDL hardware description language, an electronic code lock based on the programmable gate array FPGA is designed with a top-down design.
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Rhines, W. C. "Sociology of Design and EDA." IEEE Design & Test of Computers 23, no. 4 (April 2006): 304–10. http://dx.doi.org/10.1109/mdt.2006.103.
Повний текст джерела