Дисертації з теми "Electrical interconnect modeling"
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Kim, Byungsub 1978. "Equalized on-chip interconnect : modeling, analysis, and design." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58076.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (p. 115-118).
This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is demonstrated to search for the optimal link design parameters (wire and circuit) and to generate the optimal performance-power trade-off curve for the equalized interconnects. This thesis also proposes new circuit techniques, which improve the revealed demerits of the conventional circuit topologies. The proposed charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in the conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient nonlinear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10 mm, 2[micro]m pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 2-6 Gb/s/ch.
by Byungsub Kim.
Ph.D.
Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul) 1973. "Interconnect modeling and optimization in deep sub-micron technologies." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29230.
Повний текст джерелаIncludes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.
Vittala, Kavya. "Interconnect Modeling and Lifetime Failure Detection in FPGAs using Delay Faults." University of Toledo / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1404728195.
Повний текст джерелаPercey, Andrew K. (Andrew Kenneth). "Analysis and modeling of capacitive coupling along metal interconnect lines." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/39067.
Повний текст джерелаIncludes bibliographical references (leaf 87).
by Andrew K. Percey.
M.Eng.
Kuo, Benjamin S. "Modeling and evaluation of a hierarchical ring interconnect for system-on-chip multiprocessing." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=81543.
Повний текст джерелаChou, Mike Chuan 1969. "Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46180.
Повний текст джерелаIncludes bibliographical references (leaves 131-135).
by Mike Chuan Chou.
Ph.D.
Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
Повний текст джерелаDavid E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
Lee, Laurence H. (Laurence Hongsing). "Modeling and design of superconducting microwave passive devices and interconnects." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36452.
Повний текст джерелаIncludes bibliographical references (p. 157-163).
by Laurence H. Lee.
Ph.D.
Chiun-Shen, Liao. "A network approach for thermo-electrical modelling : from IC interconnects to textile composites." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/28471.
Повний текст джерелаBourduas, Stephan. "Modeling, evaluation, and implementation of ring-based interconnects for network-on-chip." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19244.
Повний текст джерелаCette thèse étudie les propriétés d'une interconnexion hiérarchique composée d'anneaux unidirectionnels. La topologie d'anneaux hiérarchique possède plusieurs caractéristiques souhaitables pour être utilisée comme interconnexion pour réseau-sur-puce (NoC). En premier lieu, la structure unidirectionnelle des anneaux sert à réduire la complexité de routage, ce qui implique une diminution de l'importance des mémoires tampon requises et économise l'énergie consommée par l'interconnexion. En second lieu, les faibles temps de latences et d'horloge système élevé résultent de la simplicité logique de chaque routeur. Finalement, la structure de l'interconnexion facilite une partition où chaque anneau appartient à son propre domaine contrôlé par une horloge individuelle, ce qui rend possible l'application de stratégies dynamiques permettant l'économie d'énergie. L'architecture proposée a été évaluée grâce à des simulations de modèles de hauts niveaux et par une implémentation logique résistance-transistor (RTL). De plus, les anneaux hiérarchiques sont combinés avec l'architecture de maille (« mesh ») bidimensionnelle pour former plusieurs architectures hybrides afin d'améliorer la performance du réseau. La topologie de maille démontre l'augmentation de latences, du nombre de sauts, et de la congestion avec l'agrandissement du réseau. Cependant, les architectures hybrides utilisent les anneaux hiérarchiques pour réduire la congestion au centre du réseau et diminuer le nombre de sauts et les temps de latences associés avec les communications à longue distance. Il en résulte donc une amélioration globale de la performance du système. Les résultats des simulations démontrent que les$
Hsu, Pochang. "A computer-aided design framework for modeling and simulation of VLSI interconnects." Diss., The University of Arizona, 1993. http://hdl.handle.net/10150/186363.
Повний текст джерелаPark, Tae Hong 1973. "Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8082.
Повний текст джерелаIncludes bibliographical references (p. 173-176).
Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing.
(cont.) Especially for the multi-level studies, electrical test structures and measurements in addition to surface profile scans are seen to be important in accurately determining thickness variations. The developed test vehicle and characterization of copper dishing and oxide erosion serve as a basis for further pattern dependent model development. Finally, integration of electroplating and CMP chip-scale models is illustrated; the simulated step and array heights as well as topography pattern density are used as an input for the initial starting topography for CMP simulation of subsequent polishing profile evolution.
by Tae Hong Park.
Ph.D.
Chen, Quan. "Efficient numerical modeling of random surface roughness for interconnect internal impedance extraction." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B3955708X.
Повний текст джерелаChen, Quan, and 陳全. "Efficient numerical modeling of random surface roughness for interconnect internal impedance extraction." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B3955708X.
Повний текст джерелаXie, Jianyong. "Electrical-thermal modeling and simulation for three-dimensional integrated systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50307.
Повний текст джерелаDu, Zhaobin. "Area COI-based slow frequency dynamics modeling, analysis and emergency control for interconnected power systems." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B4175783X.
Повний текст джерелаSarker, Partha Sarathi. "DYNAMIC MODELING, STABILITY ANALYSIS AND CONTROL OF AC/DC INTERCONNECTED MICROGRID USING DQ-TRANSFORMATION." Master's thesis, Temple University Libraries, 2018. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/518146.
Повний текст джерелаM.S.E.E.
In recent years, there have been significant changes in power systems due to the integration of renewables, distributed generation, switched power loads, and energy storage systems, etc. Locally these AC/DC microgrids include both DC generation (such as solar PV) and AC generation (such as wind generation), various DC and AC loads, converters and inverters, and energy storage systems, such as storage batteries and supercapacitors. DC systems are often characterized as low inertia systems whereas AC generation and systems are usually high inertia and high time constant systems. As such, various components of the microgrid will have different temporal characteristics in case of disturbances, such as short circuit, load switchings, etc. which may lead to instability of the microgrid. This research develops the first principle model for coupling the AC and the DC subsystem of an integrated AC/DC microgrid utilizing the dq-framework. The developed model is highly nonlinear and captures the dynamic interaction between the AC and DC subsystems of the microgrid. Lyapunov stability is used to evaluate the stability of the complete system. Simulation results show that the AC and DC subsystems are tightly dynamically coupled so that any disturbance in one subsystem induces transients in the other subsystem. Induced transients due to pulse loads on the AC and DC subsystems clearly show that generator damper winding alone may not be enough to mitigate transients in the microgrid. Addition of prime mover and excitation system controllers for the generator improves the transients primarily on the AC subsystem. Thus, a battery storage with a charge/discharge controller was also added to the DC subsystem. Simulations of the AC/DC microgrid with all three controllers validate the smooth operation of the system for all types of disturbances. The proposed method can be extended in modeling microgrid with multiple generators and various types of loads.
Temple University--Theses
Du, Zhaobin, and 杜兆斌. "Area COI-based slow frequency dynamics modeling, analysis and emergency control for interconnected power systems." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B4175783X.
Повний текст джерелаPasha, Soheila. "Electromagnetic Modeling of High-Speed Interconnects with Frequency Dependent Conductor Losses, Compatible with Passive Model Order Reduction Techniques." Diss., The University of Arizona, 2012. http://hdl.handle.net/10150/268354.
Повний текст джерелаHan, Ki Jin. "Electromagnetic modeling of interconnections in three-dimensional integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29642.
Повний текст джерелаCommittee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Sreedhar, Aswin. "Automatic techniques for modeling impact of sub-wavelength lithography on transistors and interconnects and strategies for testing lithography induced defects." Connect to this title online, 2008. http://scholarworks.umass.edu/theses/80/.
Повний текст джерелаMao, Jifeng. "Modeling of simultaneous switching noise in on-chip and package power distribution networks using conformal mapping, finite difference time domain and cavity resonator methods." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-10062004-125025/.
Повний текст джерелаMadhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.
Gencoglu, Cihangir. "Assessment Of The Effect Of Hydroelectric Power Plants'." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612165/index.pdf.
Повний текст джерелаReehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.
Повний текст джерелаBellache, Kosseila. "Caractérisation Multi-physique des éléments de stockage électrochimique et électrostatique dédiés aux systèmes Multi sources : Approche systémique pour la gestion dynamique d'énergie électrique." Thesis, Normandie, 2018. http://www.theses.fr/2018NORMLH21.
Повний текст джерелаThis thesis work is a continuation of the research activities of the GREAH laboratory on the issues of the management of electrical energy and improving the energy quality of production systems for renewable energy. Indeed, the coupling of several different nature sources entails the problems of dimension, quality of energy and the lifetime of the interconnected elements. The scientific approach is based on the characterization of the evolution of the resistances and capacitances of the batteries/supercapacitors cells according to the electrical and thermal constraints, followed by the modeling of accelerated cells aging. In this thesis, we propose improvements to the dynamic response of an electric propulsion fluvial boat by using the hybrid system of lithium-batteries and supercapacitors. We also propose an electrothermal approach for the multi-physical characterization and modeling of the batteries and supercapacitors aging, using combined constraints of the temperature and frequency of the DC current ripples. The experimental data has been collected to establish models of batteries and supercapacitors dedicated to multi-source systems including renewable energy sources (wind and tidal turbines). The results of the developed models shown high accuracy compared with experimental results. These models illustrated a good description of the aging phenomenon of batteries/ supercapacitors due to charging/discharging operations with a fluctuating continuous current combined with a variable temperature
Palaniappan, Arun. "Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8618.
Повний текст джерелаGumede, Nkosinomusa S. "Eskom-ZESA interconnected power system modelling." Thesis, 2016. http://hdl.handle.net/10539/21110.
Повний текст джерелаThe power system frequency must be kept as close as possible to the nominal value. This is due to the inherent design of electrical equipment to operate efficiently at the nominal frequency. Frequency regulation in an interconnected power system is the duty of all members of the interconnection. However, in the Eskom-ZESA interconnected power system Eskom engineers ignore the contribution of the ZESA system to primary frequency control. This is mainly due to the prevalent assumption that the ZESA control area is small relative to the Eskom control area and its contribution to primary frequency control of the interconnected power system is negligible. This document presents a project that examines the validity of this assumption via determination of the contribution of the ZESA system to the interconnected power system’s primary frequency control. The interconnected power systems background was studied to understand the theory behind the operation of two or more interconnected power systems. System frequency disturbances deemed to be a good representation of the Eskom-ZESA interconnected power system’s performance were selected and analysed to validate the current assumption. The results show that there is a significant support from ZESA during a system frequency disturbance. This proves that the existing assumption is not valid anymore. Furthermore; the generator model that mimics the Eskom-ZESA tie-line governing behaviour was developed. Two different types of governor models were employed; firstly the IEEEG1 governor was tuned to control generator output to match the tie-line performance and then the TGOV5 governor model was used. The IEEEG1 governor model is a simplified governor representation; as a result, it is not easy to tune the parameters to match tie-line response. However, the performance is acceptable and it can be used to represent the tieline governor response. The TGOV5 governor model is very complex as discussed in section 4.2. The model includes boiler dynamics, and this improves performance such that it is possible to tune the parameters to follow the tie-line performance as close as necessary.
GR2016
Sun, Ruey-Bo, and 孫瑞伯. "Electrical Modeling and Design for Signal Integrity of Area-Array Vertical Interconnects in Electronic Packaging." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60943366541212561875.
Повний текст джерела國立臺灣大學
電信工程學研究所
99
In order to optimize the electrical performance of electronic packaging, the electrical modeling and designs for signal integrity (SI) of vertical interconnects are the considerably critical issues. In this dissertation, the various significant kinds of noises, including reflection, crosstalk, simultaneous switching noise (SSN), and substrate loss in the area-array vertical interconnects, are investigated by taking three different types of vertical interconnects, consisting of pin type (pogo pin), ball-shape type (bump and solder ball), and via type (through silicon via, TSV) as examples. A series of novel and systematic methodologies are proposed for the investigations and noise suppression. With regard to the analysis and suppression of SSN, this dissertation takes a bump grid array as an example to propose a systematic design methodology, acquiring the optimal signal-ground assignment with the minimized loop SSN by using genetic algorithm (GA). For the reduction of computing complexity, a new circuit simplification method is developed to simplify a complete I/O buffer circuits, including package traces and a bump array, into a circuit of inductors and current sources together with its applicable range derived analytically. Based on the optimized results, the optimal signal-to-ground ratio and its associated bump assignments are obtained. Also, some heuristic designs are proposed, accordingly. As for suppressions of the reflection and crosstalk, designs of the impedance match and crosstalk reduction for all possible signal-ground assignments are very challenging. In this dissertation, a novel compromise impedance match design is proposed for a pogo pin array with the diverse pin assignments to find the permissible window of the pogo pin geometries and the upper bound of operating frequency such that all pin patterns meet the specification on return loss. Two different types of design charts are developed to greatly facilitate the design. The first one is the equivalent impedance of pogo pin versus the pin radius-to-pitch ratio. The second one is a much general chart in terms of the reflection coefficient versus the electrical length and the relative impedance difference of the pogo pin. On the other hand, for the sake of the crosstalk reduction in the pogo pin array, a new isolation structure directly integrated in a test socket is proposed. The isolation structure is appropriately designed by adopting the full-wave and quasi-static methods so that the reflection and crosstalk for all pin patterns are both smaller than -20 dB over dc to 10 GHz. The measured S parameters obtained by using the new test fixtures have good correlations with simulated ones, validating the proposed ideas and methodologies. Regarding to the suppression of dispersion noise due to the substrate loss, the equalization technique can be introduced to compensate the lossy effect. Considering the TSV interconnect in the three-dimensional integrated circuit (3D IC), a novel passive equalizer capable of the perfect compensation for lossy effects of TSV is devised. It is only composed of a parallel resistance-capacitance (RC) circuit. To design the equalizer, the analytic circuit model of TSV is derived and substantiated up to 20 GHz, and based on which, the novel significance analysis is implemented to inspect the relative importance of each parasitic element, thereby attaining a much simplified capacitance-conductance (CG) circuit model. It proves that the first order effects of TSV are attributed to the oxide liner and the lossy silicon substrate. The design theory and formulas of the equalizer can also be derived accordingly. The output eye diagram of multi-stacked TSVs in series with the designed equalizer is nearly open with zero timing jitter.
"Modelling, simulation and experimental observation of wave propagation on VLSI interconnects." 1997. http://library.cuhk.edu.hk/record=b5889206.
Повний текст джерелаThesis (M.Phil.)--Chinese University of Hong Kong, 1997.
Includes bibliographical references (leaves 127-[129]).
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- VLSI Interconnects in Circuits --- p.1
Chapter 1.2 --- Propagating Waves on Interconnects --- p.4
Chapter 2 --- Theory: FDTD --- p.6
Chapter 2.1 --- Modelling Microstrips in FDTD Mesh Space --- p.6
Chapter 2.2 --- FDTD Implementation of a Unit Cell --- p.8
Chapter 2.3 --- FDTD Implementation of a Lumped Element --- p.12
Chapter 2.4 --- FDTD Implementation of a Circuit --- p.14
Chapter 3 --- Theory: TDMS --- p.20
Chapter 3.1 --- FDTD Circuit Simulation --- p.20
Chapter 3.2 --- TDMS: Microstrip Characterization --- p.22
Chapter 3.3 --- TDMS: Parameter Extraction --- p.23
Chapter 3.4 --- TDMS: Circuit Simulation --- p.26
Chapter 4 --- TDMS Simulations --- p.30
Chapter 4.1 --- Example One: Loaded Diode --- p.30
Chapter 4.2 --- Example Two: Unbalanced Mixer --- p.38
Chapter 5 --- TDR Experiments --- p.54
Chapter 5.1 --- Example Three: Uniform Microstrip --- p.54
Chapter 5.2 --- Example Four: Coupled Microstrip --- p.61
Chapter 5.3 --- Example Five: Change-in-width Microstrip --- p.67
Chapter 6 --- Conclusion --- p.78
Chapter 7 --- Program Listing --- p.80
Chapter 7.1 --- Example Two: Unbalanced Mixer --- p.80
Chapter 7.2 --- Example Five: Change-in-width Microstrip --- p.110
Bibliography --- p.127