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Miller, Jason Eric 1976. "Software instruction caching." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40317.
Повний текст джерелаАнотація:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (p. 185-193).<br>As microprocessor complexities and costs skyrocket, designers are looking for ways to simplify their designs to reduce costs, improve energy efficiency, or squeeze more computational elements on each chip. This is particularly true for the embedded domain where cost and energy consumption are paramount. Software instruction caches have the potential to provide the required performance while using simpler, more efficient hardware. A software cache consists of a simple array memory (such as a scratchpad) and a software system that is capable of automatically managing that memory as a cache. Software caches have several advantages over traditional hardware caches. Without complex cache-management logic, the processor hardware is cheaper and easier to design, verify and manufacture. The reduced access energy of simple memories can result in a net energy savings if management overhead is kept low. Software caches can also be customized to each individual program's needs, improving performance or eliminating unpredictable timing for real-time embedded applications. The greatest challenge for a software cache is providing good performance using general-purpose instructions for cache management rather than specially-designed hardware. This thesis designs and implements a working system (Flexicache) on an actual embedded processor and uses it to investigate the strengths and weaknesses of software instruction caches. Although both data and instruction caches can be implemented in software, very different techniques are used to optimize performance; this work focuses exclusively on software instruction caches. The Flexicache system consists of two software components: a static off-line preprocessor to add caching to an application and a dynamic runtime system to manage memory during execution. Key interfaces and optimizations are identified and characterized. The system is evaluated in detail from the standpoints of both performance and energy consumption. The results indicate that software instruction caches can perform comparably to hardware caches in embedded processors. On most benchmarks, the overhead relative to a hardware cache is less than 12% and can be as low as 2.4%. At the same time, the software cache uses up to 6% less energy. This is achieved using a simple, directly-addressed memory and without requiring any complex, specialized hardware structures.<br>by Jason Eric Miller.<br>Ph.D.
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Chiou, Albert (Albert C. ). "Design study of a novel computer instruction execution unit." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45998.
Повний текст джерелаАнотація:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>Includes bibliographical references (p. 32).<br>The goal of the "Fresh Breeze Project" is to develop a multi-core chip architecture that supports a better programming model for parallel computing. This architecture combines simultaneous multithreading, a global shared address space, no memory update, and a cycle-free heap to provide a platform for robust, general-purpose, parallel computation. These design choices help simplify classically hard problems such as memory coherency, control flow, and synchronization. An HDL implementation of the core execution unit of a single processing core (many cores are on a single chip) forms the basis of further simulation and synthesis. The design must first be broken down into functional logic blocks and translated into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level "guarded atomic actions" triggered by a rule based system.<br>by Albert Chiou.<br>M.Eng.
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Chapman, David 1961. "Vision, instruction, and action." Thesis, Massachusetts Institute of Technology, 1990. http://hdl.handle.net/1721.1/17253.
Повний текст джерелаАнотація:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990.<br>Includes bibliographical references (p. 222-242).<br>by David Chapman.<br>Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1990.
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Shamsapour, Ali A. "HyperCard-based learning environment for DIADES." PDXScholar, 1990. https://pdxscholar.library.pdx.edu/open_access_etds/4128.
Повний текст джерелаАнотація:
This thesis is an attempt to create a HyperCard-based learning environment to teach DIADES and other related material. It is a departure from the classical Computer Aided Instruction methods towards a more flexible and user-controlled design. The goal was to set the foundation of a new CAI design which would closely resemble a Hyper- Text system. These systems are characterized as having interconnections between related concepts in the CAI environment.
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Pan, Heidi 1980. "High performance, variable-length instruction encodings." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/87277.
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Swenson, Shane Michael 1979. "Spatial instruction scheduling for raw machines." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/28620.
Повний текст джерелаАнотація:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.<br>Includes bibliographical references (leaves 89-91).<br>Instruction scheduling on software exposed architectures, such as Raw, must be performed in both time and space. The complexity and variance of application scheduling regions dictates that the space-time scheduling task be divided into phases. Unfortunately, the interaction of phases presents a phase ordering problem. In this thesis, the structure of program scheduling regions is studied. The scheduling regions are shown to have varying characteristics that are too diverse for a single simple algorithm to cover. A new scheduling technique is proposed to cope with this diversity and minimize the phase ordering problem. First, rather than maintaining exact mappings of instructions to time and space, the internal state of the scheduler maintains probabilities for different assignments of instructions to time and space resources. Second, a set of small scheduling heuristics cooperatively iterate over the probabilistic assignments many times in order to minimize the effects of phase ordering. A simple spatial instruction scheduler for Raw machines based on this technique is implemented and shown to outperform existing spatial scheduling systems on average.<br>by Shane Michael Swenson.<br>M.Eng.
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Khetan, Amit 1978. "Local search for optimizing instruction cache." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80076.
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Panich, Mukaya 1975. "Reducing instruction cache energy using gated wordlines." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80231.
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Lee, Vinson 1978. "Instruction set and simulation framework for transactional memory." Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/87369.
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Tung, Eric Gregory. "A configurable 3-phase machine for laboratory instruction." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37107.
Повний текст джерелаАнотація:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 177).<br>In order to learn about and work effectively with electromechanical systems, many students need exposure to these systems before completing their education. This thesis work introduces two novel teaching aids for laboratory classes. The first is a 3-phase axial-flux machine which can be configured as a permanent-magnet or induction machine with moderate effort for teaching about power electronics. The second is an introductory robot which demonstrates and controls electromagnetic actuators for teaching an introductory freshman class.<br>by Eric Gregory Tung.<br>M.Eng.
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Miller, Jason Eric 1976. "Software based instruction caching for the RAW architecture." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80552.
Повний текст джерелаАнотація:
Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (p. 39).<br>by Jason Eric Miller.<br>S.B.and M.Eng.
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Larsen, Samuel (Samuel Barton) 1975. "Exploiting superword level parallelism with multimedia instruction sets." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86445.
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Buehler, Christopher James 1974. "An instruction scheduling algorithm for communication-constrained microprocessors." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46254.
Повний текст джерелаАнотація:
Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (p. 130-132).<br>This thesis describes a new randomized instruction scheduling algorithm designed for communication-constrained VLIW-style machines. The algorithm was implemented in a retargetable compiler system for testing on a variety a different machine configurations. The algorithm performed acceptably well for machines with full communication, but did not perform up to expectations in the communication-constrained case. Parameter studies were conducted to ascertain the reason for inconsistent results.<br>by Christopher James Buehler.<br>S.M.
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Sung, Michael 1975. "Design of trace caches for high bandwidth instruction fetching." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46200.
Повний текст джерелаАнотація:
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (leaves 60-63).<br>by Michael Sung.<br>M.Eng.
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Liu, Rose F. (Rose Frances). "AXCIS : rapid processor architectural exploration using canonical instruction segments." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/36792.
Повний текст джерелаАнотація:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 73-74).<br>In the early stages of processor design, computer architects rely heavily on simulation to explore a very large design space. Although detailed microarchitectural simulation is effective and widely used for evaluating different processor configurations, long simulation times and a limited time-to-market severely constrain the number of design points explored. This thesis presents AXCIS, a framework for fast and accurate early-stage design space exploration. Using instruction segments, a new primitive for extracting and representing simulation-critical data from full dynamic traces, AXCIS compresses the full dynamic trace into a table of canonical instruction segments (CIST). CISTs are not only small, but also very representative of the dynamic trace. Therefore, given a CIST and a processor configuration, AXCIS can quickly and accurately estimate performance metrics such as instructions per cycle (IPC). This thesis applies AXCIS to in-order superscalar processors, which are becoming more popular with the emergence of chip multiprocessors (CMP). For 24 SPEC CPU2000 benchmarks and all simulated configurations, AXCIS achieves an average IPC error of 2.6% and is over four orders of magnitude faster than conventional detailed simulation.<br>(cont.) While cycle-accurate simulators can take many hours to simulate billions of dynamic instructions, AXCIS can complete the same simulation on the corresponding CIST within seconds.<br>by Rose F. Liu.<br>M.Eng.
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Sayan, Eren Sila. "Audience aware computational discourse generation for instruction and persuasion." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91868.
Повний текст джерелаАнотація:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 131-134).<br>If we are to take artificial intelligence to the next level, we must further our understanding of human storytelling, arguably the most salient aspect of human intelligence. The idea that the study and understanding of human narrative capability can advance multiple fields, including artificial intelligence, isn't a new one. The following, however, is: I claim that the right way to study and understand storytelling is not through the traditional lens of human creativity, aesthetics or even as a plain planning problem, but through formulating storytelling as a question of goal driven social interaction. In particular, I claim that any theory of storytelling must account for the goals of the storyteller and the storyteller's audience. To take a step toward such an account, I offer a framework, which I call Audience Aware Narrative Generation, drawing inspiration in particular from narratology, cognitive science, and of course, computer science. I propose questions that we need to work on answering, and suggest some rudimentary starter thoughts to serve as guidelines for continued research. I picked a small subset of the proposed questions on which to focus my computational efforts: storytelling for teaching and persuasive storytelling. More specifically, I developed exploratory implementations for addressing this subset on the Genesis story understanding platform. The results have been encouraging: On the pedagogical side, my implementation models and simulates a teacher using the story of Macbeth to instruct a student about concepts such as murder, greed, and predecessor relationships in monarchies. On the persuasion side, my implementation models and simulates various different tellings of the classic fairy tale "Hansel and Gretel" so as to make The Witch appear likable in one, and unlikable in another; to make The Woodcutter appear to be a good parent just going through difficult times in one, and a bad parent in another. Perhaps the most amusing example however, especially in these days of sensationalized and highly subjective journalism, is that given a story of the cyber warfare between Russia and Estonia, my implementation can generate one telling of the story which makes Russia appear to be the aggressor, and yet another telling which makes Estonia appear to be the aggressor. And isn't that the story of history, politics, and journalism in one neat package! Overall, I have made four key contributions: I proposed Audience Aware Narrative Generation as a new framework for developing theories of storytelling; I identified important questions that must be answered by storytelling research and proposed initial plans of attack for them; I introduced storytelling functionality into the Genesis story understanding platform; and I implemented narrative discourse generators which produce a wide range of narratives, adapting accordingly to different audiences and goals.<br>by Eren Sila Sayan.<br>M. Eng.
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Lee, Walter (Walter Cheng-Wan). "Software orchestration of instruction level parallelism on tiled processor architectures." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33862.
Повний текст джерелаАнотація:
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (p. 135-138).<br>Projection from silicon technology is that while transistor budget will continue to blossom according to Moore's law, latency from global wires will severely limit the ability to scale centralized structures at high frequencies. A tiled processor architecture (TPA) eliminates long wires from its design by distributing its resources over a pipelined interconnect. By exposing the spatial distribution of these resources to the compiler, a TPA allows the compiler to optimize for locality, thus minimizing the distance that data needs to travel to reach the consuming computation. This thesis examines the compiler problem of exploiting instruction level parallelism (ILP) on a TPA. It describes Rawcc, an ILP compiler for Raw, a fully distributed TPA. The thesis examines the implication of the resource distribution on the exploitation of ILP for each of the following resources: instructions, registers, control, data memory, and wires. It designs novel solutions for each one, and it describes the solutions within the integrated framework of a working compiler. Performance is evaluated on a cycle-accurate Raw simulator as well as on a 16-tile Raw chip. Results show that Rawcc can attain modest speedups for fine-grained applications, as well speedups that scale up to 64 tiles for applications with such parallelism.<br>by Walter Lee.<br>Ph.D.
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Ong, Jia Jan. "Hardware realization of Discrete Wavelet Transform Cauchy Reed Solomon Minimal Instruction Set Computer architecture for Wireless Visual Sensor Networks." Thesis, University of Nottingham, 2016. http://eprints.nottingham.ac.uk/32583/.
Повний текст джерелаАнотація:
Large amount of image data transmitting across the Wireless Visual Sensor Networks (WVSNs) increases the data transmission rate thus increases the power transmission. This would inevitably decreases the operating lifespan of the sensor nodes and affecting the overall operation of WVSNs. Limiting power consumption to prolong battery lifespan is one of the most important goals in WVSNs. To achieve this goal, this thesis presents a novel low complexity Discrete Wavelet Transform (DWT) Cauchy Reed Solomon (CRS) Minimal Instruction Set Computer (MISC) architecture that performs data compression and data encoding (encryption) in a single architecture. There are four different programme instructions were developed to programme the MISC processor, which are Subtract and Branch if Negative (SBN), Galois Field Multiplier (GF MULT), XOR and 11TO8 instructions. With the use of these programme instructions, the developed DWT CRS MISC were programmed to perform DWT image compression to reduce the image size and then encode the DWT coefficients with CRS code to ensure data security and reliability. Both compression and CRS encoding were performed by a single architecture rather than in two separate modules which require a lot of hardware resources (logic slices). By reducing the number of logic slices, the power consumption can be subsequently reduced. Results show that the proposed new DWT CRS MISC architecture implementation requires 142 Slices (Xilinx Virtex-II), 129 slices (Xilinx Spartan-3E), 144 Slices (Xilinx Spartan-3L) and 66 Slices (Xilinx Spartan-6). The developed DWT CRS MISC architecture has lower hardware complexity as compared to other existing systems, such as Crypto-Processor in Xilinx Spartan-6 (4828 Slices), Low-Density Parity-Check in Xilinx Virtex-II (870 slices) and ECBC in Xilinx Spartan-3E (1691 Slices). With the use of RC10 development board, the developed DWT CRS MISC architecture can be implemented onto the Xilinx Spartan-3L FPGA to simulate an actual visual sensor node. This is to verify the feasibility of developing a joint compression, encryption and error correction processing framework in WVSNs.
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Fang, Gloria(Gloria Yu Liang). "Instruction-level power consumption simulator for modeling simple timing and power side channels in a 32-bit RISC-V micro-processor." Thesis, Massachusetts Institute of Technology, 2021. https://hdl.handle.net/1721.1/130686.
Повний текст джерелаАнотація:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, February, 2021<br>Cataloged from the official PDF of thesis.<br>Includes bibliographical references (pages 139-140).<br>We create a Python based RISC-V simulator that is capable of simulating any assembly code written in RISC-V, and even perform simple power analysis of RISC-V designs. The power consumption of non-privileged RISC-V RV32IM instructions are measured experimentally, forming the basis for our simulator. These instructions include memory loads and stores, PC jumps and branches, as well as arithmetic instructions with register values. The object-oriented simulator also supports stepping and debugging. In the context of designing software for hardware use, the simulator helps assess vulnerability to side channel attacks by accepting input power consumption values. The power consumption graph of any disassembled RISC-V code can be obtained if the power consumption of each instruction is given as an input; then, from the output power consumption waveforms, we can assess how vulnerable a system is to side channel attacks. Because the power values can be customized based on what's experimentally measured, this means that our simulator can be applied to any disassembled code and to any system as long as the input power consumption of each instruction is supplied. Finally, we demonstrate an example application of the simulator on a pseudorandom function for simple side channel power analysis.<br>by Gloria (Yu Liang) Fang.<br>M. Eng.<br>M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
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Lim, Nien Yi. "Separating instruction fetches from memory accesses ILAR (Instruction Line Associative Registers) /." Lexington, Ky. : [University of Kentucky Libraries], 2009. http://hdl.handle.net/10225/1121.
Повний текст джерелаАнотація:
Thesis (M.S.)--University of Kentucky, 2009.<br>Title from document title page (viewed on May 6, 2010). Document formatted into pages; contains: viii, 59 p. : ill. (some col.). Includes abstract and vita. Includes bibliographical references (p. 56-58).
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Ponnala, Kalyan. "DESIGN AND IMPLEMENTATION OF THE INSTRUCTION SET ARCHITECTURE FOR DATA LARS." UKnowledge, 2010. http://uknowledge.uky.edu/gradschool_theses/58.
Повний текст джерелаАнотація:
The ideal memory system assumed by most programmers is one which has high capacity, yet allows any word to be accessed instantaneously. To make the hardware approximate this performance, an increasingly complex memory hierarchy, using caches and techniques like automatic prefetch, has evolved. However, as the gap between processor and memory speeds continues to widen, these programmer-visible mechanisms are becoming inadequate.
Part of the recent increase in processor performance has been due to the introduction of programmer/compiler-visible SWAR (SIMD Within A Register) parallel processing on increasingly wide DATA LARs (Line Associative Registers) as a way to both improve data access speed and increase efficiency of SWAR processing. Although the base concept of DATA LARs predates this thesis, this thesis presents the first instruction set architecture specification complete enough to allow construction of a detailed prototype hardware design. This design was implemented and tested using a hardware simulator.
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Muthukumarasamy, Muthulakshmi. "EXTRACTION AND PREDICTION OF SYSTEM PROPERTIES USING VARIABLE-N-GRAM MODELING AND COMPRESSIVE HASHING." UKnowledge, 2010. https://uknowledge.uky.edu/gradschool_diss/800.
Повний текст джерелаАнотація:
In modern computer systems, memory accesses and power management are the two major performance limiting factors. Accesses to main memory are very slow when compared to operations within a processor chip. Hardware write buffers, caches, out-of-order execution, and prefetch logic, are commonly used to reduce the time spent waiting for main memory accesses. Compiler loop interchange and data layout transformations also can help. Unfortunately, large data structures often have access patterns for which none of the standard approaches are useful. Using smaller data structures can significantly improve performance by allowing the data to reside in higher levels of the memory hierarchy. This dissertation proposes using lossy data compression technology called ’Compressive Hashing’ to create “surrogates”, that can augment original large data structures to yield faster typical data access.
One way to optimize system performance for power consumption is to provide a predictive control of system-level energy use. This dissertation creates a novel instruction-level cost model called the variable-n-gram model, which is closely related to N-Gram analysis commonly used in computational linguistics. This model does not require direct knowledge of complex architectural details, and is capable of determining performance relationships between instructions from an execution trace. Experimental measurements are used to derive a context-sensitive model for performance of each type of instruction in the context of an N-instruction sequence. Dynamic runtime power prediction mechanisms often suffer from high overhead costs. To reduce the overhead, this dissertation encodes the static instruction-level predictions into a data structure and uses compressive hashing to provide on-demand runtime access to those predictions. Genetic programming is used to evolve compressive hash functions and performance analysis of applications shows that, runtime access overhead can be reduced by a factor of ~3x-9x.
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Cheng, Diana I. "Magnetic assisted statistical assembly." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/45999.
Повний текст джерелаАнотація:
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>Includes bibliographical references (p. 87).<br>The objective of this thesis is to develop a process using magnetic forces to assemble micro-components into recesses on silicon based integrated circuits. Patterned SmCo magnetic thin films at the bottom of recesses are used to provide forces to orient, align and retain micro-devices on silicon. The overall objective is to obtain functionalities not readily available from silicon device structures alone. This thesis was done in the context of assembling optoelectronic devices, specifically integrating vertical cavity surface emitting lasers (VCSELs), edge-emitting lasers (EELs), and light emitting diodes(LEDs) onto commercially processed Si-CMOS circuits. This method, magnetically assisted statistical assembly (MASA), incorporates past methods such as Fluidic Assisted Self- Assembly (FASA) and Recess Mounting with Monolithic Metalization (RM3). Specifically, MASA addresses the main limitation to the FASA method by adding a magnetic layer as a restraint to keep assembled components correctly positioned in recesses until the time bonding may occur. Thus, all components may be permanently bonded into place simultaneously saving both time and money. This thesis will present simulations using Ansoft's Maxwell 3d providing general behavioral intuition for the behavior of a device over a target magnetic substrate. These results include using a rectangle instead of a circular disc and making recess depths greater than 2pm to overcome gravitational forces when inverting the substrate. Patterns of SmCo magnetic material, based on results from the simulations, included 50x100[mu]m recesses containing either a solid rectangle, thirty 5x10[mu]m rectangular pads, eighteen 5x10m rectangular pads or four 5x10m rectangular pads.<br>(cont.) Patterns of SmCo material also were experimented with using 50x50 [mu]m square recesses containing either a solid square or nine 5x5[mu]m square pads. Experiments with various rectangular patterns showed evidence that upside down devices do not retain as well as right side up devices. It was also seen that four 5xl0[mu]m rectangular pads did not have enough magnetic material to retain even right side up devices. Solid rectangular patterns were also determined to have too much magnetic material to align and orient the device without recesses. Once recesses were added to the experiments, the pattern with thirty 5x10m rectangles proved to assemble the most devices with an assembly ratio of 90%. However problems occurred with fabricating perfect device shapes and thus mis-shapened devices were counted in the assembly ratio. Results from experimenting with square patterns with recesses show a 88% assembly ratio with a solid square pattern. This may be due to the symmetry of the square devices and therefore has higher probability of assembly than that of the rectangular devices.<br>by Diana I. Cheng.<br>M.Eng.
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Park, Allen S. M. (Allen S. ). Massachusetts Institute of Technology. "Machine-vision assisted 3D printing." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/113162.
Повний текст джерелаАнотація:
Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 71-72).<br>I augmented a 3D printer with software for a 3D scanning system in order to incorporate feedback into the printing process. After calibration of the scanning system and the printer, the 3D scanning system is capable of taking depth maps of the printing platform. The two main extensions of 3D printing enabled by the 3D scanning system are printing on auxiliary objects and corrective printing. Printing on auxiliary objects is accomplished by scanning an auxiliary object, then positioning the printer to print directly onto the object. Corrective printing is using the scanner during the printing process to correct any errors mid-print.<br>by Allen Park.<br>M. Eng.
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Lee, Ann Ph D. Massachusetts Institute of Technology. "Language-independent methods for computer-assisted pronunciation training." Thesis, Massachusetts Institute of Technology, 2016. http://hdl.handle.net/1721.1/107338.
Повний текст джерелаАнотація:
Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 137-145).<br>Computer-assisted pronunciation training (CAPT) systems help students practice speaking foreign languages by providing automatic pronunciation assessment and corrective feedback. Automatic speech recognition (ASR) technology is a natural component in CAPT systems. Since a nonnative speaker's native language (Li) background affects their pronunciation patterns in a target language (L2), typically not only native but also nonnative training data of specific Ls is needed to train a recognizer for CAPT systems. Given that there are around 7,000 languages in the world, the data collection process is costly and has scalability issues. In addition, expert knowledge on the target L2 is also often needed to design a large feature set describing the deviation of nonnative speech from native speech. In contrast to machines, it is relatively easy for native listeners to detect pronunciation errors without being exposed to nonnative speech or trained with linguistic knowledge beforehand. In this thesis, we are interested in this unsupervised capability and propose methods to overcome the language-dependent challenges. Inspired by the success of unsupervised acoustic pattern discovery, we propose to discover an individual learner's pronunciation error patterns in an unsupervised manner by analyzing the acoustic similarity between speech segments from the learner. Experimental results on nonnative English and nonnative Mandarin Chinese spoken by students from different Ls show that the proposed method is Li-independent and can be portable to different L2s. Moreover, the method is personalized such that it accommodates variations in pronunciation patterns across students. In addition, motivated by the success of deep learning models in unsupervised feature learning, we explore the use of convolutional neural networks (CNNs) for mispronunciation detection. A language-independent data augmentation method is developed to take advantage of native speech as training samples. Experimental results on nonnative Mandarin Chinese speech show the effectiveness of the model and the method. Moreover, both qualitative and quantitative analyses on the convolutional filters reveal that the CNN automatically learns a set of human-interpretable high-level features.<br>by Ann Lee.<br>Ph. D.
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Cote, William Daniel. "A Web-based learning environment for textile engineering education." Thesis, Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/8499.
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Zehender, Nicholas (Nicholas G. ). "Network assisted file system consistency checking." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/77538.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 63-64).<br>This thesis reports on the design and implementation of Network Assisted NFSCK (or NAN), an extension to NFSCK, a research project about checking file system consistency at NetApp. NFSCK requires disk space to store temporary files, but sometimes insufficient disk space is available, and NFSCK cannot be used. NAN allows NFSCK to use an NFS server to store these temporary files. Tests were run to compare the total running time of NAN and NFSCK on various machines and data sets. Results showed that CPU was the limiting factor for NAN's performance. On machines with four CPUs, the running time of NAN was within 1% of the running time of NFSCK. On machines with two CPUs, running time was up to 6% worse with a large file data set, and up to 22% worse with a small file data set.<br>by Nicholas Zehender.<br>M.Eng.
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Sheldon, Daniel K. (Daniel Kenneth) 1974. "Computer assisted group decision making for education program development." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80120.
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Thesis (S.B. and M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1999.<br>Includes bibliographical references (leaves 48-49).<br>by Daniel K. Sheldon.<br>S.B.and M.Eng.
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Douglass, Margaret 1981. "Computer-assisted de-identification of free-text nursing notes." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33299.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.<br>Includes bibliographical references (leaves 67-70).<br>Medical researchers are legally required to protect patients' privacy by removing personally identifiable information from medical records before sharing the data with other researchers. Different computer-assisted methods are evaluated for removing and replacing protected health information (PHI) from free-text nursing notes collected in the hospital intensive care unit. A semi-automated method was developed to allow clinicians to highlight PHI on the screen of a tablet PC and to compare and combine the selections of different experts reading the same notes. Expert adjudication demonstrated that inter-human variability was high, with few false positives and many false negatives. A preliminary automated de-identification algorithm generated few false negatives but many false positives. A second automated algorithm was developed using the successful portions of the first algorithm and incorporating other heuristic methods to improve overall performance. A large de-identified collection of nursing notes was re-identified with realistic surrogate (but unprotected) dates, serial numbers, names, and phrases to form a "gold standard" reference database of over 2600 notes (approximately 340,000 words) with over 1800 labeled instances of PHI. This gold standard database of nursing notes and the Java source code used to evaluate algorithm performance will be made freely available on the Physionet web site in order to facilitate the development and validation of future de-identification algorithms.<br>by Margaret Douglass.<br>M.Eng.
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Curlette, Christina M. "Artificial intelligence-assisted data analysis with BayesDB." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/119517.
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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 67-68).<br>When applying machine learning and statistics techniques to real-world datasets, problems often arise due to missing data or errors from black-box predictive models that are difficult to understand or explain in terms of the model's inputs. This thesis explores the applicability of BayesDB, a probabilistic programming platform for data analysis, to three common problems in data analysis: (i) modeling patterns of missing data, (ii) imputing missing values in datasets, and (iii) characterizing the error behavior of predictive models. Experiments show that CrossCat, the default model discovery mechanism used by BayesDB, can address all three problems effectively. Examples are drawn from the American National Election Studies and the Gapminder database of global macroeconomic and public health indicators.<br>by Christina M. Curlette.<br>M. Eng.
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Jain, Prabhat. "Software-assisted cache mechanisms for embedded systems." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/42906.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2008.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Includes bibliographical references (leaves 120-135).<br>Embedded systems are increasingly using on-chip caches as part of their on-chip memory system. This thesis presents cache mechanisms to improve cache performance and provide opportunities to improve data availability that can lead to more predictable cache performance. The first cache mechanism presented is an intelligent cache replacement policy that utilizes information about dead data and data that is very frequently used. This mechanism is analyzed theoretically to show that the number of misses using intelligent cache replacement is guaranteed to be no more than the number of misses using traditional LRU replacement. Hardware and software-assisted mechanisms to implement intelligent cache replacement are presented and evaluated. The second cache mechanism presented is that of cache partitioning which exploits disjoint access sequences that do not overlap in the memory space. A theoretical result is proven that shows that modifying an access sequence into a concatenation of disjoint access sequences is guaranteed to improve the cache hit rate. Partitioning mechanisms inspired by the concept of disjoint sequences are designed and evaluated. A profit-based analysis, annotation, and simulation framework has been implemented to evaluate the cache mechanisms. This framework takes a compiled benchmark program and a set of program inputs and evaluates various cache mechanisms to provide a range of possible performance improvement scenarios. The proposed cache mechanisms have been evaluated using this framework by measuring cache miss rates and Instructions Per Clock (IPC) information. The results show that the proposed cache mechanisms show promise in improving cache performance and predictability with a modest increase in silicon area.<br>by Prabhat Jain.<br>Ph.D.
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El, Kordy Omar Mohamed. "The application of multimedia and knowledge based systems to computer aided engineering instruction." Thesis, Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/21415.
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Boyd, Martin C. "A distributed engineering problem generator." Thesis, Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/21288.
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Farrow, Sherry Lynn. "An implicit engineering student model for an intelligent tutoring system." Thesis, Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/21444.
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Srisethanil, Chaisak. "Pedagogical framework for an engineering intelligent tutoring system." Diss., Georgia Institute of Technology, 1996. http://hdl.handle.net/1853/20240.
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Larsen, Samuel (Samuel Barton) 1975. "Compilation techniques for short-vector instructions." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37890.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 127-133).<br>Multimedia extensions are nearly ubiquitous in today's general-purpose processors. These extensions consist primarily of a set of short-vector instructions that apply the same opcode to a vector of operands. This design introduces a data-parallel component to processors that exploit instruction-level parallelism, and presents an opportunity for increased performance. In fact, ignoring a processor's vector opcodes can leave a significant portion of the available resources unused. In order for software developers to find short-vector instructions generally useful, the compiler must target these extensions with complete transparency and consistent performance. This thesis develops compiler techniques to target short-vector instructions automatically and efficiently. One important aspect of compilation is the effective management of memory alignment. As with scalar loads and stores, vector references are typically more efficient when accessing aligned regions. In many cases, the compiler can glean no alignment information and must emit conservative code sequences. In response, I introduce a range of compiler techniques for detecting and enforcing aligned references. In my benchmark suite, the most practical method ensures alignment for roughly 75% of dynamic memory references.<br>(cont.) This thesis also introduces selective vectorization, a technique for balancing computation across a processor's scalar and vector resources. Current approaches for targeting short-vector instructions directly adopt vectorizing technology first developed for supercomputers. Traditional vectorization, however, can lead to a performance degradation since it fails to account for a processor's scalar execution resources. I formulate selective vectorization in the context of software pipelining. My approach creates software pipelines with shorter initiation intervals, and therefore, higher performance. In contrast to conventional methods, selective vectorization operates on a low-level intermediate representation. This technique allows the algorithm to accurately measure the performance trade-offs of code selection alternatives. A key aspect of selective vectorization is its ability to manage communication of operands between vector and scalar instructions. Even when operand transfer is expensive, the technique is sufficiently sophisticated to achieve significant performance gains. I evaluate selective vectorization on a set of SPEC FP benchmarks. On a realistic VLIW processor model, the approach achieves whole-program speedups of up to 1.35x over existing approaches. For individual loops, it provides speedups of up to 1.75x.<br>by Samuel Larsen.<br>Ph.D.
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Hayden, David S. (David Scott). "Wearable-assisted social interaction as assistive technology for the blind." Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/91089.
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Thesis: S.M. in Computer Science and Engineering, Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.<br>41<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 73-76).<br>This work presents an end-to-end wearable system designed to learn and assist its (potentially blind) wearers with daily social interactions. In particular, it visually identifies nearby acquaintances and provides timely, discreet notifications of their presence to the wearer. Offline, the system learns the people with whom the wearer interacts by automatically detecting social interactions through egocentric audio, video and accelerometer data and querying the wearer for the identities of persons unknown to the system.<br>by David S. Hayden.<br>S.M. in Computer Science and Engineering
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Dong, Zhaoqing Sabrina 1977. "Hardware-assisted timer protocol for high resolution global time synchronization." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86639.
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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.<br>Includes bibliographical references (leaf 114).<br>by Zhaoqing Sabrina Dong.<br>M.Eng.
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Seitz, Jeffrey L. "An interactive CD-ROM to teach harmonic and intermodulation distortion." Virtual Press, 1997. http://liblink.bsu.edu/uhtbin/catkey/1048367.
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This study had two purposes: first, to collect information relating to harmonic and intermodulation distortion from several sources into one comprehensive report and second, to describe and develop an interactive CD-ROM as a new method of learning harmonic and intermodulation distortion. The CD-ROM allows students to interact and control the percentage amount of harmonic and intermodulation distortion in order to "calibrate" their ears. In addition, the practical testing environment changes on a random basis to continually challenge the users. These situations allow students to interact at their own speed and therefore customize their learning development.<br>School of Music
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Bohorquez, Jose L. "Digitally-assisted, ultra-low power circuits and systems for medical applications." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58074.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 219-225).<br>In recent years, trends in the medical industry have created a growing demand for a variety of implantable medical devices. At the same time, advances in integrated circuits techniques, particularly in CMOS, have opened possibilities for advanced implantable systems that are very small and consume minimal energy. Minimizing the volume of medical implants is important as it allows for less invasive procedures and greater comfort to patients. Minimizing energy consumption is imperative as batteries must last at least a decade without replacement. Two primary functions that consume energy in medical implants are sensor interfaces that collect information from biomedical signals, and radios that allow the implant to communicate with a base-station outside of the body. The general focus of this work was the development of circuits and systems that minimize the size and energy required to carry out these two functions. The first part of this work focuses on laying down the theoretical framework for an ultra-low power radio, including advances to the literature in the area of super-regeneration. The second part includes the design of a transceiver optimized for medical implants, and its implementation in a CMOS process. The final part describes the design of a sensor interface that leverages novel analog and digital techniques to reduce the system's size and improve its functionality. This final part was developed in conjunction with Marcus Yip.<br>by Jose L. Bohorquez.<br>Ph.D.
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Singley, Bradford G. "Computer-Based Instruction for Engineering Education in the Developing World." Diss., CLICK HERE for online access, 2007. http://contentdm.lib.byu.edu/ETD/image/etd2090.pdf.
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Zhang, Yun. "High Quality ZnO Epitaxial Grown By Plasma Assisted Molecular Beam Epitaxy." VCU Scholars Compass, 2004. http://scholarscompass.vcu.edu/etd/883.
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Described in this thesis are the growth and characterization of high quality ZnO epitaxy layers.Zinc oxide (ZnO) epitaxy layers were grown on sapphire and epi-GaN substrates respectively, using plasma assisted molecular beam epitaxy (MBE) . Various growth conditions, such as growth temperature, II/VI ratio, and buffer layers, were employed to optimize the quality of the ZnO film. The subsequent characterization of the films was carried out to evaluate the surface, optical and crystalline properties of the film, using AFM, SEM, PL and XRD techniques. It was found out that the high quality of the ZnO film was grown on epi-GaN substrates under the Low temperature of ~ 300 degrees C, flash annealing up to ~680 degrees C, followed by high temperature growth at ~600 degrees C.
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He, Lei. "III-nitride Semiconductors Grown By Plasma Assisted Molecular Beam Epitaxy." VCU Scholars Compass, 2004. http://scholarscompass.vcu.edu/etd/1019.
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III-nitride semiconductors are of great interest owing to their commercial and military applications due to their optoelectronic and mechanical properties. They have been synthesized successfully by many growth methods. Among them, molecular beam epitaxy (MBE) is a promising epitaxial growth method owing to precise control of growth parameters, which significantly affect the film properties, composition, and thickness. However, the understanding of growth mechanism of III-nitride materials grown in this growth regime is far from being complete.In this dissertation, GaN and AIGaN growth mechanism under metal-rich conditions were investigated. The Ga surface desorption behavior during the growth was investigated systematically using reflection high-energy electron diffraction (RHEED). It was found that desorption of Ga atoms from the (0001) GaN surfaces under different III-V ratios deviates from the zeroth-order kinetics in that the desorption rate is independent of the coverage of adsorbed atoms. The desorption energies of Ga are determined to be 2.76 eV with the Ga coverage closing to 100%, 1.89 eV for a ~45% coverage, and 0.82 eV for a 10% coverage, as monitored by the change of the RHEED specular beam intensity during growth. In addition, the GaN surface morphology under different III-V ratios on porous templates matches the dependence of Ga desorption energy on the metal coverage, and III/V ratio dominates the growth mode. In a related AIGaN growth mechanism study, a competition between A1 and Ga atoms to incorporate into the film was found under metal-rich conditions. Employing this mechanism, A1xGa1-xN layers with precisely controlled A1 mole fraction, x in the range 0xxGa1-xN films was determined to be about 1 eV. The A1xGa1-xN layers grown under metal-rich conditions, as compared to that under N-rich conditions, have a better structural and optical quality. Employing A1xGa1-xN layers grown under metal-rich conditions, a lateral geometry GaN/A1GaN MQW-based photodetector was fabricated. It exhibited a flat and narrow spectral response in the range of 297~352 nm in the backillumination configuration.
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Perkins, James Michael 1978. "Magnetically assisted statistical assembly of III-V heterostructures on silicon : initial process and technology development." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/32712.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.<br>Includes bibliographical references (leaf 75).<br>This work is the initial investigation of magnetically assisted statistical assembly (MASA), a novel silicon I-v integration technique developed at M.I.T. Initially procedures for processing optoelectronic devices into magnetically sensitive 40 micron discs were performed and refined. Cobalt palladium thin films were obtained and their magnetic properties were studied. An initial procedure was developed to easily integrate these patterned, magnetized films with 60-micron diameter, 5-micron deep recesses. Pill devices were then integrated into these magnetically attractive recesses. The studied showed optoelectronic pills with magnetic layers could be successfully produced and collected. Assembly using these pills was performed and showed improved recess filling yields over the non-magnetic assembly, though more investigation needs to be done. MASA was shown to offer promise as a viable and promising technique for mixed device integration.<br>by James Michael Perkins.<br>S.M.
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Rumpler, Joseph John 1976. "Optoelectronic integration using the magnetically assisted statistical assembly technique : initial magnetic characterization and process development." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/32714.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.<br>Includes bibliographical references (p. 99-101).<br>The commercial integration of optoelectronic devices heavily relies on hybrid techniques such as wire bonding and flip-chip bonding. These methods are limited in the scale and flexibility in integration. Research focused on optoelectronic integration is performed using numerous techniques such as direct epitaxy, full-scale wafer bonding, and self-assembly. Magnetically Assisted Statistical Assembly (MASA) is an example of the latter technique and improves scale and flexibility by enabling the simultaneous integration of large numbers of individual devices. This thesis work is focused on the demonstration of the MASA concept through characterization of the magnetic materials forming the foundation for this technique and development of an adequate process technology. Both, the magnetic characteristics and the process technology required to integrate the technology are presented along with results of the integration.<br>by Joseph John Rumpler, II.<br>S.M.
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Leeds, Daniel Demeny. "Assisted auscultation : creation and visualization of high dimensional feature spaces for the detection of mitral regurgitation." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36806.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, June 2006.<br>"May 2006."<br>Includes bibliographical references (p. 83-84).<br>Cardiac auscultation, listening to the heart using a stethoscope, often constitutes the first step in detection of common heart problems. Unfortunately, primary care physicians, who perform this initial screening, often lack the experience to correctly evaluate what they hear. False referrals are frequent, costing hundreds of dollars and hours of time for many patients. We report on a system we have built to aid medical practitioners in diagnosing Mitral Regurgitation (MR) based on heart sounds. Our work builds on the "prototypical beat" introduced by Syed in [17] to extract two different feature sets characterizing systolic acoustic activity. One feature set is derived from current medical knowledge. The other is based on unsupervised learning of systolic shapes, using component Analysis. Our system employs self-organizing maps (SOMs) to depict the distribution of patients in each feature space as labels within a two-dimensional colored grid. A user screens new patients by viewing their projections onto the SOM, and determining whether they are closer in space, and thus more similar, to patients with or without MR. We evaluated our system on 46 patients. Using a combination of the two feature sets, SOM-based diagnosis classified patients with accuracy similar to that of a cardiologist.<br>by Daniel Demeny Leeds.<br>M.Eng.
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Porter, Brandon W. (Brandon William) 1974. "Educational fusion : an instructional, web-based, software development platform." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/50393.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; and, Thesis (B.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.<br>Includes bibliographical references (p. 96-98).<br>by Brandon W. Porter.<br>B.S.<br>M.Eng.
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Eng, Tony Liang. "De novo peptide sequencing from matrix-assisted laser desorption/ionization-time of flight post-source-decay spectra." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86584.
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Chang, Angela N. (Angela Ni-Hwey). "A mobile instructor interface for collaborative software development education." Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/76910.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 77-78).<br>Students are often asked to write code during lab sessions in software engineering courses. However, the overall progress and level of understanding of lecture material during the course of a single lab session is difficult for instructors to gauge, because they are limited in the amount of direct interaction they can have with students. We have built CollabodeTA, a web application optimized for Apple's iPad on top of the Collabode real-time collaborative web IDE. CollabodeTA is a tool that takes advantage of keystroke-by-keystroke and action-by- action data intercepted through Collabode to aid software lab instructors in determining student progress and understanding on in-class coding assignments. User studies using TAs from MIT's 6.005 Elements of Software Construction course and data recorded from a semester of 6.005 recitations with in-class coding assignments indicate that the mobile instructor interface shows potential as a useful tool for guiding the pace and content of such recitations based on demonstrated student understanding. Furthermore, the CollabodeTA mobile instructor interface illustrates a new use case for the Collabode real-time collaborative web IDE.<br>by Angela N. Chang.<br>M.Eng.
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Thompson, Hunter Gordon II. "The requirements and feasibility of using intelligent tutoring systems for instruction : a study concerning the undergraduate course, reinforced concrete." Thesis, Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/19285.
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