Дисертації з теми "Electric circuit analogie"
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Spinks, Stephen James. "Fault simulation for structural testing of analogue integrated circuits." Thesis, University of Hull, 1998. http://hydra.hull.ac.uk/resources/hull:8047.
Повний текст джерелаLong, David Ian. "Behavioural simulation of mixed analogue/digital circuits." Thesis, Bournemouth University, 1996. http://eprints.bournemouth.ac.uk/278/.
Повний текст джерелаKuznetsov, Eugene. "Trust in analog : analog circuit techniques for reducing the risk of malicious circuits and software." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66431.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (p. 47).
Malicious circuits and software present a significant security risk, especially in control applications. This work is concerned with increasing the trustworthiness of control circuitry by reducing its complexity. The security benefits of substituting analog control techniques in place of digital control are analyzed, and both discrete and integrated circuit designs are demonstrated.
by Eugene Kuznetsov.
M.Eng.
Shana'a, Osama K. "Circuit Implementation of a High-speed Continuous-time Current-mode Field Programmable Analog Array (FPAA)." PDXScholar, 1996. https://pdxscholar.library.pdx.edu/open_access_etds/5103.
Повний текст джерелаCuell, Charles L. "An electric circuit analogue of a nonholonomically constrained Hamiltonian system." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape9/PQDD_0016/MQ47995.pdf.
Повний текст джерелаBhattacharya, Sambuddha. "Template-driven parasitic-aware optimization of analog/RF IC layouts /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6121.
Повний текст джерелаCakir, Sinan. "Tolerance Based Reliability Of An Analog Electric Circuit." Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12612929/index.pdf.
Повний текст джерелаWorst Case Circuit Tolerance Analysis&rdquo
(WCCTA) and &ldquo
Failure Modes and Effects Analysis&rdquo
(FMEA). WCCTA involves the analysis of the circuit operation under varying parameters in their tolerance bands. These parameters include the resistances of the resistors, operating temperature and voltage input value. The operation of FPDC is checked and the most critical parameters are determined in the worst case conditions. While performing WCCTA, a method that guarantees the exact worst case conditions is used rather than probabilistic methods like Monte Carlo analysis. The results showed that the parameter variations do not affect the circuit operation unfavorably
operating temperature, voltage input variation and tolerance bands for the resistances are fairly compatible with the circuit operation. FMEA is implemented according to the short circuit and open circuit failures of all the electronic components used in FPDC. The components whose failure has catastrophic effect on the circuit operation have been determined and some preventive actions have been offered for some catastrophic failures.
Hong, Seong-Kwan. "Performance driven analog layout compiler." Diss., Georgia Institute of Technology, 1994. http://hdl.handle.net/1853/15037.
Повний текст джерелаLui, Siu-hong. "Analog circuit design by nonconvex polynomial optimization two design examples /." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39557418.
Повний текст джерелаYoon, Heebyung. "Fault detection and identification techniques for embedded analog circuits." Diss., Georgia Institute of Technology, 1998. http://hdl.handle.net/1853/13041.
Повний текст джерелаSheehan, Kevin Michael. "Evolving analogue electronic signal processing circuit behaviour in hardware." Thesis, Royal Holloway, University of London, 2002. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.272073.
Повний текст джерелаCheung, Wing-tai. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.
Повний текст джерелаParish, Simon James. "Behavioural synthesis of analogue integrated circuits." Thesis, University of Birmingham, 2010. http://etheses.bham.ac.uk//id/eprint/549/.
Повний текст джерелаEberhardt, Friedemann. "Symbolic tolerance and sensitivity analysis of large scale electronic circuits." Thesis, University of Bath, 1999. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301578.
Повний текст джерелаLui, Siu-hong, and 呂小康. "Analog circuit design by nonconvex polynomial optimization: two design examples." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39557418.
Повний текст джерелаMitros, Piotr 1979. "A framework for analog circuit optimization." Thesis, Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/28447.
Повний текст джерелаIncludes bibliographical references (p. 49-50).
This thesis presents a system for optimization of analog circuit topologies and component values. The topology is optimized using simulated annealing, while the component values are optimized using gradient descent. Local minima are avoided and constraints are kept through the use of coordinate transformations, as well as the use of default starting points for component values. The system is targeted for use in 3D integrated circuit design. The architecture is extendable, and is designed to eventually include capabilities for automated layout and mixed-signal design.
by Piotr Mitros.
M.Eng.
Feng, Hong. "Impact of atomistic device variability on analogue circuit design." Thesis, University of Glasgow, 2011. http://theses.gla.ac.uk/3074/.
Повний текст джерелаChakrabarti, Sudip. "Test generation for fault isolation in analog and mixed-mode circuits." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14899.
Повний текст джерела張永泰 and Wing-tai Cheung. "Geometric programming and signal flow graph assisted design of interconnect and analog circuits." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
Повний текст джерелаSabzavari, Abbas Mostafavi. "Fault simulation and diagnosis in analog electronic systems." Thesis, University of Exeter, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.328233.
Повний текст джерелаSimayi, Ayanda Njongi. "The use of contextually appropriate analogies to teach direct current electric circuit concepts to isiXhosa speaking learners." Thesis, Nelson Mandela Metropolitan University, 2014. http://hdl.handle.net/10948/d1016161.
Повний текст джерелаHai, Ling. "Modelling Wave Power by Equivalent Circuit Theory." Doctoral thesis, Uppsala universitet, Elektricitetslära, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-265270.
Повний текст джерелаAbel, Jerian. "Students' conceptual modeling of simple DC electric circuits during computer-based instruction." Diss., This resource online, 1995. http://scholar.lib.vt.edu/theses/available/etd-06062008-170004/.
Повний текст джерелаChoi, Pyung. "An equivalent circuit structure macromodel for analog phase locked loops." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/14875.
Повний текст джерелаBesnard, SteÌphane Claude Louis. "Optimising fault modelling and test development for VLSI analogue circuits." Thesis, University of Huddersfield, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.288503.
Повний текст джерелаOdame, Kofi. "Exploiting device nonlinearity in analog circuit design." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/29751.
Повний текст джерелаCommittee Chair: Hasler, Paul; Committee Member: Anderson, David; Committee Member: Butera, Robert; Committee Member: Minch, Bradley; Committee Member: Taylor, David. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Liu, Dong. "Analog and mixed-signal test and fault diagnosis." Ohio : Ohio University, 2003. http://www.ohiolink.edu/etd/view.cgi?ohiou1177701780.
Повний текст джерелаVALLICELLI, ELIA ARTURO. "Design of Mixed-Signal Electronic Instrumentation for Proton Sound Detectors." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2021. http://hdl.handle.net/10281/301978.
Повний текст джерелаAcoustic proton range experimental verification technique (iono-acoustics) is based on sensing the weak thermoacoustic signal emitted by the fast energy deposition (and/or the heating process) at the end of the beam range (Bragg Peak). In this context, this thesis presents the main characteristics of the micro-electronics instrumentation used for proton sound detectors introducing specific design techniques strongly oriented to both maximization of the acoustic Signal-to-Noise-Ratio (at the Acoustic Sensor level) and Noise-Figure minimization (at analog amplifier level). The first part of this thesis addresses all the instrumentation challenges related to iono-acoustic experiments providing specific technical details regarding both acoustic sensor design (i.e. how to build the sensor while maximizing the SNR) and the LNA design. The experimental results of a first experiment carried out at Maier-Leibniz Laboratory in Garching, Munich, with a proton beam at 20 MeV (sub-clinical energy) will be presented and it will be shown how a dedicated mixed-signal electronics design allows to significantly improve the signal-to-noise ratio and the accuracy of the BP localization by 6 dB. In this context, this first detector development achieves two important objectives: the improvement of the acoustic SNR and a strong simplification of the detector instrumentation w.r.t. state-of-the-art, enabling increasing accuracy of the acoustic pulse measurement, and at the same time the portability and compactness of the device. In clinical hadron-therapy applications, variable beam energy (from 65 MeV up to 200 MeV) and variable doses are used as a function of the selected medical treatment. This induces different acoustic pulses amplitude and bandwidth, forcing advanced technological solutions capable of handling a wide spectrum of signals in terms of bandwidth, amplitude, and noise. For this reason, the second part of this thesis proposes an efficient and innovative Matlab Model of the ionoacoustic physical phenomenon, based on englobing in a single mathematical Linear-Time-Invariant-System all energy conversion processes involved in iono-acoustics. The proposed ionoacoustics model replaces classical and complex simulation tools (used to characterize the proton induced acoustic signal) and facilitates the development of dedicated detectors. Finally, the design of a second version of the Proton Sound Detector will be presented that introduces the concept of space-domain averaging (instead of time-domain averaging based on multiple beam shot processing for noise attenuation and thus extra-doses). This detector uses a multi-channel sensor to perform a spatial average of the acquired signals and increase the SNR by 18 dB at the same dose compared to the classic single channel approach. This approach however requires the development of highly miniaturized electronics that cannot be implemented with off-the-shelf components on Printed Circuit Boards. The design and characterization of a multichannel analog front-end implemented on a CMOS 28 nm Application-Specified-Integrated-Circuit (ASIC) which allows to process the 64 channels of the acoustic sensor in parallel is then presented. This High-Resolution Proton Sound Detector (HR-ProSD) is completed by digital circuits implemented on Field Programmable Gate Array (FPGA) that allow to locate in real time the deposition of energy in space.
Yoo, Seoung-Jae. "Design of analog baseband circuits for wireless communication receivers." Columbus, Ohio Ohio State University, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1073617255.
Повний текст джерелаTitle from first page of PDF file. Document formatted into pages; contains xvi, 167 p.; also includes graphics (some col.). Includes abstract and vita. Advisor: Mohammed Ismail ElNaggar, Dept. of Electrical Engineering. Includes bibliographical references (p. 163-167).
Md, Ali Sawal Hamid. "System level performance and yield optimisation for analogue integrated circuits." Thesis, University of Southampton, 2009. https://eprints.soton.ac.uk/69724/.
Повний текст джерелаAggarwal, Varun. "Analog circuit optimization using evolutionary algorithms and convex optimization." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40525.
Повний текст джерелаIncludes bibliographical references (p. 83-88).
In this thesis, we analyze state-of-art techniques for analog circuit sizing and compare them on various metrics. We ascertain that a methodology which improves the accuracy of sizing without increasing the run time or the designer effort is a contribution. We argue that the accuracy of geometric programming can be improved without adversely influencing the run time or increasing the designer's effort. This is facilitated by decomposition of geometric programming modeling into two steps, which decouples accuracy of models and run-time of geometric programming. We design a new algorithm for producing accurate posynomial models for MOS transistor parameters, which is the first step of the decomposition. The new algorithm can generate posynomial models with variable number of terms and real-valued exponents. The algorithm is a hybrid of a genetic algorithm and a convex optimization technique. We study the performance of the algorithm on artificially created benchmark problems. We show that the accuracy of posynomial models of MOS parameters is improved by a considerable amount by using the new algorithm. The new posynomial modeling algorithm can be used in any application of geometric programming and is not limited to MOS parameter modeling. In the last chapter, we discuss various ideas to improve the state-of-art in circuit sizing.
by Varun Aggarwal.
S.M.
Mitros, Piotr 1979. "Constraint satisfaction modules : a methodology for analog circuit design." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42237.
Повний текст джерелаIncludes bibliographical references (p. 119-122).
This dissertation describes a methodology for solving convex constraint problems using analog circuits. It demonstrates how this methodology can be used to design circuits that solve function-fitting problems through iterated gradient descent. In particular, it shows how to build a small circuit that can model a nonlinearity by observation, and predistort to compensate for this nonlinearity. The system fits into a broader effort to investigate non-traditional approaches to circuit design. First, it breaks the traditional input-output abstraction barrier; all ports are bidirectional. Second, it uses a different methodology for proving system stability with local rather than global properties. Such stability arguments can be scaled to much more complex systems than traditional stability criteria.
by Piotr Mitros.
Ph.D.
Li, Harry W. "A noniterative DC analysis program for analog integrated circuits." Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/15977.
Повний текст джерелаHe, Lizhong. "1-Ghz CMOS Analog Signal Squaring Circuit." Wright State University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=wright1472476550.
Повний текст джерелаTavakoli, Dastjerdi Maziar 1976. "Analog VLSI circuits for inertial sensory systems." Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86766.
Повний текст джерелаIncludes bibliographical references (leaves 67-68).
by Maziar Tavakoli Dastjerdi.
S.M.
Knight, Clinton D. "WWW-based testing of analog circuits." Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/14863.
Повний текст джерелаA'Ain, Abu Khari Bin. "Power supply voltage control testing technique as a novel electrical test strategy for analogue integrated circuits." Thesis, Lancaster University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.337370.
Повний текст джерелаVichik, Sergey. "Quadratic and linear optimization with analog circuits." Thesis, University of California, Berkeley, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10086165.
Повний текст джерелаIn this work we propose and investigate a new method of solving quadratic and linear optimization problems using analog electrical circuits instead of digital computation.
We present the design of an analog circuit which solves Quadratic Programming (QP) or Linear Programming (LP) problems. In particular, the steady-state circuit voltages are the components of the QP (LP) optimal solution. The thesis shows how to construct the circuit and provides a proof of equivalence between the circuit and the QP (LP) problem.
We study the stability of the analog optimization circuit. The circuit dynamics are modeled as a switched affine system. A piece-wise quadratic Lyapunov function and the KYP lemma are used to derive the stability criterion. The stability criterion characterizes the range of critical circuit parameters for which the QP circuit is globally asymptotically stable.
The proposed method is used to build a printed circuit board (PCB) using programmable components to allow solution of various QP problems. The board supports implementation of an MPC controller for buck DC-DC converter. We conduct an experimental study to evaluate the performance of the analog optimization circuit.
We study the feasibility of very high speed implementation of the optimization circuit using Analog Very Large Scale Integration (AVLSI) technology. In AVLSI, all the required circuit components are built on top of a silicon substrate using advanced photo-lithographic technologies. AVLSI circuits are fast, small and cheap. Thus, AVLSI implementation is paramount to make the proposed technology commercially competitive.
We discuss the possible usage of the proposed method to make fast MPC controllers, image processors, communication decoders and analog co-processors. In fact, any application that requires a repeating solution of related optimization problems can benefit from this technology. Besides being faster than the digital computers, analog computers are more power efficient, may occupy smaller area on silicon and may be more resilient in harsh environments.
Pous, i. Sabadí Carles. "Case based reasoning as an extension of fault dictionary methods for linear electronic analog circuits diagnosis." Doctoral thesis, Universitat de Girona, 2004. http://hdl.handle.net/10803/7728.
Повний текст джерелаDurant aquests últims anys, les tècniques d'Intel·ligència Artificial han esdevingut un dels camps de recerca més importants per a la diagnosi de falles. Aquesta tesi desenvolupa dues d'aquestes tècniques per tal de cobrir algunes de les mancances que presenten els diccionaris de falles. La primera proposta es basa en construir un sistema fuzzy com a eina per identificar. Els resultats obtinguts son força bons, ja que s'aconsegueix localitzar la falla en un elevat tant percent dels casos. Per altra banda, el percentatge d'encerts no és prou bo quan a més a més s'intenta esbrinar la desviació.
Com que els diccionaris de falles es poden veure com una aproximació simplificada al Raonament Basat en Casos (CBR), la segona proposta fa una extensió dels diccionaris de falles cap a un sistema CBR. El propòsit no és donar una solució general del problema sinó contribuir amb una nova metodologia. Aquesta consisteix en millorar la diagnosis dels diccionaris de falles mitjançant l'addició i l'adaptació dels nous casos per tal d'esdevenir un sistema de Raonament Basat en Casos. Es descriu l'estructura de la base de casos així com les tasques d'extracció, de reutilització, de revisió i de retenció, fent èmfasi al procés d'aprenentatge.
En el transcurs del text s'utilitzen diversos circuits per mostrar exemples dels mètodes de test descrits, però en particular el filtre biquadràtic és l'utilitzat per provar les metodologies plantejades, ja que és un dels benchmarks proposats en el context dels circuits analògics. Les falles considerades son paramètriques, permanents, independents i simples, encara que la metodologia pot ser fàcilment extrapolable per a la diagnosi de falles múltiples i catastròfiques. El mètode es centra en el test dels components passius, encara que també es podria extendre per a falles en els actius.
Testing circuits is a stage of the production process that is becoming more and more important when a new product is developed. Test and diagnosis techniques for digital circuits have been successfully developed and automated. But, this is not yet the case for analog circuits. Even though there are plenty of methods proposed for diagnosing analog electronic circuits, the most popular are the fault dictionary techniques. In this thesis some of these methods, showing their advantages and drawbacks, are analyzed.
During these last decades automating fault diagnosis using Artificial Intelligence techniques has become an important research field. This thesis develops two of these techniques in order to fill in some gaps in fault dictionaries techniques. The first proposal is to build a fuzzy system as an identification tool. The results obtained are quite good, since the faulty component is located in a high percentage of the given cases. On the other hand, the percentage of successes when determining the component's exact deviation is far from being good.
As fault dictionaries can be seen as a simplified approach to Case-Based Reasoning, the second proposal extends the fault dictionary towards a Case Based Reasoning system. The purpose is
not to give a general solution, but to contribute with a new methodology. This second proposal improves a fault dictionary diagnosis by means of adding and adapting new cases to develop a
Case Based Reasoning system. The case base memory, retrieval, reuse, revise and retain tasks are described. Special attention to the learning process is taken.
Several circuits are used to show examples of the test methods described throughout the text. But, in particular, the biquadratic filter is used to test the proposed methodology because it is
defined as one of the benchmarks in the analog electronic diagnosis domain. The faults considered are parametric, permanent, independent and simple, although the methodology can be extrapolated to catastrophic and multiple fault diagnosis. The method is only focused and tested on passive faulty components, but it can be extended to cover active devices as well.
Le, Huy X. P. "Characterization of hot-carrier reliability in analog sub-circuit design." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/41379.
Повний текст джерелаIncludes bibliographical references (leaves 52-54).
by Huy X.P. Le.
M.Eng.
Monzon, Joshua Jen C. "Analog VLSI circuit design of spike-timing-dependent synaptic plasticity." Thesis, Massachusetts Institute of Technology, 2008. http://hdl.handle.net/1721.1/54636.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (p. 61-63).
Synaptic plasticity is the ability of a synaptic connection to change in strength and is believed to be the basis for learning and memory. Currently, two types of synaptic plasticity exist. First is the spike-timing-dependent-plasticity (STDP), a timing-based protocol that suggests that the efficacy of synaptic connections is modulated by the relative timing between presynaptic and postsynaptic stimuli. The second type is the Bienenstock-Cooper-Munro (BCM) learning rule, a classical ratebased protocol which states that the rate of presynaptic stimulation modulates the synaptic strength. Several theoretical models were developed to explain the two forms of plasticity but none of these models came close in identifying the biophysical mechanism of plasticity. Other studies focused instead on developing neuromorphic systems of synaptic plasticity. These systems used simple curve fitting methods that were able to reproduce some types of STDP but still failed to shed light on the biophysical basis of STDP. Furthermore, none of these neuromorphic systems were able to reproduce the various forms of STDP and relate them to the BCM rule. However, a recent discovery resulted in a new unified model that explains the general biophysical process governing synaptic plasticity using fundamental ideas regarding the biochemical reactions and kinetics within the synapse. This brilliant model considers all types of STDP and relates them to the BCM rule, giving us a fresh new approach to construct a unique system that overcomes all the challenges that existing neuromorphic systems faced. Here, we propose a novel analog verylarge- scale-integration (aVLSI) circuit that successfully and accurately captures the whole picture of synaptic plasticity based from the results of this latest unified model. Our circuit was tested for all types of STDP and for each of these tests, our design was able to reproduce the results predicted by the new-found model. Two inputs are required by the system, a glutamate signal that carries information about the presynaptic stimuli and a dendritic action potential signal that contains information about the postsynaptic stimuli. These two inputs give rise to changes in the excitatory postsynaptic current which represents the modifiable synaptic efficacy output. Finally, we also present several techniques and alternative circuit designs that will further improve the performance of our neuromorphic system.
by Joshua Jen C. Monzon.
M.Eng.
Aluru, Gunasekhar. "Exploring Analog and Digital Design Using the Open-Source Electric VLSI Design System." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849770/.
Повний текст джерелаPradhan, Almitra. "Accurate Analog Synthesis Based On Circuit Matrix Models." University of Cincinnati / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1258661691.
Повний текст джерелаBagheri, Rajeoni Alireza. "ANALOG CIRCUIT SIZING USING MACHINE LEARNING BASED TRANSISTORCIRCUIT MODEL." University of Akron / OhioLINK, 2021. http://rave.ohiolink.edu/etdc/view?acc_num=akron1609428170125214.
Повний текст джерелаKillens, Jacob. "Utilizing standard CMOS process floating gate devices for analog design." Master's thesis, Mississippi State : Mississippi State University, 2001. http://library.msstate.edu/etd/show.asp?etd=etd-04092001-110957.
Повний текст джерелаROTA, LUCIANO. "Implementation and Validation Methods for Electronic Integrated Circuits and Devices." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2023. https://hdl.handle.net/10281/404776.
Повний текст джерелаIn the last three decades Mobile Telecommunication (TLC) electronics has undergone a great improvement, this limited branch of electronics proved to be one of the major driving motor in the development of the new Complementary Metal-Oxide-Semiconductor (CMOS) technologies. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. This situation has become extremely favorable for the development of high performance digital devices which are able to reach speed and memory capability previously unbelievable. Also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital integrated circuits (ICs). First task of this thesis work was the implementation and measurement of different integrated circuits in two deep sub-micron technology nodes as 28nm bulk-CMOS and 16nm FinFET (Fin Field Effect Transistor). In particular the second one of these introduces novelty about the structure of transistor used to implement the circuits. Each circuit created faces various difficulties due to the particular behaviour of such advanced technologies, in particular in terms of low intrinsic gain and limited signal swing as consequence of low supply voltage. I worked in FinFET16 project with the main task to realize and validate the layout of a 4^th Order Fully-Differential Super-Source-Follower Analog Filter. After measurements the filter achieves 15.1 dBm in-band IIP3 at 10 MHz & 11 MHz input tones, with 968 µW power consumption from a single 1V supply voltage. In-band integrated noise is 85.78 µVrms for an overall Figure-of-Merit of 162.8 dB (j-1) which outperforms analog filters State-of-the-Art. I also collaborated as layoutist in other two projects realized with 28nm CMOS technology. The first one was the PRIN Brain28nm project that concerns the implementation of a neural signal acquisition chain. The goal of this work was the realization of a biosensor that uses the EOMOSFET structure with the 28nm CMOS technological node. The use of this technology makes this circuit more competitive when compared to the biosensors present in literature. The last one was Pignoletto project realized in collaboration with RedCat Devices. It concerns the implementation and theorical analysis of two different typologies of ICs measured under radiation: two digital cells and one Analog to Digital Converter. Under radiation measurements will be realize in January 2023. In the second part of my third year I started a work activity in Pavia site of AMS-Osram S.r.l as validation engineer. This company is a world leader in the field of optical sensors and the application of the latter in the automotive sector. The project I am carrying out involves the creation of a validation setup for an IC, in order to verify the correct performance of the multiple functions for which this chip is designed. A first analysis, useful for the preliminary study for the realization of the setup, was carried out through the use of an FPGA (Cyclone1000) on which the code that realizes the logic part of the IC was loaded using the Quartus software. Once the correct operation of the FPGA was validated, through the use of an STM32 micro-controller, various configurations and functions have been tested and correctly validated. The final purpose of this activity, which will continue in the coming months, is the validation of some communication methods between different devices, fundamental for the interface of the IC with automotive standards, and the creation of an updated version of the FPGA code and its subsequent verification. This activity appears to be a novelty in the field of integrated circuit design as it would allow to highlight problems and malfunctions of the circuit.
O'Halloran, Micah G. (Micah Galletta) 1978. "A clock-based analog memory element for integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/87317.
Повний текст джерелаIncludes bibliographical references (leaves 117-118).
by Micah G. O'Halloran.
S.M.
El-Gamal, Mohamed A. "Fault location and parameter identification in analog circuits." Ohio : Ohio University, 1990. http://www.ohiolink.edu/etd/view.cgi?ohiou1172776742.
Повний текст джерелаNalbantis, Dimitris. "World Wide Web based layout synthesis for analogue modules." Thesis, University of Kent, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365218.
Повний текст джерелаDai, Hong. "Development of a decomposition approach for testing large analog circuits." Ohio : Ohio University, 1989. http://www.ohiolink.edu/etd/view.cgi?ohiou1172006982.
Повний текст джерела