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Добірка наукової літератури з теми "DYNAMIC COMPARATORS"

Автор: Grafiati
Опубліковано: 11 вересня 2023

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Статті в журналах з теми "DYNAMIC COMPARATORS"

1

Song, Bangyu, and Yi Zhao. "A comparative research of innovative comparators." Journal of Physics: Conference Series 2221, no. 1 (May 1, 2022): 012021. http://dx.doi.org/10.1088/1742-6596/2221/1/012021.

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Анотація:
Abstract This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over conventional comparators in noise and delay. A triple-latch feedforward (TLFF) comparator improves on the triple-tail fully dynamic comparator. The triple-latch feedforward (TLFF) dynamic comparator consists of three-stage latches and a parallel feedforward path. It has a smaller delay time than other circuit designs, especially for large differential input signals.
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2

Liu, Yuchuan. "An Review of Dynamic CMOS Comparators." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 113–20. http://dx.doi.org/10.54097/hset.v44i.7273.

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Анотація:
CMOS dynamic comparators contributes a major role on the implementation of mixed signal successive approximation register (SAR) type of analog to digital converters (ADC). High precision, dynamic range, low voltage operation, high speed, low power consumption, reliability and offset voltage are the critical factors to be considered while designing CMOS dynamic comparators. This paper reviewed the performance of some popular dynamic CMOS comparators such as StrongARM latch comparator, double- tail dynamic-latched comparator, dynamic bias comparator and triple stage somparator.
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3

Du, Chengze. "Performance analysis of high-speed, low-power comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 292–301. http://dx.doi.org/10.54097/hset.v27i.3770.

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Анотація:
This article mainly presents a summary of development of dynamic comparators and the optimization to conventional comparator in recent years. By comparing the design of two different comparators, the design method of less power consumption, high speed or small delay, and low input referred noise can be concluded. The Dynamic comparator is designed to have small delay and less power consumption compared with two-stage comparator. The dynamic-bias comparator spends less power for operation the circuit compared with double-tail comparator. The FIA comparator operates under the controlling of logic NOR gate.
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4

Tang, Chengyun. "Performance analysis of comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 172–82. http://dx.doi.org/10.54097/hset.v27i.3742.

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Анотація:
This article reviews the innovative and improved structure of three comparators, and summarizes the optimization ideas to further optimize the design parameters of the comparators in the future. The Triple-Tail Dynamic Comparator proposes a multi-stage design to break connection between speed and noise. The Dynamic Bias Latch-Type (DB) Comparator takes an innovative approach to reducing energy consumption by stabilizing the source node voltage of the input pairs. The floating inverter amplififier (FIA)-based pre-amplififier further improves the energy efficiency based on the design of the low-power comparator, and also optimizes parameters such as common-mode output voltage and noise.
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5

Li, Yichen. "The Performance analysis of Low-Power High-Speed comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 72–82. http://dx.doi.org/10.54097/hset.v27i.3723.

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Анотація:
Comparators are the essential block for planning high-speed analog and. This paper presents three inventive designs of the comparators in recent years. First, innovated by classic two-stage comparator, the comparator with a transconductance-enhanced latching stage is suitable for low-power, high-speed operation. Second, triple-latch feed-forward(TLFF) fully dynamic comparator guarantees the maximum possible gain and speed for a specific power across the entire input range. Finally, the comparator with a dynamic floating inverter maximizes efficiency by reusing the current.
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6

Sun, Yuan. "A brief review on novel comparator design." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 418–27. http://dx.doi.org/10.54097/hset.v27i.3785.

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Анотація:
This paper reviewed three different kinds of comparators to show their respective advantage range. The Dynamic-bias comparator extends its pre-amplifier part with a capacitor and has a smaller power with a smaller input referred noise than Elzakker’s comparator but has a higher delay. The Quad high-speed comparator introduced the Quad into the comparator’s latch part. It has a lower delay and also make the calculation of the output voltage easier for it only depends on the skew factor. The low-power dynamic bias has a cross-couple device on its pre-amplifier part which slows down the discharge of the capacitors. It has a higher delay but lower the energy consumption by 30%.
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7

Wang, Sudong. "Review of Four Improving Designs of Dynamic Latch Comparator." Highlights in Science, Engineering and Technology 44 (April 13, 2023): 129–37. http://dx.doi.org/10.54097/hset.v44i.7287.

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Анотація:
In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy efficiency. The overall performance of these comparators is evaluated in this paper.
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8

Fan, Jiangfeng. "Performance Analysis of Low-Power CMOS Dynamic Comparators." Highlights in Science, Engineering and Technology 27 (December 27, 2022): 62–71. http://dx.doi.org/10.54097/hset.v27i.3722.

Повний текст джерела
Анотація:
This paper studies four structures of CMOS dynamic comparators introduced in recent years. Based on conventional double-tail comparator, a comparator with a tail capacitor prevents output nodes of preamplifier from completely discharging to reduce energy consumption. Another comparator with a cross-coupled pairs achieves the same purpose of the first design. A comparator adds a floating inverter amplifier (FIA) to realize both dynamic bias and current reuse, achieve low energy consumption and be insensitive to the VCM. The triple-latch feed-forward (TLFF) comparator decreases delay conspicuously.
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9

sharma*, D. Pavan kumar, and P. Sreehari Rao. "A Low Input Referred Noise Dynamic Comparator for High Speed Applications." International Journal of Recent Technology and Engineering (IJRTE) 8, no. 4 (November 30, 2019): 4768–72. http://dx.doi.org/10.35940/ijrted6881.118419.

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Анотація:
Comparators play a pivotal role in design of analog and mixed signal circuits. Comparators employ regenerative feedback both in input pre-amplifier stage and output stage. The designed comparator resolves 5mV with resolution of 8 bits and dissipates 11mW of power using 1.2V supply in 130nm CMOS technology while operating at clock frequency of 1.25 GHz.
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10

Chen, Zhenxiang, Yuheng Ni, and Zhenghao Xiong. "The Analysis of High-Speed Low-Power Dynamic Comparators." Journal of Physics: Conference Series 2187, no. 1 (February 1, 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2187/1/012022.

Повний текст джерела
Анотація:
Abstract This article reviews 5 different articles on optimizing comparators and focuses on their innovations. Many innovative methods are used to get a higher comparison speed, lower power consumption and degraded noise comparator. Many novel methods such as connecting the conventional two-stage dynamic comparator to a transconductance-enhanced latching stage, adding a charge pump to the Miyahara’s comparator, engendering two propagating edges in two inverter loops and measuring the distance between the two edges to compare different input voltage and using an inverter-based input pair which is powered by a floating reservoir capacitor can significantly achieve these goals. What’s more, a three-stage feedforward fully dynamic comparator with an extra parallel feedforward path, which is a completely innovatory and newly designed comparator, is also proposed.
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Більше джерел

Дисертації з теми "DYNAMIC COMPARATORS"

1

Hedayati, Raheleh. "A Study of Successive Approximation Registers and Implementation of an Ultra-Low Power 10-bit SAR ADC in 65nm CMOS Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-72767.

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Анотація:
In recent years, there has been a growing need for Successive Approximation Register (SAR) Analog-to-Digital Converter in medical application such as pacemaker. The demand for long battery life-time in these applications poses the requirement for designing ultra-low power SAR ADCs. This thesis work initially investigates and compares different structures of SAR control logics including the conventional structures and the delay line based controller. Additionally, it focuses on selection of suitable dynamic comparator architecture.  Based on this analysis, dynamic two-stage comparator is selected due to its energy efficiency and capability of working in low supply voltages. Eventually, based on these studies an ultra-low power 10-bit SAR ADC in 65 nm technology is designed. Simulation results predict that the ADC consumes 12.4nW and achieves an energy efficiency of 14.7fJ/conversion at supply voltage of 1V and sampling frequency of 1kS/s. It has a signal-to-noise-and-distortion (SINAD) ratio of 60.29dB and effective-number-of-bits (ENOB) of 9.72 bits. The ADC is functional down to supply voltage of 0.5V with proper performance and minimal power consumption of 6.28nW.
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2

Muralidharan, Vaishali. "Logic Encryption Using Dynamic Keys." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1613751124204643.

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3

Fuentes, Alejandro. "Cultural diversity and indigenous peoples' land claims: argumentative dynamics and jurisprudential approach in the Americas." Doctoral thesis, Università degli studi di Trento, 2012. https://hdl.handle.net/11572/367661.

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Анотація:
The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this study proposes a new approach focused on the equal functional value of each culture vis-à-vis the cultural producer and beneficiary (the individual). Therefore, it is argued that multiculturalism plea for equal ethno-cultural partition of the public societal space is based on political aspirations and then subjected to –in open, pluralist and democratic societies– the dynamics and methodological procedures of the so-called ‘democratic game’. The second section of this work (Chapters IV, V, and VI) focuses on the specific case of indigenous peoples from both a theoretical and jurisprudential point of view. First, the very notion of indigenous peoples is deconstructed and critically examined. Their special relationship with their traditional lands has been identified as the main objective characteristic that sustains their claims for cultural distinctiveness and differential legal treatment. Then, Chapters V and VI refer to a critical legal analysis of the jurisprudence of the Inter-American Court of Human Rights in connection with indigenous peoples’ land claims, and the role that the element of ‘special relationship with traditional lands’ has played in the recognition of their right to communal property over traditional lands as protected by the American Convention on Human Rights (Article 21 ACHR). In this sense, special attention is given to the interpretative methods applied by the Court, and –in particular– its underlined ontological assumptions.
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4

Fuentes, Alejandro. "Cultural diversity and indigenous peoples' land claims: argumentative dynamics and jurisprudential approach in the Americas." Doctoral thesis, University of Trento, 2012. http://eprints-phd.biblio.unitn.it/767/1/AF_Doctoral_Thesis.pdf.

Повний текст джерела
Анотація:
The present study is divided in two differentiable but conceptually interrelated sections. Within the first section (Chapters I, II, and III), the focus is on the assessment of the argumentative logic behind the multiculturalist proposal for equally divided societies, among equally positioned ethno-cultural groups. A critical and analytical review of the multiculturalist argumentative constructions shows that its justification lies on the dogmatic assumption of the equal worth or dignity of cultures, which is ontologically incorrect. Cultures cannot be axiologically compared. Instead, this study proposes a new approach focused on the equal functional value of each culture vis-à-vis the cultural producer and beneficiary (the individual). Therefore, it is argued that multiculturalism plea for equal ethno-cultural partition of the public societal space is based on political aspirations and then subjected to –in open, pluralist and democratic societies– the dynamics and methodological procedures of the so-called ‘democratic game’. The second section of this work (Chapters IV, V, and VI) focuses on the specific case of indigenous peoples from both a theoretical and jurisprudential point of view. First, the very notion of indigenous peoples is deconstructed and critically examined. Their special relationship with their traditional lands has been identified as the main objective characteristic that sustains their claims for cultural distinctiveness and differential legal treatment. Then, Chapters V and VI refer to a critical legal analysis of the jurisprudence of the Inter-American Court of Human Rights in connection with indigenous peoples’ land claims, and the role that the element of ‘special relationship with traditional lands’ has played in the recognition of their right to communal property over traditional lands as protected by the American Convention on Human Rights (Article 21 ACHR). In this sense, special attention is given to the interpretative methods applied by the Court, and –in particular– its underlined ontological assumptions.
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5

Benedetto, Alessandra. "Pre-contractual agreements in international commercial contracts: legal dynamics and commercial expediency." Doctoral thesis, Universita degli studi di Salerno, 2012. http://hdl.handle.net/10556/1302.

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Анотація:
2010 - 2011
La materia dei contratti internazionali è andata acquisendo sempre maggiore importanza e diffusione negli ultimi anni. Questo fatto costituisce, in qualche modo, la conseguenza dei profondi cambiamenti che hanno interessato il mondo delle relazioni commerciali. Oggigiorno, grazie alla creazione di un mercato unico europeo e, soprattutto, quale conseguenza diretta della globalizzazione, la gran parte dei businessmen tendono a spingere i propri affari ben oltre i confini nazionali, quando non accantonano addirittura la dimensione “geografica” e si avvalgono dei più moderni strumenti della comunicazione forniti dalla tecnologia (e-commerce). La categoria dei contratti internazionali dà vita, invero, a non pochi problemi: anzitutto, non è dato rinvenirne una specifica definizione e non è sempre facile stabilire quale regime normativo (nazionale) sia applicabile nel singolo caso, a prescindere dalle apposite regole già esistenti. Un altro aspetto molto rilevante è costituito dalla notevole complessità (spesso dovuta al valore economico dell’operazione commerciale) della fase delle negoziazioni durante la quale le parti, solitamente, si comunicano l’un l’altra la propria volontà e la misura entro la quale sono disposti a farsi reciproche concessioni, fissano i singoli steps attraverso cui addivenire al raggiungimento di un accordo, valutano la concreta fattibilità dell’affare. In un tale contesto complesso esse, spesso, fissano in appositi documenti i profili del futuro regolamento contrattuale su cui hanno già raggiunto un accordo e, nel far questo, non di rado escludono i lawyers dalla redazione degli stessi. Il risultato pratico è che, piuttosto frequentemente, le formulazioni di questi documenti danno vita a notevoli problemi interpretativi. La risoluzione di una controversia emersa dalla lettera di un contratto internazionale rende necessario che il giudice o, più spesso, l’arbitro tenga in debito conto gli sviluppi della legislazione in molti degli ordinamenti nazionali, degli strumenti normativi transnazionali e di ogni altra pratica emersa in tema di accordi commerciali. Giudici e arbitri, infatti, nel formulare le proprie decisioni non possono prescindere da tali sviluppi avutisi nella pratica del commercio, andando oltre i confini tracciati dalla normativa nazionale prescelta. Questa tesi si propone di analizzare gli effetti connessi al contenuto dei documenti pre-contrattuali, secondo quella che è la disciplina degli ordinamenti di Common Law e di Civil Law, nonché negli strumenti a vocazione transnazionale come, ad esempio, i Principi UNIDROIT, i Principles of European Contract Law, Draft Common Frame of Reference, U.N. Convention on the International Sales of Good (CISG) e, emenata recentemente, la proposta di regolamento Common European Sales Law. Più specificamente, due sono i profili presi in considerazione: anzitutto, ci si domanda fino a che punto una dichiarazione pre-contrattuale possa considerarsi vincolante in sé e per sé. In secondo luogo, si tratta di appurare fino a che punto una dichiarazione pre-contrattuale possa produrre effetti giuridici venendo incorporata nel futuro contratto o, comunque, inducendo alla stipula del contratto stesso. Il metodo d’indagine adottato consiste, anzitutto, nell’analisi delle regole sulla formazione dei contratti previste dagli ordinamenti più rappresentativi afferenti al Common Law ed al Civili Law, nonché dai documenti transazionali su menzionati. Segue, poi, uno studio sull’interpretazione e la qualificazione delle lettere di intenti e degli altri pre-contractual statements risultati di maggiore impiego nella prassi del commercio internazionale e, prima ancora, alla luce delle disposizioni normative riconducibili agli ordinamenti nazionali. La tesi si propone, in definitiva, di conseguire i seguenti obiettivi: 1) verificare quali siano gli eventuali riflessi sugli attuali trends relativi alla disciplina nazionale e transnazionale; 2) individuare quali fattori di policy incidono sulla evoluzione giuridica; 3) appurare se si venga a creare, o meno, una qualche interferenza tra diritto nazionale e transnazionale; 4) stabilire quale sia la relazione esistente tra Hard Law e Soft Law. [a cura dell'autore]
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6

Camurani, Andrea. "Metodi di calibrazione e sistema di misura di Timing Mismatch per un convertitore RFDAC realizzato con architettura a current steering in tecnologia FinFET." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/20229/.

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Анотація:
Il presente lavoro di tesi, svolto presso Xilinx in Irlanda, è focalizzato alla calibrazione e misura delle non idealità dinamiche presenti nei convertitori digitali-analogici (Digital to Time Converter) a radio frequenza, con architettura a Current-Steering. Questa architettura, controllata da una logica combinata di bit termometrici (6 MSB) e bit binari (10 LSB), permette di avere alte prestazioni di velocità. Le non idealità consistono nel disallineamento temporale di questi bit, che aumentano tanto più la frequenza del dato in ingresso aumenta. La necessità di metodi di calibrazione per questi effetti è necessaria al fine di ottenere delle prestazioni del convertitore accettabili per il mercato. In questa tesi viene quindi data una visione riguardante la calibrazione di questi errori temporali, forniti da un modello scritto in Verilog A, di un convertitore RFDAC a 16 bit operante con una frequenza di clock di 6.4GHz. In realtà, su silicio, questi errori temporali devono essere misurati con precisione da un sistema di misura. Si è contribuito al progetto e alla caratterizzazione, utilizzando librerie FinFET TSMC (Taiwan Semiconductor Manufacturing Company) in Cadence Virtuoso, di un sistema di misura integrato che consente di misurare il disallineamento temporale di questi bit, con una precisione di 150fs.
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7

Quo, Chang Feng. "Reverse engineering homeostasis in molecular biological systems." Thesis, Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49144.

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Анотація:
This dissertation is an initial study of how modern engineering control may be applied to reverse engineer homeostasis in metabolic pathways using high-throughput biological data. This attempt to reconcile differences between engineering control and biological homeostasis from an interdisciplinary perspective is motivated not only by the observation that robust behavior in metabolic pathways resembles stabilized dynamics in controlled systems, but also by the challenges forewarned in achieving a true meeting of minds between engineers and biologists. To do this, a comparator model is developed and applied to model the effect of single-gene (SPT) overexpression on C16:0 sphingolipid de novo biosynthesis in vitro, specifically to simulate and predict potential homeostatic pathway interactions between the sphingolipid metabolites. Sphingolipid de novo biosynthesis is highly regulated because its pathway intermediates are highly bioactive. Alterations in sphingolipid synthesis, storage, and metabolism are implicated in human diseases. In addition, when variation in structure is considered, sphingolipids are one of the most diverse and complex families of biomolecules. To complete the modeling paradigm, wild type cells are defi ned as the reference that exhibits the "desired" pathway dynamics that the treated cells approach. Key model results show that the proposed modern engineering control approach using a comparator to reverse engineer homeostasis in metabolic systems is: (a) eff ective in capturing observed pathway dynamics from experimental data, with no signifi cant di fference in precision from existing models, (b) robust to potential errors in estimating state-space parameters as a result of sparse data, (c) generalizable to model other metabolic systems, as demonstrated by testing on a separate independent dataset, and (d) biologically relevant in terms of predicting steady-state feedback as a result of homeostasis that is verifi ed in literature and with additional independent data from drug dosage experiments.
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8

Matěj, Jan. "Návrh a optimalizace spínaného komparátoru v 250 nm CMOS technologii." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-318180.

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Анотація:
This diploma thesis deals with design methods and optimization techniques of dynamic latched comparators. It compares latched and continuous comparators and describes their principle. Then it analyses three popular latched comparator structures with respect to offset, speed and kickback noise. It shows practical comparator design focused on offset precision.
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9

Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.

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Анотація:
Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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10

BONIFAZI, MAURIZIO. "Analog circuits design for cellular neural network." Doctoral thesis, Università degli Studi di Roma "Tor Vergata", 2008. http://hdl.handle.net/2108/705.

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Анотація:
Il paradigma delle Reti Neurali Artificiali (ANN) consiste nell’applicazione del modello neurale “biologico” per la risoluzione di problemi che spesso sono troppo complessi per un’architettura di Von Neumann. La letteratura offre differenti approcci per l’implementazione di ANN. Qualche implementazione è di tipo software, altre sono soluzioni circuitali come circuiti digitali full-custom o FPGA (Field Programmable Gate Array), come pure circuiti analogici, e il tipo di implementazione di certo dipende dal tempo di esecuzione adeguato al tipo di applicazione. Questa tesi riguarda la progettazione di nuovi circuiti analogici adattati per le Reti Neurali. In particolare, saranno utilizzate le Reti Neurali Cellulari (CNN) proposte nel 1981 dal Prof. L.O.Chua (University of California – Berkeley). Il “Laboratorio di Circuiti” dell’Università di Roma “Tor Vergata” ha progettato e realizzato alcuni chip analogici dedicati a questo tipo di Reti Neurali. Questi chip appartengono alla famiglia “Digital Programmable CNN” (DPCNN) e presentano principalmente due caratteristiche: la programmabilità digitale dei pesi sinaptici come una particolare architettura orientata ad una struttura interconnessa (cioè connettendo tra loro più di questi chip è possibile realizzare reti di grande dimensione). In questa tesi viene data una visione di insieme sulle ANN, sulle CNN e sulle Star-CNN: cosa sono, come funzionano ed a cosa servono. In perticolare verrà descritta la famiglia DP-CNN. Questa tesi propone una nuova architettura chiamata TD-CNN (Time Division CNN), che sfrutta una particolare strategia mirata a ridurra l’area di occupazione su silicio di una cella elementare, per aumentare l’integrabilità della rete. Oltretutto la stessa strategia a divisione di tempo verrà applicata alle TD-Star CNN. In particolare questi circuiti sono le non-linerità digitalmente programmabili (cioè DPTA – Digital Programmable Transconductance Amplifier e DPTA – Digital Programmable Transconductance Comparator) e circuiti particolari per la multiplazione (DM-SH – Dynamic Mirror Sample and Hold e DM-MUX – Dynamic Mirror Multiplexer). Sono mostrate alcune simulazioni dei circuiti per permettere lo studio di queste nuove architetture, e la modifica delle dinamiche introdotte dalla strategia a divisione di tempo.
The Artificial Neural Network (ANN) paradigm consists of the application of biological “neural” models to the solution of particular problems that often are very hard to solve for the classical “Von Neumann” architectures. Different are the approaches proposed in literature for the implementation of an ANN. Some of them are software implementations only while, others are circuital solutions as full custom digital circuits or programmed FPGAs (Field Programmable Gate Array) as well as analogue circuits and the typology of the implementation certainly depends on the length of the processing time that you believe adequate for the particular application. This thesis is focused on the design of new analogue circuits well suited for Neural Network applications. In particular, the class of the Cellular Neural Networks (CNN), proposed in 1981 by Prof. L.O.Chua (University of California - Berkeley), will be exploited. In this area, the “Laboratorio Circuiti” at University of Rome “Tor Vergata” designed and manufactured several analogue chips devoted to this class of Neural Networks. These chips belong to the Digital Programmable CNN (DPCNN) chip family and present two main features: the digital programmability of the synaptic weights as well as a special architecture oriented to an interconnection structure (i.e. it is possible to carry out large network by connecting together more of these chips). In this thesis work you will find an overview about the Artificial Neural Network, the Cellular Neural Network and the Star Cellular Neural Network: what they are, how they work and why they are useful. In particular, the DP-CNN chip family will be deeply described. This thesis proposes the TD-CNN (Time Division CNN), a particular design strategy, devoted to reduce the silicon area occupation of the a elementary cell in order to improve the VLSI integrability of the network. Moreover, the same time-division strategy will be applied to TD-Star CNN. In particular, these circuits consist of the digitally programmable non-linearity circuits (i.e. the Digital Programmable Transconductance Amplifier - DPTA and Digital Programmable Transconductance Comparator – DTPC) and special circuit for to carry out the multiplexing feature (i.e. the Dynamic Mirror Sample and Hold – DM-SH and the Multiplexer – DM-MUX). Several circuital simulations will be shown in order to study the behavior of this modified architecture and the modifications on the dynamics introduced by the time division strategy.
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Книги з теми "DYNAMIC COMPARATORS"

1

Analysis of Dynamic Latched Comparator with Reduced Delay and Energy for High Speed ADCs. Tiruchengode, India: ASDF International, 2017.

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Частини книг з теми "DYNAMIC COMPARATORS"

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Ansari, Noman Ahmed, Priyansh Jaiswal, Mohit Tyagi, and Poornima Mittal. "Design and Comparative Analysis of Dynamic Comparators for SAR ADC." In Lecture Notes in Electrical Engineering, 391–401. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4300-3_34.

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Sowmya, K. B., and Meghashree Doddamani. "Swift Double-Tail Dynamic Comparator." In Lecture Notes in Electrical Engineering, 485–90. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-1906-0_41.

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Soram, Julia, and Shyam Akashe. "A Relative Investigation of TIQ Comparator and Dynamic Latched Comparator." In Springer Proceedings in Physics, 291–97. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2367-2_37.

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Ramkaj, Athanasios T., Marcel J. M. Pelgrom, Michiel S. J. Steyaert, and Filip Tavernier. "Ultrahigh-Speed High-Sensitivity Dynamic Comparator." In Analog Circuits and Signal Processing, 121–47. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-22709-7_4.

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Gandhi, Priyesh P., and Niranjan M. Devashrayee. "Low-Offset High-Speed CMOS Dynamic Voltage Comparator." In Advances in Intelligent Systems and Computing, 209–17. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_23.

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Kushwaha, Ritesh Kumar, Prem Kumar, and P. Karuppanan. "Study and Analysis of Low Power Dynamic Comparator." In Lecture Notes in Electrical Engineering, 435–49. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-32-9775-3_40.

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Singh, Tejender, and Suman Lata Tripathi. "Design and analysis of a shared charged dynamic latch comparator." In Intelligent Circuits and Systems, 384–90. London: CRC Press, 2021. http://dx.doi.org/10.1201/9781003129103-60.

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Murali Krishna, G., G. Karthick, and N. Umapathi. "Design of Dynamic Comparator for Low-Power and High-Speed Applications." In Lecture Notes in Electrical Engineering, 1187–97. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7961-5_110.

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Yadav, Sugandha. "Low Power SAR ADC Based on Charge Redistribution Using Double Tail Dynamic Comparator." In Lecture Notes in Electrical Engineering, 557–67. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-2685-1_53.

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Velagaleti, Silpakesav, Pavankumar Gorpuni, and K. K. Mahapatra. "A Novel High Speed Dynamic Comparator Using Positive Feedback with Low Power Dissipation and Low Offset." In Information and Communication Technologies, 45–49. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-15766-0_7.

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Тези доповідей конференцій з теми "DYNAMIC COMPARATORS"

1

Molaei, Hasan, and Khosrow Hajsadeghi. "A low-power comparator-reduced flash ADC using dynamic comparators." In 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2017. http://dx.doi.org/10.1109/icecs.2017.8292010.

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Efstathiou, Constantinos, Laura Agalioti, and Yiorgos Tsiatouhas. "Efficient Dynamic Logic Magnitude Comparators." In 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2022. http://dx.doi.org/10.1109/vlsi-soc54400.2022.9939570.

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Babayan-Mashhadi, Samaneh, Mojtaba Daliri, and Reza Lotfi. "Analysis of power in dynamic comparators." In 2013 21st Iranian Conference on Electrical Engineering (ICEE). IEEE, 2013. http://dx.doi.org/10.1109/iraniancee.2013.6599853.

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Sachdeva, Yogesh, Nalin Nehra, Shikhar Bansal, and Garima. "Review of Dynamic Comparators for ADCs." In 2021 Second International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2021. http://dx.doi.org/10.1109/icesc51422.2021.9532865.

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Sangeetha, R., A. Vidhyashri, M. Reena, R. B. Sudharshan, Sangeetha govindan, and J. Ajayan. "An Overview Of Dynamic CMOS Comparators." In 2019 5th International Conference on Advanced Computing & Communication Systems (ICACCS). IEEE, 2019. http://dx.doi.org/10.1109/icaccs.2019.8728470.

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Li, Zhuoling, Yuan Ma, and Zan Xie. "A Review of Improved CMOS Dynamic Comparators." In 2022 IEEE International Conference on Electrical Engineering, Big Data and Algorithms (EEBDA). IEEE, 2022. http://dx.doi.org/10.1109/eebda53927.2022.9745016.

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Spinogatti, Valerio, Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, and Alessandro Trifiletti. "Robust Body Biasing Techniques for Dynamic Comparators." In 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME). IEEE, 2023. http://dx.doi.org/10.1109/prime58259.2023.10161788.

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Zhang, Lijun. "Online Learning in Changing Environments." In Twenty-Ninth International Joint Conference on Artificial Intelligence and Seventeenth Pacific Rim International Conference on Artificial Intelligence {IJCAI-PRICAI-20}. California: International Joint Conferences on Artificial Intelligence Organization, 2020. http://dx.doi.org/10.24963/ijcai.2020/731.

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Анотація:
The usual goal of online learning is to minimize the regret, which measures the performance of online learner against a fixed comparator. However, it is not suitable for changing environments in which the best decision may change over time. To address this limitation, new performance measures, including dynamic regret and adaptive regret have been proposed to guide the design of online algorithms. In dynamic regret, the learner is compared with a sequence of comparators, and in adaptive regret, the learner is required to minimize the regret over every interval. In this paper, we will review the recent developments in this area, and highlight our contributions. Specifically, we have proposed novel algorithms to minimize the dynamic regret and adaptive regret, and investigated the relationship between them.
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Amaya, Andres, Rodolfo Villamizar, and Elkim Roa. "An offset reduction technique for dynamic voltage comparators." In 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME). IEEE, 2016. http://dx.doi.org/10.1109/prime.2016.7519549.

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Liu, Jia, Fule Li, Weitao Li, Hanjun Jiang, and Zhihua Wang. "A flash ADC with low offset dynamic comparators." In 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC). IEEE, 2017. http://dx.doi.org/10.1109/edssc.2017.8126480.

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