Дисертації з теми "Doherty power amplifiers"
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Brand, Konrad Frederik. "The experimental design and characterisation of Doherty power amplifiers." Thesis, Link to the online version, 2006. http://hdl.handle.net/10019.1/2594.
Повний текст джерелаShao, Jin. "Advanced Power Amplifiers Design for Modern Wireless Communication." Thesis, University of North Texas, 2015. https://digital.library.unt.edu/ark:/67531/metadc804973/.
Повний текст джерелаJansen, Roelof. "Evaluation of Doherty Amplifier Implementations." Thesis, Stellenbosch : Stellenbosch University, 2008. http://hdl.handle.net/10019.1/20445.
Повний текст джерелаENGLISH ABSTRACT: Modern communication systems demand efficient, linear power amplifiers. The amplifiers are often operated in the backed-off power levels at which linear amplifiers such as class B amplifier are particularly inefficient. The Doherty amplifier provides an improvement as it increases efficiency at backed of power levels. Doherty amplifiers consists of two amplifiers, a carrier amplifier and a peaking amplifier, of which the output is combined in a novel way. Implementation of the Doherty amplifier with transistors is not ideal. One of the main problems is the insufficient current production of the peaking amplifier at peak envelope power (PEP) if it is implemented as a class C amplifier. A suggested solution to this problem is a bias adaption system that controls the peaking amplifier gate voltage dynamically depending on the input power levels. The design and evaluation of such a adaptive Doherty amplifier is the main goal of this thesis. A classical Doherty amplifier with and an uneven Doherty amplifier with unequal power division between the carrier and peaking amplifiers are also evaluated and compared with the adaptive Doherty amplifier. The amplifiers are designed using a 10 W LDMOS FET device, the MRF282. The adaptive Doherty amplifier and the uneven Doherty amplifier show significant improvements in efficiency and output power over the even Doherty amplifier. At PEP the adaptive Doherty delivers 42.4 dBm at 39.75 % power added efficiency (PAE), the uneven Doherty amplifier 41.9 dBm at 40.75 % PAE and the even Doherty amplifier 40.8 dBm at 38.6 % PAE. At 3dB backed-off input power the adaptive Doherty amplifier has an efficiency of 34.3%, compared to 34.9 5% for the uneven Doherty amplifier and 29.75 % for the even Doherty amplifier.
AFRIKAANSE OPSOMMING: Moderne kommunikasie stelsels vereis effektiewe, linieêre drywing versterkers. Die versterkers word dikwels in laer drywings vlakke bedryf waar linieêre versterkers soos ’n klas B versterker besondere lae effektiwiteit het. Die Doherty versterker bied ’n uitweg omdat dit verbeterde effektiwiteit by lae drywings vlakke bied. ’n Doherty versterker bestaan uit twee versterkers, die hoof versterker en die aanvullende versterker, waarvan die uittrees met ’n spesiale kombinasie netwerk bymekaar gevoeg word. Die implementasie van Doherty versterkers met transistors is nie ideaal nie. Een van die hoof probleme is die onvoldoende stroom wat deur die aanvullings versterker gebied word by piek omhulsel drywing (POD). ’n Oplossing vir die probleem is om ’n aanpassings sisteem te gebruik wat die aanvullende versterker se hekspanning dinamies beheer afhangende van die intree drywings vlakke. Die ontwerp en evaluasie van so ’n aanpassings Doherty versterker is die hoof doel van hierdie tesis. ’n Klassieke Doherty versterke met gelyke drywings verdeling en ’n ongelyke Doherty versterker wat gebruik maak van ongelyke drywings verdeling tussen die hoof-en aanvullende versterkers is ook gevalueer en vergelyk met die aanpassings Doherty versterker. Die versterkers was ontwerp met ’n 10 W LDMOS FET, die MRF282. Die aanpassings Doherty versterker en die ongelyke Doherty versterker het aanmerklike verbeteringe in effektiwiteit en uittree drywing gebring in vergelyking met die ewe Doherty versterker. By POD het die aanpassings versterker 42.4 dBm teen 39.75 % drywing toegevoegde effektiwiteit (DTE) gelewer, die ongelyke Doherty versterker 41.9 dBm teen 40.75 % DTE, en die ewe Doherty versterker 40.8 dBm teen 38.6 DTE. By ’n intree drywingsvlak 3 dB laer as POD het die aanpassings Doherty versterker ’n effektiwiteit van 34.3 % getoon, in vergelyking met die onewe Doherty versterker se 34.9 % en die ewe Doherty versterker se 29.75 % DTE.
Yahyavi, Mehran. "On the design of high-efficiency RF Doherty power amplifiers." Doctoral thesis, Universitat Politècnica de Catalunya, 2016. http://hdl.handle.net/10803/398236.
Повний текст джерелаLos amplificadores de potencia (PAs) son uno de los elementos más importantes para los transmisores inalámbricos desde el punto de vista del consumo energético. Un aspecto muy importante es su eficiencia energética, un concepto relacionado con el back-off de salida (OBO), que a su vez viene condicionadpo por el PAPR de la señal modulada a amplificar. Una baja eficiencia de los PA hace que la pérdida de energía se manifieste en forma de calor. De hecho, esta cuestión conduce al incremento de los costes y tamaño, esto último por los radiadores. Además, el compromiso entre la linealidad y la eficiencia en los PA es otro problema importante. Para hacer frente a las circunstancias que producen la degradación de la eficiencia, el amplificador de potencia tipo Doherty (DPA) es una de las técnicas más útiles que proporcionan una buena eficiencia incluso para los altos PAPR comunes en señales de comunicación modernos. Sin embargo, el limitado ancho de banda (BW) de este tipo de PA (alrededor del 10% del ancho de banda fraccional) y su importancia (en los sistemas inalámbricos modernos, tales como LTE, WiMAX, Wi-Fi y sistemas de satélites) han animado a los investigadores para mejorar este inconveniente en los últimos años. Algunos aspectos típicos que limitan el BW en los DPA son: i) transformadores de longitud de cuarto de onda, ii) redes de compensación de fase y circuitos de adaptación de salida, iii) compensación de las líneas y los dispositivos no ideales. Los transformadores de cuarto de onda actuan como un inversor de impedancia en la técnica de modulación de carga de la DPA "("load modulation"). Concretamente, el objetivo futuro de diseño de DPA es disminuir el impacto de estos problemas. En este contexto, esta tesis doctoral se centra en mejorar el ancho de banda fraccional de DPA utilizando los nuevos métodos que están relacionados con el uso de transformadores de impedancias en vez de inversores en el subcircuito de modulación de carga. Este estudio tiene dos niveles. En primer lugar, se presenta una novedosa estructura del DPA de banda ancha usándose dispositivos de GaN en la banda de 2,5 GHz con un divisor Wilkinson asimétrico. El transformador de impedancias de la arquitectura propuesta se basa en una red de adaptación, incluyendo una línea cónica con múltiples secciones del transformador en la etapa principal. El BW de este DPA ha sido de 1,8 a 2,7 GHz. Además, se obtiene una eficiencia de drenador de más del 33% en todo el BW, tanto a nivel de potencia máxima como a nivel del OBO. En segundo lugar, aprovechando los beneficios de un adaptador de Klopfenstein, se propone un nuevo diseño del DPA. Con la sustitución de la lina conica por el Klopfenstein se reduce el coeficiente de reflexión de transformador de impedancias. Sobre un prototipo práctico de esta nueva estructura del Doherty, en la banda de 2,25 GHz, se ha demostrado que el BW resultante se incrementa en comparación con la topología convencional mientras se mantienen las cifras de eficiencia. Por otra parte, en este estudio se demuestra que el diseño basado en el Klopfenstein permite una afinación fácil del retardo de grupo a través de la reactancia de salida del taper, lo que resulta en un ajuste más sencillo que otros diseños publicados recientemente en el que el transformador de cuarto de onda se sustituye por multi-líneas de transmisión de la sección (híbridos o similar). Los resultados experimentales han mostrado un 43-54% de eficiencia de drenador sobre 42 dBm de potencia de salida, en el intervalo de 1,7 a 2,75 GHz. Concretamente, los resultados presentados en esta nueva estructura tipo-Doherty implican una técnica de modulación de carga que utiliza una combinación de un Klopfenstein junto con un transformador de múltiples secciones con el fin de obtener un alto ancho de banda con la eficiencia habitual en DPAs.
Els amplificadors de potència (PA) són un dels elements més importants per els sistemes ràdio ja que sone ls principals consumidors d'energía. Un aspecte molt important és l'eficiència de l'amplificador, aspecte relacionat amb el back-off de sortida (OBO) que a la seva vegada ve condicionat pel PAPR del senyal modulat. Una baixa eficiència dels PA fa que la pèrdua d'energia en manifesti en forma de calor. De fet, aquesta qüestió porta a l'increment dels costos i grandària, degut als dissipadors de calor. A més, el compromís entre la linealitat i l'eficiència en els PA es un altre problema important. Per fer front a les circumstàncies que porten a la degradació de l'eficiència, l'amplificador de potència Doherty (DPA) és una de les tècniques més útils i que proporcionen una bona eficiència per als alts PAPR comuns en senyals de comunicació moderns. No obstant això, l'ample de banda limitat (BW) d'aquest tipus de PA (al voltant del 10% de l'ample de banda fraccional) i la seva importància (en els sistemes moderns, com ara LTE, WiMAX, Wi-Fi i sistemes de satèl·lits) han animat els investigadors per millorar aquest inconvenient en els últims anys. Alguns aspectes tipicament limitadors del BW en els DPA son: i) transformadors de longitud d'quart d'ona, ii) xarxes de compensació de fase en circuits / adaptacions de sortida, iii) compensació de les línies i els dispositius no ideals. Els transformadors de quart d'ona s'utilitzen com a inversors d'impedàncies en la tècnica de modulació de càrrega del DPA ("load modulation"). Concretament, l'objectiu futur de disseny d'DPA és disminuir l'impacte d'aquests problemes. En aquest context, aquesta tesi doctoral es centra en millorar l'ample de banda fraccional dels DPA utilitzant nous mètodes que estan relacionats amb l'ús de transformadors d'impedàncies, en comptes d'inversors, en el subcircuit de modulació de càrrega. Aquest treball té dos nivells. En primer lloc, es presenta un DPA novedós que fa servir dispositus GaN DPA a la banda de 2,5 GHz amb un divisor Wilkinson asimètric. El transformador d'impedàncies de l'arquitectura proposada es basa en una xarxa d'adaptació, incloent una línia cònica amb múltiples seccions del transformador en l'etapa principal. El BW d'aquest DPA ha mostrat ser d'1,8 a a 2,7 GHz. A més, s'obté una eficiència de drenador de més del 33% en tot el BW, tant a nivell de potència màxima com de OBO. En segon lloc, sobre la base dels beneficis del adaptador de Klopfenstein, un proposa un nou disseny on un Klopfenstein substitueix la anterior línia cònica. Aquesta substitució repercuteix en la reducció del coeficient de reflexió de transformador d'impedàncies.Des d'una realització pràctica (prototipus) d'aquest nou amplificador tipus Doherty a la banda de 2,25 GHz, s'ha demostrat que el BW resultant s'incrementa en comparació amb la topologia convencional mentre es mantenen les xifres d'eficiència. D'altra banda, en aquest estudi es demostra que el disseny basat en el Klopfenstein permet una afinació fàcil del retard de grup a través de la reactància de sortida de la forma cònica, el que resulta en un ajust més senzill que altres dissenys publicats recentment en què el transformador de quart d'ona es substitueix per multi-línies de transmissió de la secció (híbrids o similar). Els resultats experimentals han mostrat un 43-54% d'eficiència de drenador en 42 dBm de potència de sortida, en l'interval de 1,7-2,75 GHz. Concretament, els resultats presentats en aquest nou amplificador tipus Doherty impliquen una tècnica de modulació de càrrega específic que utilitza una combinació del Klopfenstein juntament amb un transformador de múltiples seccions per tal d'obtenir un alt ample de banda amb la usual eficiència en DPAs.
Viswanathan, Vani. "Efficiency Enhancement of Base Station Power Amplifiers Using Doherty Technique." Thesis, Virginia Tech, 2004. http://hdl.handle.net/10919/9907.
Повний текст джерелаMaster of Science
Nunes, Luís Carlos Cótimos. "Nonlinear distortion generation mechanisms in Doherty amplifiers." Doctoral thesis, Universidade de Aveiro, 2015. http://hdl.handle.net/10773/15944.
Повний текст джерелаNowadays, wireless communications systems demand for greater mobility and higher data rates. Moreover, the need for spectral efficiency requires the use of non-constant envelope modulation schemes. Hence, power amplifier designers have to build highly efficient, broadband and linear amplifiers. In order to fulfil these strict requirements, the practical Doherty amplifier seems to be the most promising technique. However, due to its complex operation, its nonlinear distortion generation mechanisms are not yet fully understood. Currently, only heuristic interpretations are being used to justify the observed phenomena. Therefore, the main objective of this work is to provide a model capable of describing the Doherty power amplifier nonlinear distortion generation mechanisms, allowing the optimization of its design according to linearity and efficiency criteria. Besides that, this approach will allow a bridge between two different worlds: power amplifier design and digital pre-distortion since the knowledge gathered from the Doherty operation will serve to select the most suitable pre-distortion models.
Presentemente, os sistemas de comunicações sem fios exigem uma maior mobilidade e elevadas taxas de transferência. Para além disso, a necessidade de eficiência espectral obriga ao uso de esquemas de modulação de envolvente variável. Consequentemente, o desenvolvimento de amplificadores de elevada eficiência, com uma elevada largura de banda e, ao mesmo tempo, lineares, tornou-se num dos maiores desafios para os engenheiros de projeto de amplificadores de potência. Por forma a cumprir estes requisitos muito rigorosos, o amplificador em configuração Doherty parece ser a técnica mais promissora. Contudo, devido à sua complexa operação, os seus mecanismos de geração de distorção não linear não são ainda completamente conhecidos. Atualmente, apenas interpretações heurísticas estão a ser usadas para justificar os fenómenos observados. Nesse sentido, o principal objetivo deste trabalho é desenvolver um modelo capaz de descrever os mecanismos de geração da distorção não linear em amplificadores Doherty, permitindo assim, a optimização do seu projeto, tendo em conta as especificações de linearidade e eficiência. Para além disso, esta abordagem permitirá uma ponte entre dois mundos diferentes: projecto de amplificadores de potência e pré-distorção digital, uma vez que o conhecimento recolhido da operação do Doherty ajudará na escolha de modelos de pré-distorção mais adequados.
Jang, Haedong. "NONLINEAR EMBEDDING FOR HIGH EFFICIENCY RF POWER AMPLIFIER DESIGN AND APPLICATION TO GENERALIZED ASYMMETRIC DOHERTY AMPLIFIERS." The Ohio State University, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=osu1406269587.
Повний текст джерелаMarkos, Asdesach Zena. "Efficiency enhancement of linear GaN RF power amplifiers using the Doherty technique." Kassel Kassel Univ. Press, 2008. http://d-nb.info/99160427X/04.
Повний текст джерелаBaker, Bryant. "A 3.6 GHz Doherty Power Amplifier with a 40 dBm Saturated Output Power using GaN on SiC HEMT Devices." PDXScholar, 2014. https://pdxscholar.library.pdx.edu/open_access_etds/1781.
Повний текст джерелаAcimovic, Igor. "Contributions to the Design of RF Power Amplifiers." Thesis, Université d'Ottawa / University of Ottawa, 2013. http://hdl.handle.net/10393/24406.
Повний текст джерелаMarkos, Asdesach Zena [Verfasser]. "Efficiency enhancement of linear GaN RF power amplifiers using the Doherty technique / Asdesach Zena Markos." Kassel : Kassel University Press, 2009. http://d-nb.info/1006970711/34.
Повний текст джерелаSrirattana, Nuttapong. "High-Efficiency Linear RF Power Amplifiers Development." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/6899.
Повний текст джерелаCui, Xian. "Efficient radio frequency power amplifiers for wireless communications." Columbus, Ohio : Ohio State University, 2007. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1195652135.
Повний текст джерелаBathich, Khaled [Verfasser], Georg [Akademischer Betreuer] Boeck, and Renato [Akademischer Betreuer] Negra. "Analysis and Design of Efficiency-Enhancement Microwave Power Amplifiers Using the Doherty Technique / Khaled Bathich. Gutachter: Renato Negra. Betreuer: Georg Boeck." Berlin : Technische Universität Berlin, 2013. http://d-nb.info/1065664729/34.
Повний текст джерелаKamarudin, Syalwani. "Advanced Doherty power amplifier design for modern communication systems." Thesis, Cardiff University, 2018. http://orca.cf.ac.uk/115269/.
Повний текст джерелаTarar, Mohsin Mumtaz. "Design and Implementation of as Asymmetric Doherty Power Amplifier at 2.65 GHz in GaN HEMT Technology." Thesis, Linköpings universitet, Elektroniska komponenter, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-75976.
Повний текст джерелаSmith, Karla Jenny Isabella. "Gate Bias Control and Harmonic Load Modulation for a Doherty Amplifier." Thesis, University of Canterbury. Electrical and Computer Engineering, 2009. http://hdl.handle.net/10092/2856.
Повний текст джерелаSeneviratne, Sashieka. "Efficiency Enhancement of Pico-cell Base Station Power Amplifier MMIC in GaN HFET Technology Using the Doherty Technique." Thèse, Université d'Ottawa / University of Ottawa, 2012. http://hdl.handle.net/10393/23078.
Повний текст джерелаSajedin, M., Issa T. Elfergani, Jonathan Rodriguez, Raed A. Abd-Alhameed, M. Fernandez-Barciela, and M. Violas. "Ultra-Compact mm-Wave Monolithic IC Doherty Power Amplifier for Mobile Handsets." MDPI, 2021. http://hdl.handle.net/10454/18600.
Повний текст джерелаThis work develops a novel dynamic load modulation Power Amplifier (PA) circuity that can provide an optimum compromise between linearity and efficiency while covering multiple cellular frequency bands. Exploiting monolithic microwave integrated circuits (MMIC) technology, a fully integrated 1W Doherty PA architecture is proposed based on 0.1 µm AlGaAs/InGaAs Depletion- Mode (D-Mode) technology provided by the WIN Semiconductors foundry. The proposed wideband DPA incorporates the harmonic tuning Class-J mode of operation, which aims to engineer the voltage waveform via second harmonic capacitive load termination. Moreover, the applied post-matching technique not only reduces the impedance transformation ratio of the conventional DPA, but also restores its proper load modulation. The simulation results indicate that the monolithic drive load modulation PA at 4 V operation voltage delivers 44% PAE at the maximum output power of 30 dBm at the 1 dB compression point, and 34% power-added efficiency (PAE) at 6 dB power back-off (PBO). A power gain flatness of around 14 ± 0.5 dB was achieved over the frequency band of 23 GHz to 27 GHz. The compact MMIC load modulation technique developed for the 5G mobile handset occupies the die area of 3.2.
This research was funded by the European Regional Development Fund (FEDER), through COMPETE 2020, POR ALGARVE 2020, Fundação para a Ciência e a Tecnologia (FCT) under i-Five Project (POCI-01-0145-FEDER-030500). This work is also part of the POSITION-II project funded by the ECSEL joint Undertaking under grant number Ecsel-345 7831132-Postitio-II-2017-IA. This work is supported by FCT/MCTES through national funds and when applicable co-funded EU funds under the project UIDB/50008/2020-UIDP/50008/2020. The authors would like to thank the WIN Semiconductors foundry for providing the MMIC GaAs pHEMT PDKs and technical support. This work is supported by the Project TEC2017-88242-C3-2-R- Spanish Ministerio de Ciencia, Innovación e Universidades and EU-FEDER funding.
Barakat, Ayman. "Doherty power amplifier efficiency and bandwidth enhancement based on a generic design approach." Thesis, Queen's University Belfast, 2017. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.725336.
Повний текст джерелаLajovic, Carneiro Marcos. "Design, optimization and integration of Doherty power amplifier for 3G/4G mobile communications." Phd thesis, Université Sciences et Technologies - Bordeaux I, 2013. http://tel.archives-ouvertes.fr/tel-00942844.
Повний текст джерелаCarneiro, Marcos Lajovic. "Design, optimization and integration of Doherty power amplifier for 3g/4g mobile communications." reponame:Repositório Institucional da UnB, 2013. http://repositorio.unb.br/handle/10482/15244.
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Os sinais dos novos padrões de comunicação (LTE/LTE-Advanced) apresentam uma elevada diferença entre o pico e a média de sua potência (PAPR), sendo inadequados para o uso com os amplificadores de potência convencionais por apresentarem eficiência máxima apenas quando trabalham com sua potência máxima. Os novos sinais, na maior parte do tempo, demandam médias e baixas potências, concentrando a operação dos amplificadores de potência em uma região de baixa eficiência, o que provoca excessiva dissipação de energia em forma de calor e redução do tempo da bateria. Os amplificadores de potência Doherty por apresentarem uma eficiência constante por uma larga faixa de potências representam uma solução favorável para o problema da PAPR. Devido à tendência atual de redução dos dispositivos e integração completa da cadeia de RF em um único chip, decidiu-se implementar esse amplificador de potência na tecnologia CMOS 65nm por ela já ser adequada à implementação de circuitos digitais, o que permite a integração de um sistema completo. Este trabalho apresenta a metodologia de projeto e medições de um amplificador de potência Doherty totalmente integrado em tecnologia CMOS 65nm com desempenho de eficiência de potência adicionada (PAE) constante ao longo de uma retração de potência de 7dB. Medidas feitas de 2.4GHz à 2.6GHz mostram o desempenho constante de PAE começando no nível de 20% até 24%, com uma potência máxima de 23,4dBm. O circuito é totalmente descrito com todos os valores de componentes e detalhes de leiaute para posterior reprodução. As curvas que mostram o efeito de modulação ativa de carga, as correntes dos sub-amplificadores e o comportamento constante de PAE demonstram a implementação de um autêntico amplificador de potência Doherty. O circuito foi projetado com atenção especial para o baixo custo, utiliza apenas componentes discretos, cada sub-amplificador possui topologia cascode de saída simples e suas redes de entrada/saída são otimizadas para economizar área de chip e produzir um desempenho constante de PAE. _______________________________________________________________________________________ ABSTRACT
The signals of the new communication standards (LTE / LTE-Advanced) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. These signals demands low and medium power for most part of the time, which concentrates the operation of power amplifiers in a region of low efficiency, resulting in excessive heat dissipation and reduction of battery time. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. Given the current trend of reducing devices and full integration of RF chain on a single chip, it was decided to implement this power amplifier in 65nm CMOS technology due to its performance for digital circuits, allowing the integration of a whole system. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm. The circuit is fully described with all components values and layout details for further reproduction. Curves showing the active load-pull effect, sub-amplifiers behavior and constant PAE prove that it is a genuine Doherty Power Amplifier. The circuit was designed with special attention to low cost, it is composed by only lumped components, each sub-amplifier has single-ended cascode topology and their input/output networks are optimized to save die area and to produce a constant PAE. _______________________________________________________________________________________ RESUMÉ
L’amplificateur de puissance (PA) est l’élément qui consomme le plus d’énergie dans les architectures d’émission-réception RF des terminaux mobiles. Les PAs conventionnels ont un rendement maximum seulement au niveau de puissance maximum, tandis que pour des niveaux de puissance plus bas, le rendement des PAs est très faible. Or les nouveaux standards de communications à haut débit (4G/LTE advanced) utilisent des modulations à enveloppe non-constante. Ainsi, le rapport entre la puissance maximum et la puissance moyenne du signal (PAPR – Peak to Average Power Ratio) est élevé. C’est le cas également pour l’OFDM qui possède un fort PAPR avec les porteuses multiples. Ainsi, lorsqu’un signal a un fort PAPR, cela signifie que le rendement moyen du PA utilisé est faible. La conséquence directe est la rapide décharge des batteries des terminaux mobiles. L’Amplificateur de Puissance Doherty (APD) est une technique connue d'amélioration du rendement. Cette technique permet d’augmenter le rendement moyen des amplificateurs en améliorant le rendement aux faibles niveaux de puissance, tout en maintenant le rendement maximum sur une plus grande plage de puissance de sortie. Cette technique est bien adaptée pour résoudre le problème de rendement pour les signaux à forts PAPR. De nombreux travaux proposent des solutions intégrées des APD dans une technologie à faible coût, mais au détriment du maintien d’un rendement à puissance ajoutée (Power Added-Efficiency, PAE) constant sur une grande plage de puissance. Nos travaux de recherche proposent un APD totalement intégré en technologie 65nm CMOS de STMicroelectronics à 2,535 GHz avec une PAE constante sur une plage de recul en puissance de sortie de 8 dB. Pour la conception de cet amplificateur, nous avons utilisé sept niveaux de métaux sur les dix couches de métaux de la technologie, les capacités sont de type MOM afin de respecter des contraintes faible coût. Le principe de l’APD est d’utiliser l’effet connu sous le nom de « load-pull actif » : une charge vue par une source de courant peut être modifiée par l’application d’un courant provenant d’une deuxième source. Pour atteindre cet objectif, l’architecture Doherty utilise deux amplificateurs de classes différentes en parallèle. Le PA principal (classiquement polarisé en classe B ou AB) fonctionne pour tous les niveaux de puissance et le PA auxiliaire (classiquement en classe C) ne fonctionne que pour les niveaux de puissance moyens et forts. L’augmentation de rendement s’explique par la transformation d’impédance de drain du PA principal, à cause de la combinaison de deux facteurs en même temps, la charge inversée vue par la ligne de transmission d’un quart d’onde et le courant du PA auxiliaire qui augmente. En effet, lorsque le courant du PA auxiliaire augmente, l’impédance vue par le PA principal se réduit. L’APD a été conçu avec les transistors à drain étendu haute tension pour soutenir une grande excursion de tension et produire des niveaux de puissance de sortie plus élevés. Les limites de Vdd et Vgs du transistor sont de 2.75V et de 5.5V, respectivement. Chaque sous-amplificateur a été conçu avec une topologie cascode pour donner au PA une meilleure isolation vis-à-vis des effets de désadaptation d’impédances entre la sortie et l’entrée. De plus, cette topologie permet d’avoir une plus grande tension d’alimentation Vdd par rapport à la topologie source commune. Les deux amplificateurs, principal et auxiliaire, ne sont cependant pas identiques. En effet, les dimensions des transistors dépendent du courant traversant chaque amplificateur. Ainsi, le transistor grille commune du PA principal est constitué de 28 transistors en parallèle, tandis que le transistor source commune du PA principal est composé de 26 transistors en parallèle. Pour le PA auxiliaire, le transistor grille commune est composé de 26 transistors en parallèle et son transistor source commune est composé de 14 transistors en parallèle. Chaque sous-amplificateur a été conçu et optimisé individuellement en prenant en compte les réseaux d'adaptation, l’inductance d’arrêt, les impédances d'entrée prévues par le diviseur de puissance et l’impédance de sortie prévue pour avoir l’effet loadpull actif de l’APD. Tout au long du travail de conception, les performances des deux PAs ont été tracées sur le même graphique pour équilibrer correctement le point de compression de chacun. Les courbes de PAE de chacun ont été optimisées dans le but de produire un APD avec une PAE constante sur une large gamme de puissance. Après la connexion des sous-amplificateurs dans le même schéma électrique, les lignes de transmission à éléments localisés ont été ajoutées, puis la topologie a été ré-optimisée pour réduire le nombre d'inductances et ainsi réduire l’espace utilisé dans la puce. À l'entrée, le diviseur de Wilkinson, la ligne de transmission déphasage et les réseaux d’adaptation d’entrée des PAs principal et auxiliaire ont été fusionnés et optimisés. À la sortie de l’APD, les réseaux d’adaptation de sortie des deux PAs et la ligne de transmission d’inversion de charge ont aussi été fusionnés et optimisés. Pour atteindre l'objectif d’avoir une PAE constante, une méthodologie d'optimisation séquentielle a été appliquée pour bien équilibrer tous les éléments dans le schéma de l’APD en respectant toutes les limites de tensions des transistors. Le circuit a été implémenté dans une surface de 1,72x1,68mm². Il a été conçu pour être mesuré avec des sondes directement positionnées sur les trois différents types de plots. Ce travail présente la méthodologie de conception et des résultats de mesure d'un amplificateur de puissance Doherty entièrement intégré dans la technologie 65 nm CMOS avec une PAE constante sur 7 dB de plage de puissance. Les mesures de 2,4 GHz à 2,6 GHz montrent des performances constantes en PAE de 20% jusqu'à 24% avec une puissance de sortie maximale de 23,4 dBm. Le circuit est entièrement décrit avec les valeurs des composants et les détails de layout pour permettre sa reproduction. Ce travail montre l'effet de modulation active de charge, le comportement en courant des sous-amplificateurs et la performance constante en PAE, ce qui démontre l’implémentation d’un véritable amplificateur de puissance Doherty. Le circuit est composé uniquement d'éléments localisés, et les réseaux d’entrée et de sortie sont optimisés pour réduire la taille de la puce et pour produire une PAE constante. L’amplificateur de puissance Doherty présenté est le premier APD totalement intégré en technologie 65 nm CMOS avec une PAE constante sur une large gamme de puissance. Il respecte de ce point de vue la théorie de Doherty. La comparaison avec un amplificateur de puissance classique polarisé en classe AB montre une amélioration de la PAE pour les niveaux de faible et moyenne puissance, permettant ainsi d’augmenter nettement le rendement moyen de l’amplificateur. Aucun autre APD publié ne présentait ce type de caractéristique en rendement dans cette technologie. La technologie 65nm CMOS est généralement plus appropriée pour les applications numériques, par conséquent, l’utilisation de cette technologie s'inscrit dans la tendance actuelle du développement d’un système complet sur une seule puce, où les étages numérique et analogique sont intégrés sur la même puce silicium.
Popp, Daniel [Verfasser]. "Research and Design of High Power and High Bandwidth Digital Three-Way Doherty Power Amplifier / Daniel Popp." München : Verlag Dr. Hut, 2021. http://d-nb.info/1232846651/34.
Повний текст джерелаGhazaany, Tahereh S., Raed A. Abd-Alhameed, Mark B. Child, N. T. Ali, Jonathan Rodriguez, and Abubakar S. Hussaini. "Optimum Design of Doherty RFPA for Mobile WiMAX Base Stations." Springer for the ICST, 2010. http://hdl.handle.net/10454/4484.
Повний текст джерелаRF power amplifiers in mobile WiMAX transceivers operate in an inherently nonlinear manner. It is possible to amplify the signal in the linear region, and avoid distortion, using output power back-off; however, this approach may suffer significant reduction in efficiency and power output. This paper investigates the use of Doherty techniques instead of back-off, to simultaneously achieve good efficiency and acceptable linearity. A 3.5 GHz Doherty RFPA has been designed and optimized using a large signal model simulation of the active device, and performance analysis under different drive levels. However, the Doherty EVM is generally poor for mobile WiMAX. Linearity may be improved by further digital pre-distortion, and a simple pre-distortion method using forward and reverse AM-AM and AM-PM modeling. Measurements on the realized amplifier show that this approach satisfies the EVM requirements for WiMAX base stations. It exhibits a PAE over 60%, and increases the maximum linear output power to 43 dBm, whilst improving the EVM.
Galajda, Jan. "Výkonový zesilovač v pásmu L." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-316443.
Повний текст джерелаNeslen, Cody R. "Negative Conductance Load Modulation RF Power Amplifier." DigitalCommons@CalPoly, 2010. https://digitalcommons.calpoly.edu/theses/312.
Повний текст джерелаKing, Matthew E. "Linear Power-Efficient RF Amplifier with Partial Positive Feedback." DigitalCommons@CalPoly, 2012. https://digitalcommons.calpoly.edu/theses/811.
Повний текст джерелаPIACIBELLO, ANNA. "Advanced High Efficiency Architectures for Next Generation Wireless Communications." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2732877.
Повний текст джерелаAyad, Mohammed. "Etude et Conception d’amplificateurs DOHERTY GaN en technologie Quasi - MMIC en bande C." Thesis, Limoges, 2017. http://www.theses.fr/2017LIMO0027.
Повний текст джерелаThis work responds to an increased industrial need for on carrier signals with variable envelope amplification used by current telecommunications systems. These signals have a strong PAPR and an envelope statistical distribution centred below the envelope peak value, the reason why the telecom industrialists then require a robust and reliable high power amplifiers having an energy expenditure along of the envelope dynamics associated with an acceptable level of linearity. This document presents the results of the study and realization of two, high efficiency, Doherty Power Amplifiers (DPA) encapsulated in QFN plastic packages. The first is a conventional Doherty power Amplifier (DPA-SE) and the second is a dual-input Doherty power amplifier (DPA-DE). These C-band demonstrators are based on the use of Quasi-MMIC technology combining power bars based on the AlGaN/GaN transistors on SiC to matching circuits in ULRC technology. The Quasi-MMIC approach combined with Quasi-MMIC approach combined with QFN plastic package solution for better thermal behaviour management offers electrical performances similar to those of MMIC technology with very attractive coasts and manufacturing cycles. During this work, a new evaluation method for the transistors dedicated to the design of DPA was developed and implemented. The intensive use of 2.5D and 3D electromagnetic simulations made it possible to take into account the coupling effects existing between the different circuits in the QFN package environment. The results of the tests of the amplifiers realised and operating on 1GHz bandwidth validated the design method and showed that the advanced concepts associated with the Quasi-MMIC approach as well as plastic encapsulation technologies can generate innovative microwave functions. The characterizations of the DPA-DE have noted the interest inherent in the preformation of the excitation signals and the bias points of each stage of the amplifier
Takacs, Edward, Christopher M. Durso, and David Dirdo. "A ROBUST DIGITAL WIRELESS LINK FOR TACTICAL UAV’S." International Foundation for Telemetering, 2005. http://hdl.handle.net/10150/604917.
Повний текст джерелаA conventionally designed radio frequency amplifier operated in its linear region exhibits low DC to RF conversion efficiency. Typically, for a power amplifier designed for digital modulation applications, the amplifier is operated “backed-off” from its P1dB point by a factor of 10 or -10 dB. The typical linear amplifier is biased for either Class A or Class A/B operation depending on the acceptable design trade-offs between efficiency and linearity between these two methods. A novel design approach to increasing the efficiency of a linear RF power amplifier using a modified Odd-Way Doherty technique is presented in this paper. The design was simulated, built and then tested. The design yields improvements in efficiency and linearity.
Hussaini, Abubakar S. "Energy efficient radio frequency system design for mobile WiMax applications. Modelling, optimisation and measurement of radio frequency power amplifier covering WiMax bandwidth based on the combination of class AB, class B, and C operations." Thesis, University of Bradford, 2012. http://hdl.handle.net/10454/5749.
Повний текст джерелаHussaini, Abubakar Sadiq. "Energy efficient radio frequency system design for mobile WiMax applications : modelling, optimisation and measurement of radio frequency power amplifier covering WiMax bandwidth based on the combination of class AB, class B, and C operations." Thesis, University of Bradford, 2012. http://hdl.handle.net/10454/5749.
Повний текст джерелаZhang, Hao. "Circuit d'amplification Doherty intégré large bande pour applications radio cellulaires de puissance." Thesis, Poitiers, 2019. http://www.theses.fr/2019POIT2265.
Повний текст джерелаThis work presents the design, realization and measurement result of integrated broadband Doherty amplification circuits for base stations, required for 5G. Initially, based on the research for techniques to improve electrical efficiency for signals with high dynamic range, the Doherty technique is chosen to continue the work. Studies on different Doherty architectures showed that performance can be improved and extended by adding a third stage (3-way Doherty) with calculated auxiliary transistors’ sizes for which are operated in class C mode. Limitations on the practical use of the Doherty technique is demonstrated by the considerations of various non linearities of the LDMOS transistors. The research of wideband architectures shows simultaneous advantages of integration and broadband capability by the CdS absorption technique and the use of mixed type of input splitters. Based on the results of various studies, three-way Doherty MMIC power amplifiers were designed and realized using the CdS absorption technique with an asymmetry ratio of 1 : 3 : 3 in the band of 1805 MHz to 2170 MHz. Experimental performances have shown the potentialities of the 3-way Doherty and a clear efficiency improvement over the entire frequency band. Specific wideband operating conditions are presented to reduce distortion products of third (IMD 3), 10th and 12th (IMD 10/12). The linearity measurements at different instantaneous bandwidths are very encouraging and validate the new asymmetric three-way Doherty architecture
Courty, Alexis. "Architecture d'amplificateur de puissance linéaire et à haut rendement en technologie GaN de type Doherty numérique." Thesis, Limoges, 2019. http://www.theses.fr/2019LIMO0067/document.
Повний текст джерелаThe high capabilities of current and future 5G communication satellite links lead the processed signals in the payloads to simultaneously exhibit large amplitude variations (PAPR>10dB) and wide instantaneous bandwidths (BW>1GHz). Within the microwave transmission subsystem, the operation of the power amplification stage is highly constrained by the transmitted waveforms, it is one of the most energy-consuming module of the payload affecting as well the integrity of the transmitted signal. In this context, the functions dedicated to digital signal processing and currently implemented by the digital processor (such as filtering, channeling, and possibly the demodulation and regeneration of baseband signals) embedded in the payloads, represent a potential solution that would reduce the constraints reported on the power amplification function and help to manage the allocated power ressource. This work proposes a study on the capability of dual input power amplifier architectures in order to manage the efficiency-linearity trade-off over a wide bandwidth. This study is carried out on a 20W GaN Doherty demonstrator operating in C band. The combination of the output signals on the RF load is managed by an optimal amplitude and phase distribution that is digitally controlled at the input. Firstly, a wideband design methodology of Doherty amplifier is introduced and validated on a C band demonstrator. In a second time the experimental tool allowing the extraction of amplitude and phase input distributions is presented, the dual input characterization is achieved and compared with simulation results. Finally, in perspective of this work, a preliminary study of the capabilities of the digital Doherty for the management of an output load mismatch (VSWR management) is carried out and the results are put forward
Ayari, Lotfi. "Contribution au développement d’un banc de mesures temporelles 4-canaux pour la caractérisation avancée de composants et de sous-systèmes RF non linéaires." Thesis, Limoges, 2016. http://www.theses.fr/2016LIMO0117/document.
Повний текст джерелаThe future communications for civil and military applications will use complex wideband modulated signals to be transmitted through multi-channel DOHERTY power amplifiers which should have high performance in terms of power, efficiency, OBO, and bandwidth. In order to meet these stringent requirements, designers need time-domain characterization tools for calibrated measurements and for optimizing voltages and currents at both ports of non-linear connectorized or on-wafer devices. This work successfully implements time-domain characterization tools used to meet specific needs for transistor modeling, to optimize their operation in terms of pulse to pulse stability, and to search optimal conditions of their operation modes in a Doherty power amplifier. For this implementation, mathematical modeling is performed to evaluate sampler’s performances in terms of time-domain sampling efficiency in order to choose the best suited sampling architecture for RF time-domain measurements. Rigorous calibration procedures have been developed to obtain simultaneously full time-domain calibrated waveforms (from low Frequencies to Microwave frequencies)
Pereira, Joana Lopes Silva. "Doherty amplifier and antenna combiner." Master's thesis, 2018. http://hdl.handle.net/10773/25033.
Повний текст джерелаA arquitetura Doherty convencional é tipicamente utilizada em transmissores sem fios pela sua capacidade de aumentar a eficiência média de um tradicional amplificador em classe B. O amplificador Doherty consiste em dois amplificadores em paralelo (chamados de amplificadores carrier e peaking) que são ligados, na saída, através de um combinador de /4. Este combinador de saída geralmente tem um impacto significativo na largura de banda do amplificador, pois é tipicamente construído a partir de uma estrutura de linhas de transmissão com dimensões ajustadas para uma frequência. Outras estruturas de combinadores não convencionais podem ser projetadas, visando uma largura de banda maior, contribuindo para um aumento geral da largura de banda do amplificador Doherty. Sendo este um tópico de investigação de elevada relevância para o desenvolvimento de amplificadores de alta eficiência e largura de banda, seria interessante ter um setup de laboratório que implemente um amplificador de potência Doherty para o qual estruturas combinadoras distintas possam ser ligadas à saída do amplificador e testadas. Nesse sentido, o projeto de dois amplificadores (carrier e peaking) foi realizado num simulador de circuitos (ADS, da Keysight) junto com o divisor de potência de entrada que compõe a arquitetura Doherty. A placa principal do amplificador Doherty foi projetada para incorporar os amplificadores carrier e peaking, e também o divisor de potência na entrada, e foi preparada de modo que pudesse ser ligada a qualquer combinador desejado a ser testado. Um combinador de potência Doherty tradicional foi projetado e ambas as placas (amplificador Doherty e o combinador) foram produzidas, soldadas e testadas no laboratório de RF. O amplificador medido apresentou as características típicas de um amplificador Doherty com aproximadamente 75% de eficiência de dreno na potência máxima e aproximadamente 50% no ponto de output back-off. Além disso, foi projetado um segundo combinador com dois objetivos. O primeiro foi demonstrar o funcionamento do amplificador Doherty projetado com um combinador de saída distinto, mostrando que, como pretendido neste trabalho, o amplificador desenhado é adequado para testar múltiplas estruturas combinadoras. O segundo objetivo foi servir como teste preliminar para avaliar a possibilidade de fundir o combinador de saída com a antena. Aproveitando o acoplamento eletromagnético entre antenas, esta segunda estrutura combinadora utiliza duas antenas que foram projetadas para se comportarem simultaneamente como combinador de saída do amplificador Doherty e como elemento radiante.
Mestrado em Engenharia Eletrónica e Telecomunicações
Ji, Jien-Rong, and 紀建榮. "Design of High Efficiency High Power Broadband Amplifiers with Automatic Gain Control and Doherty Power Amplifier." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/63345277136376315717.
Повний текст джерела國立中央大學
電機工程學系
105
The power amplifier is a critical building block in the RF transmitter. The efficiency、bandwidth and the ability of providing the stable output are essential issues for the power amplifiers. This thesis focuses on the efficiency and back-off power efficiency enhancement and the power amplifiers with automatic gain control loop to provide a stable output. The reactance compensation method is applied to the VHF class-E power amp lifers in chapter 2, and two 10 W and a 100 W broadband power amplifiers were implemented using Freescale laterally diffused metal oxide semiconductor (LDMOS) transistors. The 3 dB fractional bandwidth of 10 W and 100 W power amplifiers reaches 45–175 MHz (123%) and 75–135 MHz (60%) respectively, and the highest efficiency of 10 W and 100 W class-E power amplifiers in the 3 dB fractional bandwidth is 63% at 130 MHz and 76% at 110 MHz respectively, and the highest power gain in the 3 dB fractional bandwidth is 20.8 dB at 105 MHz and 20.4 dB at 100 MHz Gain control range of 10 W class E power amplifier is from 16.6 to 21.4 dB when DC drain voltage varying from 20–50 V. In chapter 3, the automatic gain control loop is applied to the power amplifiers implemented in chapter 2. The automatic gain control loop can alleviate the effect of input power variation on the output power. The output power of the loops are over 10 W and 100 W respectively, and the input dynamic ranges are 4.5 dB at 105 MHz and 4.4 dB at 120 MHz respectively. In chapter 4, the design of Doherty power amplifier is introduced, and a 10 W VHF Doherty power amplifier is implemented by using laterally diffused metal oxide semiconductor (LDMOS). The highest efficiency of the power amplifier measured at 180 MHz reaches 69%, and the efficiency at 6–dB back-off power is 41%, and the 3 dB fractional bandwidth is 50% (130–220 MHz), and the highest power gain in the 3 dB fractional bandwidth is 21.6 dB at 180 MHz, and the output power at 1 dB gain compression point is 30.8 dBm (at 180 MHz), and the output power at third-order intercept point is 46.6 dBm. A K-band Doherty power amplifier is also implemented by PHEMT technology in chapter 4, and the highest small signal gain reaches 7 dB at 26 GHz, but the negligence during the EM simulation results in the difference between simulation and measurement results, and the difference will be discussed in chapter 4. Lastly, the future work and the conclusions are made in chapter 5.
Wu, Yu-Ting David. "A Doherty Power Amplifier with Extended Bandwidth and Reconfigurable Back-off Level." Thesis, 2013. http://hdl.handle.net/10012/7385.
Повний текст джерела"Novel Doherty power amplifier design for advanced communication systems." 2015. http://library.cuhk.edu.hk/record=b6116094.
Повний текст джерелаDoherty 功率放大器结构简单,增加效率的同时能保持中等线性度,故而受到了广泛关注。本文囊括了三个有关增加Doherty 放大器工作带宽、延展高效率区或提高功率利用因子的创新设计。
第一个设计中,复数合路阻抗被用于扩宽Doherty 放大器的高效率区。关于动态阻抗范围,电流比因子和漏极效率的理论分析说明,复数合路阻抗可以当作新的自由度来增加放大器的高效率区。为了验证有关理论,以2GHz 为工作频点,我们使用了相同的基于GaN 工艺的晶体管,分别设计了使用复数合路阻抗和纯实数合路阻抗的Doherty 放大器。连续波测试结果显示,使用复数合路阻抗的Dohety 放大器能够提高9.1dB 的输出回退范围,比基于纯实数合路阻抗的传统设计要高3.6dB。此外,使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示,基于复数合路阻抗的设计在输出功率为33.2dBm 时,其平均漏极效率高达57.4%。
第二个设计中使用了随频率变化的复数合路阻抗,通过控制漏极电流,来同时增加Doherty 放大器的工作带宽和高效率区。为了验证有关理论,我们设计了输出功率42dBm、工作带宽1.8-2.2GHz、输出回退区9dB 的Doherty 放大器。连续波测试结果显示,在8.5dB 回退点处,该设计在8.5dB 回退点和饱和输出点的漏极效率分别高达55-59%和69-73%。使用单载波、均峰比9.6dB 的WCDMA 信号的测试显示,该设计在输出功率为33.5dBm 时,其平均漏极效率高达53-58%,邻道抑制比也能保持在-30dBc。
最后一个设计中,一种在辅助支路加入变换器的Doherty 结构被用于宽带放大。理论分析显示了该结构能够增加功率利用因子,并提供宽带Doherty 特性。为了验证有关理论,我们设计了输出功率20W、工作带宽1.6-2.4GHz、功率利用因子得到改善的Doherty 放大器。连续波测试结果显示,该设计的功率利用因子高达0.94,所有频点均可得到良好的Doherty 效率特性,该设计在6dB回退点和饱和输出点的漏极效率分别高达55-64%和68-76%。在2GHz 处,使用单载波、均峰比6.6dB 的WCDMA 信号的测试显示,该设计在输出功率为37dBm时,其平均漏极效率高达56%,邻道抑制比低于-37dBc。
As modern communication system demands higher spectrum efficiency and data rate, new communication standard using complex modulation scheme has emerged and led to transmitting signal with ever-increasing Peak-to-Average Power Ratio (PAPR). Moreover, the co-existence of different standards requires RF transceivers to support signal transmission at multiple carrier frequencies. Therefore, wideband operation and efficient amplification of high PAPR signal are prime requirements for base-station PA design.
For efficiency enhancement, the Doherty Power Amplifier (DPA) [1] has been regarded as the most popular approach due to its circuit simplicity and moderate linearity. Three innovative DPA design techniques relating to the enhancement of operating bandwidth, high efficiency range and power utilization factor (PUF) are proposed in this work.
In the first demonstration, a novel DPA configuration with Complex Combining Load (CCL) is presented to extend the high efficiency range of the amplifier. Theoretical analysis of dynamic load span, current ratio and drain efficiency reveals that complex combining load can offer a new degree of freedom to boost the Output Back-off (OBO) of DPA. For verification, a 2GHz, equal-cell, GaN HEMT-based DPA is simulated, prototyped and measured with both complex and resistive combining loads. Under Continuous Wave (CW) excitation, measurement results show that the CCL DPA can attain an OBO of 9.1 dB which is 3.6 dB higher than that of the RCL design. In addition, by the use of single-carrier WCDMA signal with PAPR of 9.6 dB and at an average output power of 33.2 dBm, the CCL design is found to deliver an average drain efficiency of 57.4%.
The second design presents a novel technique to extend the bandwidth and efficiency range of DPA by the adoption of frequency-varying Complex Combining Load and proper input current control strategy. For verification, a 42 dBm, 1.8-2.2 GHz DPA with OBO of 8.5 dB was designed, built and characterized. Under CW stimulation, a back-off efficiency (8.5 dB) of 55-59% and saturation efficiency of 69-73% were observed over the entire bandwidth. With single carrier WCDMA signal excitation (PAPR of 9.6 dB), an average drain efficiency of 53-58% was obtained at 33.5 dBm average output power and Adjacent Channel Leakage Power Ratio (ACLR) of around -30 dBc.
In the last technique, a novel DPA configuration with auxiliary transformer is presented for broadband operation. Theoretical analysis reveals that the presented design can offer enhanced PUF and wideband Doherty behavior. Based on the proposed theory, a 1.6-2.4 GHz, 20 W DPA with improved PUF is designed, simulated and measured. Under CW excitation, measurement results indicate that the presented DPA can achieve a PUF of 0.94, good Doherty behavior over the entire frequency band with a 6 dB back-off efficiency of 55-64% and saturated efficiency of 68-76%. In addition, by the use of single-carrier WCDMA signal (centered at 2 GHz) with PAPR of 6.6 dB and at an average output power of 37 dBm, an average drain efficiency of 56% is obtained with ACLR of better than -37 dBc.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Fang, Xiaohu.
Thesis (Ph.D.) Chinese University of Hong Kong, 2015.
Includes bibliographical references.
Abstracts also in Chinese.
Huang, Kuan Lin, and 黃冠霖. "Research of High Efficiency Doherty Power Amplifier with Adjustable Input Power Ratio of Main and Auxiliary Amplifiers." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/23158456783739496114.
Повний текст джерелаGonçalves, Cristiano Ferreira. "Load insensitive radio frequency power amplifiers." Doctoral thesis, 2021. http://hdl.handle.net/10773/33222.
Повний текст джерелаOs amplificadores de potência de estado sólido (SSPAs) evoluíram significativamente nas últimas décadas, principalmente devido à utilização de novas tecnologias de transístores, como os transístores de alta mobilidade (HEMTs) de nitreto de gálio (GaN), de ferramentas muito avançadas de projeto assistido por computador (CAD) e de algoritmos de pré-distorção digital (DPD) muito evoluídos. Isto levou a uma melhoria de desempenho considerável, em termos de eficiência energética, potência de saída e linearidade. Normalmente, para obter estes níveis de desempenho, os engenheiros projetam os amplificadores permitindo que os transístores utilizados operem muito perto do seu limite físico de funcionamento seguro e considerando que vão operar para uma carga fixa. No entanto, os amplificadores projetados são utilizados em diversas aplicações industriais e/ou telecomunicações e, em alguns casos, como por exemplo fornos micro-ondas ou estações base 5G, a sua carga de saída pode variar devido a várias causas, que podem ser previsíveis ou imprevisíveis. Neste cenário não ideal, os transístores utilizados operam para cargas não ótimas e o desempenho dos amplificadores pode ser muito degradado. Além disso, em projetos muito otimizados, onde os transístores são operados perto do seu limite de funcionamento seguro, a sua durabilidade pode ser reduzida ou, em casos extremos, podem até ser permanentemente danificados. Portanto, para melhorar o desempenho dos amplificadores em cenários de carga variável, são necessárias novas arquiteturas e/ou técnicas que visam reduzir a variação da carga vista pelos transístores utilizados. Esta tese apresenta várias estratégias para melhorar a insensibilidade dos amplificadores em relação à variação de carga. As técnicas apresentadas são baseadas em malhas de adaptação dinâmicas (TMNs) e na variação da tensão de alimentação dos amplificadores. As malhas de adaptação desenvolvidas permitiram reduzir a variação de carga vista pelo amplificador e a variação da sua tensão de alimentação permitiu melhorar o desempenho para operação com cargas não ótimas. Estas abordagens foram testadas e validadas em amplificadores baseados num só transístor, e, posteriormente, com base nas suas vantagens e desvantagens, a técnica mais promissora – a modulação da tensão de alimentação – foi selecionada para o projeto de um amplificador Doherty, que é imprescindível para telecomunicações. Além disso, como em algumas aplicações a variação da carga de saída pode ser imprevisível, também desenvolvemos um sistema completo que inclui um circuito de medida de impedância e compensação do desempenho do amplificador em tempo real.
Programa Doutoral em Engenharia Eletrotécnica
"High-Efficiency Doherty-Based Power Amplifiers Using GaN Technology For Wireless Infrastructure Applications." Doctoral diss., 2018. http://hdl.handle.net/2286/R.I.51658.
Повний текст джерелаDissertation/Thesis
Doctoral Dissertation Electrical Engineering 2018
Lai, Yun-Jhu, and 賴畇茿. "Implementations on X/Ka-band CMOS Wideband Unilateralized Power Amplifiers and X-band GaN Power Amplifiers with Low Impedance Binary Power Combining Technique and Doherty Architecture." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/e24f34.
Повний текст джерела國立中央大學
電機工程學系
106
The thesis developed five power amplifiers that were designed in tsmcTM 0.18-µm CMOS, tsmcTM 90-nm CMOS and WINTM 0.25-µm GaN for both X-band and Ka-band operations. The best transistor size and biasing current density of the used transistors were chosen by simulating in different processes. The wideband matching was realized by the magnetically coupling transformer and the enhanced efficiency was realized by using Doherty architecture. Finally, the circuit performance was verified by the measuring small and large signal parameters, such as S-parameters, output power, linearity and modulated signals, etc., The first power amplifier was fabricated in tsmcTM 0.18-µm CMOS technology for X-band operation. This two-stage power amplifier adopted the unilateralization technique which was constructed by a class A amplifier in parallel with class B one to increase the overall output 1-dB compression power (OP1dB) and power added efficiency (PAE). The wide operating bandwidth was achieved by using magnetically coupling Balun for the output matching and T-type matching for the inter-stage matching. The measurement results showed a small signal gain of 20.1 dB, the saturated output power (Psat) and OP1dB are 20.1 dBm and 18.4 dBm, respectively. The peak output power and PAE are improved by the amount of 3.8 dB and 3.4%, respectively, while adopted this composited power amplifier architecture. The chip area is 1.78 (1.95×1.13) mm2. The second and third chips were fabricated in tsmcTM 90-nm CMOS technology for Ka-band operation. Two amplifiers were realized by using unilateralization technique in common-source topology. The input and output matching design followed the previous work and the inter-stage matching was realizes by magnetic transformer. The third power amplifier applied a pre-matching design to minimize the chip size and increase the operating bandwidth. These power amplifiers displayed the gains of 17.43 dB and 14.5dB, respectively. The saturated output powers were measured to 14.73 dBm and 18.4 dBm. The OP1dB were 10.7dBm and 14.5 dBm, respectively. The chip areas are 0.73 (1.41×0.405) mm2 and 0.67 (1.01×0.67) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The fourth chip presents an X-band monolithic microwave integrated circuit (MMIC) binary-combining power amplifier in WINTM 0.25-µm GaN technology. The output of the two-stage CS power amplifiers combined two circuit paths to double the output power and the low impedance combiner reduced the power loss. The measured results exhibited a peak gain of 16.35 dB, a saturation output power of 33.2dBm and an OP1dB of 24.5dBm. The chip area is 3.47 (1.98×1.75) mm2. The last power amplifier also was fabricated in WINTM 0.25-µm GaN technology. A Doherty power amplifier (DPA) adopted a T-type network for the output matching to reduce the chip size and a Lange-coupler for the input matching. The DPA achieved a peak gain of 11.8 dB, a saturation output power of 35.9 dBm, a PAE at 6-dB power back-off of 39.9% and a peak PAE 41.5%. The chip area is 3.03 (1.73×1.75) mm2.
Mahmoud, Mohamed Ahmed. "Adaptive Power Amplifiers for Modern Communication Systems with Diverse Operating Conditions." Thesis, 2013. http://hdl.handle.net/10012/8043.
Повний текст джерелаChang, Yu-Chih, and 張瑜芝. "A 24GHz Doherty Power Amplifier." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/36270064652324302070.
Повний текст джерела國立臺灣大學
電信工程學研究所
99
This research proposes two circuits, one is a Doherty Power Amplifier (DPA), and the other one is a transformer-coupled fully differential power amplifier, both operating at 24 GHz. Although the DPA has been extensively investigated, the effects of DPA at high frequency DPA is still relatively unexplored. Test results, suggest it is hard to achieve high power-added-efficiency (PAE) using DPA construction at higher frequencies. A single-stage 24 GHz DPA fabricated in the TSMC 130-nm CMOS process presented in this thesis, has a measured gain of 6.9 dB, delivered output power is 10 dBm, measured bandwidth is 22.73 % and the chip area is 0.57 mm². However, measured PAE is only 8.3 %, and this single-stage PA consumes 25 mA from a bias voltage of 1.2V. In order to achieve higher PAE and gain without compromising power consumption, I intend to present a differential amplifier with cross-coupled capacitors. To verify this proposed method, a differential circuit and a transformer-coupled fully differential amplifier have been designed for comparison. A simulation test strongly supports the argument that using neutralization technique improves stability. A single-stage PA using this kind of circuit configuration obtains an outstanding bandwidth of 69.6 % vi with same supply voltage, simulated gain is 11.059 dB, PAE is 24.244 % .
Lin, Jhen-Hong, and 林振宏. "Design of CMOS Doherty Power Amplifier." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/gmvnxx.
Повний текст джерела國立中山大學
通訊工程研究所
102
This thesis presents a fully integrated transformer-based Doherty power amplifier in a standard 90 nm CMOS process. Doherty architecture has been proposed to enhancement the average efficiency of the transmitter, and improve efficiency under the back-off. There are two parts of this thesis, the first part is to introduce a traditional linearly power amplifier, and realize a fully integrated class A power amplifier at 2.4 GHz. The cascode structure is used in the power cells since the power amplifier is a fully differential design, a balun is utilized to convert between single-ended and differential signals, and to serve as an impedance matching network. The second part is to realize a fully integrated 2.4 GHz Doherty power amplifier. A main amplifier and an auxiliary amplifier are integrated to have a combined output power. A asymmetrical series combining transformer is used to achieve uneven Doherty operation. The Doherty architecture demonstrates efficiency enhancement under back-off, which is important for high peak-to-average-power-ratio communication systems.
CHEN, HAO-ZHE, and 陳浩哲. "Doherty Power Amplifier Design with Digital Predistortion." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/76e833.
Повний текст джерела國立中正大學
電機工程研究所
106
In this study, a power amplifier is designed for efficiency and linearity by using gallium nitride high electron mobility transistors. The gain of this power amplifier is about 13 dB and the output power is 38 dBm. The architecture of this power amplifier is based on Doherty topology of which having the advantages of high linearity and efficiency. Doherty architecture uses active load modulation technology at output port and combines the characteristics with class AB and class C operations to implement high linearity and efficiency. The final result is that the third-order intermodulation distortion being reduced to be lower than -30 dBc when the output power of the two-tone measurement is 36 dBm and the one-tone input power is 25 dBm. The output power is 38.2 dBm as the efficiency being 41.9 % at 3.2 GHz. The second part of this study is focused on the power amplifier combined with baseband digital pre-distortion methods to improve linearity. This study improves the linearity of power amplifier by taking the memory effects into considerations during employing baseband digital pre-distortion methods. In wireless communication systems, the power amplifier is a crucial component in transmitter. Because of its inherent nonlinear and memory properties, causing signal distorted not only in-band , but also regrowing out-of-band. It affects the power efficiency at the same time. The baseband digital pre-distortion is one of the most effective ways to compensate for distortion. In this study, via Ethernet, Keysight’s SystemVue software was used to control the signal generator and capture the output signals of the power amplifier with the signal analyzer by the software of VSA89600. The resulted power amplifier performance behaves with a EVM value of 1.06% (-39.5 dB) through the assistance of digital pre-distortion.
"Parallel Doherty RF Power Amplifier For WiMAX Applications." Master's thesis, 2018. http://hdl.handle.net/2286/R.I.51661.
Повний текст джерелаDissertation/Thesis
Masters Thesis Electrical Engineering 2018
Yang, Li-Yuan. "Doherty CMOS RF Power Amplifier for Wireless Applications." 2008. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2702200815212200.
Повний текст джерелаHu, Jhe-Hao, and 胡哲豪. "Research on GaAs and GaN Doherty Power Amplifier." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/53s5z7.
Повний текст джерела國立臺灣大學
電信工程學研究所
106
In wireless communication system, when the microwave signal transmits in the air, the receiver could encounter the signal distortion which causes the decoding error due to the noise interference. Therefore, if we can strengthen the transmitting signal and make better signal-to-noise ratio (SNR) of the signal, we can improve the propability of correct decoding for the reason that how to make the power amplifier deliver more output power in wireless transmitter. Besides the high output power, the demand for high efficiency of power amplifier in wireless communication system has increased because power amplifier consumes the most dc power in the transmitter. Therefore, the optimization of the efficiency becomes a key issue. In this thesis, a 38 GHz power amplifier, a 38 GHz quasi-Doherty power amplifier in 0.15-μm depletion mode GaAs pHEMT MMIC process and a 10 GHz 0.25-μm GaN HEMT Doherty power amplifier are proposed. In chapter 2, a 38 GHz power amplifier in 0.15-μm GaAs pHEMT process is proposed to achieve high power and gain. The proposed PA consists of two stage common-source architecture. However, the device size of the power stage and the driver stage are both selected larger than the traditional design. However, the simulated results also achieve high efficiency and gain. In the measurement, due to the lack of thermal consideration, the S-parameter and power performance is lower than the simulated results. In chapter 3, a 10 GHz 0.25-μm GaN HEMT Doherty power amplifier is proposed to improve the back-off efficiency. The main path consists of common source topology and is biased at class-AB to provide enough gain at small-signal. The auxiliary path also consists of common source topology and is biased at class-C to provide high gain at large-signal and to save dc power consumption for small-signal operation. In addition, the PA module is also simulated and measured in this chapter. However, the output power is the watt-level, so the design should be cared about the thermal effect and measured surrounding. Therefore, we set up the environment as cool as possible. In chapter 4, a 38 GHz quasi-Doherty power amplifier in 0.15-μm is used to improve the back-off efficiency. The major drawbacks of the symmetrical DPA architecture is the low current of the class-C peak amplifier at millimeter wave frequency (MMW). Therefore, the main path and auxiliary path both consist of common source topology, which are biased at class-A and class-AB, respectively. The different to chapter 2 are the load impedance and the bias condition choice of each amplifier and the compensation line of the main path. Besides, the input return loss is different from simulated result. The debug result is provided.