Статті в журналах з теми "Dispositifs CMOS et integration"

Abstract : GaN-on-Si HEMTs are emerging as a viable candidate for front-end-of-module (FEM) implementation in 5G and beyond user equipment and small-cell applications [1][2]. This is because GaN HEMTs based power amplifiers and switches have high power handling capability as well as excellent switch figure-of-merit (Ron × Coff). The cost-effective integration of GaN HEMTs on silicon substrates not only benefit from standard CMOS back-end-of-the-line processing but also wafer-level integration with Si-CMOS [1][3], enabling complex functionality and better performance than the standalone counterparts. An example can be a hybrid beamformer where GaN HEMTs can enable much smaller antenna array and therefore a smaller system form factor. For 5G wireless applications, standalone or co-integrated GaN HEMT based FEMs can lead to a more energy efficient and compact system as compared to standalone Si-CMOS technologies. However, for both amplifiers and switches, GaN-on-Si HEMTs present thermal management and substrate loss related issues. In this work, we study and model the impact of GaN HEMT integration on Si substrate on RF substrate losses and non-linearities. The growth of III-N buffer is the most significant factor in determining RF losses and harmonic distortion contribution from the substrate. High temperature annealing and ion implantation steps encountered during HEMT processing can also degrade the substrate performance. In addition, we demonstrate a direct co-relation between substrate losses and harmonic distortion analogous to silicon-on-insulator technologies (Figure 1). However, the bias dependence of RF losses and harmonics show a strong time dependence (memory effects) which is more complex to model [11]. We discuss the approaches to understand and model these effects. References: [1] H. W. Then et al, IEEE IEDM Tech. Dig., 2021, pp. 230-234. [2] B. Parvais et al, IEEE IEDM Tech. Dig., 2020, pp. 155-158. [3] W. E. Hoke et al, J. Vac. Sci. Technol. B 30, 02B101 (2012). [4] Drillet F et al, IJMWT 13, 517–522, 2021. [5] L. Cao et al, CSMANTECH conference Tech. Dig., 2020. [6] Roda Neve et al, IEEE TED, Vol. 59, NO. 4, pp. 924-932, 2012. [7] S. Yadav et al., in IEEE IEDM Tech. Dig., 2020, pp. 159-162. [8] Rack et al, ECS Trans., 92 (4), pp. 79-94, 2019. [9] Zhu et al, IEEE Microw. Wireless Compon. Lett., vol. 28, no. 8, pp. 377–379, 2018. [10] Raskin et al, IEEE SiRFIC, 2015. [11] P. Cardinael et al, IEEE ESSDERC 2021, pp. 303-306. Figure 1

Quantum computers have been attractive because they could realize large-scale and highly complicated calculations that conventional computers cannot solve within a finite time. The large-scale integration of qubits, which are the building block of quantum computers, is required to realize their practical application. Indeed, fault-tolerant quantum computers require the integration of one million qubits. Therefore, silicon qubits is a high-profile candidate because they have advanced process and miniaturization technologies developed with VLSI. In addition, silicon qubits are advantageous in operation temperature. Superconductor qubits operate at the cryogenic temperature at around a few tens mK; in contrast, the operation principle of silicon qubits can operate at a much higher temperature over 1 K. The high-temperature operation can realize quantum computers with small and high-power refrigerators; therefore, we can expect desktop quantum computers instead of ongoing supercomputer-size ones. We must promote integration technology development for silicon qubits; however, the silicon qubit research was mainly in the physics field. Then, nowadays, the integration technology development is accelerated in the world. The challenges are in all conventional research fields: devices, integration, and circuits. We must re-develop the silicon technologies for quantum. For example, on the device design, now we do not have a good tool to design the qubits like TCAD; therefore, we must re-develop the TCAD technologies for quantum [1]. Actually, this is the starting point of our recent research activities; we are going to develop a quantum device simulator, clarify the requirements on the fabrication process of silicon qubits, and propose new technologies to reduce the variability to realize large-scale integration [2]. As for the integration, the quantum calculation circuits require several integrated items: qubits, qubit couplers, micro-magnets, and readout systems. The situation is quite different from the conventional VLSI case for which only the transistors should be integrated. Therefore, we must go re-developing new technologies to integrate all these items. Regarding the circuits, we must use CMOS circuits to generate input signals for qubits and readout the results of quantum calculation, which should be operated at cryogenic temperature. This is so-called “cryo-CMOS.” We must explore a new side of the transistor technologies, which is not investigated so far, because the physics of the MOSFET operation is quite different from the conventional room-temperature operation, hampering the circuit design due to the lack of the device operation model. In this situation, despite the long history of MOSFETs, new phenomena of transistor operation are discovered. For example, the low-frequency current noise increases at a low temperature. The origin of the noise is on the interface traps, instead of the fixed charges in the gate oxides as is the case for room temperature operation [3]. Therefore, we must re-developing CMOS circuit technologies from the bottom of the technologies, device physics. In this presentation, I’m going to overview the status of silicon technology developments for quantum from the viewpoints of devices, integration, and circuits. Also, we introduce some of our recent results to contribute to the developments. Acknowledgment: Our work is supported by MEXT Quantum Leap Flagship Program (Q-LEAP) JPMXS0118069228. [1] H. Asai et al., IEEE Electron Devices Technology and Manufacturing Conference 2021. [2] S. Iizuka et al., Tech. Dig. Symp. VLSI Technology 2021. [3] H. Oka et al., Tech. Dig. Symp. VLSI Technology 2020.

In recent years, two-dimensional (2D) materials-based RRAMs have gained high importance because of their thermal and mechanical stability, and better potentiation-depression controllability. 2D materials based conductive bridge random access memory (CBRAM) has been considered as promising approach for neuromorphic and image processing technology [1]. Despite much progress in CMOS technology, the growth and deposition technology of 2D materials for semiconductor integrated circuit are much complex and is generally available at wafer scale [2]. In addition, high growth temperature for high quality of 2D materials complicates direct wafer growth and makes transfer process desirable. At the device level, challenges are linked to controlled and uniform growth of 2D material for high density electronic structure. Recently, discreet 2D based memristor have been used in crossbar structure as synapse for neuromorphic computing. However, the plasma-assisted chemical vapor reaction (PACVR) based memristor for neuromorphic application are rarely demonstrated. Here, we report the co-integration of plasma-assisted chemical vapor reaction (PACVR) with silicon CMOS technology to provide brain-inspired computing device. PACVR offers compatibility with temperature limited 3D integration process and also provides much better thickness control over a large area. Furthermore, it an easy platform for direct and controlled synthesis of TMDs compared to conventional CVD approach. The PACVR grown WSe2 layer (~2 nm) on silicon substrate is realized, which exhibits both threshold and bipolar switching. The threshold and bipolar switching emulate integrate-fire neuron function and is obtained by modulating the compliance current in the device. The dynamics of the switching is closely related to the diffusive dynamics of the active metal (Ag or Cu) which can be controlled by device current. As a result, the WSe2/Si memristor shows synaptic behavior for neuromorphic system with learning accuracy of 96%. References: Wang, C.-Y. et al. 2D layered materials for memristive and neuromorphic applications. Electron. Mater. 6, 1901107 (2020) Zhang, X. et al. Two-dimensional MoS2-enabled flexible rectenna for Wi-Fi-band wireless energy harvesting. Nature 566, 368–372 (2019). Figure 1

The next-generation internet (6G) requires highly functional devices that e.g. realize frequencies in the THz range for higher data rates and lower latencies. Those requirements exceed the physical limits of established CMOS technologies based on silicon (Si). Hence, there is demand for other semiconductor materials with superior electronic and optical properties that complement Si. One of the key candidates is the III-V compound semiconductor, indium phosphide (InP). Due to its high electron mobility and direct band gap, InP-based devices allow access to frequencies >100 GHz and operate at the optical fibre compatible wavelength of 1.55 μm.1 With the perspective of leveraging the advantages of Si-based CMOS technology and III-V semiconductors, hetero-integration of III-V materials on Si is of great interest. However, existing integration approaches entail certain disadvantages: (i) High dislocation densities due to the lattice mismatch of InP and Si for integration via hetero-epitaxial growth;2 (ii) limited integration density and the requirement of accurate alignment for flip-chip integration; and (iii) high process-related losses of Si and III-V materials as well as thermal stress and low thermal conductivity of adhesive layers degrading device performance for wafer/die bonding technologies.3 Another promising approach for III-V-on-Si integration is micro-transfer-printing (μTP) that involves pick-up and transfer of µm-small chips from a source substrate to a target substrate with high alignment accuracy by using an elastomeric stamp. Advantages of μTP are high integration densities and efficient material use. The technique was already implemented for III-V-on-Si photonic integrated circuits by transfer of epitaxial III-V layers.4 However, using sacrificial III-V interlayers for release and adhesives for bonding still leads to transfer issues and low operation temperature for the devices, respectively. We pursue a new approach to hetero-integration of III-V on Si that aims at the transfer of single-crystalline InP coupons onto Si via μTP. This will be achieved by obtaining crystalline coupons with a thickness of d ≤ 10 µm and two polished surfaces that attain low roughness, needed i.a. for µTP. If the high structural quality of the single-crystalline InP source material can be maintained, this process will provide high quality templates for subsequent epitaxial growth. Towards this goal, we developed a sophisticated micro-preparation process in cooperation with the Leibniz Institute for High Performance Microelectronics IHP.5 Starting from 4-inch single crystals with homogeneous, low dislocation density of 2×103 cm- 2 grown at IKZ,6 thinned InP dies were obtained by sawing, grinding and employing an optimized two-step chemical mechanical polishing (CMP). In order to produce µm-sized transfer-printable coupons, the InP dies were micro structured by means of photolithography assisted patterning and wet (under-)etching (Fig. 1). The coupons can then be picked up with a stamp and transferred to the target wafer. Main innovation of this process is the resin which serves as low stress fixing layer for CMP as well as sacrificial layer for later release. The optimized CMP process with abrasive-free final polishing yielded InP platelets of the desired thickness below 10 μm with low thickness deviation < 1 µm and excellent surface roughness of S q ≈ 0.3 nm (Fig. 2a,b,d). This value even meets the requirements for adhesive-free bonding (S q ≤ 2 nm) and subsequent epitaxial growth (S q ≤ 0.5 nm). X-ray rocking curve mapping provides accurate spatial maps of lattice deformations in the material that may be a consequence of the mechanical processing. Rocking curve widths mappings of the 004 reflection of a (001) sample before and after thinning are homogeneous and below 25 arcsec in the majority of the sample area. Overall no signs of systematic crystal quality deterioration in the product platelets compared to bulk samples have been detected. In summary, the feasibility of μm-thin InP platelet fabrication was demonstrated. Final platelets meet the prerequisites of low and uniform thickness, high planarity, low roughness and little crystal quality deterioration. Furthermore, first InP platelets could successfully be patterned to 100–400 µm-sized coupons using optical lithography and wet etching (Fig. 2c). This opens a path to take the next steps towards hetero-integration on Si by means of µTP with high potential for adhesive-free bonding. References [1] J. C. Rode, et al. IEEE Trans. Electron Devices 2015, 62, 2779–2785. [2] Q. Li, K. M. Lau Prog. Cryst. Growth Charact. Mater. 2017, 63, 105–120. [3] X. Guo, et al. J. Semicond. 2019, 40, 101304. [4] J. Zhang, et al. APL Photonics 2019, 4, 110803. [5] IKZ-IHP Patent filed - DE 10 2022 100 661.1. [6] K. Giziewicz, et al. 51st Annual Meeting of the German Association of Crystal Growth, 2021, Berlin. Figure 1

Non-Von Neumann computing application constituted by artificial synapses based on electrochemical random-access memory (ECRAM) has aroused tremendous attention owing to its capability to perform parallel operations, thus reducing the cost of time and energy spent [1-3]. Existing ECRAM synapses comprise two-terminal memristors and three-terminal synaptic transistors (SynT). While low cost, scalability, and high density are the highlights for memristors, their nonlinear, asymmetric state modulation, high ON current withdrawal, and sneak path in crossbar array integration prevent them from becoming the ideal synaptic elements for artificial neural networks (ANN) [4]. SynT configuration, on the other hand, offers an additional electrolyte-gated control from which ion doping content can be monitored via redox reactions, thus decoupling write-read actions and improving the linearity of programming states [5-6]. Nevertheless, existing SynTs suffer from different integration issues stemming from liquid-based ionic conductors and manually exfoliated channels. Moreover, several kinds of SynTs possess highly conductive channels in the range of µS to mS, significantly scaling up the energy spent for analog states reading. Despite having numerous communications on the performance of different ECRAM, a comprehensive electrochemical view of ion intercalation into the active material, the main root of conductance modulation, is clearly missing. In this work, we present the elaboration procedure of an all-solid-state synaptic transistor composed of nanoscale electrolyte and channel layers. The devices have been elaborated on 8’’ Silicon wafers using microfabrication processes compatible with conventional semiconductor technology and CMOS back end of line (BEoL) integration. (Figure 1a) We demonstrate the excellent synaptic plasticity properties of short-term potentiation (STP) and long-term potentiation (LTP) of our SynT. We performed tests to study the correlation between linearity, asymmetry, and the number of analog states. By averaging the amount of injected ions per write operation, we estimated the energy consumed for switching among adjacent states of this device is 22.5 pJ, yielding area-normalized energy of 4 fJ/µm2. In addition, operating in the range of nS, our SynTs meet the critical criteria of low energy consumption for both write and read operations. Endurance was highlighted by cycling in ambient conditions with 100 states of potentiation and depression for over 1000 cycles with only a slight variation of Gmax/Gmin ratio of 6.2 % (Figure 1b, c). Approximately 95 % accuracy in MNIST pattern recognition test on ANN in the crossbar array configuration has been obtained by simulation with SynTs as synaptic elements reassured SynT is a promising candidate for future neuromorphic computing hardware. To shed light on the properties of intercalation phenomena of Li ions into the TiO2 layer, a further electrochemical study on a cell comprising Ti/TiO2/LiPON/Li corresponding to the SynT gate stack was performed. This understanding will help to elucidate the correlation with conductance modulation characteristics for a synaptic transistor. Multiple tests were carried out, including cyclic voltammetry (CV) with different scan rates, rate capability with Galvanostatic cycling with potential limit (GCPL), and electrochemical impedance spectroscopy (EIS) on different states of charge. A circuit model was introduced to fit the frequency response of the cell, and it explained well the behavior of charging capability at different OCV (Figure 1d). References [1] P. Narayanan et al., “Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory,” IBM J. Res. Dev., vol. 61, no. 4/5, p. 11:1-11:11, Jul. 2017, doi: 10.1147/JRD.2017.2716579. [2] J. Tang et al., “ECRAM as Scalable Synaptic Cell for High-Speed, Low-Power Neuromorphic Computing,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2018, p. 13.1.1-13.1.4. doi: 10.1109/IEDM.2018.8614551. [3] Y. Li et al., “In situ Parallel Training of Analog Neural Network Using Electrochemical Random-Access Memory,” Front. Neurosci., vol. 15, p. 636127, Apr. 2021, doi: 10.3389/fnins.2021.636127. [4] M. A. Zidan, H. A. H. Fahmy, M. M. Hussain, and K. N. Salama, “Memristor-based memory: The sneak paths problem and solutions,” Microelectron. J., vol. 44, no. 2, pp. 176–183, Feb. 2013, doi: 10.1016/j.mejo.2012.10.001. [5] Y. van de Burgt et al., “A non-volatile organic electrochemical device as a low-voltage artificial synapse for neuromorphic computing,” Nat. Mater., vol. 16, no. 4, pp. 414–418, Apr. 2017, doi: 10.1038/nmat4856. [6] E. J. Fuller et al., “Li-Ion Synaptic Transistor for Low Power Analog Computing,” Adv. Mater., vol. 29, no. 4, p. 1604310, Jan. 2017, doi: 10.1002/adma.201604310. Figure 1

D-band (110-170GHz) spectrum is gaining attention for various applications, including 6G mm-Wave, sub-THz sensing, and radar. These systems require lattice spacing for antenna elements at sub-1mm and a very low loss signal path from antenna to integrated chip. A highly efficient front-end in a very small form factor will be required for these systems. This drives the requirement for a monolithically integrated high-gain, high-efficiency front-end that also leverages the benefits of a high-speed / high-density digital CMOS. Silicon germanium (SiGe) heterojunction bipolar transistors (HBT) integrated along with a high-density CMOS provide such an all-silicon monolithic solution. The US government is fostering the expansion of “unique and differentiated domestic manufacturing” with funding through DARPA’s Technologies for Mixed-mode Ultra Scaled Integrated Circuits (T-MUSIC) [1] program to enable disruptive RF mixed-mode technologies by developing high performance RF analog integrated with advanced digital CMOS. Through the T-MUSIC program, DARPA seeks to: 1) advance RF and mixed-mode devices to support ultra-wideband RF frontends from HF to 100 GHz; 2) integrate those devices with high density digital CMOS electronics at the wafer scale to enable embedded digital intelligence; 3) develop and explore ultra-high resolution broadband mixed-mode circuit building blocks for DoD-relevant applications; 4) explore innovative device topologies and materials to form THz devices in an advanced digital CMOS fabrication platform; and 5) establish a domestic ecosystem that facilitates enduring DoD access to differentiated capabilities for high performance RF mixed-mode SoCs. Under T-MUSIC, GlobalFoundries is demonstrating BiCMOS on 45nm PDSOI, which is the focus of this paper, and 22nm FDSOI CMOS with goals of increasing HBT performance of fT/fMAX from 350/500 GHz to 400/600 GHz and 600/700 GHz. HBTs with fT/fMAX of 380/550GHz GHz have been demonstrated building upon previously published results [2]. This paper will touch on some of the challenges that were encountered in achieving that result and discuss those anticipated in future work. Achieving these results required scaling transistor dimensions. Vertical scaling of the emitter, base and collector layers, with higher doping concentrations, reduces transit time but results in higher current densities and higher electric fields. Lateral scaling of the transistor structure reduces parasitic capacitance and resistance but concentrate the power dissipation in a smaller area. The thermal conductivity of silicon is 148W/m-K whereas that of silicon dioxide is ~1.4W/m-K. Even a thin layer of oxide will significantly increase the self-heating of the HBT. Therefore, we replace the SOI with coplanar epitaxy in regions where the HBTs are formed. The vertical scaling of the HBT requires limiting the thermal cycles that the HBT will experience during processing and suggests forming the HBT as late as possible in the CMOS process. However, the thermal cycles associate with the epitaxy and film depositions to form the HBT impact the CMOS transistors which suggests forming the HBT early in the process. We found a point in the process that offers the best compromise minimizing the impact to the doped-channel PDSOI CMOS while achieving the HBT performance goals. Work is just beginning on integration tradeoffs for FDSOI with metal gate and high-K dielectrics. Advanced-node CMOS processes can form components having smaller dimensions which offers advantages for lateral scaling but also presents challenges for forming the HBT. The contact height in 45nm is significantly less than the height of the HBT structure used in GF’s 9HP process. We changed the formation of the emitter and base so that the emitter and base contacts are almost coplanar in contrast to 9HP where the emitter was almost twice the height of the base. This problem is being further exasperated as we migrate to 22nm. The shrinking of BEOL wiring dimensions, along with the ability of the HBT to drive high currents, presents challenges in designing within limits imposed by electromigration. The use of wider wires is constrained by metal density rules. The use of stacked metal levels and redundant vias impact the parasitic capacitances and resistances of the interconnects. The paper and presentation will review these, and other challenges encountered in achieving BiCMOS integration of SiGe HBTs with fT/fMAX of 380/550GHz GHz [see figure] on a 45nm PDSOI CMOS and touch future work. This research was developed with funding from the Defense Advanced Research Projects Agency (DARPA) and is Approved for Public Release, Distribution Unlimited. The views, opinions and/or findings expressed are those of the author and should not be interpreted as representing the official views or policies of the Department of Defense or the U.S. Government. [1] https://www.darpa.mil/attachments/T-MUSIC_Proposers%20Day_Presentations_Combined.pdf [2] J. Pekarik et al., 2021 IEEE BCICTS, 2021, pp. 1-4, Figure 1

Nowadays, “more Moore” and “more than Moore” device architectures are becoming more and more complex. In CEA-Leti, we work on the “CoolCubeTM” 3D sequential integration which is based on the stacking of FDSOI devices [1]. We present solutions, at T<500°C, for the integration of SiP Raised Sources & Drains (RSD) in the upper devices without degrading the electrical performances of the bottom ones. We also target a lowering of the RSD resistance and an increase of the electron mobility in the channel of NMOS devices thanks to tensile strain [2]. Such a know-how will be useful to minimize the contact resistance and fabricate other types of devices such as FINFETs or h-GAA (e.g. nano-sheet devices) with Si (110) surfaces. Experiments were carried out in an Applied Materials epitaxy reactor featuring (i) liquid precursor delivery, together with H2, N2 or He carrier gas capability, enabling the use of Cl2; (ii) “High Precision Temperature Control (HPTC)”, allowing excellent LT control and enabling flexible rotation speeds; (iii) “precision flow distribution PFD-III”, enhancing uniformity performances. Selective Epitaxial Growth (SEG) is usually obtained with “co-flow” processes at rather high temperatures (>600°C). Chlorinated precursors (SiH2Cl2 (+ GeH4) + HCl, typically) are then sent simultaneously into the growth chamber. At LT (<500C°C), HCl cannot decompose, however. To overcome those limitations, we used a Cyclic Deposition Etch (CDE) strategy, with non-selective depositions followed by selective chemical vapor etches, to obtain SiP SEG. This strategy allowed us to obtain high quality films, as shown in Fig.1. The Omega-2Theta scans around the (004) X-Ray Diffraction order for tensile SiP (t-SiP) layers grown at T < 500°C with different Phosphorus concentrations were indeed typical of monocrystalline layers, with well-defined and intense peaks together with numerous thickness fringes. The substitutional P contents in those ~ 60 nm thick t-SiP layers were in the 1.02% - 5.42% range. The good layer uniformity in terms of thickness and P content, over a 300mm wafer radius, is shown in figure Fig.2. These layers grown at T <500°C were smooth, as shown in Fig.3, with a 0.21 nm Root Mean Square (RMS) roughness for a 60nm thick Si:P layer, i.e. a value close to the typical RMS roughness for t-SiP layers grown at high temperature with a chlorinated chemistry. The electrical resistivity in various t-SiP layers is plotted in Fig.4 as function of the substitutional phosphorus concentration and for various growth temperatures in the 450°C – 525°C range. Reducing the temperature by 75°C halved the electrical resistivity. We were able to achieve a resistivity as low as 0.21 mOhm.cm for a t-SiP layer with 5.8% of P grown at 450°C. We then evaluated, at first on tests structures without gates, our process selectivity. A top view Scanning Electron Microscopy image of a t-SiP layer grown non-selectively, with numerous amorphous SiP nuclei on SiO2, is shown in Fig 5.a. After some careful optimization, we succeeded in having fully selective processes versus SiO2, as shown in Fig 5.b. We then tested such optimized processes on low density FD-SOI devices with 28 nm design rules. A top-view SEM image of transistors after such a growth is shown in Fig.6. The growth selectivity was excellent, with nitride spacers and hard masks as well as isolations free of a-SiP nuclei for 31 nm of t-SiP with 4.5% of P deposited in the Sources/Drains. The surface was smooth, with a RMS roughness as low as 0.30nm on active areas, as shown in Fig.7. Thanks to High Resolution Reciprocal Space Maps (HR-RSM), we measured a Phosphorus concentration of 4.5% for that SiP layer grown on SOI. The very high quality of that epitaxy layer, with well-defined thickness fringes, is obvious in Fig.8. Cross-sectional Transmission Electron Microscopy (TEM) images such as the one shown in Fig. 9 enabled us to confirm, at the nanoscale, the excellent quality of such layers in RSDs. To sum up, we were able to develop a tensile Si:P process which was shown to be selective, at a temperature lower than 500°C, against SiO2 and SiN. Such t-SiP layers were successfully integrated in the Sources/Drains regions of FD-SOI 28nm devices. The very low material resistivity and the high phosphorus content should yield, notably because of tensile strain, performant NMOS devices in the near future. [1] C. Fenouillet-Beranger et al., IEEE TED 68, 3142-3148 (2021) [2] V. Chan et al., IEEE 2005 Custom Integrated Circuits Conference 2005, pp. 667-674 Figure 1

Following a trend similar to Moore’s low which prevailed for decades for active circuits, RF integrated passive components have reinvented themselves over the years in order to sustain continuous performance and size requirements. Their roadmap is still unrolling, thanks to a wide variety of new materials integration: high-k dielectrics for capacitors[1] ,[2] , magnetic material for inductors [3], aluminium nitride[4] (now scandium doped) for RF filters, or more recently phase-change materials for RF switches[5]. In the last few years, RF integrated passives built upon Lithium-based materials have attracted strong attention because of their state-of-the-art performances and their direct integration on silicon wafers. Lithium-based piezoelectric materials are used since 40 years by the SAW filters industry, which processes LiTaO3 (LTO) or LiNbO3 (LNO) bulk wafers in dedicated fabs. Recently, however, layered SAW devices exploiting thin films of these materials directly on a silicon wafer have exhibited dramatically improved performances. These devices leverage the latest developments in single crystal Li-based layer transfer, or in deposition techniques (PVD, ALD[6], Pulse-Laser-Deposition, ...) of epitaxial, textured, or amorphous Li-based thin films, all of which achievable in industrial grade semiconductor equipments. In this presentation, we will give an overview of the potential of integrating lithium-based materials on silicon through different examples of promising RF components for 5G. First, we will show how the availability of Li-based Piezoelectric-on-Insulator (POI) wafers[7] is a game changer for 5G filtering. We will present very promising perspectives regarding the development of LNO-based Bulk Acoustics Wave filters (BAW)[8] ,[9],[10] which aim at extending the application space of POI SAW filters towards the upper 5G bands and even Wi-Fi 6E [5-7 GHz] . Different examples of Li-based materials integrations will be given3,4,5,[11] . Secondly, we will discuss the potential of a new type of Li-based hybrid micro supercapacitors integrated on silicon. LiPON thin films offer a unique combination of dual properties, being both a dielectric and an electrolyte[12]. Their integration on silicon is not only bringing potentially ultra-high capacitance densities, but also local on-chip energy storage for 5G components, opening a new paradigm in use of the device in a system[13] ,[14] . After that, we will open the horizon of the potential of Li-based materials integration towards other types of RF devices, like RF switchs, and elaborate on their synergy with Li-transistors for neuromorphic applications[15] and with more conventional lithium microbatteries integrated on silicon[16]. Finally, the integration of Lithium in a silicon industrial environment and the remaining challenges will be discussed. The similarities and discrepancies of the different Li-based processes will be analyzed as well as the compatibility with a silicon CMOS and/or microsystem fab, and the potential for wafers size scaling. Risks like sensitivity to humidity and potential Li contamination will be outlined with some relevant preventive protocols in order to make the Lithium integration on silicon a real and credible disruptive solution regarding 5G challenges. [1] F. Roozeboom, et al. ECS 2007 [2] M. Bousquet et al., ECAPD 2014 [3] J. P. Michel et al., IEEE Trans. Magnetics 55, n°7, pp. 1-7 (2019) » [4] A. Reinhardt et al., IFCS 2011 [5] A. Leon et al., IEEE Trans. Microwave Theory and Techniques, vol. 68, n°1, pp. 60-73 (2020)” [6] M. Bedjaoui et al. ECS Meeting (October 10-14, 2021). [7] E. Butaud et al. IEDM 2020 [8] M. Bousquet et al., Proc. IEEE International Ultrasonics Symposium 2019. [9] M. Bousquet et al., Proc. IEEE International Ultrasonics Symposium 2020. [10] A. Reinhardt et al., Proc. Joint Conference of EFTF & IFCS 2021 [11] L. Sauze et al, Thin solid films, 726, may 2021 [12] L. Le Van-Jodin et al, Solid State ionic, 2013 [13] V. Sallaz et al, Journal of Power Source, 2020 [14] V. Sallaz et al. submitted to ECS 2021 [15] N-A Ngyuen et al,” submitted to ECS 2021 [16] S. Oukassi et al, IEDM 2019

3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1]. In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated. References: “Heterogenous Integration Roadmap”, 2022, https://eps.ieee.org/hir “Heterogeneous Integration Enabled by the State-of-the-Art 3DIC and CMOS Technologies: Design, Cost, and Modeling”, X. Lin et al., International Electron Devices Meeting, IEDM Technical Dig., 2021 “Sentaurus Interconnect User Guide”, 2022, https://www.synopsys.com/silicon/tcad “Quantum ATK: An integrated platform of electronic and atomic-scale modelling tools”, S. Smidstrup et al., J. Phys.: Condens. Matter 32, 015901, 2020

This work deals with the wafer-level integration of advanced group III-V devices and integrated circuits on silicon substrate for RF-sensor integration, such as radar functions a very high frequencies beyond 300 GHz [1]. The aim is to achieve both performance improvements on device level, co-integration with digital functions, and advanced integration to achieve a greener usage of material critical to the environment. Submillimeter-Wave frequency bands beyond 300 GHz allow for broadband transmit and receive windows, serviceable to both communications and radar-based applications—increasing data rates and imaging resolutions, respectively. On the other hand, CMOS co-integration is called for by the data acquisition- and other mixed-mode- and fast digital functions. As examples of the integration schemes Terahertz Monolithic Integrated Circuit amplifiers (TMICs) are implemented in an advanced transferred-substrate InGaAs-channel HEMT technology with 20-nm gate length on silicon. The inverted III-V HEMT heterostructure is grown by molecular beam epitaxy (MBE) on 100-mm semi-isolating GaAs wafers and transferred to silicon substrates by using a SiO2-based wafer bond process with subsequent wafer thinning and removal of the GaAs substrate. Thus, only a 100-nm-thick III-V heterostructure layer is remaining on the Si substrate. This advanced transferred-substrate technology also offers the implementation of HEMT devices with backside gate [2,3] to achieve better sub-threshold slope, or field plates to increase both channel confinement and higher breakdown voltages. The 20-nm InGaAs-OI HEMT technology features typical values for the OFF-state breakdown voltage of 5 V and and maximum drain-current density of 1200 mA/mm, respectively. A maximum transconductance of 2400 mS/mm is achieved. The expected cutoff frequency values fT and fmax are above 500 GHz and 1 THz, respectively [4]. A fully passivated back-end-of-line (BEOL) process is used, including three metal layers (MET1–MET3). A NiCr 50 Ohm sq thin-film-resistor layer, as well as an SiN layer for the implementation of MIM capacitors between MET2 andMET3. S-parameter characteristics of a six-stage and nine-stage TMIC amplifiers in the frequency band from 620 to 730 GHz are given as examples. During the on-wafer characterization, the HEMT devices in cascode configuration have been biased at VD= 2 V (1 V drain–source voltage per device) and a current of 350 mA/mm. The measured small-signal gain of the six-stage cascode TMIC amplifier is in the range of 22–25 dB over the frequency range from 670 to above 700 GHz. This corresponds to 4 dB of gain per cascode stage around the 670-GHz frequency range. A nine-stage TMIC amplifier, on the other hand, achieves at least 30 dB of measured gain from 660 to about 700 GHz. This again corresponds to a gain per stage below 4 dB. Such results prove both the advancements in integration as well as state-of-the-art circuit performance co-integrated on silicon. References: [1] B. Gashi et al., "Broadband 400 GHz On-Chip Antenna With a Metastructured Ground Plane and Dielectric Resonator," in IEEE Transactions on Antennas and Propagation, vol. 70, no. 10, pp. 9025-9038, Oct. 2022, doi: 10.1109/TAP.2022.3177527. [2] A. Tessmann et al., "20-nm In0.8Ga0.2As MOSHEMT MMIC Technology on Silicon," in IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2411-2418, Sept. 2019, doi: 10.1109/JSSC.2019.2915161. [3] A. Leuther et al., "InGaAs HEMT MMIC Technology on Silicon Substrate with Backside Field-Plate," 2020 50th European Microwave Conference (EuMC), 2021, pp. 187-190, doi: 10.23919/EuMC48046.2021.9337957. [4] L. John, et al., "High-Gain 670-GHz Amplifier Circuits in InGaAs-on-Insulator HEMT Technology," in IEEE Microwave and Wireless Components Letters, vol. 32, no. 6, pp. 728-731, June 2022, doi: 10.1109/LMWC.2022.3160093.

3D monolithic integration of logic and memory devices has emerged as one of the key enablers for next-generation electronic devices to address the ever-increasing demand for higher integration density, better performance and energy efficiency. BEOL-compatible oxide semiconductors show great potential to revolutionize the field thanks to their unique properties [1]. We present our recent advancement related to BEOL-compatible oxide semiconductors for logic and memory applications. The digital-etch-enabled nanowire transistors and α-IGZO-based eDRAM will first be discussed, followed by the ferroelectric (FE) memories with high performance and novel structures utilizing α-IGZO or ALD-deposited ZnO as the channel. Ultra-scaled amorphous IGZO (α-IGZO) nanowire field-effect transistors (NW-FETs) hold great potential for applications demanding high performance and integration density. To realize the fabrication of high-quality and aggressively-scaled nanowire structures, a novel digital etching method for amorphous α-IGZO materials has been proposed and demonstrated [2]. Confirmed by the SEM images of an α-IGZO nanowire before and after digital etching, a notable nanowire width W NW reduction can be observed. We have the thinnest α-IGZO nanowire achieved by the digital etching with a W NW of approximately 20 nm. By further developing the transistor upon the nanowire, the α-IGZO NW-FET attains a good subthreshold swing (SS) of 80 mV/decade and a high peak extrinsic transconductance (G m, ext) of 612 μS/μm at V DS of 2 V (456 μS/μm at V DS = 1 V). Compared to the previous studies, our IGZO NW-FET achieves one of the highest peak G m values among all IGZO-based FETs. Besides the BEOL compatibility and high on-current, ultra-low subthreshold leakage makes α-IGZO FETs extremely promising for eDRAM. We further investigated the potential of α-IGZO eDRAM by developing the charge-domain compute-in-memory (CiM) [3]. Experiments have demonstrated small SS, large on-state current, and long-time charge retention with our dedicated 4T1C memory cell. With differential cell structure, an even higher tolerance for charge loss can be attained. With experiment-calibrated benchmarking in the VGG-8 network for CIFAR-10 image classification tasks, 2092 TOPS/W power efficiency for the CiM core can be expected, outperforming the prior TFT and CMOS-based CiM approaches, exhibiting significant advantages for ultra-low-power applications. The integration of doped-HfO2 FE material and oxide semiconductor, both BEOL-compatible with large-scale and cost-effective deposition, presents a promising avenue for advancing data storage in the future. We have developed the high-performance α-IGZO Fe-FET with a metal-ferroelectric-metal-oxide-semiconductor (MFMIS) structure as well as the Fe TCAM [4]. The α-IGZO Fe-FET achieves a large memory window of ~3 V with high reliability, while the Fe TCAM reduces the transistor number from 16 to 2 compared to the traditional SRAM-based one. Besides α-IGZO, we believe that ALD-based oxide semiconductors featuring high controllability of film thickness and conformal coverage of the 3D structures can create new opportunities for novel device structure and integration. The fin-gate ZnO Fe-FET stands for a great example while not only outstanding device performance but also suppressed device-to-device variation due to the unique structure have been demonstrated, holding tremendous promise for high-density 3D integration [5]. Acknowledgments: This work is supported by Singapore Ministry of Education (Tier 2: MOE2018-T2-2-154, Tier 1: R-263-000-D65-114). References: [1] S. Dutta et al., IEDM, p. 36.4., 2020. [2] K. Han et al., VLSI, 2021, p. T10-1. [3] J. Liu et al., IEDM, 2021, p. 46.2. [4] C. Sun et al., VLSI, 2021, p. T7-4. [5] Q. Kong et al., IEDM, 2022, p. 12.3.

Abstract—Wafer direct bonding is now a widely spread technique in microelectronics. However in many interesting applications, wafer bonding is not adapted due to size, material or technological node differences. Die to wafer bonding could then lead to innovative devices. After explaining some specific fundamental mechanisms, III/V die to wafer bonding and copper hybrid bonding will be presented for photonic and 3D applications. Introduction SOI or backside image sensors’ fabrication in mass production, for instance, calls upon direct wafer bonding that has become a standard technology available in many industrial microelectronic factories. Direct bonding of 200 mm or 300 mm silicon wafers are nowadays well mastered. For many innovative applications, it could be interesting to introduce new materials like InP, AsGa, GaN on a silicon platform. Heterostructure bonding then needs to be developed. This could be done with wafer-to-wafer bonding. However, wafers made of these new materials usually have diameters much smaller than that of silicon wafers, especially if CMOS are required on the silicon wafers. Indeed, advanced CMOS devices are nowadays only available on 200/300 mm silicon wafers. Even if the bonding of a small wafer on a bigger one is easily feasible, the silicon surface lost will be detrimental to the cost of the device. Moreover, usually, a very small surface of the new material is needed on the silicon wafer. With a wafer-to-wafer bonding (W2W), the new material surface loss will be quite important. Die-to-wafer (D2W) bonding is thus the solution to both issues in order to put only a small amount of new material where it is needed and populate all the active area on silicon wafers. D2W is also interesting in hybrid bonding with silicon wafers. Indeed, D2W enlarges design rules to mix different technologies (material, dies size) on the same bottom wafer while enabling high density of copper interconnects.. Hybrid D2W is then foreseen as being the next step for hybrid bonding in order to widen its application field. Results Starting with the well know fundamental mechanisms of silicon dioxide bonding [1] as well as copper and hybrid surface bonding [2], D2W bonding behavior will be discussed. Some specific features indeed have to be taken into account for die bonding. For instance, all the edge effects, during and after the bonding or the annealing, have a great impact on the bonding energy as well as on the interface defectivity. Moreover, specific bonding techniques using for instance liquid water films can be used only in D2W bonding. If these specific features are under control, very innovative structures can be obtained. It is possible for instance to bond small 3mm*3mm InP dies onto 200mm silicon photonic wafers as shown in Fig.1a [3]. Moreover, hybrid bonding interfaces can also be obtained between 6mm*4mm dies and a 300mm wafer as shown in Fig.1b. Obviously, alignment in mandatory during hybrid bonding. This can be obtained thanks to a die to wafer bonder. However, innovative technologies such as capillary assisted self-assembly can also be really interesting [4 -7]. The electrical characterization of the D2W hybrid bonding connection will be also discussed, showing roughly the same good results as for W2W hybrid bonding. Acknowledgment This work was funded thanks to the French National program “Programme d’Investissement d’Avenir IRT Nanoelec” ANR-10-AIRT-05. References 1 F. Fournel, et al., ECS J. Solid State Sci. Technol. 4, P124 (2015). 2 L.D. Cioccio, et al., J. Electrochem. Soc. 158, P81 (2011). 3 B. Szelag et al., Hybrid III-V/Silicon technology for laser integration on a 200 mm fully CMOS-compatible silicon photonics platform, IEEE J. Sel. Top. Quantum Electron., In Press (2019). 4 A. Jouve, et al., ECTC (2019). 5 T. Fukushima, et al., in 2011 IEEE 61st Electron. Compon. Technol. Conf. ECTC (2011), pp. 2050–2055. 6 E. Bourjot, et al., ECTC(2021) Figure 1

Microelectronics has benefited enormously from electrochemistry, particularly in metallization. Metallizing through-holes in multilevel printed circuit boards was a major, successful application of electroless Cu (1). Electroless Co-based magnetic films deposited on non-magnetic electroless nickel films on rigid aluminum disks propelled the magnetic storage industry for years. A decade or more ago, it looked as if electroless Co(W)(P) was the ideal candidate to replace PVD Ta-based liners for CMOS back-end-of-line (BEOL) builds (2). Its cost undid it, however, despite meeting selectivity, diffusion barrier and reliability requirements. Electrolytic Cu has been an outstanding success for CMOS BEOL interconnect metallization, mostly because of its submicron feature superfilling ability (3). Following such success, electrolytic and electroless deposition methods have never been far from microelectronics researchers’ interest. In this talk, I will describe examples of electrochemical metallization in chip level, power conversion and MEMS areas that I have worked on. MRAM Final Interconnect Level Capping We recently developed a maskless, electroless, high-P-content, Ni(P) capping process for the final Cu bitline wiring level in our STTM MRAM 200 mm wafer test vehicles. This replaced a two litho mask, final aluminum metal interconnect level, drastically shortening process time. This novel protective layer enables functional testing of MRAM device memory state retention in an air atmosphere at elevated temperatures (4). The Ni(P)-coated wafers show virtually unchanged device resistance and magnetoresistance (MR) for MRAM 4Kb arrays. Magnetic Inductor Fabrication Magnetic inductors are increasing in importance in the ongoing development of integrated, on-chip power conversion. The latter is critical for realizing the dream of granular, DC-DC power delivery using dedicated voltage regulators (VR). Traditionally, the large size of the inductor component has impeded efforts to fabricate the VR in one module. We explored potentially manufacturable processes for magnetic-core inductors with enhanced inductance using through-mask electrodeposited Ni45Fe55 (Fig. 1) (5) and electroless Co(W)(P) layers (6). Electroless Co(W)(P) yoke material performed best overall, showing excellent magnetic properties, good magnetic anisotropy and coercivity of less than 0.1 Oe (6). The resistivity of the Co(W)(P) material was about 90-100 µΩcm; a value of 100 µΩcm is desired to limit yoke eddy current loss at high frequencies. Device scaling has finally brought magnetic inductor fabrication within reach of BEOL CMOS fabs. Magnetic Minimotor Fabrication High-aspect-ratio optical or X-ray lithography (LIGA) and electrodeposition processes were used to fabricate variable-reluctance, nearly planar, integrated minimotors with 6-mm-diameter rotors on silicon wafers (7). The motors comprised six electrodeposited Ni81Fe19 (Permalloy) horseshoe-shaped cores that surrounded the rotor. We formed copper coils around each core. LIGA processing provided vertical wall profiles, which were important for the rotor and stator core pole tips (see stator pole tip, feature D, in Fig. 2). We fabricated the rotors separately and slipped them onto the shaft after releasing them from the substrate wafer. Shaft fabrication via electrodeposition occurred as part of the stator fabrication process. The LIGA fabricated minimotor (100 μm thick Permalloy core with 40 μm thick rotor) represented the successful integration of aligned X-ray exposures and planarizing dielectric into a MEMS fabrication process, producing a working, five-layer magnetic motor. I will show some minimotor operational data. [1]. See papers in IBM J. Res. Develop., 28(6) (1984), available online. [2]. See, e.g., Y. Shacham-Diamand et al., J. Electrochem. Soc., 148 (2001) C162. [3]. P. C. Andricacos et al., IBM J. Res. Develop., 42, 567 (1998). [4]. E. J. O'Sullivan et al., 2019 Meet. Abstr. MA2019-02 916; doi: 10.1149/MA2019-02/15/916. [5]. E. J. O'Sullivan et al., ECS Transactions 50(10):93-105, doi: 10.1149/05010.0093ecst. [6]. N. Wang et al., MMM-Intermag, paper HG-11, 2013. [7]. E. J. O'Sullivan et al., IBM J. of Res. Develop., 42, 681 (1998). Acknowledgements The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where some of the fabrication work described in this talk was carried out. Figure 1

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit. [1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

With the introduction of novel stacked CMOS transistor integration schemes such as sequential 3D and CFETs [1,2], there is an increasing need for highly active source/drain layers with a low overall thermal budget. For some integration schemes, processing temperatures below ~ 525°C are desired [3] and in most cases, the contacts need to be formed on the {110} surfaces of exposed Si nanosheets. In this paper, we report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low temperatures using Cyclic-Deposition and Etch (CDE) with HCl/GeH4 as an etchant [4,5], we rely for this work on Cl2-based etching in combination with Si3H8 as a high-order Si precursor [6]. The Si:P layers were grown in a 300 mm ASM Intrepid® ES reduced pressure chemical vapor deposition reactor on Si (001) substrates. Figure 1 shows some typical characteristics for the Si:P layers without etching (“Dep-only”) and CDE Si:P layers below 500°C. As the temperature is lowered, the growth rate and P incorporation for a given PH3 flow decreases substantially, while the active concentration increases. For both the “Dep-only” and CDE layers, a minimum develops in the resistivity which corresponds to a maximum in active concentration as derived from micro-Hall measurements. Due to the etching during CDE, a P-enrichment takes place and the P concentration in the layers is enhanced compared to the “Dep-only” case. A minimum resistivity of 0.28 mOhm.cm (Pact ~ 6e20/cm3) is obtained for CDE at 480°C which is slightly larger than the minimum resistivity of 0.24 mOhm.cm (Pact ~ 1e21/cm3) for the “Dep-only” case at the corresponding temperature. Figure 2 shows the application of the CDE process on wafers with fins. By lowering the deposition time at a constant etching time per cycle, a (wafer-scale) selective regime can be reached. For the “Dep-only” case, quite some defects and nuclei are present on the sidewalls of the Si-fins and the oxide dielectric, respectively, which are finally removed by sufficient Cl2 etching. Figure 3 compares the corresponding X-TEMs of the above fins after “Dep-only” and selective CDE conditions. For the “Dep-only” case we can only observe a mono-crystalline growth in the <100> direction. For other growth directions like <110>, epitaxial breakdown-down occurs resulting in a substantially reduced crystalline thickness. With the use of Cl2 based CDE, a selective growth can be reached as well as a clear structural improvement in the <110> growth direction, which is very important for the application in nanosheet devices. Finally, once a (111) facet is formed, twin defects occur as expected for low temperature Si:P and Si:C:P [7]. The growth behavior of the CDE processes in relevant nanosheet geometries is currently under investigation. References [1] W. Rachmady et al. in Proc. IEDM 2019. [2] C.-Y. Huang et al. in Proc. IEDM 2020. [3] A. Vandooren et al. in Proc. VLSI 2018. [4] N. Loubet et al., Thin Solid Films 520, pp.3149-3154 (2012). [5] J.M. Hartmann et al., Semicond. Sci. Technol. 28, p.025018 (2013). [6] M. Bauer, ECS Trans. 50(9), pp. 499–506 (2012). [7] J. Tolle et al., ECS Trans. 50(9), pp. 491-497 (2012). [8] E. Rosseel et al., ECS Trans. 75(8), pp.347-359 (2016). Figure 1

Abstract. Optical Time-of-Flight measurement gives the possibility to enhance 2-D sensors by adding a third dimension using the PMD principle. Various applications in the automotive (e.g. pedestrian safety), industrial, robotics and multimedia fields require robust three-dimensional data (Schwarte et al., 2000). These applications, however, all have different requirements in terms of resolution, speed, distance and target characteristics. PMDTechnologies has developed 3-D sensors based on standard CMOS processes that can provide an optimized solution for a wide field of applications combined with high integration and cost-effective production. These sensors are realized in various layout formats from single pixel solutions for basic applications to low, middle and high resolution matrices for applications requiring more detailed data. Pixel pitches ranging from 10 micrometer up to a 300 micrometer or larger can be realized and give the opportunity to optimize the sensor chip depending on the application. One aspect of all optical sensors based on a time-of-flight principle is the necessity of handling background illumination. This can be achieved by various techniques, such as optical filters and active circuits on chip. The sensors' usage of the in-pixel so-called SBI-circuitry (suppression of background illumination) makes it even possible to overcome the effects of bright ambient light. This paper focuses on this technical requirement. In Sect. 2 we will roughly describe the basic operation principle of PMD sensors. The technical challenges related to the system characteristics of an active optical ranging technique are described in Sect. 3, technical solutions and measurement results are then presented in Sect. 4. We finish this work with an overview of actual PMD sensors and their key parameters (Sect. 5) and some concluding remarks in Sect. 6.

3D integration is gaining more and more interest for a large panel of applications including CMOS Image Sensor, High Performance Computing, DRAM including HBM stacks and display. Image sensors based on hybrid bonding 3D stacking are the state-of-the-art in imaging applications[1]. Highest integration densities with micron-size pixels are achieved using copper-oxide hybrid bonding in advanced CMOS Image Sensor (CIS) processes. Recently, functional imagers with sub 1 µm pitch of hybrid bonding interconnection have shown great performances in term of reliability [2]. Hybrid bonding low temperature (< 300°C) is increasingly requested by the industry to reduce thermal budget of sensible chips integration such as Image sensors, displays, or memory. Surface Activated Bonding (SAB) is one of the most promising method to enable very low temperature hybrid bonding as very early proposed by Suga et al [3]. Up to know, they have been mainly performed using modified SAB technology [4] or with Oxide recess [5]. In this study, 200 mm wafers with 2.5 µm copper pads spaced 2.5 µm apart (5 µm pitch) in a silicon oxide matrix are used. SAB uses argon atom bombardment as surface activation. This bombardment is performed in UHV (ultra- high vacuum) at room temperature during several tens of seconds. Surface copper oxide is removed during the activation, leaving dangling metallic bonds on copper pads surface. Under UHV, two identical wafers are then immediately bonded at RT under a low pressure of 0.3 MPa. Noteworthy, no precise alignment is performed for this hybrid bonding. In order to better understand bonding behavior, a first part of the study focuses on the etching effect due to argon bombardment. AFM (Atomic force microscope) inspections are performed on such activated hybrid surfaces. Then the SAB bondings are characterized by SAM (Scanning Acoustic Microscopy) with or without annealing at 150°C and 200°C during 2 hours. Once the top silicon is removed by grinding, further characterizations such as TEM (Transmission Electron Microscopy) and ACOM (Automated Crystal Orientation Mapping) are carried out. For comparison purposes, standard atmospheric hybrid bonding samples are also fabricated at an annealing temperature between 200°C and 300°C. They are characterized in the same way. SAB for hybrid bonding proves its relevance in this study. Indeed, all bonded samples are successfully grinded and thinned out leaving only the damascene structure (which thickness is around 1 µm) above the bonding interface. Despite oxide/oxide and copper/oxide weak SAB interface, the thinning success for the non-annealed sample demonstrates that enough copper/copper interfaces are successfully obtained. As first suggested by AFM scans after surface activation (Figure 1) and subsequently confirmed by SAM, optimized CMP dishing and etching generated during the SAB activation step allow contacting the copper pads at room temperature. However, improved bonding closure is shown by SAM on the annealed samples. Besides, TEM sections show an excellent copper bonding interface on every SAB samples, even those without annealing. These characterizations have been performed on both SAB hybrid bonding samples and atmospheric ones, allowing comparing both processes and a better understanding of hybrid SAB ones. As could be seen on figure 2, the great copper bonding quality could be summarized by a rebuilt of the copper grains (triple grain boundaries at the interface) and the presence of few defects in the bonding pads. In addition, ACOM provides information about the crystallography of the copper pads all over a section in the bonding. SAB seems to have an effect on the pad crystallography. This will be discuss regarding the process differences. To sum up, bonding of hybrid surfaces at room temperature is successfully realized thanks to SAB. SAM characterizations after bonding, mechanical strength in grinding and TEM images confirm that this process is more than promising in the field of low temperature hybrid bonding. In the wake of these encouraging results, new vehicles including electric test structures are to be bonded with alignment in a SAB system. This new study will allow not only to validate the process on aligned bonded structures but also to qualify the electrical performances of hybrid SAB. Figure 1

Abstract. In this work an Application Specific Integrated Circuit (ASIC) for an implantable electrochemical biosensor system (SMART implant, Stett et al., 2014) is presented. The ASIC drives the measurement electrodes and performs amperometric measurements for determining the oxygen concentration, potentiometric measurements for evaluating the pH-level as well as temperature measurements. A 10-bit pipeline analog to digital (ADC) is used to digitize the acquired analog samples and is implemented as a single stage to reduce power consumption and chip area. For pH measurements, an offset subtraction technique is employed to raise the resolution to 12-bits. Charge integration is utilized for oxygen and temperature measurements with the capability to cover current ranges between 30 nA and 1 μA. In order to achieve good performance over a wide range of supply and process variations, internal reference voltages are generated from a programmable band-gap regulated circuit and biasing currents are supplied from a wide-range bootstrap current reference. To accommodate the limited available electrical power, all components are designed for low power operation. Also a sequential operation approach is applied, in which essential circuit building blocks are time multiplexed between different measurement types. All measurement sequences and parameters are programmable and can be adjusted for different tissues and media. The chip communicates with external unites through a full duplex two-wire Serial Peripheral Interface (SPI), which receives operational instructions and at the same time outputs the internally stored measurement data. The circuit has been fabricated in a standard 0.5-μm CMOS process and operates on a supply as low as 2.7 V. Measurement results show good performance and agree with circuit simulation. It consumes a maximum of 500 μA DC current and is clocked between 500 kHz and 4 MHz according to the measurement parameters. Measurement results of the on-chip ADC show a Differential Non Linearity (DNL) lower than 0.5 LSB, an Integral Non Linearity (INL) lower than 1 LSB and a Figure of Merit (FOM) of 6 pJ/conversion.

The use of electric vehicles (EVs) can reduce greenhouse gas emissions, air pollution, dependency on fossil fuels, and their adverse health effects on humans. But, we can only utilize the full environmental benefits of EVs when they are charged with renewable energy sources with zero or low carbon emissions. As a solution, Mobarak et al. [1] suggested integrating low-cost, flexible, and thin-film copper indium gallium selenide (CIGS) solar cells directly onto the steel of all the upward-facing body parts of the vehicles. But, this integration of solar cells comes with an aesthetic drawback. Previously, colorful photovoltaics (PVs) have been designed with one-dimensional (1D) photonic crystals or various 1D and 2D metallic nanostructures for aesthetic building-integrated photovoltaics (BIPVs) [2, 3]. However, the functionality of our application differs from that of BIPV as we need maximum absorption of the solar spectrum to obtain maximum conversion efficiency. Thus, we propose replacing the anti-reflective coating (ARC) present in the solar cells with a notch filter (a narrow high-reflection region in the visible range along with high transmission for the rest of the solar spectrum) to obtain colors. High-performance notch filters with a narrow and ultra-steep notch are well known in literature [4, 5]. Generally, high-performance notch filters are designed with a minimum of 45 layers. It is challenging to use filters with many layers on solar cells due to fabrication and thickness complexities. Thus, we created designs with a maximum of 27 layers for possible integration with photovoltaics. We used OptiLayer [6] to simulate our designs and the gradual evolution technique was used to optimize the designs. We performed our simulations with a multilayer structure of alternating high and low refractive indices of 2.09 and 1.45, respectively, on top of a silicon substrate. We optimized this multilayer structure for three reference wavelengths (400 nm, 550 nm, and 700 nm) resembling three colors. Our designs have notch widths of less than 100 nm for all the reference wavelengths with an average of 70% reflection in the high-reflection region and less than 20% reflection in the high-transmission area. To fabricate our designs, we need materials that are transparent to the solar spectrum targeted by the active material of the solar cells. The materials also need to have refractive indices closer to our simulation. Thus, we chose the combination of silicon nitride and silicon dioxide as our high and low refractive index material, respectively [7, 8]. To better understand our designs’ optical characteristics, we fabricated a scaled-down version of our structure with 5-10 layers. We used electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECR-PECVD) to deposit the multilayer structure on silicon wafers. To obtain the silicon nitride and silicon dioxide layers, we used a SiH4/N2/O2/Ar precursor mixture. By tuning the gas flow rate in the reactor chamber, we tuned the stoichiometry and obtained the required refractive index for each layer. To characterize the refractive index and thickness for each layer, we used variable angle spectroscopic ellipsometry (VASE). We made a detailed comparison of our simulation and fabrication results. References [1] M. H. Mobarak, R. N. Kleiman, J. Bauman, Solar-charged electric vehicles: A comprehensive analysis of grid, driver, and environmental benefits, IEEE Transactions on Transportation Electrification 7 (2021) 579–603. doi:10.1109/TTE.2020.2996363. [2] G. Y. Yoo, et al., Multiple-color-generating cu(in,ga)(s,se)2 thin-film solar cells via dichroic film incorporation for power-generating window applications, ACS Applied Materials & Interfaces 9 (2017) 14817–14826. doi:10.1021/acsami.7b01416, pMID: 28406026. [3] K. T. Lee, et al., Colored dual-functional photovoltaic cells, Journal of Optics 18 (2016) 064003. [4] U. Schallenberg, et al., Design and manufacturing of high-performance notch filters, volume 7739, International Society for Optics and Photonics, SPIE, 2010, pp. 720 – 728. doi:10.1117/12.856580. [5] J. Zhang, et al., Design and fabrication of ultra-steep notch filters, Opt. Express 21 (2013) 21523–21529. doi:10.1364/OE.21.021523. [6] OptiLayer, 1994. URL: https://www.optilayer.com/support/faq, accessed: 2021-12-06. [7] A. Z. Subramanian, et al., Low-loss singlemode pecvd silicon nitride photonic wire waveguides for 532–900 nm wavelength window fabricated within a cmos pilot line, IEEE Photonics Journal 5 (2013) 2202809–2202809. doi:10.1109/JPHOT.2013.2292698. [8] W. D. Sacher, et al., Visible-light silicon nitride waveguide devices and implantable neurophotonic probes on thinned 200 mm silicon wafers, Opt. Express 27 (2019) 37400–37418. doi:10.1364/OE.27.037400

The use of 1D and 2D nanomaterials in emerging electronics and sensor technologies is becoming increasingly important due to their unique properties. Here we would like to highlight a scalable process for suspended nanomaterials that provides additional scope for the development of device properties that can be used in advanced concepts ranging from molecular sensing to quantum applications [1]. For example those applications benefit from arrangements as CNT-based nanoresonators with extremely high quality factors [2] usable for quantum bits with long coherence time [3] or suspended sensing nanomaterials for ultra-low power and extremely sensitive gas sensors [4]. Moreover, straining allows to tune intrinsic physical properties of nanomaterials. Thus, the strain-dependence of the band gap (e.g. CNTs <100meV/% [5], MoS2 ~60meV/% [6],) paves the way for integrated-, highly-efficient-, and tunable light sources for on-chip spectrometry in the context of photonic integrated circuits (PICs), as recently reviewed in [7]. Our technological solution to manufacture suspended nanomaterials is aligned with established semiconductor processing chains on 200 mm wafer level and is developed to be modular integrable and compatible with MEMS, MEOMS or CMOS technologies [8]. Along the process chain, we demonstrate wafer-validated deposition processes for semiconducting CNT films which properties can be adjusted with respect to density and even alignment. In particular, for straining aligned CNTs as well as any transferable 2D nanomaterial, we implemented a stressed functional SiO2/SiN layer stack arranged on embedded sacrificial Cu-structures on the wafer surface. After contacting of the nanomaterial and release of sacrificial elements, stressed layers relax, strain and suspend the nanomaterial. This surface engineering approach greatly simplifies the introduction of strain into nanomaterials and makes it accessible for arbitrary device numbers on wafers as well as for monolithic 3D electronic concepts. Unique features include in-plane strains that are applicable in multiaxial directions and can be controlled by designing only two lithography planes. We show that devices with CNTs strained up to 1% determined from Raman spectral analysis, have a positive impact on sensor operation. We show application examples such as a mechanical stress sensor with extremely low on-set sensitivity. References [1] A. Baydin, F. Tay, J. Fan, M. Manjappa, W. Gao, and J. Kono, “Carbon Nanotube Devices for Quantum Technology,” Materials (Basel, Switzerland), vol. 15, no. 4, 2022. [2] J. Moser, A. Eichler, J. Güttinger, M. I. Dykman, and A. Bachtold, “Nanotube mechanical resonators with quality factors of up to 5 million,” Nature Nanotechnology, vol. 9, no. 12, pp. 1007–1011, 2014. [3] I. Khivrich and S. Ilani, “Nanotubes resound better,” Nature Nanotech, vol. 9, no. 12, pp. 963–964, 2014. [4] D.-H. Baek, J. Choi, and J. Kim, “Fabrication of suspended nanowires for highly sensitive gas sensing,” Sensors and Actuators B: Chemical, vol. 284, pp. 362–368, 2019. [5] L. Yang and J. Han, “Electronic structure of deformed carbon nanotubes,” Physical review letters, vol. 85, no. 1, pp. 154–157, 2000. [6] C. R. Zhu et al., “Strain tuning of optical emission energy and polarization in monolayer and bilayer MoS${}_{2}$,” Phys. Rev. B, vol. 88, no. 12, p. 121301, 2013. [7] M. Pandey, C. Pandey, R. Ahuja, and R. Kumar, “Straining techniques for strain engineering of 2D materials towards flexible straintronic applications,” Nano Energy, vol. 109, p. 108278, 2023. [8] S. Bottger, F. Dietz, M. Hartmann, N. Dahra, E. Kaulfersch, and S. Hermann, “Functional CMOS extension with integrated carbon nano devices,” in 2022 Smart Systems Integration (SSI): 27-28 April 2022, Grenoble, France, 2022, pp. 1–4.

CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option to replace finFETs. Reduced gate lengths should be feasible thanks to their improved electrostatics, thus allowing further scaling of the contacted-gate-pitch and of the cell height via a reduced number of metal tracks. Other key characteristics include high design flexibility, with various NS widths possible on a given wafer, and larger drivability per layout footprint by increasing the number of vertically stacked NS per device and/or using wider NS [1,2] (Fig.1). An extension of this technology could in principle be envisioned by strongly reducing the p-n separation in the so-called forksheet configuration [3]. Beyond that, the concept of stacking devices with different polarity on top of each other is also being looked at [4,5]. Other future technology candidates include FETs with vertical transport [6] and non-silicon channels [7]. Each new architecture will have its own specific challenges such as the internal routeability for stacked structures in functional logic blocks (e.g., standard cell or SRAM) but, in general, many elements can be shared by the various branches of the NS family of devices. Overall, a careful balance between drive strength and capacitance is required in NS FETs engineering. In particular, the presence of dielectric inner spacers in-between vertically stacked nanosheets is a critical element, also as it leads to a different growth regime for the source/drain (S/D) epi as compared to the situation in finFETs [8]. This is an important differentiator as channel strain induced by S/D has been traditionally used to boost device performance. The feasibility of continuing using process-induced stress techniques for mobility enhancement is in fact a key challenge for several new architectures, namely for the top device in stacked structures or when S/D are placed in different vertical levels. Moreover, faced with power scaling stagnation, cold computing is also becoming an attractive option to consider for enabling high performance boosting in an energy efficient way. Our results confirm improved DC properties for NS FETs (e.g., subthreshold swing (SS), mobility), with similar mechanisms responsible for their noise behavior at room and low temperatures (300K (RT), 78K) [9]. In addition to the need for the introduction of new transistor technologies, given the increased complexity and cost in back-end-of-line processing, it has also become ever more pressing to address both wiring and power delivery network (PDN) bottlenecks to take full advantage of the scaling performance benefits at transistor level. The concept of moving the PDN to the wafer’s backside (BS) such that it can alleviate routing congestion on its frontside (FS) has been recently gaining traction [10,11]. This is illustrated in Fig.2 wherein, by combining logic and 3D technologies, both wafer sides are used. In our work, after frontside processing, device and carrier wafers are bonded at RT, including a 523K post-bond anneal. Extreme wafer thinning is then implemented prior to nano-through-silicon-vias (n-TSV) definition (landing on the metal-1 level (M1) in the frontside) and backside metallization. Evaluating the impact on scaled transistors from BS processing, our results show similar p/n threshold voltages (VTs) can be obtained with an extra sinter at the end of fabrication. Inclusion of an additional high-pressure H2-anneal prior to the final sinter is also seen to help lower the SS values for pmos without significant IOFF effect. Reliability-wise, constant ramped voltage stress measurements also show no BTI degradation for p/nmos, with additional indication of potential benefits by the final anneal(s) treatment selection. These findings are further corroborated by LF-noise analysis. References [1] N. Loubet et al., VLSI Tech. Dig., 2017, p.230. [2] A. Veloso et al., SSDM Tech. Dig., 2019, p.559. [3] P. Weckx et al., IEDM Tech. Dig., 2019, p.871. [4] W. Rachmady et al., IEDM Tech. Dig., 2019, p.697. [5] C.-Y. Huang et al., IEDM Tech. Dig., 2020, p.425. [6] A. Veloso et al., IEDM Tech. Dig., 2019, p.230. [7] P.-C. Shen et al., Nature, 2021, Vol.593, p.211. [8] G. Eneman et al., ECS Trans., 2020, Vol.98(5), p.253. [9] B. Cretu et al., EuroSOI-ULIS Tech. Dig., 2021. [10] A. Veloso et al., VLSI Tech. Dig., 2021, TFS2-6. [11] https://www.intel.com/content/www/us/en/events/accelerated.html. Figure 1

Ge-on-Si photodiodes have been firstly reported more than twenty years ago opening the way for the integration of IR photodetectors on Si. A tremendous development has been done, moving from vertically illuminated, stand-alone devices, to waveguide integrated arrays of photodetectors and CMOS integrated imagers. Usually, the Ge epilayer act as the absorbing material for the NIR radiation, while Si acts only as a substrate. Here we report on a dual-band Ge-on-Si photodetector where light detection can take place both within the Ge epilayer and the underlying Si substrate: the device responsivity can thus be tuned from the VIS to the SWIR spectral range by means of an external bias. Therefore, the presented device can be implemented as a VIR-SWIR CMOS compatible imager. Two photodiodes in a back-to-back configuration are formed by p-doping the back side of a high resistivity Si wafer and by epitaxially growing a p-i-n heterojunction Ge-on-Si layer on the front side (Fig.1a)). An external bias can be applied to the whole layer stack by means of ohmic contacts formed on the top Ge layer and on the wafer backside (Fig.1b)). When a positive bias is applied between the top and bottom contact, the Ge diode is forward biased while the Si diode is reversed biased. In such a configuration the photocurrent generated within the Si substrate by back illuminating the device, will flow through the external circuit and be detected. By reversing the bias polarity, still maintaining a backside illumination, the photocurrent will be generated within the Ge epilayer: in this way it is possible to tune the device responsivity simply by controlling the external bias. A TCAD model has been set up to optimize doping levels, in particular that of the Si substrate, determining the most effective position the p-n junction within the Si photodiode and investigating the role played by substrate thickness[1]. According with the simulation outcome, a p-type layer has been formed on the backside of an intrinsic Si wafer by spin-on-dopant obtaining a boron-doped layer with an average concentration of 2×1019cm-3 and a thickness of ≈300nm. The epitaxial growth has been performed by low-energy plasma-enhanced chemical vapor deposition (LEPECVD). Firstly, a 200nm thick phosphorous-doped Si layer has been deposited at 760°C followed by 3 µm thick nominally undoped Ge, grown at 500°C. Six thermal annealing cycles between 600-780°C have been performed in-situ to reduce the threading dislocation density. As a final step 150nm of boron-doped Ge have been deposited. Ge mesas with dimensions ranging between 100-500µm have been realized by standard UV-lithography and dry etching on the Ge-on-Si epitaxial layer. The mesas have been etched down to the intrinsic Si surface to electrically isolate the different devices on the same chip. The top ohmic contacts have been realized by e-beam deposition of a Ti/Al metal stack and lift-off. Different bottom ohmic contact have been tested both by depositing two rectangular stripes of Ti/Au or by depositing a transparent ITO layer on the backside of the chip. Optical characterization was performed by means of a lamp-monochromator set-up. The VIS/SWIR bias dependent dual-band operation of the device is demonstrated in Fig.1c), where the spectral responsivity is shown for two different applied voltages. The peak responsivities are 0.41A/W and 0.63A/W at 960nm and 1520nm, respectively. The specific detectivity D* of the device has been found to be 7·1011cmHz1/2/W and 2·1010cmHz1/2/W in the VIS and NIR, respectively[2]. VIS-SWIR single-pixel imaging was performed by mounting the chip on a rastering system comprising a three-axis stage. In this way the pixel can scan the image plane behind a piano-convex lens. Two images, one in the VIS and one in the SWIR, can be obtained by repeating the scanning and changing the polarity of the applied bias at the device Fig.4d). A coloured VIS image has been obtained by repeating the measurements three times with three different optical bandpass filters (450nm, 550nm and 650nm) resulting in three images with R, G, and B components, which have been combined to obtain the final VIS image. In conclusion, we have designed and fabricated a voltage-tunable dual-band photodetector operating in the VIS and SWIR range. The device is based on a couple of p-i-n photodiodes connected back-to-back formed within a Ge-on-Si epitaxial structure. The device architecture enables to electronically select the shorter (400-1100nm) or longer (1000-1600nm) wavelength range with a relatively low applied voltage. VIS-SWIR single-pixel imaging has been performed. [1] A.De Iacovo, et al., Journal of Lightwave Technology, 37(14), 3517(2019). [2] E.Talamas Simola, et al., Opt. Express 27, 8529-8539(2019). Figure 1

Space has been aptly called the “final frontier” (thank you, Star Trek!). The application needs of the global space and aerospace communities are predictably many and varied, ranging from a diverse set of communications and imaging satellites, to the GPS constellation, to microwave and millimeter-wave (mmW) remote sensing to support weather forecasting and climate science, to exploration of other worlds, which include: the mighty James Webb Space Telescope (probing the origins of the universe), the shadowed polar craters of the Moon (the search for water ice), Mars surface (colonization?), and Europa (the search for extraterrestrial life in the water ocean beneath the 10 km ice cap). While classically, orbital satellites were massive, tough to launch, and extremely expensive (a few $Bs), the current (and rapidly accelerating) trend has swung decidedly towards using relatively low-cost (a few $M) and easy to launch constellations of single or multi-U CubeSats (1U = 10x10x10 cm3) to cost-effectively address the plethora of emerging needs. These days, this has been increasingly supported by commercial space ventures (e.g., SpaceX, BlueOrigin et al., vs. the old gang—NASA and DoD), which are proliferating rapidly. As appealing as space is for visioning fun new science and slick applications, it remains a decidedly unfriendly place to visit. Space is the quintessential “extreme environment,” bathed in intense radiation from both our Sun (high energy electrons and protons trapped by the Earth’s magnetosphere in radiation belts) and the cosmos (GeV energy galactic cosmic rays from supernovae). By way of level setting, a satellite in the most benign Earth orbit, Low Earth Orbit (LEO – 160-1000 km up from the surface), experiences 100,000 rad of ionizing radiation dose over mission life. In comparison, 500 rad will do a person in! That is, we are asking a lot of our electronics in such systems, and given the extreme cost constraints of launch weight, adding a few inches of lead shielding is not the ideal solution! In addition, it is mighty chilly in space (2.73 K = -455°F, the cosmic background), and when the sunlight shines on you, it gets uncomfortably warm, very quickly (e.g., on the surface of the Moon, from -180°C to +120°C from darkness to light, within a few moments). Yep, space is a tough place to do business. As I have long argued [1], SiGe HBT BiCMOS technology provides a unique solution for many of the needs of these emerging space systems, including: 1) extreme levels of performance (multi-hundred GHz) with the SiGe HBT and high integration levels with on-board CMOS, for realizing compelling system functionality/unit volume, at low cost; 2) the rapid improvement of all electronic circuit relevant performance metrics with cooling, with operational capability down into the mK quantum regime (SiGe HBTs love chilly weather!); 3) the ability to operate robustly up to 150-200°C, with modest performance loss; 4) the ability to operate robustly over wide temperature ranges (in principle from mK to 150-200°C); 5) built-in robustness to multi-Mrad total ionizing dose radiation; and 6) built-in heavy ion induced latchup immunity (read: those pesky GeV cosmic rays). Long ago (1990s), the notion of creating a low-cost Si-based electronic + photonic integrated circuit (EPIC) “superchip” was envisioned (Soref), which brought together advanced SiGe HBTs (analog, RF-mmW), CMOS (digital), and Si integrated photonics (with the possible exception of a laser, which could be flipped onto the die worse case). In essence, EPICs are a low-cost, high-yielding, reliable, highly integrated Si platform for putting electrons and light into the same conversation! Clearly this represents a paradigm shift to business as usual. Now, with even more compelling system functionality/unit volume, at low cost. Such an EPIC superchip could in principle satisfy all-comers-of-new-needs. While photonics has long been used in space (think solar cells, imagers), EPICs are new to that space game, but possess great potential for the emergent needs in this new vision of CubeSat/SmallSat driven space systems, including, thing like: LIDAR (spacecraft-to-spacecraft positioning); deep space and within-constellation optical communications (huge data rate improvement); and on-spacecraft high bandwidth data transport (think data center in the sky for instruments that spew out tons of data that need to get back home quickly). This field of EPICs in space is only a few years old, but already much has been learned, and results look very encouraging. In this invited talk, I will highlight the current status and the future trends of using SiGe electronic and photonics in space systems. [1] J.D. Cressler, Proc. IEEE, vol. 93, pp. 1559-1582, 2005. Figure 1

Since mid-infrared (MIR) wavelengths have a great potential for optical communication, sensing, and quantum information, Si-based MIR photonic integrated circuits (PICs) have been developed by leveraging Si photonics technology for near-infrared wavelengths. However, the transparency wavelength window of Si is from 1.2 µm to 8 µm, limiting the available wavelengths in the MIR spectrum. Ge is emerging as a waveguide material to overcome this difficulty because Ge is transparent in the entire MIR spectrum. A Ge-on-Si waveguide is one of the promising platform for a MIR PICs. We have also proposed a Ge-on-insulator (GeOI) platform for MIR integrated photonics [1]. The strong optical confinement in a GeOI waveguide enables an ultracompact MIR PIC. Using wafer bonding and smart-cut, a GeOI wafer was successfully fabricated [2]. As a result, we have demonstrated various Ge passive devices, thermo-optic phase shifters, and modulators on a GeOI platform [3][4]. The propagation loss of a GeOI waveguide is one of the issues. The crystal defects induced by hydrogen implantation for smart-cut generates holes in a Ge film. As a result, evening using an n-type Ge donor wafer for smart-cut, a final Ge layer tends to be p-type. Since free-hole absorption in Ge is significant, the propagation loss of a p-type GeOI becomes large. To suppress hole generation, the optimization of the hydrogen implantation conditions was conducted. We found that the higher the implantation energy was, the deeper the center of the defect position was from a Ge surface [5]. When the implantation energy increases from 80 keV to 160 keV, the defects can be removed from a 300-nm-thick Ge device layer, enabling an n-type GeOI wafer. As a result, a low-loss GeOI waveguide with a propagation loss of 2.3 dB/cm was demonstrated. The monolithic integration of Ge passive waveguides and photodetectors (PDs) is also essential for a MIR PIC. We examined the defect-assist photodetection mechanism in a GeOI waveguide with a lateral PIN junction. When a reverse voltage was applied to the PIN junction, the substantial photocurrent was observed at a wavelength of 2 µm for which Ge is transparent. The defect-assist photodetection is expected to be enhanced due to the large intrinsic carrier density in Ge. As a result, the responsivity of 0.25 A/W was obtained at -5 V. In conclusion, we have developed a GeOI photonics platform for MIR wavelengths. We have achieved a low-loss Ge waveguide, PDs, and optical modulators, the indispensable building blocks for large-scale MIR PICs. The functionality of a GeOI platform can be extended with emerging materials including graphene and phase change materials. This work was partly based on the results from the project JPNP13004, commissioned by the New Energy and Industrial Technology Development Organization (NEDO) and supported by JST-Mirai Program Grant Number JPMJMI20A1, JSPS KAKENHI Grant Number JP20H02198, and the Canon Foundation. Reference [1] Z. Zhao, C.-M. Lim, C. Ho, K. Sumita, Y. Miyatake, K. Toprasertpong, S. Takagi, and M. Takenaka, “Low-loss Ge waveguide at the 2-µm band on an n-type Ge-on-insulator wafer,” Opt. Mater. Express, vol. 11, no. 12, pp. 4097–4106, 2021. [2] J. Kang, X. Yu, M. Takenaka and S. Takagi, “Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding,” Materials Science in Semiconductor Processing, vol. 42, Part 2, pp. 259-263, 2016. [3] M. Takenaka et al., “Heterogeneous CMOS Photonics Based on SiGe/Ge and III–V Semiconductors Integrated on Si Platform,” IEEE J. Sel. Top. Quantum Electron., vol. 23, no. 3, pp. 64–76, May 2017. [4] T. Fujigaki, S. Takagi, and M. Takenaka, “High-efficiency Ge thermo-optic phase shifter on Ge-on-insulator platform,” Opt. Express, vol. 27, no. 5, p. 6451, Mar. 2019. [5] Z. Zhao et al., “Low-loss Ge waveguide at the 2-µm band on an n-type Ge-on-insulator wafer,” Opt. Mater. Express, OME, vol. 11, no. 12, pp. 4097–4106, Dec. 2021. [6] Z. Zhao, C.-P. Ho, K. Toprasertpong, S. Takagi, and M. Takenaka, “Monolithic Germanium PIN Waveguide Photodetector Operating at 2 μm Wavelengths,” Optical Fiber Communication Conference (OFC2020), W4G.3, San Diego, 8–12 March 2020.

This article explores the behaviour of small- and medium-sized enterprises (SMEs) regarding mandatory and voluntary measures established by the French government to reduce carbon dioxide (CO2) emissions generated by freight transport operations. Through semi-structured interviews with fourteen SMEs (five shippers, eight carriers and a consultant) located throughout France, this research examines the integration of sustainable development into organizational and decision-making practices since the introduction of these programmes on the French territory. Our qualitative study suggests that active environmental implications stem mainly from the company's internal dynamics, driven by its management, as well as end customers’ expectations. The voluntary policies seem to appeal more to SMEs than the mandatory measures implemented since 2013. This research shows that the carriers surveyed are highly environmentally proactive, regardless of their size. It also sheds light on techniques that could increase the efficiency and widespread adoption of governmental measures, in particular through the increasing use of on-board telematics. Cet article explore le comportement des petites et moyennes entreprises (PME) suite aux dispositifs obligatoires et volontaires mis en place par le gouvernement français pour réduire les émissions de CO2 générées par le transport de marchandises. Grâce à des entretiens semi-directifs réalisés auprès de quatorze entreprises réparties sur le territoire français (cinq chargeurs, huit transporteurs et un consultant), nous examinons la prise en compte du développement durable dans les pratiques organisationnelles et décisionnelles des PME depuis l’apparition de ces dispositifs. Notre étude qualitative suggère que les implications environnementales actives découlent principalement de la dynamique interne de l'entreprise, pilotée par sa direction, ainsi que des attentes des clients finaux. Ce sont les démarches volontaires qui semblent séduire davantage les PME par rapport aux dispositifs obligatoires mis en place depuis 2013. Nous identifions une forte proactivité environnementale des transporteurs interrogés, quelle que soit leur taille. Notre travail apporte également un éclairage sur les techniques qui permettraient d’accroître l’efficacité et l’adoption des dispositifs gouvernementaux, notamment via une utilisation croissante de la télématique embarquée.

Résumé : Dans un contexte de pratiques éducatives en renouvellement, la recherche participative étudie l’apport d’un environnement d’apprentissage hybride pour l’analyse réflexive de stagiaires en enseignement secondaire. Des analyses qualitatives et quantitatives descriptives illustrent le potentiel des dispositifs mis en place pour soutenir l’intégration à un contexte de stage innovateur, une réflexivité diversifiée et la coélaboration de connaissances. Abstract : In the context of evolving educational practices, participatory research is used to study the contribution of a hybrid learning environment when used by student teachers in secondary teaching for reflective analysis. Both quantitative analysis and qualitative descriptives illustrate the potential of the devices and strategies used to support the student teachers in their integration into an innovative practicum context, a diversified reflective practice and knowledge building.

ABSTRACTEngineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies.The Smart Cutä technology, introduced in the mid 1990's by M. Bruel [2] is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs [3], InP [4], SiC [5], GaN [6], Germanium [7] ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates?In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates.[1] B. Ghyselen et al., ICSI3 proc., 173 5 (2003)[2] M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995)[3] E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998)[4] E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999)[5] L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)[6] A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127[7] F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004).[8] B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118[9] H. Larèche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004)[10] G. Meneghesso et al , IEDM 2007, to be published[11] Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004)[12] J. Dorsaz and al., Proceedings, ICNS6 (2005)[13] S.G. Thomas et al., IEEE EDL Vol. 26, July 2005.[14] K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34

The soft error rates per single-bit due to alpha particles in sub-micron technology is expectedly reducedas the feature size is shrinking. On the other hand, the complexity and density of integrated systems are accelerating which demand ecient soft error protection mechanisms, especially for on-chip communication. Using soft error protection method has to satisfy tight requirements for the area and energy consumption, therefore a low complexity and low redundancy coding method is necessary. In this work, we propose a method to enhance Parity Product Code (PPC) and provide adaptation methods for this code. First, PPC is improved as forward error correcting using transposable retransmissions. Then, to adapt with dierent error rates, an augmented algorithm for configuring PPC is introduced. The evaluation results show that the proposed mechanism has coding rates similar to Parity check’s and outperforms the original PPC.Keywords Error Correction Code, Fault-Tolerance, Network-on-Chip. References [1] R. Baumann, Radiation-induced soft errors in advanced semiconductor technologies, IEEETransactions on Device and materials reliability. 5-3 (2005) 305–316. https://doi.org/10.1109/tdmr.2005.853449.[2] N. Seifert, B. Gill, K. Foley, P. Relangi, Multi-cell upset probabilities of 45nm high-k + metal gateSRAM devices in terrestrial and space environments, in: IEEE International Reliability Physics Symposium 2008, IEEE, AZ, USA, 2008, pp. 181–186.[3] S. Lee, I. Kim, S. Ha, C.-s. Yu, J. Noh, S. Pae, J. Park, Radiation-induced soft error rate analyses for 14 nmFinFET SRAM devices, in: 2015 IEEE International Reliability Physics Symposium (IRPS), IEEE, CA, USA, 2015, pp. 4B–1.[4] R. Hamming, Error detecting and error correcting codes, Bell Labs Tech. J. 29-2 (1950) 147–160. https://www.doi.org/10.1002/j.1538-7305.1950.tb00463.x.[5] M. Hsiao, A class of optimal minimum odd-weight-column SEC-DED codes, IBMJ. Res. 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Chen, Error-control coding for data networks, first ed., Springer Science and BusinessMedia, New York, 2012.[16] L. Peterson, B. Davie, Computer networks: a systems approach, fifth ed., Elsevier, New York, 2011.[17] K. Dang, et al., Soft-error resilient 3D Network-on-Chip router, in: 2015 IEEE 7thInternational Conference on Awareness Science and Technology (iCAST), China, 2015, pp. 84–90.[18] K. Dang, et al., A low-overhead soft–hard fault-tolerant architecture, design and managementscheme for reliable high-performance many-core 3D-NoC systems, The Journal of Supercomputing.73-6 (2017) 2705–2729. https://www.doi.org/10.1007/s11227-016-1951-0.[19] D. Ernst, et al., Razor: A low-power pipeline based on circuit-level timing speculation, in: The36th annual IEEE/ACM International Symposium on Microarchitecture, IEEE, CA, USA, 2003, pp. 10–20.[20] H. Mohammed, W. Flayyih, F. Rokhani, Tolerating permanent faults in the input port of the network onchip router, Journal of Low Power Electronics and Applications. 9-1 (2019) 1–11. https://www.doi.org/10.3390/jlpea9010011.[21] G. Hubert, L. Artola, D. Regis, Impact of scaling on the soft error sensitivity of bulk, FDSOI and FinFETtechnologies due to atmospheric radiation, Integration, the VLSI journal. 50 (2015) 39–47. https://www.doi.org/10.1016/j.vlsi.2015.01.003.[22] J.-s. Seo, et al., A 45nm cmos neuromorphic chip with a scalable architecture for learning in networks of spiking neurons, in: 2011 IEEE Custom Integrated Circuits Conference (CICC), IEEE, CA, USA, 2011, pp. 1–4.[23] NanGate Inc., Nangate Open Cell Library 45 nm. http://www.nangate.com, (accessed 16.06.16) (2016).

We review our recent work on optical biosensors based on microring resonators (MRR) integrated with 4x4 multimode interference (MMI) couplers for multichannel and highly sensitive chemical and biological sensors. The proposed sensor structure has advantages of compactness, high sensitivity compared with the reported sensing structures. By using the transfer matrix method (TMM) and numerical simulations, the designs of the sensor based on silicon waveguides are optimized and demonstrated in detail. We applied our structure to detect glucose and ethanol concentrations simultaneously. A high sensitivity of 9000 nm/RIU, detection limit of 2x10-4 for glucose sensing and sensitivity of 6000nm/RIU, detection limit of 1.3x10-5 for ethanol sensing are achieved. Keywords Biological sensors, chemical sensors, optical microring resonators, high sensitivity, multimode interference, transfer matrix method, beam propagation method (BPM), multichannel sensor References [1] Vittorio M.N. Passaro, Francesco Dell’Olio, Biagio Casamassima et al., "Guided-Wave Optical Biosensors," Sensors, vol. 7, pp. 508-536, 2007.[2] Caterina Ciminelli, Clarissa Martina Campanella, Francesco Dell’Olio et al., "Label-free optical resonant sensors for biochemical applications," Progress in Quantum Electronics, vol. 37, pp. 51-107, 2013.[3] Wen Wang (Editor), Advances in Chemical Sensors: InTech, 2012.[4] Lei Shi, Yonghao Xu, Wei Tan et al., "Simulation of Optical Microfiber Loop Resonators for Ambient Refractive Index Sensing," Sensors, vol. 7, pp. 689-696, 2007.[5] Huaxiang Yi, D. S. Citrin, and Zhiping Zhou, "Highly sensitive silicon microring sensor with sharp asymmetrical resonance," Optics Express, vol. 18, pp. 2967-2972, 2010.[6] Zhixuan Xia, Yao Chen, and Zhiping Zhou, "Dual Waveguide Coupled Microring Resonator Sensor Based on Intensity Detection," IEEE Journal of Quantum Electronics, vol. 44, pp. 100-107, 2008.[7] V. M. Passaro, F. Dell’Olio, and F. Leonardis, "Ammonia Optical Sensing by Microring Resonators," Sensors, vol. 7, pp. 2741-2749, 2007.[8] C. Lerma Arce, K. De Vos, T. Claes et al., "Silicon-on-insulator microring resonator sensor integrated on an optical fiber facet," IEEE Photonics Technology Letters, vol. 23, pp. 890 - 892, 2011.[9] Trung-Thanh Le, "Realization of a Multichannel Chemical and Biological Sensor Using 6x6 Multimode Interference Structures," International Journal of Information and Electronics Engineering, Singapore, vol. 2, pp. 240-244, 2011.[10] Trung-Thanh Le, "Microring resonator Based on 3x3 General Multimode Interference Structures Using Silicon Waveguides for Highly Sensitive Sensing and Optical Communication Applications," International Journal of Applied Science and Engineering, vol. 11, pp. 31-39, 2013.[11] K. De Vos, J. Girones, T. Claes et al., "Multiplexed Antibody Detection With an Array of Silicon-on-Insulator Microring Resonators," IEEE Photonics Journal, vol. 1, pp. 225 - 235, 2009.[12] Daoxin Dai, "Highly sensitive digital optical sensor based on cascaded high-Q ring-resonators," Optics Express, vol. 17, pp. 23817-23822, 2009.[13] Adrián Fernández Gavela, Daniel Grajales García, C. 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El estudio de la geometría favorece procesos propios del quehacer matemático y resulta una potente herramienta para resolver situaciones del mundo real. En la actualidad, pese a su presencia en los diferentes diseños curriculares, investigaciones de distintos países destacan su ausencia en las aulas y su estudio con poco sentido. En esta tesis se aborda la problemática de la enseñanza de la geometría en la escuela secundaria argentina. Con fundamento en la Teoría Antropológica de lo Didáctico, se presentan los resultados de un estudio descriptivo e interpretativo. En esta investigación se procuró comprender las características de las organizaciones matemáticas que se proponen estudiar y que se estudian en torno a la geometría en la escuela secundaria de la provincia de Río Negro (Argentina). También se pretendió conocer y comprender las ideas de los profesores acerca del estudio de la geometría en este nivel educativo. La investigación demandó la construcción de un Modelo Praxeológico de Referencia en torno a la geometría en correspondencia con el diseño curricular de la provincia en mención. Este modelo se centró en el estudio del triángulo, poniendo en evidencia la potencialidad de esta figura para el estudio de diferentes nociones de geometría, y sirvió de marco referencial para realizar el análisis de las etapas posteriores de la tesis. El desarrollo de la investigación demandó recoger y analizar el diseño curricular para el estudio de la matemática en la escuela secundaria en la provincia de Río Negro y las producciones registradas en las clases de matemática de estudiantes de los cuatro primeros años de tres escuelas secundarias de dicha provincia. También se realizaron entrevistas en profundidad a los profesores que participaron de la investigación, y que facilitaron los registros de clases de los estudiantes. El análisis de los datos permitió hacer inferencias acerca de la Organización Matemática Propuesta a Enseñar, de la Organización Matemática Estudiada en torno a la geometría y de decisiones didácticas de los profesores para el estudio de la geometría en la escuela secundaria. En esta investigación, los principales resultados indican un reduccionismo de saberes geométricos que se proponen estudiar, los cuales están centrados casi exclusivamente en la geometría plana. En los registros de clases analizados, predomina una estructura que se corresponde con la metodología tradicional de enseñanza. Se asocia al estudio de organizaciones matemáticas puntuales y no se vislumbra un proceso de articulación e integración entre ellas. Las tareas se caracterizan por ser cerradas, demandando la aplicación de una técnica específica para su hacer. Por otra parte, los profesores manifiestan la importancia del estudio de la geometría, relacionándola con situaciones del mundo real, pero esto no se refleja en sus propuestas. Las aplicaciones de las nociones geométricas estudiadas se presentan bajo tareas en contexto pseudo real, generando una actividad matemática reducida y ligada al fenómeno de monumentalización de saberes. Finalmente, en función del análisis de datos realizado y en contraste con el Modelo Praxeológico de Referencia, se identificaron situaciones del mundo real, de las que se derivan tareas que podrían ser estudiadas en este nivel educativo. Además, se retomaron tareas propuestas por los profesores a fin de reformular sus enunciados para que se dirijan a un estudio con sentido para el estudiante. Los resultados reportados indican que es necesario continuar el estudio de dispositivos didácticos que involucren a la geometría en situaciones del mundo real, que ofrezcan a los estudiantes herramientas matemáticas para comprender, describir, representar y transformar el mundo en el que viven. The study of geometry favours mathematical processes and is a powerful tool for solving realworld situations. At present, despite its presence in the different curricular designs, research from different countries highlights its absence in the classroom and its study with little sense. This thesis addresses the problem of geometry teaching in Argentinean secondary school. Based on the Anthropological Theory of the Didactic, we present the results of a descriptive and interpretative study. In this research we attempt to understand the characteristics of the mathematical organizations related to geometry that are usually proposed to study, and those that are effectively studied, in secondary school level in the province of Río Negro (Argentina). In addition, we also seek to know and understand teachers' ideas about the study of geometry at this educational level. This research demanded the construction of a Praxeological Reference Model related to geometry in correspondence with the curricular design in the above mentioned province. This model focused on the study of the triangle, highlighting the potential of this figure for the study of different notions of geometry, and served as a reference framework for the analysis of the subsequent stages of this thesis. On the one hand, the development of the research required the collection and analysis of the curricular design for the study of mathematics in the secondary school in the province of Río Negro. On the other hand, we also included in our study the productions done for mathematics lessons by students coursing the first four years, of three different secondary schools in the province. In-depth interviews were also conducted with the teachers who participated in the research, and who provided the students' class records. The analysis of the data allowed inferences to be made about the Mathematical Organisation Proposed to Teach, the Mathematical Organisation Studied in relation to geometry in secondary schools, and teachers' didactic decisions for the study of geometry in secondary school. In this research, the main results indicate a reductionism of the geometric knowledge that is proposed to be studied, which is centred almost exclusively on plane geometry. In the classroom records analysed, the predominating structure corresponds to the traditional teaching methodology. It is associated with the study of specific mathematical organisations, with no glimpse of articulation and integration among them. These tasks are characterised by being closed, and requiring the application of a specific technique. On the other hand, teachers state the importance of the study of geometry, relating it to real-world situations, but this is not reflected in their proposed activities. The applications of the geometric notions studied are presented under tasks in a pseudo-real context, generating a reduced mathematical activity linked to the phenomenon of monumentalisation of knowledge. Finally, based on the data analysis we carried out and contrasting it with the Praxeological Reference Model, we identified real-world situations that provide geometric tasks that could be studied at this educational level. In addition, tasks proposed by teachers were also taken up in order to reformulate their statements and direct them towards the study meaningful for the student. The results reported indicate that it is necessary to continue studying didactic devices that involve geometry in real-world situations, offering students mathematical tools to understand, describe, represent and transform the world where they live. L'étude de la géométrie favorise les processus mathématiques et constitue un outil puissant pour résoudre des situations du monde réel. Actuellement, malgré sa présence dans des diverses constructions curriculaires, des recherches réalisées dans des différentes de pays soulignent son absence en classe et remarquent que son étude n'a pas de sens. Cette thèse aborde le problème de l'enseignement de la géométrie dans les écoles secondaires argentines. Sur la base de la Théorie Anthropologique de la Didactique, les résultats d'une étude descriptive et interprétative sont présentés. Dans cet travail de recherche nous visons à comprendre les caractéristiques des organisations mathématiques que l'on se propose d'étudier, et ces qui sont effectivement étudiées, en relation à la géométrie aux écoles secondaires dans la province de Río Negro (Argentine). L'objectif est également de comprendre les idées des enseignants sur l'étude de la géométrie à ce niveau d'éducation. La recherche a exigé la construction d'un Modèle Praxéologique de Référence sur la géométrie d’accord avec la conception curriculaire de la province sous étude. Ce modèle se concentrait sur l'étude du triangle, mettant en évidence le potentiel de cette figure pour l'étude de différentes notions de géométrie, et aussi a été utilisé comme cadre de référence pour l'analyse des étapes suivantes de cette thèse. Le développement de ce travail de recherche a demandé la collecte et l'analyse du programme d'études des mathématiques dans l'enseignement secondaire de la province de Río Negro, et aussi des productions enregistrées dans les classes de mathématiques des étudiants des quatre premières années de trois écoles secondaires de la province. Nous avons également mené des entretiens approfondis avec les enseignants qui ont participé à la recherche, et qui ont fourni les dossiers de classe des étudiants. L'analyse des données nous a permis de faire déductions sur l'Organisation Mathématique que l'on se Propose d'enseigner, sur l'Organisation Mathématique étudiée en relation avec la géométrie, et les décisions didactiques des enseignants pour l'étude de la géométrie dans l'école secondaire. Dans cette recherche, les principaux résultats indiquent un réductionnisme des connaissances géométriques, qui sont presque exclusivement centrées sur la géométrie plane. Dans les registres de classe analysés, il y a une prédominance d'une structure qui correspond à la méthodologie d'enseignement traditionnelle. Elle est associée à l'étude d’organisations mathématiques particulières, il n'y a aucune évidence d'un processus d'articulation et d'intégration entre elles, et elles se centrent sur le bloc pratique-technique. Les tâches se caractérisent par le fait qu'elles sont fermées et qu'elles requièrent l'application d'une technique spécifique pour les réaliser. D'autre part, les enseignants soulignent également l'importance de l'étude de la géométrie, en la reliant à des situations du monde réel, mais cela ne se reflète pas dans leurs propositions aux élèves. Les applications des notions géométriques étudiées sont présentées sous la forme de tâches dans un contexte pseudo-réel, qui ne généré qu'une activité mathématique réduite liée au phénomène de monumentalisation des connaissances. Enfin, sur la base de l'analyse des données effectuée et en contraste avec le Modèle Praxéologique de Référence, des situations du monde réel ont été identifiées, à partir desquelles on trouve des tâches qui pourraient être étudiés à ce niveau d'enseignement. En outre, les tâches proposées par les enseignants ont été reprises afin de reformuler leurs déclarations pour les rendre plus significatifs pour les étudiants. Les résultats rapportés indiquent qu'il est nécessaire de poursuivre l'étude de dispositifs didactiques qui impliquent la géométrie dans des situations réelles, afin d’offrir aux élèves des outils mathématiques pour comprendre, décrire, représenter et transformer le monde où ils vivent.