Дисертації з теми "Discrete power switching devices"

Two MOS-Bipolar composite power semiconductor switching devices are proposed and experimentally demonstrated. These devices feature high voltage and high current capabilities, fast switching speeds, simple gate drive requirements, savings in chip area, reverse bias second breakdown ruggedness and large safe operating areas. Application characteristics of the devices for high frequency power inverter circuits are discussed. Monolithic integration of the two composite devices are also proposed.
Ph. D.

In a number of electrical engineering problems, so-called "crossing points" -- the instants at which two continuous-time signals cross each other -- are of interest. Often, particularly in applications using a Digital Signal Processor (DSP), only periodic samples along with a partial statistical characterization of the signals are available. In this situation, we are faced with the following problem: Given limited information about these signals, how can we efficiently and accurately estimate their crossing points?
For example, an audio amplifier typically receives its input from a digital source decoded into regular samples (e.g. from MP3, DVD, or CD audio), or obtained from a continuous-time signal using an analog-to-digital converter (ADC). In a switching amplifier based on Pulse-Width Modulation (PWM) or Click Modulation (CM), a signal derived from the sampled audio is compared against a deterministic reference waveform; the crossing points of these signals control a switching power stage. Crossing-point estimates must be accurate in order to preserve audio quality. They must also be simple to calculate, in order to minimize processing requirements and delays.
We consider estimating the crossing points of a known function and a Gaussian random process, given uniformly-spaced, noisy samples of the random process for which the second-order statistics are assumed to be known. We derive the Maximum A-Posteriori (MAP) estimator, along with a Minimum Mean-Squared Error (MMSE) estimator which we show to be a computationally efficient approximation to the MAP estimator.
We also derive the Cramer-Rao bound (CRB) on estimator variance for the problem, which allows practical estimators to be evaluated against a best-case performance limit. We investigate several comparison estimators chosen from the literature. The structure of the MMSE estimator and comparison estimators is shown to be very similar, making the difference in computational expense between each technique largely dependent on the cost of evaluating various (generally non-linear) functions.
Simulations for both Pulse-Width and Click Modulation scenarios show the MMSE estimator performs very near to the Cramer-Rao bound and outperforms the alternative estimators selected from the literature.

In modern power electronics systems there is a growing trend to replace discrete devices with integrated power electronic modules (IPEMs). In this way, several components can be replaced by a single component. By using prefabricated building blocks, the engineer simplifies the design process, reducing the total design cycle time and cost. By integrating only the necessary components to provide power switching, the end user has a pre-optimized building block with the flexibility to be used in a large variety of applications. Besides simplifying the design process, power modules should be designed in such a way as to improve the performance of the power converter. This begs the question as to how best to judge if one IPEM has better performance than another or better performance than its discrete counterpart. In analyzing a converterâ s performance, popular criteria include efficiency, power density, device stresses, and EMI. All of these criteria are strongly linked to the switching characteristics of the IPEMâ s power devices. This thesis is a comprehensive study of the requirements for obtaining and analyzing the switching characteristics of the IPEMâ s power devices. It outlines the important switching characteristics and the implications of each characteristic on converter performance. It deals with the relevant measurement issues, specifically addressing the minimum requirements, which sensors are most suitable, and problems leading to inaccurate data. A parametric study is conducted to determine the effects of several circuit and operating parameters on the switching characteristics. Using the resulting data and the knowledge from the measurement study, we can decide how to design the testbed layout, what operating conditions should be chosen for testing, and what effects of the tester must be decoupled to truly see the effects of IPEM design. The thesis concludes with the design of standard test equipment and procedures.
Master of Science

The ultimate goal for power electronics is to convert one form of raw electrical energy into a usable power source with the lowest amount of loss. A considerable portion of these losses are due to the use of switching devices themselves. Device losses can be apportioned to conduction loss and switching loss. It is commonly known and practiced that conduction loss can be reduced by driving MOSFETs and IGBTs harder with gate voltages closer to the maximum rating. This lowers the voltage across the device in the path of the amplified current and ultimately reduces power dissipated by the device. However, switching losses of these devices are not as easily characterized or intuitive for power electronics designers. This is mainly due to the fact that the parasitic reactive elements are nonlinear and not as readily documented as I-V characteristics of a given power device. For example, non-linear parasitic capacitances in the device are given for a fixed frequency across a voltage sweep. Parasitic inductance is typically not even mentioned in the datasheet. The switching losses of these devices depend on these mysterious reactances. A functional way to obtain estimates of switching loss is to test the device under the conditions the device will be used. However, this task must be approached carefully in order to accurately measure the voltage and current of the device. Measurement devices also have parasitic impedances of their own that can add or subtract to switching energy during turn on or turn off and create misleading results. Preliminary testing was performed on multiple devices. After preliminary testing and deliberation, a device-measurement printed circuit board was made to easily replace switching devices of the same package. This thesis presents switching loss measurements of medium-power capable devices in the tens of kW range. It also aims to attribute characteristics of switching voltage and current waveforms to the internal structure of the devices. The device tester designed is versatile since the output buffer of the gate drive is comprised of D-PAK totem pole BJTs. This is able to drive both current and voltage driven devices, i.e. SiC J-FETs (current-driven) and other voltage-driven devices (i.e. MOSFETs and IGBTs). It also allows for TO-220 and TO-247 packaged power diodes.
Master of Science

Mes travaux de thèse dans les laboratoires SATIE de ENS de Cachan et Ampère de l’INSA de Lyon se sont déroulés dans le cadre du projet Gestion OptiMisée de l'Energie (GENOME) pour étudier le potentiel de certains composants de puissance (JFET, MOSFET et BJT) en carbure de silicium (SiC) dans des convertisseurs électroniques de puissance dédiés à des applications aéronautiques suite au développement de l'avion plus électrique. La première partie de mes travaux étudie la robustesse de MOSFET et BJT en SiC soumis à des régimes de court circuit. Pour les MSOFET SiC, en soumettant ces transistors à la répétition de plusieurs courts-circuits, nous observons une évolution du courant de fuite de grille qui semble être un bon indicateur de vieillissement. Nous définissons une énergie critique répétitive pour évaluer la robustesse à la répétition de plusieurs courts-circuits. Aucun effet significatif de la température ambiante n’a pu être mis en évidence sur la robustesse des MOSFET et BJT SiC sous contraintes de court-circuit. Pour les MOSFET, nous avons également constaté une élévation significative du courant de fuite de grille en augmentant de 600V à 750V la tension, ce qui se traduit également par une défaillance plus rapide. Après ouverture des boîtiers des MOSFET Rohm ayant présenté un court-circuit entre grille et source après défaillance, on remarque une fusion de la métallisation de source qui vient effectivement court-circuiter grille et source. Dans ce mode de défaillance particulier, le court-circuit entre grille et source auto-protège la puce en lui permettant de s’ouvrir.La deuxième partie de ce mémoire est consacrée à l’étude de JFET, MSOFET et BJT SiC en régime d’avalanche. Les JFET de SemiSouth et les BJT de Fairchild présentent une bonne robustesse à l’avalanche. Mais le test d'avalanche révèle la fragilité du MOSFET Rohm puisqu’il entre en défaillance avant d’entrer en régime d’avalanche. La défaillance du MOSFET Rohm et sa faible robustesse en régime d’avalanche sont liées à l’activation du transistor bipolaire parasite. Le courant d'avalanche n’est qu’une très faible partie du courant dans l’inductance et circule du drain/collecteur à la grille/base pour maintenir le transistor en régime linéaire. Une résistance de grille de forte valeur diminue efficacement le courant d'avalanche à travers la jonction drain-grille pour le JFET.La troisième partie concerne l’étude de la commutation de BJT SiC à très haute fréquence de découpage. Nous avons dans un premier temps cherché à valider des mesures de pertes par commutation. Après avoir vérifié l'exactitude de la méthode électrique par rapport à une méthode calorimétrique simplifiée, nous montrons que la méthode électrique est adaptée à l’estimation des pertes de commutation mais nécessite beaucoup d’attention. En raison de mobilité élevée des porteurs de charge dans le SiC, nous montrons que le BJT SiC ne nécessite pas l’utilisation de diode d’anti-saturation. Enfin, aucune variation significative des pertes de commutation n’a pu être constatée sur une plage de température ambiante variant de 25°C à 200°C.La quatrième partie concentre l’étude du comportement de MOSFET SiC sous contraintes HTRB (High Temperature Reverse Bias) et dans une application diode-less dans laquelle les transistors conduisent un courant inverse à travers le canal, exception faite de la phase de temps mort pendant laquelle c’est la diode de structure qui assurera la continuité du courant dans la charge. Les résultats montrent que la diode interne ne présente aucune dégradation significative lors de la conduction inverse des MOSFET. Le MOSFET Cree testé montre une dérive de la tension de seuil et une dégradation de l’oxyde de grille qui sont plus significatives lors des essais dans l’application diode-less que sous des tests HTRB. La dérive de la tension de seuil est probablement due au champ électrique intense régnant dans l’oxyde et aux pièges de charge dans l'oxyde de grille
My PhD work in laboratories SATIE of ENS de Cachan and Ampère of INSA de Lyon is a part of project GEstioN OptiMisée de l’Energie (GENOME) to investigate the potential of some Silicon carbide (SiC) power devices (JFET, MOSFET and BJT) in power electronic converters dedicated to aeronautical applications for the development of more electric aircraft.The first part of my work investigates the robustness of MOSFET and SiC BJT subjected to short circuit. For SiC MOSFETs, under repetition of short-term short circuit, a gate leakage current seems to be an indicator of aging. We define repetitive critical energy to evaluate the robustness for repetition of short circuit. The effect of room temperature on the robustness of SiC MOSFET and BJT under short circuit stress is not evident. The capability of short circuit is not improved by reducing gate leakage current for MOSFET, while BJT shows a better robustness by limiting base current. For MSOFET, a significant increase in gate leakage current accelerates failure for DC voltage from 600V to 750V. After opening Rohm MOSFETs with a short circuit between gate and source after failure, the fusion of metallization is considered as the raison of failure. In this particular mode of failure, the short circuit between gate and source self-protects the chip and opens drain short current.The second part of the thesis is devoted to the study of SiC JFET, MSOFET and BJT in avalanche mode. The SemiSouth JFET and Fairchild BJT exhibit excellent robustness in the avalanche. On the contrary, the avalanche test reveals the fragility of Rohm MOSFET since it failed before entering avalanche mode. The failure of Rohm MOSFET and its low robustness in avalanche mode are related to the activation of parasitic bipolar transistor. The avalanche current is a very small part of the current in the inductor. It flows from the drain/collector to the gate/base to drive the transistor in linear mode. A high-value gate resistance effectively reduces the avalanche current through the drain-gate junction to the JFET.The third part of this thesis concerns the study of switching performance of SiC BJT at high switching frequency. We initially attempted to validate the switching loss measurements. After checking the accuracy of the electrical measurement compared to calorimetric measurement, electrical measurement is adopted for switching power losses but requires a lot of attention. Thanks to high carrier charge mobility of SiC material, SiC BJT does not require the use of anti-saturation diode. Finally, no significant variation in switching losses is observed over an ambient temperature range from 25°C to 200°C.The fourth part focuses on the study of SiC MOSFET behavior under HTB (High Temperature Reverse Bias) and in diode-less application in which the transistors conduct a reverse current through the channel, except for the dead time during which the body diode ensure the continuity of the current in the load. The results show that the body diode has no significant degradation when the reverse conduction of the MOSFET. Cree MOSFET under test shows a drift of the threshold voltage and a degradation of the gate oxide which are more significant during the tests in the diode-less application than under HTRB test. The drift of the threshold voltage is probably due to intense electric field in the oxide and the charge traps in the gate oxide

The recent application of semiconductor materials, such as GaN, to power electronics has led to the development of a new generation of devices, which promise lower losses, higher operating frequencies and reductions in equipment size. The aim of this research is to study the capabilities of emerging GaN power devices, to understand their advantages, drawbacks, the challenges of their implementation and their potential impact on the performance of power converters. The thesis starts by presenting the development of a simple model for the switching transients of a GaN cascode device under inductive load conditions. The model enables accurate predictions to be made of the switching losses and provides an understanding of the switching process and associated energy flows within the device. The model predictions are validated through experimental measurements. The model reveals the suitability of the cascode device to soft-switching converter topologies. Two GaN cascode transistors are characterised through experimental measurement of their switching parameters (switching speed and switching loss). The study confirms the limited effect of the driver voltage and gate resistance on the turn-off switching process of a cascode device. The performance of the GaN cascode devices is compared against state-of-the-art super junction Si transistors. The results confirm the feasibility of applying the GaN cascode devices in half and full-bridge circuits. Finally, GaN cascode transistors are used to implement a 270V - 28V, 1.5kW, 1 MHz phase-shifted full-bridge isolated converter demonstrating the use of the devices in soft-switching converters. Compared with a 100 kHz silicon counterpart, the magnetic component weight is reduced by 69% whilst achieving a similar efficiency of 91%.

As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors.
Doctor of Philosophy
Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

The trend of electrification in transportation applications has led to the fast development of high-power-density power electronics converters. High-switching-frequency and high-temperature operations are the two key factors towards this target. Both requirements, however, are challenging the fundamental limit of silicon (Si) based devices. The emerging wide-bandgap, silicon carbide (SiC) power devices have become the promising solution to meet these requirements. With these advanced devices, the technology barrier has now moved to the compatible integration technology that can make the best of device capabilities in high-power-density converters. Many challenges are present, and some of the most important issues are explored in this dissertation. First of all, the high-temperature performances of the commercial SiC MOSFET are evaluated extensively up to 200 degree C. The static and switching characterizations show that the device has superior electrical performances under elevated temperatures. Meanwhile, the gate oxide stability of the device - a known issue to SiC MOSFETs in general - is also evaluated through both high-temperature gate biasing and gate switching tests. Device degradations are observed from these tests, and a design trade-off between the performance and reliability of the SiC MOSFET is concluded. To understand the interactions between devices and circuit parasitics, an experimental parametric study is performed to investigate the influences of stray inductances on the MOSFETs switching waveforms. A small-signal model is then developed to explain the parasitic ringing in the frequency domain. From this angle, the ringing mechanism can be understood more easily and deeply. With the use of this model, the effects of DC decoupling capacitors in suppressing the ringing can be further explained in a more straightforward way than the traditional time-domain analysis. A rule of thumb regarding the capacitance selection is also derived. A Power Electronics Building Block (PEBB) module is then developed with discrete SiC MOSFETs. Integrating the power stage together with the peripheral functions such as gate drive and protection, the PEBB concept allows the converter to be built quickly and reliably by simply connecting several PEBB modules. The high-speed gate drive and power stage layout designs are presented to enable fast and safe switching of the SiC MOSFET. Based on the PEBB platform, the state-of-the-art Si and SiC power MOSFETs are also compared in the device characteristics, temperature influences, and loss distributions in a high-frequency converter, so that special design considerations can be concluded for the SiC MOSFET. Towards high-temperature, high-frequency and high-power operations, integrated wire-bond phase-leg modules are also developed with SiC MOSFET bare dice. High-temperature packaging materials are carefully selected based on an extensive literature survey. The design considerations of improved substrate layout, laminated bus bars, and embedded decoupling capacitors are all discussed in detail, and are verified through a modeling and simulation approach in the design stage. The 200 degree C, 100 kHz continuous operation is demonstrated on the fabricated module. Through the comparison with a commercial SiC phase-leg module designed in the traditional way, it is also shown that the design considerations proposed in this work allow the SiC devices in the wire-bond structure to be switched twice as fast with only one-third of the parasitic ringing. To further push the performance of SiC power modules, a novel hybrid packaging technology is developed which combines the small parasitics and footprint of a planar module with the easy fabrication of a wire-bond module. The original concept is demonstrated on a high-temperature rectifier module with SiC JFET. A modified structure is then proposed to further improve design flexibility and simplify module fabrication. The SiC MOSFET phase-leg module built in this structure successfully reaches the switching speed limit of the device almost without any parasitic ringing. Finally, a new switching loop snubber circuit is proposed to damp the parasitic ringing through magnetic coupling without affecting either conduction or switching losses of the device. The concept is analyzed theoretically and verified experimentally. The initial integration of such a circuit into the power module is presented, and possible improvements are proposed.
Ph. D.

With the development of solar energy, power conversion systems responsible for energy delivering from photovoltaic (PV) modules to ac or dc grid attract wide attentions and have significantly increased installations worldwide. Modular power conversion system has the highest efficiency of maximum power point tacking (MPPT), which can transfer more solar power to electricity. However, this system suffers the drawbacks of low power conversion efficiency and high cost due to a large number of power electronics converters. High-power density can provide potentials to reduce cost through the reduction of components and potting materials. Nowadays, the power electronics converters with the conventional silicon (Si) based power semiconductor devices are developed maturely and have limited improvements regarding in power conversion efficiency and power density. With the availability of wide bandgap devices, the power electronics converters have extended opportunities to achieve higher efficiency and higher power density due to the desirable features of wide bandgap devices, such as low on-state resistance, small junction capacitance and high switching speed. This dissertation focuses on the application of wide bandgap devices to the dc-dc power conversion for the modular PV applications in an effort to improve the power conversion efficiency and power density. Firstly, the structure of gallium-nitride (GaN) device is studied theoretically and characteristics of GaN device are evaluated under testing with both hard-switching and soft-switching conditions. The device performance during steady-state and transitions are explored under different power level conditions and compared with Si based devices. Secondly, an isolated high-efficiency GaN-based dc-dc converter with capability of wide range regulation is proposed for modular PV applications. The circuit configuration of secondary side is a proposed active-boost-rectifier, which merges a Boost circuit and a voltage-doubler rectifier. With implementation of the proposed double-pulse duty cycle modulation method, the active-boost-rectifier can not only serve for synchronous rectification but also achieve the voltage boost function. The proposed converter can achieve zero-voltage-switching (ZVS) of primary side switches and zero-current-switching (ZCS) of secondary side switches regardless of the input voltages or output power levels. Therefore, the proposed converter not only keeps the benefits of highly-efficient series resonant converter (SRC) but also achieves a higher voltage gain than SRC and a wide range regulation ability without adding additional switches while operating under the fixed-frequency condition. GaN devices are utilized in both primary and secondary sides. A 300-W hardware prototype is built to achieve a peak efficiency of 98.9% and a California Energy Commission (CEC) weighted efficiency of 98.7% under nominal input voltage condition. Finally, the proposed converter is designed and optimized at 1-MHz switching frequency to pursue the feature of high-power density. Considering the ac effects under high frequency, the magnetic components and PCB structure are optimized with finite element method (FEM) simulations. Compared with 140-kHz design, the volume of 1-MHz design can reduce more than 70%, while the CEC efficiency only drops 0.8% at nominal input voltage condition. There are also key findings on circuit design techniques to reduce parasitic effects. The parasitic inductances induced from PCB layout of primary side circuit can cause the unbalanced resonant current between positive and negative half cycles if the power loops of two half cycles have asymmetrical parasitic inductances. Moreover, these parasitic inductances reflecting to secondary side should be considered into the design of resonant inductance. The parasitic capacitances of secondary side could affect ZVS transitions and increase the required magnetizing current. Because of large parasitic capacitances, the dead-time period occupies a large percentage of entire switching period in MHz operations, which should be taken into consideration when designing the resonant frequency of resonant network.
Doctor of Philosophy
Solar energy is one of the most promising renewable energies to replace the conventional fossils. Power electronics converters are necessary to transfer power from solar panels to dc or ac grid. Since the output of solar panel is low voltage with a wide range and the grid side is high voltage, this power converter should meet the basic requirements of high step up and wide range regulation. Additionally, high power conversion efficiency is an important design purpose in order to save energy. The existing solutions have limitations of narrow regulating range, low efficiency or complicated circuit structure. Recently, the third-generation power semiconductors attract more and more attentions who can help to reduce the power loss. They are named as wide band gap devices. This dissertation proposed a wide band gap devices based power converter with ability of wide regulating range, high power conversion efficiency and simple circuit structure. Moreover, this proposed converter is further designed for high power density, which reduces more than 70% of volume. In this way, small power converter can merge into the junction box of solar panel, which can reduce cost and be convenient for installations.

Wireless power transfer (WPT) with loosely coupled coils is a promising solution to deliver power to a battery in a variety of applications. Due to its convenience, wireless power transfer technology has become popular in consumer electronics. Thus far, the majority of the coupled coils in these systems are planar structure, and the magnetic field induced by the transmitter coil is in one direction, meaning that the energy power transfer capability degrades greatly when there is some angle misalignment between the coupled coils. To improve the charging flexibility, a three–dimensional (3D) coils structure is proposed to transfer energy in different directions. With appropriate modulation current flowing through each transmitter coil, the magnetic field rotates in different directions and covers all the directions in 3D space. With omnidirectional magnetic field, the charging platform can provide energy transfer in any direction; therefore, the angle alignment between the transmitter coil and receiver coil is no longer needed. Compensation networks are normally used to improve the power transfer capability of a WPT system with loosely coupled coils. The resonant circuits, formed by the loosely coupled coils and external compensation inductors or capacitors, are crucial in the converter design. In WPT system, the coupling coefficient between the transmitting coil and the receiving coil is subject to the receiver's positioning. The variable coupling condition is a big challenge to the resonant topology selection. The detailed requirements of the resonant converter in an omnidirectional WPT system are identified as follows: 1). coupling independent resonant frequency; 2). load independent output voltage; 3). load independent transmitter coil current; 4). maximum efficiency power transfer; 5). soft switching of active devices. A LCCL-LC resonant converter is derived to satisfy all of the five requirements. In consumer electronics applications, Megahertz (MHz) WPT systems are used to improve the charging spatial freedom. 6.78 MHz is selected as the system operation in AirFuel standard, a wireless charging standard for commercial electronics. The zero voltage switching (ZVS) operation of the switching devices is essential in reducing the switching loss and the switching related electromagnetic interference (EMI) issue in a MHz system; therefore, a comprehensive evaluation of ZVS condition in an omnidirectional WPT system is performed. And a design methodology of the LCCL-LC converter to achieve ZVS operation is proposed. The big hurdle of the WPT technology is the safety issue related to human exposure of electromagnetic fields (EMF). A double layer shield structure, including a magnetic layer and a conductive layer, is proposed in a three dimensional charging setup to reduce the stray magnetic field level. A parametric analysis of the double shield structure is conducted to improve the attenuation capability of the shielding structure. In an omnidirectional WPT system, the energy can be transferred in any direction; however the receiving devices has its preferred field direction based on its positioning and orientation. To focus power transfer towards targeted loads, a smart detection algorithm for identifying the positioning and orientation of receiver devices based on the input power information is presented. The system efficiency is further improved by a maximum efficiency point tracking function. A novel power flow control with a load combination strategy to charge multiple loads simultaneously is explained. The charging speed of the omnidirectional WPT system is greatly improved with proposed power flow control.
Doctor of Philosophy
Wireless power transfer (WPT) is a promising solution to deliver power to a battery in a variety of applications. Due to its convenience, wireless power transfer technology with loosely coupled coils has become popular in consumer electronics. In such system, the receiving coil embedded in the receiving device picks up magnetic field induced by the transmitter coil; therefore, energy is transferred through the magnetic field and contactless charging is achieved. Thus far, the majority of the coupled coils in these systems are planar structure, and the magnetic field induced by the transmitter coil is in one direction, meaning that the energy power transfer capability degrades greatly when there is some angle misalignment between the coupled coils. To improve the charging flexibility, a three–dimensional (3D) coils structure is proposed to transfer energy in different directions, also known as in omnidirectional manner. With omnidirectional magnetic field, the charging platform can provide energy transfer in any direction; therefore, the angle alignment between the transmitter coil and receiver coil is no longer needed. In a WPT system with loosely coupled coils, the energy transfer capability suffers from weak coupling condition. To improve the power transfer capability, the electrical resonance concept between the inductor and capacitor at the power transfer frequency is adopted. A novel compensation network is proposed to form a resonant tank with the loosely coupled coils and maximize the power transfer at the operating frequency. As for the WPT system with loosely coupled coils, the energy transfer capability is also proportional to the operating frequency. Therefore, Megahertz (MHz) WPT systems are used to improve the charging spatial freedom. 6.78 MHz is selected as the system operation in AirFuel standard, a wireless charging standard for commercial electronics. The zero voltage switching (ZVS) operation of the switching devices is essential in reducing the switching loss and the switching related electromagnetic interference (EMI) issue in a MHz system; therefore, a comprehensive evaluation of ZVS condition in an omnidirectional WPT system is performed. The big hurdle of the WPT technology is the safety concern related to human exposure of electromagnetic fields (EMF). Therefore, a double layer shield structure is first applied in a three dimensional charging setup to confine the electromagnetic fields effectively. The stray field level in our charging platform is well below the safety level required by the regulation agent. Although the energy can be transferred in an omnidirectional manner in the proposed charging platform, the energy should be directed to the target loads to avoid unnecessary energy waste. Therefore, a smart detection method is proposed to detect the receiver coil's orientation and focus the energy transfer to certain direction preferred by the receiver in the setup. The energy beaming strategy greatly improves the charging speed of the charging setup.

Advanced power semiconductor devices have consistently proven to be a major force in pushing the progressive development of power conversion technology. The emerging wide-band-gap (WBG) material based power semiconductor devices are considered as gaming changing devices which can exceed the limit of silicon (Si) and be used to pursue groundbreaking high-frequency, high-efficiency, and high-power-density power conversion. The switching performance of cascode GaN HEMT is studied at first. An accurate behavior-level simulation model is developed with comprehensive consideration of the impacts of parasitics. Then based on the simulation model, detailed loss breakdown and loss mechanism analysis are studied. The cascode GaN HEMT has high turn-on loss due to the reverse recovery charge and junction capacitor charge, and the common source inductance (CSI) of the package; while the turn-off loss is extremely small attributing to unique current source turn off mechanism of the cascode structure. With this unique feature, the critical conduction mode (CRM) soft switching technique is applied to reduce the dominant turn on loss and significantly increase converter efficiency. The switching frequency is successfully pushed to 5MHz while maintaining high efficiency and good thermal performance. Traditional packaging method is becoming a bottle neck to fully utilize the advantages of GaN HEMT. So an investigation of the package influence on the cascode GaN HEMT is also conducted. Several critical parasitic inductance are identified, which cause high turn on loss and high parasitic ringing that may lead to device failure. To solve the issue, the stack-die package is proposed to eliminate all critical parasitic inductance, and as a result, reducing turn on loss by half and avoiding potential failure mode of the cascode GaN device effectively. Utilizing soft switching and enhanced packaging, a GaN-based MHz totem-pole PFC rectifier is demonstrated with 99% peak efficiency and 700 W/in3 power density. The switching frequency of the PFC is more than ten times higher than the state-of-the-art industry product while it achieves best possible efficiency and power density. Integrated power module and integrated PCB winding coupled inductor are all studied and applied in this PFC. Furthermore, the technology of soft switching totem-pole PFC is extended to a bidirectional rectifier/inverter design. By using SiC MOSFETs, both operating voltage and power are dramatically increased so that it is successfully applied into a bidirectional on-board charger (OBC) which achieves significantly improved efficiency and power density comparing to the best of industrial practice. In addition, a novel 2-stage system architecture and control strategy are proposed and demonstrated in the OBC system. As a continued extension, the critical mode based soft switching rectifier/inverter technology is applied to three-phase AC/DC converter. The inherent drawback of critical mode due to variable frequency operation is overcome by the proposed new modulation method with the idea of frequency synchronization. It is the first time that a critical mode based modulation is demonstrated in the most conventional three phase H-bridge AC/DC converter, and with 99% plus efficiency at above 300 kHz switching frequency.
Ph. D.

Thesis (M.S.)--University of Missouri-Columbia, 2008.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on August 14, 2009) Includes bibliographical references.

Le projet industriel français MEGaN vise le développement de module de puissance à base de compostant HEMT en GaN. Une des application industrielle concerne l’aéronautique avec une forte contrainte en isolation galvanique (>100 kV/s) et en température ambiante (200°C). Le travail de thèse a été concentré sur une brique module de puissance (bras d’onduleur 650 V 30 A). L’objectif est d’atteindre un prototype de facteur de forme peu épais, 30 cm2 et embarquant l’ensemble des fonctions driver, alimentation de driver, la capacité de bus et capteur de courant phase. Cet objectif implique un fort rendement énergétique, et le respect de l’isolation galvanique alors que la contrainte en surface est forte. Le manuscrit, outre l’état de l’art relatif au module de puissance et notamment celui à base de transistor GaN HEMT, aborde une solution d’isolation de signaux de commande à base de micro-transformateur. Des prototypes de micro-transformateur ont été caractérisés et vieillis pendant 3000 H pour évaluer la robustesse de la solution. Les travaux ont contribué à la caractérisation de plusieurs composants GaN afin de mûrir des modèles pour la simulation circuit de topologie de convertisseur. Au sein du travail collaboratif MEGaN, notre contribution ne concernait pas la conception du circuit intégré (driver de grille), tout en ayant participé à la validation des spécifications, mais une stratégie d’alimentation du driver de grille. Une première proposition d’alimentation isolée pour le driver de grille a privilégié l’utilisation de composants GaN basse-tension. La topologie Flyback résonante avec clamp permet de tirer le meilleur parti de ces composants GaN mais pose la contrainte du transformateur de puissance. Plusieurs technologies pour la réalisation du transformateur ont été validées expérimentalement et notamment une proposition originale enfouissement du composant magnétique au sein d’un substrat polymère haute-température. En particulier, un procédé de fabrication peu onéreux permet d’obtenir un dispositif fiable (1000 H de cyclage entre - 55 ; + 200°C), avec un rendement intrinsèque de 88 % pour 2 W transférés. La capacité parasite d’isolation est réduite par rapport aux prototypes précédent. Deux prototypes d’alimentations à forte intégration utilisent soit les transistors GaN basse tension (2.4 MHz, 2 W, 74 %, 6 cm2), soit un circuit intégré dédié en technologie CMOS SOI, conçu pour l’application (1.2 MHz, 2 W, 77 %, 8.5 cm2). Le manuscrit propose par la suite une solution intégrable de mesure de courant de phase du bras de pont, basé sur une magnétorésistance. La comparaison expérimentale vis à vis d’une solution à résistance de shunt. Enfin, deux prototypes de convertisseur sont décrits, dont une a pu faire l’objet d’une validation expérimentale démontrant des pertes en commutation réduites
The french industrial project MEGaN targets the development of power module based on GaN HEMT transistors. One of the industrial applications is the aeronautics field with a high-constraint on the galvanic isolation (>100 kV/s) and ambient temperature (200°C). The intent of this work is the power module block (3 phases inverter 650 V 30 A). The goal is to obtain a small footprint module, 30 cm2, with necessary functions such as gate driver, gate driver power supply, bulk capacitor and current phase sensor. This goal implies high efficiency as well as respect of the constraint of galvanic isolation with an optimized volume. This dissertation, besides the state of the art of power modules and especially the GaN HEMT ones, addressed a control signal isolation solution based on coreless transformers. Different prototypes based on coreless transformers were characterized and verified over 3000 hours in order to evaluate their robustness. The different studies realized the characterization of the different market available GaN HEMTs in order to mature a circuit simulation model for various converter topologies. In the collaborative work of the project, our contribution did not focus on the gate driver chip design even if experimental evaluation work was made, but a gate driver power supply strategy. The first gate driver isolated power supply design proposition focused on the low-voltage GaN HEMT conversion. The active-clamp Flyback topology allows to have the best trade-off between the GaN transistors and the isolation constraint of the transformer. Different transformer topolgies were experimentally performed and a novel PCB embedded transformer process was proposed with high-temperature capability. A lamination process was proposed for its cost-efficiency and for the reliability of the prototype (1000 H cycling test between - 55; + 200°C), with 88 % intrinsic efficiency. However, the transformer isolation capacitance was drastically reduced compared to the previous prototypes. 2 high-integrated gate driver power supply prototypes were designed with: GaN transistors (2.4 MHz, 2 W, 74 %, 6 cm2), and with a CMOS SOI dedicated chip (1.2 MHz, 2 W, 77 %, 8.5 cm2). In the last chapter, this dissertation presents an easily integrated solution for a phase current sensor based on the magnetoresistance component. The comparison between shunt resistor and magnetoresistance is experimentally performed. Finally, two inverter prototypes are presented, with one multi-level gate driver dedicated for GaN HEMT showing small switching loss performance

Power Quality (PQ) has gained a lot of importance in the last decade. Several solutions to power quality problems have been proposed and developed. With the advent of solid state technology and power electronics in the power system protection devices, faster switching is achievable. In order to control and minimize the power quality problems which occur in extremely short times of less than 100ms, the need arises for a selection of devices that can switch faster than today. Also, the economic losses that occur in the network due to the power quality problems increase the incentive to transform the existing devices into faster and e fficient devices. This transformation can be seen as valuable from both a technical and economical point of view to the distribution networks today where a large number of customers are connected. However, in order to interpret the value these fast switching devices render to the distribution network a prior study is required. This thesis presents a picture of the devices that can be suitable for fast switching in today’s distribution network, and how to determine their value to the distribution network. Further it summarizes the research work related to this field. The description of the devices and technical aspects is presented first. A literature review of proposed devices is given. The technical aspects of power quality and its problems is described. An approach to estimate the value of the fast switching devices is detailed from different literature. The study shows that fast switching devices can be worthy to invest in when seen from a distribution network’s perspective provided that different technical aspects are taken into account.

A recent International Technology Roadmap for Semiconductors (ITRS) report (2.0, 2015 edition) has shown that Moore’s law is unlikely to hold beyond 2028. There is a need for alternate devices to replace CMOS based devices, if further miniaturization and high energy efficiency is desired. The goal of this dissertation is to experimentally demonstrate the feasibility of nanomagnetic memory and logic devices that can be clocked with acoustic waves in an extremely energy efficient manner. While clocking nanomagnetic logic by stressing the magnetostrictive layer of a multiferroic logic element with with an electric field applied across the piezoelectric layer is known to be an extremely energy-efficient clocking scheme, stressing every nanomagnet separately requires individual contacts to each one of them that would necessitate cumbersome lithography. On the other hand, if all nanomagnets are stressed simultaneously with a global voltage, it will eliminate the need for individual contacts, but such a global clock makes the architecture non-pipelined (the next input bit cannot be written till the previous bit has completely propagated through the chain) and therefore, unacceptably slow and error prone. Use of global acoustic wave, that has in-built granularity, would offer the best of both worlds. As the crest and the trough propagate in space with a velocity, nanomagnets that find themselves at a crest are stressed in tension while those in the trough are compressed. All other magnets are relaxed (no stress). Thus, all magnets are not stressed simultaneously but are clocked in a sequentially manner, even though the clocking agent is global. Finally, the acoustic wave energy is distributed over billions of nanomagnets it clocks, which results in an extremely small energy cost per bit per nanomagnet. In summary, acoustic clocking of nanomagnets can lead to extremely energy efficient nanomagnetic computing devices while also eliminating the need for complex lithography. The dissertation work focuses on the following two topics: Acoustic Waves, generated by IDTs fabricated on a piezoelectric lithium niobate substrate, can be utilized to manipulate the magnetization states in elliptical Co nanomagnets. The magnetization switches from its initial single-domain state to a vortex state after SAW stress cycles propagate through the nanomagnets. The vortex states are stable and the magnetization remains in this state until it is ‘reset’ by an external magnetic field. 2. Acoustic Waves can also be utilized to induce 1800 magnetization switching in dipole coupled elliptical Co nanomagnets. The magnetization switches from its initial single-domain ‘up’ state to a single-domain ‘down’ state after SAW tensile/compressive stress cycles propagate through the nanomagnets. The switched state is stable and non-volatile. These results show the effective implementation of a Boolean NOT gate. Ultimately, the advantage of this technology is that it could also perform higher order information processing (not discussed here) while consuming extremely low power. Finally, while we have demonstrated acoustically clocked nanomagnetic memory and logic schemes with Co nanomagnets, materials with higher magnetostriction (such as FeGa) may ultimately improve the switching reliability of such devices. With this in mind we prepared and studied FeGa films using a ferromagnetic resonance (FMR) technique to extract properties of importance to magnetization dynamics in such materials that could have higher magneto elastic coupling than either Co or Ni.

Thesis (MScEng)--Stellenbosch University, 2013.
ENGLISH ABSTRACT: The increased necessity to obtain power from other sources than conventional fossil fuels has led to the growing interest in solar power. The problem with the proposed technology is that it can only provide power during the day and therefore requires some sort of storage system, if power is to be supplied throughout the day and night. A number of storage systems exist, but the one of particular interest for this research, is packed rock beds. Rock beds have the advantage that if designed right, they have the potential to be one of the most cost effective means of storing thermal energy for solar power plants. Discrete Element Models (DEM) of rock beds were therefore developed through both experimental and numerical procedures, by conducting a series of sensitivity, calibration and verification studies. The developed models were then used to study various aspects associated with rock beds, which were either too impractical, impossible or too expensive to conduct through actual experimental work. This research focused specifically on the potential of constructing self-supporting tunnels within the rock beds in order to improve the air flow uniformity through the bed, while minimizing the pressure drop. It was observed that if the appropriate steps were followed, stable self-supporting tunnels could be formed. Valuable information such as the rock orientations resulting from different packing directions could also be derived from the models and finally, a method to convert the DEM models into the appropriate format such that it could be imported into a CFD preprocessor for future CFD studies, was developed.
AFRIKAANSE OPSOMMING: Die verhoogde noodsaaklikheid om energie te verkry uit ander bronne as konvensionele fossielbrandstowwe, het gelei tot die groeiende belangstelling in sonkrag energie. Die probleem met die voorgestelde tegnologie is dat dit net energie gedurende die dag kan voorsien en dus word daar ’n stoorstelsel benodig indien energie deur beide die dag en nag voorsien moet word. Tans bestaan daar wel ’n aantal van hierdie stoorstelsels, maar die een wat van besondere belang is in hierdie navorsing, is verpakte klip beddens. Klip beddens het die voordeel dat, indien dit reg ontwerp is, dit oor die potensiaal beskik om een van die mees koste-doeltreffende middels te wees vir die stoor van termiese energie vir sonkragstasies. Diskreet Element Modelle (DEM) van die klip beddens is ontwikkel deur gebruik te maak van beide experimentele en numeriese metodes waartydens ’n reeks sensitiwiteits-, kalibrasie- en verifiëring studies uitgevoer is. Die ontwikkelde modelle is gebruik om verskeie aspekte van klip beddens te ondersoek, wat of te onprakties, onmoontlik of te duur is vanuit ’n eksperimentele oogpunt. Hierdie navorsing het spesifiek gefokus op die potensiaal om self-ondersteunende tonnels binne in die klip beddens te vorm, ten einde die egaligheid van die lugvloei deur die bed te verbeter, terwyl die drukval geminimeer word. Daar is waargeneem dat stabiele self-ondersteunende tonnels wel gevorm kon word indien die toepaslike stappe gevolg is. Waardevolle inligting soos die klip oriëntasies wat as gevolg van die verskillende verpakkings rigtings onstaan kon ook vanuit die model verkry word. Ten slotte is ’n metode ontwikkel om die DEM modelle na die toepaslike formaat te omskep sodat dit ten einde gebruik kan word in numeriese vloeidinamika studies.

A mesure que les demandes dans le domaine de l'électronique de puissance tendent vers des conditions de plus en plus extrêmes (forte densité de puissance, haute fréquence, haute température,…), l'évolution des systèmes de traitement de l'énergie électrique se heurte aux limites physiques du silicium. Une nouvelle approche basée sur l'utilisation des matériaux semi-conducteurs grand gap permettra de lever ces limites. Parmi ces matériaux, le diamant possède les propriétés les plus intéressantes pour l'électronique de puissance: champ de rupture et conductivité thermique exceptionnels, grandes mobilités des porteurs électriques, possibilité de fonctionnement à haute température… Les récents progrès dans la synthèse du diamant par des méthodes de dépôt en phase vapeur (CVD) permettent d'obtenir des substrats de caractéristiques cristallographiques compatibles avec l'exploitation de ces propriétés en électronique de puissance. Cependant, l'utilisation du diamant en tant que matériau électronique reste toutefois délicate à ce jour du fait de la grande difficulté de trouver des dopants convenables (en particulier les donneurs) dans le diamant. En outre, certaines propriétés du diamant telles que sa dureté extrême et son inertie chimique, faisant de lui un matériau unique, posent aussi des difficultés dans son utilisation technologique. L'objectif de ces travaux de thèse a été dans un premier temps d'évaluer les bénéfices que pourrait apporter le diamant en électronique de puissance ainsi que l'état de l'art de sa synthèse par dépôt en phase vapeur. Ensuite, différentes étapes technologiques nécessaires à la fabrication de composants sur diamant ont été étudiées: Gravure RIE, dépôt de contacts électriques. Enfin, ces travaux ont été illustrés par la réalisation et la caractérisation de diodes Schottky, dispositifs élémentaires de l'électronique de puissance. Les résultats obtenus permettent d'établir un bilan des verrous scientifiques et technologiques qu'il reste à relever pour une exploitation industrielle de la filière diamant
As applications in the field of power electronics tend toward more extreme conditions (high power density, high frequency, high temperature ...), evolution of electric power treatment systems comes up against physical limits of silicon, the main semiconductor material used in electronic industry for over 50 years. A new approach based on the use of wide bandgap semiconductor materials will permit to overcome those limits. Among these materials, diamond is a very attractive material for power electronics switch devices due to its exceptional properties: high electric breakdown field, high carriers mobilities, exceptional thermal conductivity, high temperature operating possibility... However, the use of diamond as an electronic material is still very problematic due to the difficulty in the synthesis of high electronic grade CVD diamond and to find suitable dopants (in particular donors) in diamond. Besides, some of the unique properties of diamond, such as its extreme hardness and chemical inertness that make it an attractive material also cause difficulties in its application. Nevertheless, recent progress in the field of chemical vapor deposition (CVD) synthesis of diamond allow the study of the technological steps (RIE etching, ohmic and Schottky contacts, passivation,...) necessary for future diamond power devices processing. This is the aim of this thesis. In a first section, the uniqueness of diamond, the promise it bears as a potential material for specific electronic devices and the difficulties related to its application were reviewed. Then, the different technological steps required for power switching devices processing were studied: RIE etching, Ohmic and Schottky contacts. Finally, these works were illustrated by carrying out and electrical characterizations of Schottky Barrier Diodes. The achieved results allow us to make a summary of scientific and technological locks that remain for an industrial exploitation of diamond in power electronic switch devices field

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior
This work presents the analysis, design example, simulations and experimental results on a soft-switching bidirectional isolated three-phase dc-dc converter using dual phase-shift control with variable duty cycle. The topology uses three single H-bridges in the primary side and a three-phase inverter in the secondary side. High-frequency isolation is ensured by using three single-phase transformers connected in open delta-wye configuration. The variation of both phase-shift (PS) angles between the H-bridge legs and/or primary and secondary sides allows controlling the power flow, while reduced reactive power flow is possible. The variable duty cycle is used to ensure a constant voltage bus and/or zero voltage switching (ZVS) operation. A detailed analysis is presented considering a model based on the fundamental components for the voltages and currents in the transformer and, aiming its validation, a second analysis from the operation stages of the converter has also been developed. Besides, the dynamic model of the converter, based on fundamental components and employing the gyrator theory has been developed. A design example with nominal values assumptions, stresses and specifications for components, discrete control system characterization and its FPGA programming are presented. Simulation and experimental results in steady state and closed-loop performance are presented and discussed to validate the proposed approach.
Este trabalho apresenta a anÃlise, exemplo de projeto, simulaÃÃes e resultados experimentais de um conversor CC-CC trifÃsico isolado bidirecional com comutaÃÃo suave, dual phase shift (DPS) e razÃo cÃclica variÃvel. A topologia utiliza trÃs pontes H monofÃsicas no lado primÃrio e um inversor trifÃsico no lado secundÃrio. A isolaÃÃo em alta frequÃncia à garantida utilizando-se trÃs transformadores monofÃsicos conectados em uma configuraÃÃo delta aberto/estrela. A variaÃÃo de ambos os Ãngulos de deslocamento de fase, entre os braÃos de uma ponte H e/ou entre os lados primÃrio e secundÃrio, permitem o controle do fluxo de potÃncia. Esta flexibilidade garante a obtenÃÃo de um baixo conteÃdo reativo na anÃlise de projeto da topologia. A razÃo cÃclica variÃvel à utilizada para assegurar um barramento constante e uma operaÃÃo dos interruptores com comutaÃÃo suave. Uma anÃlise matemÃtica da estrutura à apresentada considerando um modelo baseado em componentes fundamentais e, com o propÃsito de comprovar a validade deste modelo, uma segunda anÃlise a partir das etapas de operaÃÃo do conversor tambÃm foi desenvolvida. O modelo dinÃmico do conversor, baseado nas componentes fundamentais, tambÃm foi concebido com auxÃlio da teoria do gyrator. Um exemplo de projeto, com a obtenÃÃo de valores nominais, esforÃos e especificaÃÃes dos componentes, caracterizaÃÃo do sistema de controle discreto e sua programaÃÃo atravÃs de FPGA sÃo desenvolvidos. SimulaÃÃes e resultados experimentais do conversor operando em regime permanente e dinÃmico sÃo apresentados para validar o modelo proposto.

De nos jours, les énergies renouvelables remplacent les énergies fossiles. Pour assurer une l’interconnexion entre toutes ces installations électriques, l’électronique de puissance est nécessaire. Les principales spécifications de la prochaine génération de convertisseur de puissances sont un rendement et une densité de puissance élevés, fiabilité et faibles coûts. L’intégration PCB des composants actifs et/ou passifs est perçue comme une approche prometteuse, peu onéreuse et efficace. Les délais ainsi que les coûts de fabrication des convertisseurs de puissance peuvent considérablement réduits. L’intégration permet également d’améliorer les performances des convertisseurs. Dans ce but, un concept original d’inductance 3D pliable utilisant la technologie PCB est présenté. Il permet un coût faible pour une production en série, ainsi qu’une excellente reproductibilité. Un usinage partiel de la carte PCB est utilisé, permettant le pliage et la conception des enroulements de l’inductance. Différents prototypes sont développés par le biais d’une procédure d’optimisation. Des tests électriques et thermiques sont réalisés pour valider l’applicabilité du concept au sein de convertisseurs de puissance.Le développement d’une procédure d’optimisation appliqué aux convertisseurs hautement intégrés utilisant l’enterrement PCB est présenté. Tous les choix importants, facilitant l’intégration PCB, e.g. réduction des composants passifs, sont présentés. Cela inclut la sélection de la topologie adéquate avec la modulation associée. La procédure de design et les modèles analytiques sont introduits. Il en résulte un convertisseur comprenant quatre pont-complet entrelacés avec des bras fonctionnant à basse (50 Hz) et haute (180 kHz) fréquences. Cette configuration autorise une variation de courant importante dans les inductances, assurant ainsi la commutation des semi-conducteurs à zéro de tension (ZVS), et ceux sur une période complète du réseau. L’impact de la forte variation de courant sur le filtre CEM est compensé par l’entrelacement. Deux prototypes d’un convertisseur AC/DC bidirectionnel de 3.3 kW sont présentés, les résultats théorique et pratique sont analysés.Pour augmenter la densité de puissance du system, un filtre actif de type “Buck” est étudié. La procédure d’optimisation est adaptée à partir de la procédure implémentée pour le convertisseur AC/DC. L’approche utilisée, mène à un convertisseur opérant également en ZVS durant une période compète du réseau, et ce, à fréquence de commutation fixe. Les technologies sélectionnées, condensateur céramique et inductance compatible avec la technologie PCB sont favorable à l’intégration et sont implémenté sur le prototype
Nowadays, the green energy sources are replacing fossil energies. To assure proper interconnections between all these different electrical facilities, power electronics is mandatory. The main requirements of next generation converters are high efficiency, high power density, high reliability and low-cost. The Printed Circuit Board (PCB) integration of dies and/or passives is foreseen as a promising, low-cost and efficient approach. The manufacturing time and cost of power converters can be drastically reduced. Moreover, integration allows the converter performances to be improved. For this purpose, an original 3D folded power inductor concept using PCB technology is introduced. It is low cost for mass production and presents good reproducibility. A partial milling of the PCB is used to allow bending and building the inductor winding. Prototypes are designed through an optimisation procedure. Electrical and thermal tests are performed to validate the applicability in power converters. The development of an optimisation procedure for highly integrated converters, using PCB embedding, is presented. All important choices, facilitating the PCB integration, e.g. reduction of passive components, are presented. It includes the selection of the suitable converter topology with the associated modulation. The design procedure and implemented analytical models are introduced. It results in four interleaved full-bridges operating with low (50 Hz) and high (180 kHz) frequency legs. The configuration allows high current ripple in the input inductors inducing zero voltage switching (ZVS) for all the semiconductors, and for a complete grid period. The impact of high current ripple on the EMI filter is compensated by the interleaving. Two prototypes of a 3.3 kW bidirectional AC/DC converters are presented, theoretical and practical results are discussed. To further increase the power density of the overall system, a Buck power pulsating buffer is investigated. The optimisation procedure is derived from the procedure implemented for the AC/DC converter. The result favours an original approach, where the converter also operates with ZVS along the entire main period at a fixed switching frequency. The selected technologies for prototyping are integration friendly as ceramic capacitors and PCB based inductors are implemented in the final prototype

Nanomagnetic logic, incorporating logic bits in the magnetization orientations of single-domain nanomagnets, has garnered attention as an alternative to transistor-based logic due to its non-volatility and unprecedented energy-efficiency. The energy efficiency of this scheme is determined by the method used to flip the magnetization orientations of the nanomagnets in response to one or more inputs and produce the desired output. Unfortunately, the large dissipative losses that occur when nanomagnets are switched with a magnetic field or spin-transfer-torque inhibit the promised energy-efficiency. Another technique offering superior energy efficiency, “straintronics”, involves the application of a voltage to a piezoelectric layer to generate a strain which is transferred to an elastically coupled magnetrostrictive layer, causing magnetization rotation. The functionality of this scheme can be enhanced further by introducing magnetocrystalline anisotropy in the magnetostrictive layer, thereby generating four stable magnetization states (instead of the two stable directions produced by shape anisotropy in ellipsoidal nanomagnets). Numerical simulations were performed to implement a low-power universal logic gate (NOR) using such 4-state magnetostrictive/piezoelectric nanomagnets (Ni/PZT) by clocking the piezoelectric layer with a small electrostatic potential (~0.2 V) to switch the magnetization of the magnetic layer. Unidirectional and reliable logic propagation in this system was also demonstrated theoretically. Besides doubling the logic density (4-state versus 2-state) for logic applications, these four-state nanomagnets can be exploited for higher order applications such as image reconstruction and recognition in the presence of noise, associative memory and neuromorphic computing. Experimental work in strain-based switching has been limited to magnets that are multi-domain or magnets where strain moves domain walls. In this work, we also demonstrate strain-based switching in 2-state single-domain ellipsoidal magnetostrictive nanomagnets of lateral dimensions ~200 nm fabricated on a piezoelectric substrate (PMN-PT) and studied using Magnetic Force Microscopy (MFM). A nanomagnetic Boolean NOT gate and unidirectional bit information propagation through a finite chain of dipole-coupled nanomagnets are also shown through strain-based "clocking". This is the first experimental demonstration of strain-based switching in nanomagnets and clocking of nanomagnetic logic (Boolean NOT gate), as well as logic propagation in an array of nanomagnets.

L'objectif du projet CONCIGI-HT (CONvertisseur alternatif-continu Compact à Isolement Galvanique Intégré Haute Tension) est d'augmenter le rendement des chaînes de traction tout en réduisant la masse et le volume de la fonction de conversion Alternatif/Continu. Pour cela, l'ensemble transformateur basse fréquence - redresseur est remplacé par une structure multi-convertisseurs, directement connectée à la caténaire haute tension et intégrant des transformateurs fonctionnant en moyenne fréquence (plusieurs kHz). Cette thèse concerne plus particulièrement la caractérisation et la mise en œuvre de composants semi-conducteurs haute tension dans des structures de conversion statiques à étage intermédiaire moyenne fréquence. L'étude est effectuée sur la base d'une chaîne de traction de 2 MW fonctionnant sur un réseau 25 kV/50 Hz. Le premier chapitre présente l'état de l'art de l'Automotrice à Grande Vitesse (AGV) récemment produite par ALSTOM. C'est la chaîne de traction de cet engin qui sert de référence pour l'étude des nouvelles topologies à transformateur moyenne fréquence. Le deuxième chapitre décrit tout d'abord la structure d'une chaîne de traction classique et présente ensuite deux topologies multicellulaires à transformateur moyenne fréquence applicables en traction électrique ferroviaire (la structure indirecte à redresseur de courant MLI et convertisseur DC/DC à résonance ainsi que la topologie directe associant des convertisseurs duaux). Les avantages et inconvénients de ces topologies sont mis en évidence. Le troisième chapitre concerne la mise en œuvre et la caractérisation en commutation douce de composants Silicium 6,5 kV dans les deux topologies présentées précédemment. Deux bancs de test, représentant un étage élémentaire de conversion, ainsi que des allumeurs spécifiques dédiés à la commutation douce, ont été réalisés. Ils permettent l'étude des semi-conducteurs en régime permanent dans des conditions nominales de fonctionnement (3,6 kV / 100 A). Le quatrième chapitre présente la mise en œuvre et la caractérisation de composants en carbure de silicium (SiC). Pour cela des modules de puissance à base de puces 10 kV (MOSFET et Diodes) ont été réalisés. Les résultats expérimentaux, obtenus sur les bancs de test réalisés au chapitre précédent, mettent en évidence une réduction significative des pertes et démontrent la viabilité de la topologie à convertisseurs duaux pour une application en 25 kV/50 Hz. La conclusion présente un premier design d'un bloc élémentaire et les gains en masse et volume ainsi que les économies d'énergies qui pourront être obtenus par rapport à une structure classique
The objective of the CONCIGI-HT project (Compact AC/DC converter with Integrated High Voltage Galvanic Insulation) is to increase the efficiency of traction drives while reducing the mass and volume of the AC/DC conversion. To do that, the part low-frequency transformer - rectifier is replaced by a multi-converter topology, directly connected to the high voltage power supply and incorporating medium frequency transformers (several kHz). This thesis relates more particularly to the characterization and implementation of high voltage semiconductors in conversion topologies with intermediate medium frequency link. The study is performed on the basis of a traction drive of 2 MW operating on a 25 kV/50 Hz power supply. The first chapter presents the state of the art of the Automotrice à Grande Vitesse (AGV) recently produced by ALSTOM. The traction drive of this vehicle is used as a reference for the study of new topologies with medium frequency transformer. The second chapter first describes the structure of a conventional traction drive and then presents two multicellular topologies with medium frequency transformer applicable to railway traction (the indirect structure with PWM rectifier and DC/DC resonant converter and the direct topology combining dual converters). The advantages and disadvantages of these topologies are highlighted. The third chapter deals with the implementation and soft switching characterization of 6.5 kV Silicon components in both topologies presented above. Two test benches, representing a basic conversion stage, as well as specific drivers dedicated to the soft switching, has been made. They allow the study of semiconductors in nominal operating conditions (3.6 kV / 100 A). The fourth chapter presents the implementation and characterization of silicon carbide components (SiC). For this, power modules based on 10 kV chips (MOSFET and Diodes) have been achieved. The experimental results obtained on test benches made in the previous chapter, show a significant reduction in losses and demonstrate the viability of the dual converter topology for a 25 kV/50 Hz application. The conclusion presents the first design of an elementary block and gains in mass and volume as well as the energy savings that can be achieved compared to a conventional structure

В даний час спектр застосування світлодіодних джерел світла дуже широкий. Успіхи в розробці ефективних світлодіодів дозволили використовувати їх для цілей освітлення. Для підключення світлодіодів до стандартної електричної мережі 220/380 В необхідні пристрої стабілізації струму. Найбільш економічні стабілізатори струму для світлодіодів засновані на методі шпротному-імпульсної модуляції, при цьому всебічні дослідження імпульсного режиму живлення світлодіодів не проводилися. Результати наукових досліджень можуть бути використані при створенні пристроїв стабілізації струму світлодіодів. Використання оптимізованих режимів живлення світлодіодів з точки зору електротехніки є можливим шляхом підвищення їх ефективності і терміну служби.
Метою кваліфікаційної роботи було дослідити перехідні процесів, що відбуваються при живленні світлодіодів імпульсним струмом, і їх впливу на світлотехнічні і електротехнічні характеристики. Розроблено методику обробки результатів на початковій стадії кінетичних досліджень, що передбачає виявлення характеру загасання світіння (релаксації поглинання), яке може бути обумовлено молекулярними реакціями і описується кінетикою першого і другого порядку. Розроблено методику та змонтовано установку для вимірювання енергетичних характеристик напівпровідникових джерел світла при імпульсному живленні.
The purpose of the qualification work was to investigate transients that occur when powering LEDs with pulsed current, and their impact on lighting and electrical characteristics. A method for processing the results at the initial stage of kinetic research has been developed, which involves identifying the nature of luminescence attenuation (absorption absorption), which may be due to molecular reactions and is described by first- and second-order kinetics. A method has been developed and an installation for measuring the energy characteristics of semiconductor light sources at pulsed power supply has been installed.
ЗМІСТ ВСТУП 6 1 АНАЛІТИЧНИЙ РОЗДІЛ 8 1.1 Структура і принцип робота світлодіода 8 1.2. Будови блоків живлення для світлодіодів 11 1.2.1. Лінійні блоки живлення світлодіодів 11 1.2.2 Імпульсні блоки живлення світлодіодів 12 1.3. Способи підвищення ефективності світлодіодного драйвера 14 1.4. Висновки до розділу 18 2 ПРОЕКТНО-КОНСТРУКТОРСЬКИЙ РОЗДІЛ 19 2.1. Кінетика та спектральний аналіз результатів імпульсних вимірів 19 2.2. Розкладання кінетичних кривих у світлодіодах 22 2.3. Кінетика реакцій у світлодіодах 28 2.3.1. Швидкість реакції у світлодіодах 28 2.3.2. Реакція нульового порядку 29 2.3.3. Реакція першого порядку 30 2.3.4. Реакція другого порядку 31 2.4. Експериментальної установки для проведення світлотехнічних і електротехнічних вимірювань 32 2.5. Висновки до розділу 35 3 НАУКОВО-ДОСЛІДНИЦЬКИЙ РОЗДІЛ 36 3.1. Електричні характеристики світлодіодного кола при імпульсному живленні 36 3.2. Світлотехнічні характеристики світлодіодного кола при імпульсному живленні 45 3.3. Висновки до розділу 51 4 ОХОРОНА ПРАЦІ ТА БЕЗПЕКА В НАДЗВИЧАЙНИХ СИТУАЦІЯХ 53 4.1. ОХОРОНА ПРАЦІ 53 4.1.1. Організація охорони праці на підприємстві 53 5 4.1.2. Вимоги до виробничого освітлення та його нормування 55 4.1.3. Штучне освітлення виробничих приміщень, його нормування та види 56 4.1.4. Вплив кольору на покращення умов праці та підвищення продуктивності виробництва 57 4.2. БЕЗПЕКА В НАДЗВИЧАЙНИХ СИТУАЦІЯХ 61 4.2.1. Причини електротравматизму. Вплив електричного струму на організм людини 61 4.2.2. Стійкість роботи об’єкту енергетики і фактори, що на них впливають 65 ЗАГАЛЬНІ ВИСНОВКИ 67 ПЕРЕЛІК ПОСИЛАНЬ 68

Series Active Filters (SAF) are designed for harmonic isolation and load voltage regulation of single-phase and three-phase voltage harmonic source type nonlinear loads. The novel Absolute Value Method (AVM) for load voltage harmonic extraction is proposed and applied in the control algorithm of SAF. The SAF compensated systems are represented by simplified linear models such that SAF controller gains can be easily determined. Harmonic isolation and load voltage regulation performances of 2.5 kW single-phase and 10 kW three-phase SAF compensated systems are evaluated by detailed simulations. Laboratory prototype single-phase and three-phase SAFs and loads are designed and manufactured. Digital signal processor based control platform is employed. Exclusive laboratory tests are conducted. Via laboratory experiments and simulations it is shown that AVM yields superior harmonic isolation and load voltage regulation performance compared to the conventional low/high pass filtering method. Theory, simulations, and experiments are well correlated and illustrate the feasibility of the proposed method.

Multi functional health monitoring wearable devices are quite prominent these days. Usually these devices are battery-operated and consequently are limited by their battery life (from few hours to a few weeks depending on the application). Of late, it was realized that these devices, which are currently being operated at fixed voltage and frequency, are capable of operating at multiple voltages and frequencies. By switching these voltages and frequencies to lower values based upon power requirements, these devices can achieve tremendous benefits in the form of energy savings. Dynamic Voltage and Frequency Scaling (DVFS) techniques have proven to be handy in this situation for an efficient trade-off between energy and timely behavior. Within imec, wearable devices make use of the indigenously developed MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). This system is optimized for efficient and accurate collection, processing, and transfer of data from multiple (health) sensors. MUSEIC v2 has limited means in controlling the voltage and frequency dynamically. In this thesis we explore how traditional DVFS techniques can be applied to the MUSEIC v2. Experiments were conducted to find out the optimum power modes to efficiently operate and also to scale up-down the supply voltage and frequency. Considering the overhead caused when switching voltage and frequency, transition analysis was also done. Real-time and non real-time benchmarks were implemented based on these techniques and their performance results were obtained and analyzed. In this process, several state of the art scheduling algorithms and scaling techniques were reviewed in identifying a suitable technique. Using our proposed scaling technique implementation, we have achieved 86.95% power reduction in average, in contrast to the conventional way of the MUSEIC v2 chip’s processor operating at a fixed voltage and frequency. Techniques that include light sleep and deep sleep mode were also studied and implemented, which tested the system’s capability in accommodating Dynamic Power Management (DPM) techniques that can achieve greater benefits. A novel approach for implementing the deep sleep mechanism was also proposed and found that it can obtain up to 71.54% power savings, when compared to a traditional way of executing deep sleep mode.
Nuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.

Conselho Nacional de Desenvolvimento Científico e Tecnológico
One of the main goals of the electric utilities is to provide energy to its customers in a reliable and low cost way. Traditionally, the electricity sector regulatory commissions impose continuity targets, which must be carried out, to avoid great penalties. For many years, the electric utilities have adopted the practice of allowing the increment of temporary interruptions, aiming the reduction of permanent interruptions in energy supply, through coordinated protection schemes. However, due to the increase growing in electronic loads, and the existence of complex power-driven industrial processes, there is a less tolerance in short duration interruptions events. Therefore, the reliability must be characterized as widely way, considering the occurrence of such disturbances. The definition of protection devices types, and its arrangement in the feeder, enables the restriction of faults propagation, reducing the number of consumers subject to interruptions in energy supply. Similarly, the allocation of switching devices in an optimized way, provides a reduction of the interruptions duration, allowing the isolation of portions of the network subject to failure, the reconfiguration of the feeder and restoration of the supply to the consumer, in permanent interruptions cases. Targeting these factors, in this work are proposed two methods to optimize the reliability of electrical distribution systems. The optimization with a single objective is based on optimized allocation of protective and switching devices in the feeder, aiming the minimization of the reliability indices that considers the occurrence of permanent interruptions in energy supply. It is possible the choice of different indices, considering parameters such as load, number of consumers, and energy costs related to the occurrence of interruptions. The protection scheme, in this case is pre-defined (coordinated or selective), and applied to all reclosers allocated in the process of optimization, as well as the breaker of the substation. The second methodology - called double objective - is based on simultaneous minimization of reliability index that take into account the occurrence of permanent interruptions, and the indicator MAIFIE (Momentary Average Interruption Event Frequency Index), which considers the incidence of events that cause temporary interruptions in energy supply. Thus, besides the allocation of protection and switching devices, the optimization consists in definition of the protection scheme to be employed in reclosers and circuit breaker at the substation. Both formulations result in models of nonlinear programming with discontinuous and non-differentiable objective functions, subject to non-linear restrictions. These restrictions reflect in economic and technical limitations, such as coordination and selectivity between the protective devices, topology of the feeder, maximum number of devices available for allocation, and others. In order to find the best solution of the problem with single objective, a Simple Genetic Algorithm is proposed. A conjunct of best solutions of the dual objective problem was accomplished by using Multiobjective Genetic Algorithm. Among these, the most appropriate solution is selected through the use of Fuzzy Inference System. The performance of the algorithms and the quality of the solutions were verified by submitting a real 421 bus distribution system in the process of optimization. The results are commented and compared with the commonly practices used by electric companies.
Uma das principais metas das empresas concessionárias é fornecer energia a seus clientes de forma confiável e com baixo custo. Tradicionalmente, órgãos reguladores do setor elétrico estabelecem metas de continuidade, que devem ser satisfeitas sob pena da aplicação de vultosas multas. Durante muitos anos, as concessionárias têm adotado a prática de permitir o incremento das interrupções temporárias, visando à diminuição na ocorrência das interrupções permanentes no fornecimento de energia, pelo emprego do esquema de proteção coordenado. Entretanto, com o crescente aumento das cargas eletrônicas, e a existência de processos industriais automatizados cada vez mais complexos, existe uma menor tolerância à ocorrência de interrupções de curta duração. Logo, a confiabilidade deve ser caracterizada de forma mais ampla, considerando a ocorrência deste tipo de distúrbio. A definição dos tipos de dispositivos de proteção, e a disposição dos mesmos em locais específicos do alimentador, possibilitam restringir a propagação de faltas, reduzindo o número de consumidores submetidos a interrupções no fornecimento de energia. De forma semelhante, a alocação de chaves de manobras de maneira otimizada provê meios de reduzir a duração das interrupções, possibilitando a isolação de trechos da rede sob condição de falta, a reconfiguração do alimentador e o restabelecimento do fornecimento à parte dos consumidores, caso ocorram interrupções permanentes. Visando estes fatores, neste trabalho são propostas duas metodologias de otimização da confiabilidade de sistemas elétricos de distribuição. A otimização com objetivo único consiste na alocação de dispositivos de proteção e manobras no alimentador, visando à minimização de indicadores de confiabilidade que consideram a ocorrência de interrupções permanentes no fornecimento de energia. É possível a escolha de diferentes indicadores, considerando parâmetros como: carga, número de consumidores, energia e custos relacionados à ocorrência de interrupções. O esquema de proteção, neste caso é pré-definido (coordenado ou seletivo), sendo aplicado a todos os religadores alocados no processo de otimização, inclusive ao disjuntor da subestação. A segunda metodologia denominada duplo objetivo consiste na minimização simultânea de um indicador de confiabilidade que considera a ocorrência de interrupções permanentes, e do indicador MAIFIE (Momentary Average Interruption Event Frequency Index), que considera a ocorrência de eventos causadores de interrupções temporárias no fornecimento de energia. Desta forma, além da alocação dos dispositivos de proteção e manobras, o processo de otimização visa definir o esquema de proteção a ser empregado nos religadores, bem como no disjuntor da subestação. Ambas as formulações resultam em modelos de programação não-lineares, com funções objetivo descontínuas e não diferenciáveis, sujeitas a restrições não-lineares. Estas restrições refletem limitações técnicas e econômicas, tais como coordenação e seletividade entre os dispositivos de proteção, topologia do alimentador, número máximo de dispositivos disponíveis para alocação, entre outras. Na busca da melhor solução do problema com objetivo único é empregado o Algoritmo Genético Simples. Um conjunto de soluções ótimas do problema duplo objetivo é obtido utilizando o Algoritmo Genético Multiobjetivo. Dentre estas, a solução mais adequada é selecionada por meio de um Sistema de Inferência Nebulosa. O desempenho dos algoritmos e a qualidade das soluções foram verificados submetendo um sistema de distribuição real de 421 barras ao processo de otimização. Por fim, os resultados são comentados e comparados com as práticas mais utilizadas pelas concessionárias.

Cette thèse s'inscrit dans un contexte de développement durable où les enjeux énergétiques consistent à concevoir des convertisseurs de puissance plus disséminés, donc avec une Spécification ambitieuse en termes de densités massique et volumique. Les composants à semiconducteur dit à grand Gap permettent l’augmentation de la fréquence de commutation et permettent un fonctionnement à plus haute température locale. Les commutations à front raides et à haute fréquence des transistors rendent le système plus sensible aux éléments parasites. Ceci perturbe en retour la commutation des transistors et génère des pertes joules supplémentaires. Dans ce contexte les travaux ont été effectués dans le cadre d’une cotutelle entre les laboratoires Ampère (INSA Lyon) et LN2 (Université de Sherbrooke), le but étant d’apporter des contributions à l’optimisation de la commutation des HEMTs GaN. Le premier axe des travaux consiste à mettre en place des stratégies de contrôle de vitesses de commutation en tension et en courant, par la grille, dans le but d’améliorer la signature CEM. Les circuits de contrôle proposés sont développés dans un premier temps en boucle ouverte puis dans un second temps en boucle fermée afin de compenser des non-linéarités (température, courant de charge et tension de fonctionnement). Les prototypes de contrôle de grille ont été testés à partir de composants discrets du marché. Des limites apparaissent, que l’intégration monolithique GaN doit corriger à terme, en particulier en atténuant fortement le problème des inductances parasites. Les analyses en simulation ont reposé sur l’adoption d’un modèle comportemental de HEMT GaN identifiable. Le deuxième axe des travaux consiste à vérifier de manière systémique différentes stratégies de contrôle de grille notamment pour la gestion du compromis entre pertes joule pendant les temps morts au sein d’un à bras d’onduleur et la performance fréquentielle des commutations. Aux termes de ces travaux, les systèmes de contrôles développés en boucle ouverte ont permis de ralentir les vitesses de commutation d’au moins 30 %, occasionnant une augmentation des pertes de commutation, dans un ordre de grandeur inférieur à 50 %. Due à la rapidité de commutation des HEMT GaN et aux limites des composants discrets du marché, le taux de réduction des vitesses de commutation obtenu avec la boucle fermée (taux de réduction inférieur à 20 %) est moins intéressant qu’avec la boucle ouverte. L’utilisation d’un circuit monolithique peut être une alternative pour augmenter le taux de réduction des vitesses de commutation en boucle fermée. Des résultats de simulation sous SPICE en vue du circuit monolithique sont à la base de cette hypothèse. Concernant le deuxième axe, l’application de commande multiniveaux de grille des transistors du bras d’onduleur a permis de réduire les pertes de conduction inverse et les pertes dues aux phénomènes de Cross Talk d’au moins 30 %
This thesis is part of the sustainable development context where the energy challenges rely on designing numerous and lumped power converters with good power density and high efficiency. New power semiconductor devices, namely wide band semiconductors (GaN, SiC) are used in designing the converters. The high frequency control of these converters makes the system more sensitive to parasitic elements. The latter elements disrupt the switching behavior of the transistors and generate additional losses. In this context this work was carried out in a cotutelle partnership between Ampère Laboratory in Villeurbanne and LN2 laboratory at the University of Sherbrooke; the aim being to make a contribution in optimizing the switching conditions of GaN HEMTs. The first work axis consists in managing the voltage and current switching speed through gate control strategies in order to improve the conducted EMI. Firstly, most of the proposed control circuits are developed in open-loop and then secondly in closed-loop in order to compensate the effects of non-linearities (with respect to temperature, load current and operating voltage). Concerning the development of control systems, it can be done first by the use of available discrete components, then by the alternative of the monolithic GaN integration which is considered in order to bring more speed and efficiency. Monolithic integration would also solve the problem of parasitic inductances. To facilitate the design of integrated circuits and control systems, the development of a behavioral model of HEMT GaN will serve as a modeling tool. The second axis of the work consists in experimentally validating well-adapted control system for the gate of the power transistor in order to master the transient behaviors of the power transistors. Namely it is necessary to allow a satisfying management of losses during dead time in a half bridge converter. At the end of this work, the control systems developed in open loop made it possible to slow the switching speeds by at least 30 % but causing an increase in switching losses up to 50% in some cases. Due to the fast switching speed of HEMT GaNs and the limitations of discrete components on the market, the reduction rate of switching speeds obtained with the closed loop (reduction rate less than 20%) is less attractive than that of the open loop. Using a monolithic circuit can be an alternative to increase the rate of reduction of closed loop switching speeds. SPICE simulation toward monolithic circuit are the basis of this hypothesis. Concerning the second axis, the application of multilevel gate voltage control of the transistors of half bridge made it possible to reduce the losses of reverse conduction and the losses due to the phenomena of Cross Talk by at least by 30 %

For the last four decades, silicon CMOS technology has captured a significant share in IC, smart power IC, SoC, and the power device market. But there is aggressive research on other materials such as graphene & similar 2D materials and wideband gap materials. But, several aspects, including the fabrication process to improve device performance [7,9,12,13], understanding the device reliability physics [8,10,11], interconnection and packaging, need to be matured before these compound materials take the limelight. Besides these, a fab set-up for large scale production requires high NRE capital. On the other hand, Silicon had been through a great degree of maturity. Moreover, for intelligent power applications, Silicon has superior reliability. Therefore, Silicon is predicted to capture the power device market till the other materials gain perfection. Besides the commercial market, the requirement for discrete and integrated power device technology within the strategic sector is enormous. Discrete power switching devices (often power MOS or IGBT switch) and power RF devices are used in numerous onboard power electronic and power RF applications. The first part of this work strives to bridge the device-circuit co-design gap that has severely limited predictive modelling of circuits for high power applications such as Radio Frequency Power Amplifiers (RF PAs) using high power devices LDMOSs and GaN HEMTs. A correlation between the device’s intrinsic parameters and PA performance is explored, and the iterative process aims to provide a high-performing circuit. LDMOS is one of the prominent power devices which adopts CMOS processing and easy integration. The lateral double diffused MOSFET (LDMOS) is the predominant power device in implementing Power integrated circuits PICs because of its attractive electrical characteristics such as low on-resistance, high breakdown voltage, high input impedance and fast switching frequency. To obtain high breakdown voltage with low on-resistance for LDMOS, RESURF technology is used, in which the vertical p-n junction depletion layer between the n-type drift region and p-type epitaxial region and its interaction with lateral p-n junction depletion between the p-type channel and n-type drift region is optimised to reduce the surface electric field to obtain high breakdown voltage. A field plate (FP) on top of the gate and a drain field plate on top of the drift region is introduced to improve breakdown voltage further. These field plates help reduce feedback capacitance (Cgd) and increase the breakdown voltage FP LDMOS. This work explores optimising the field plates for achieving breakdown characteristics above 900V without altering the on-resistance of the devices [2]. It covers major classical power devices from conventional design to non-conventional device designs. Conventional devices without field plates show 30% lower breakdown voltages than those with field plates. It can be concluded that field plates play a vital role in enhancing the breakdown characteristics of the device. Taking optimised design further, the field plates are introduced into non-conventional devices, where RESURF and SOI-based devices are explored. Along with the performance studies, the reliability of these structures is also explored. Regarding reliability, RESURF based devices show a higher tendency of deviation/degradation when stressed, up to 20% higher than the breakdown condition like that of the conventional devices without Fp. Further, the role of each field plate individually under the ESD condition is explored [3]. It was clearly understood that field plates at the source side play a significant role in distributing the junction electric field, while field relaxation at the drain side helps in improving the failure threshold. Gate and Source field plates improve the trigger voltage characteristics up to 54%, while drain field plate improves the failure threshold up to 60%. Power semiconductor device industries are aggressively looking for system-on-chip (SOC) solutions for power amplifier (PA) circuits and are exploring different technologies, including gallium arsenide (GaAs), to more recent and intriguing gallium nitride (GaN) technologies, for power transistors with Radio Frequency (RF) applications. The advantage of silicon technology for RF applications lies mature fabrication process at low cost and their easy integration capability with the CMOS technology. Applications that require radio frequency power amplifiers such as broadcast, ISM (industrial, scientific, and medical), avionics, radar, wideband communications, telecom & satellite communications, RF heating applications, etc. Among them, the 50V RF LDMOS device is mainly used in wireless broadcast, ISM, and radar, which requires a higher breakdown voltage and power density. For 50V RF LDMOS with 0.35µm CMOS technology, the breakdown voltage must be higher than 100 V to guarantee a reliable operation. RESURF technology and the introduction of field plates have improved the breakdown voltage to 114V. Both DC and RF performance of various designs of FP RF LDMOS are evaluated, and results show that industry-leading performance is achieved [1]. Electrostatic Discharge (ESD) robustness was studied for the FP RF LDMOS designs as ESD has been identified as a source of damage to unprotected devices. Hot Carrier Injection (HCI) reliability was also investigated to address the complete reliability of these devices. Though Silicon-based transistors have the advantage of mature technology, the requirement for high power and high-frequency devices demands transistors based on semiconductor materials with large breakdown voltage and high electron velocity. GaN is an attractive candidate for power amplifier applications because of several superior qualities in amplifier applications achieved due to its semiconductor properties. The wide bandgap in Gallium Nitride based transistors results in higher breakdown voltages because the ultimate breakdown field is the field required for band-to-band impact ionisation. Also, its high electron saturation velocities allow high-frequency operation. GaN can be used to fabricate high electron mobility transistors (HEMTs), which have high carrier concentration and higher electron mobility due to reduced ionised impurity scattering. A rigorous device-circuit co-design investigation of AlN/GaN HEMT to explore its feasibility for power amplifier operation at frequencies > 1THz. Both class A and class AB operations were invested. A novel device-circuit co-design methodology was adopted [4], which involves (i) device design optimisation using a well-calibrated TCAD setup, (ii) careful extraction of large-signal model cards with I-V, C-V & S-parameter matching, and finally (iii) source-load pull-based power amplifier design/exploration, for every device design investigated. For PA operation, both class A and class AB operations were invested while exploring PA gain, output power, efficiency at 1dB compression point, and linearity through dual-tone (IMD3) investigations. Besides, a complete range of device design parameters was investigated to explore the ultimate scalability limit and narrow down the device design window that can enable THz operation. The last two decades have witnessed significant scaling in MOS technology from sub-micron to sub-nm level. To achieve devices with good performance at a small dimension, it was essential to explore new device architectures which could offer subthreshold swing (SS) values below 60 mV/dec. Several CMOS-like structures were designed, such as Fin-FETs, Nanowire Gate All Around (GAA) MOSFETs, Carbon nanotube FETs, Tunnel FETs, etc., which could lower the leakage current at small dimensions. Among these, TFET could achieve SS less than 60 mV/dec attributed to a fundamentally different mechanism for carrier injection. Hence, TFET is considered a future on the roadmap. A prediction of reliability is essential in choosing a device for a particular application. Therefore, it is necessary to understand the reliability of devices at the design stage itself. As technologies advance towards the deep submicron, the ESD (Electrostatic Discharge) protection design issues have become more critical. The second part of this work tries to understand the ESD robustness of a couple of novel Tunnel FET architectures. A novel Fin-enabled vertical or area-scaled tunnelling FET is proposed for sub- 10-nm channel length operation. This device enables a smooth transition from FinFET technology to Fin-based vertical TFETs, while enjoying the benefits of FinFET architecture. To make this device commercial, it’s essential to understand the reliability performance of this device. This work explores the reliability physics of this device with detailed physical insight into the device’s operation and failure under ESD stress conditions [5]. The proposed device has a deep N+ implant underneath the P+ source, like adding a pocket between the source and gate for the ESD protection applications. Early avalanche assisted BTBT at the source-pocket junction, in addition to the drain-substrate junction, causes the device to turn on at lower voltages, lower self-heating resulting in improved failure current in the proposed device with less area overhead.

碩士
國立交通大學
電子工程學系 電子研究所
101
As the technology development, the nonvolatile memory (NVM) plays an important role in our daily life, such as mobile phones, digital cameras and laptop, have significantly increase the demand for nonvolatile memory (NVM) with the years in semiconductor industry. The flash memory nowadays is considered as the mainstream. However, due to the further scaling limitation, it faces serious challenges. The resistive random access memory (RRAM) shows a great potential for the next generation NVM application, due to its low operation voltage, high-speed switch, low power, high density integration and simple structure, etc. In this study, we report the effect of different top electrode (Nickel, Tantalum Nitride) and a low 0.752mW (188μA at 4V; 2.6μA at -5V) power resistive switching RRAM device with Ni/Al2O3 (6nm)/TiO2/TaN RRAM structure. The RRAM device characteristics, such as on/off resistance ratio (>100), data retention (104s at 60℃), satisfactory pulse switching endurance (50 cycles), current distribution, and conduction mechanism, etc., are investigated. The top electrode with different work function may have influences for the electrical properties. This RRAM device indicates that the carrier transport is dominated by the hopping conduction via material defects such as oxygen-vacancies in this RRAM. Such as low-power switching is a great promise for future scalable memory application, a merit of this RRAM.

Thesis (M.S.)--University of Wisconsin--Madison, 2002.
Typescript. eContent provider-neutral record in process. Description based on print version record. Includes bibliographical references (p. 205-212).

博士
國立臺灣大學
電機工程學研究所
105
The gallium nitride (GaN) cascode switch has received much attention recently for line-operated medium-high frequency (200 kHz to 500 kHz) applications. Because of its device structure, there are two package options available with regard to the tab internal connection; either the drain terminal or the source terminal is electrically connected to the metallic plate of the device package, unlike the conventional vertical power Si based MOSFET in which the drain terminal can be connected to the device metallic plate. It is proposed in the dissertation that taking advantage of the unique feature of GaN devices packages mentioned above and using a proper combination of the GaN devices in a converter circuit converter common mode noise can be reduced. As a result, the converter conducted EMI can be reduced. The theory is explained and the rule for proper package selection are described in the dissertertation. A 240-Watt LLC power converter with a front-end power-factor-correction (PFC) circuit was built for experimental verification. In the experiment, significant reduction in the conducted EMI was observed. The proposed strategy can be applied to other converter or inverter configurations. GaN devices provide an option, unavailable in power MOSFET devices to significantly reduce the converter conducted EMI.

博士
國立成功大學
機械工程學系
102
This research aims to design a flux-switching actuator with an auto-locking function for power assist devices. Traditional actuators used in situations of brief travel and discontinuity, such as power assistive devices, usually need to stop at a position for a long time but still require electric power supply to maintain sufficient electromagnetic force. This research presents a new flux switching device (FSD) based on the design concept of dual gap permanent magnet motors (PM motors) and magnetic bases. Applications of this device include incorporation with direct-drive motors or motors with gear ratios, which further enable high/low cogging torque switching ability by modifying the flux path. When the proposed actuator is operated in low cogging torque mode, it functions as the traditional device; however, when the actuator needs to maintain the same position, the cogging torque is adopted automatically and alternates to electromagnetic force in high cogging torque mode. This feature can improve the safety of users and products. In order to widen FSD applications, this research also presents two improved actuator designs. The first improvement starts with investigations of the rotor structure and output characteristics of line start permanent magnet motors (LSPMMs). Moreover, the open angle of V-shaped magnets, which possesses better efficiency, is designed such that the prototype efficiency can reach 90%. With this investigation, this research integrates the rotor structure of LSPMMs into the actuator design and presents a new outer rotor type LSPMM, which can be incorporated with FSD and can start up without sensors, encoders, or inverters. To summarize the second improvement, four axial winding coils are added to improve the actuator design, which ensures that the axial magnetic field is controllable; thus, the switching process becomes smoother and the performance more stable. With these two improvements, the actuator developed in this dissertation is applicable to various conditions.

碩士
亞洲大學
資訊工程學系碩士班
100
Discrete power MOSFETs are increasingly playing an important role in automotive electronics such as motor control where inductive loads are driven by the power devices. As a consequence, the ability of the MOSFET to withstand instances of unclamped inductive switching (UIS) is an important performance metric i.e. the ruggedness of the MOSFET. It had been proposed that the current failure mode is considered to be dominant at small external inductances while temperature failure usually occurred in device connected to large external inductive loads in UIS test. However, the failure mechanisms of device caused by the variation of external inductor cannot reflect the natural failure phenomena in power devices. In this work we present failure analysis of N-LDMOS under avalanche breakdown condition shows that the failure mechanism in a power MOSFET device depends on the number of device-fingers at a fixed inductive load. By TCAD simulation we observe that the device with lesser number of fingers (till 16) fail because of current failure mechanism as heat generated due to high current eventually destroys the parasitic transistor and hence contributes to failure. For higher fingers ranging from 16 to 100, time in avalanche, tAV gets prolonged in multi-finger device design. As a result, self-heating is more which causes temperature-failure in multi-finger device. The maximum amount of UIS energy i.e. Energy in avalanche, Single pulse (EAS) sustained by the device before failure is evaluated by Synopsys simulation tools. It is found that EAS has a linear relationship with number of device finger and device-width. We also present the optimized structure by modifying the poly-gate length which results higher energy in avalanche. Sensitive parameters in repetitive UIS tests such as duty cycle and finger design layout are also studied.

D.Ing. (Electrical and Electronic Engineering)
The non-linear resonant pole (NLRP) inverter is part of the family of soft switching topologies based on resonant phenomena. The sequence of commutation that occurs between the semiconductors of a conventional voltage source inverter is modified through the mechanisms of energy exchange between added passive energy storage components. The NLRP inverter, through its psuedo resonant behaviour (resonant transition), gives rise to zero voltage and zero current turn-on of the switching devices as well as soft turn-off. The switching device voltage stresses are around 1 p.u, while the current stresses are reduced to around 1.3 p.u, by feeding back a portion of the load current. The rms current flowing through the inductor and switches is greatly reduced by driving the inductor into saturation (non-linear mode of operation). The advantages of soft switching, such as high switching frequency which allows greater dynamic response and higher power densities, along with reduced EMI, are achieved with this topology. Detailed analysis at multi- and sub-cycle levels is carried out, resulting in circuit equations and the criteria for commutation success. The commutation boundaries of the inverter are defined and methods discussed on how to extend them. The modulation of the NLRP inverter and some aspects regarding its use as part of both low and high performance induction motor drives are presented.

碩士
國立交通大學
電子研究所
105
In this thesis, a 13.56MHz regulated rectifier is proposed which consists of rectification and regulation functions in one converter. By adopting the digital pulse width modulation (DPWM) technology to generate a regulated DC output voltage. Since the wireless power transmission system for the higher frequency 13.56 MHz, the switching delay of the power transistor will seriously affect the transmission efficiency of the rectifier. Thus, an adaptive switch delay compensation techniques (ADCT) have also been developed. To achieve high efficiency in different input amplitude range, also can reduce the effects of process variation. ADCT can compensate for both turn-on and turn-off delay by calibrate the comparator input offset voltage and the power MOS conduction time automatically to achieve maximum conversion power and minimize the reverse leakage current. Regulated rectifier proposed in this paper is fabricated in TSMC 0.18um process, followed by simulation can reach the highest power conversion efficiency was 88.8%, the output power is 36mW. Can tolerate a range of input AC amplitude is 1V ~ 3.3V.

碩士
國立中山大學
電機工程學系研究所
91
The first topic of this thesis is a novel voltage tripler using 4 clocks with different phases. Both the positive and negative polarities of the voltage are generated to serve as the boosted voltage and the back bias voltage. The proposed design is carried out by pass transistors and switched capacitors. The second topic is a low-power discrete cosine transform (DCT) processor. It is suitable for portable applications. The number of clock cycles needed for processing an 8×8 block of pixels is increased, but the chip area is reduced. The reduction of the chip area leads to the reduction of the power dissipation.

碩士
國立臺北科技大學
電機工程系電力電子產業研發碩士專班
105
GaN HEMTs are already devoloped in recent years, stability of GaN HEMTs has grow year by year, it has more suitable choosing for any specifications. The characteristic of GaN HEMTs is better than Si MOSFET in every way. Used GaN HEMTs component can let converter operate in higher frequency. The objective of this thesis is to design and implement a digital-controllor full bridge resonant converter. Because of parasitic inductance let MOSFET effect large voltage stress when MOSFET operate the high frequency. Therefore, the thesis used advantage of planar to reduce leakage inductance, stray capacitance and increase the power density. The signal processor, TMS320F2335, is used as control platform. The design specifications include: input DC voltage of 400V, output voltage of 12V, total power rating of 300 W, switching frequency of 450 kHz ~ 550 kHz. Simulation and experimental result show is 90.63% about half load condition the efficiency. These results confirm the design and implementation.

碩士
國立臺灣大學
資訊工程學研究所
106
The well development of Mobile Communications Networks (MCNs) causes the dramatically increasing of the smart devices. The smart devices such as wearable devices have limited battery lifetime so that it has the better choice to use the NB-IoT protocol to transmit the small data for the purpose of power saving. The wearable devices are also able to make the voice call through the VoLTE. Therefore, the interworking of the NB-IoT and LTE networks is necessary in the future. The power saving issue is generated if both NB-IoT and LTE interface of the UE attach to the networks. We propose the Protocol to Protocol Switching Mechanism (P2PSM) to enable the dual-mode UE to be supported in the NB-IoT and LTE interworking network and reduce the power consumption. The analytical models and simulation experiments are conducted to investigate the performance of the P2PSM mechanism. Our study shows that the proposed P2PSM mechanism can efficiently reduce the power consumption of the UE.

Lastwechseltests stellen eine standardisierte und etablierte Methode zur Zuverlässigkeitsbewertung und Produktqualifizierung in der Leistungselektronik dar. Sie basieren auf der Applikation von wiederkehrenden Laststromimpulsen, welche im Leistungsbauelement in zyklischen Temperaturschwankungen umgesetzt werden. Die dabei induzierten thermo-mechanischen Spannungen, hervorgerufen durch die unterschiedlichen Werkstoffeigenschaften der im Verbundsystem beteiligten Fügepartner, führen letztendlich zu den typischen Versagensmechanismen in der Aufbau- und Verbindungstechnik. Herkömmliche Lastwechseltests bilden allerdings die komplexen Belastungssituationen unter Feldbedingungen, in welchen unterschiedliche Lastfaktoren simultan auftreten, nur ungenügend nach. Im Kontext der Einführung neuartiger Bauelement- und Package-Technologien, rauer werdenden Umgebungsbedingungen sowie steigenden Zuverlässigkeits- und funktionalen Sicherheitsanforderungen ergibt sich somit der Bedarf an verbesserten Methoden zur Zuverlässigkeitstestbewertung. Ein möglicher Ansatz besteht in der Kombination verschiedener Belastungsarten, mit dem Ziel, Testeffizienz sowie Testabdeckung zu erhöhen. Im Rahmen dieser Arbeit wurden daher unter Verwendung eines selbstentwickelten Lastwechselteststandes systematische Lastwechseltestuntersuchungen, sowohl in standardmäßiger Ausführung als auch mit überlagerten passiven Temperaturzyklen, an diskreten Leistungsbauelementen durchgeführt. Neben der Untersuchung unterschiedlicher Sperrschichttemperaturprofile erfolgte auch ein Vergleich unterschiedlicher Bauelementtypen. Auf Basis einer qualitativen und quantitativen Testauswertung wurden belastungsbasierte Lebensdauermodelle aufgestellt. Dabei zeigte sich, dass die den Standard-Lastwechseltests zugrunde-liegenden Lebensdauermodelle nicht die Testergebnisse der überlagerten Lastwechseltests vorhersagen konnten. Die Ursache dafür lag im temperaturabhängigen Werkstoffverhalten der Moldmasse begründet, welches Einfluss auf den dominierenden Fehlermodus Bonddrahtabheber hat. Daher wird die Verwendung von fall-sensitiven Lebensdauermodellen vorgeschlagen, da somit die veränderte Schädigungsphysik beim Überschreiten des Glasüberganges der Moldmasse berücksichtigt werden kann. Darüber hinaus wird in dieser Arbeit eine neue Methode zur optischen in-situ-Untersuchung von Leistungsbauelementen vorgestellt, welche zukünftig die Untersuchung von thermisch-transienten sowie thermo-mechanischen Vorgängen unter aktiver Belastung erlaubt.:Symbol- und Abkürzungsverzeichnis Danksagung Kurzfassung Abstract 1 Einleitung 1.1 Motivation 1.2 Fokus und Ziel der Arbeit 2 Grundlagen zur Leistungselektronik und zu ihrer Zuverlässigkeitsbewertung 2.1 Aufbau typischer Leistungselektronikkomponenten und Module 2.1.1 Leistungsklassen und klassische Aufbauvarianten 2.1.2 Leistungshalbleiter 2.1.3 Substrattechnologien für Leistungsmodule 2.1.4 Verbindungstechniken in Leistungselektronikmodulen 2.1.4.1 Chipflächen- und Baugruppenkontaktierung 2.1.4.2 Chipanschlusskontaktierung 2.1.4.3 Kühlkörperanbindung 2.1.5 Verkapslungskonzepte 2.1.6 Kühlkonzepte in der Leistungselektronik 2.2 Typische Fehlermodi und -mechanismen 2.3 Lebensdauerbewertung von Leistungselektronik0 2.3.1 Globale Ansätze zur Produktqualifizierung und Zuverlässigkeitsbewertung0 2.3.2 Lebensdauertests in der Leistungselektronik 2.3.2.1 Überblick und Einordnung von Lastwechseltests 2.3.2.2 Testkonzepte und -strategien 2.3.3 Lebensdauermodellierung 3 Neue methodische Ansätze und Prüfstandsentwicklung 3.1 Überlagerung von aktiven Lastwechseln mit passiven Temperaturzyklen 3.2 Entwicklung und Aufbau eines Lastwechselprüfstandes zur Untersuchung von überlagerten Belastungstests 3.2.1 Konzeption 3.2.2 Kühlkörper-Design 3.2.3 Steuer- und Auswertesoftware 3.2.4 Lastwechselteststand 3.2.5 Messprozedur 3.2.6 Validierung der Tvj-basierten Temperaturmessung 3.3 Optisches In-situ-Monitoring während Lastwechseltests 3.3.1 Testaufbau und Probenpräparation 3.3.2 IR-Messungen an angeschliffenem Prüfling 4 Prüfgegenstände, Testplanung und Testdurchführung 4.1 Auswahl und Übersicht der Prüflinge 4.2 Testkonzeption und Versuchsplanung 4.2.1 Lastwechseltests 4.2.2 Temperaturschocktests 4.3 Testaufbau und -durchführung 4.3.1 Lastwechseltests 4.3.2 Temperaturschocktests 5 Testergebnisse 5.1 Messdatenanalyse und Auswerteprozedur 5.2 Statistische Testauswertung 5.2.1 Übersicht über Testergebnisse 5.2.2 Weibull-Verteilungen 5.3 Fehleranalytik 5.3.1 Bonddrahtausfälle 5.3.2 Lotdegradation 5.4 Optische In-situ-Analyse während aktiver Belastung 5.4.1 Methodik 5.4.2 Verschiebungsfelder in Abhängigkeit von ∆Tvj und Tvj,m 5.4.3 Einfluss der Einschaltzeit ton auf Verschiebungsfelder 5.4.4 Ableitung der Dehnungsfelder und Ergebnisdiskussion 6 Lebensdauermodellierung 6.1 Belastungsbasierte Lebensdauermodelle 6.1.1 Lebensdauerdiagramme und -einflussfaktoren 6.1.2 Multiple lineare Regression 6.1.3 Berücksichtigung der effektiven Temperatur T(v)j,eff 6.1.4 Vergleich der Lebensdauermodelle mit überlagerten Testergebnissen 6.1.5 Zusammenfassung 146 6.1.6 Einordnung der ermittelten Lebensdauermodelle 6.2 FE-Analyse zur Validierung der Ergebnisse aus der Lebensdauermodellierung 7 Zusammenfassung und Ausblick Literaturverzeichnis Abbildungsverzeichnis Tabellenverzeichnis
Active power cycling tests represent a standardized and well-established method for reliability evaluation and product qualification in power electronics. They are based on the application of recurring load current pulses, which are converted into cyclic temperature swings in the power component. The thereby induced thermo-mechanical stress, caused by the different material properties of the joining partners involved in the composite system, ultimately leads to the typical failure modes and mechanisms in the devices. However, these conventional tests do not sufficiently stimulate the complex load schemes in field operations in which different load factors occur simultaneously. In the context of the introduction of novel device and package technologies, increasingly harsh environmental operation conditions as well as increasing reliability and functional safety requirements, there is a need for improved reliability test methods. One possible approach is the combination of different load factors in order to increase test efficiency and test coverage. Within the scope of this thesis, systematic reliability investigations, including standard power cycling tests as well as power cycling tests superimposed with passive thermal cycles, were therefore carried out on discrete power components using a self-developed test rig. In addition to the investigation of different junction temperature profiles, a comparison of different component types was performed. On the basis of a qualitative and quantitative test evaluation, load-based lifetime models were derived. It was found that the lifetime models determined on the basis of the standard power cycling tests could not predict the test results of the superimposed power cycling tests. The reason for this was the influence of the temperature-dependent material behaviour of the moulding com-pound, which has an influence on the failure mode wire-bond lift-off. Based on these findings, the use of case-sensitive lifetime models is suggested that are able to take the changed damage physics into account. In addition, a new method for the optical in-situ investigation of moulded power devices is presented, which allows the investigation of thermal-transient as well as thermo-mechanical processes in the package under active loading conditions.:Symbol- und Abkürzungsverzeichnis Danksagung Kurzfassung Abstract 1 Einleitung 1.1 Motivation 1.2 Fokus und Ziel der Arbeit 2 Grundlagen zur Leistungselektronik und zu ihrer Zuverlässigkeitsbewertung 2.1 Aufbau typischer Leistungselektronikkomponenten und Module 2.1.1 Leistungsklassen und klassische Aufbauvarianten 2.1.2 Leistungshalbleiter 2.1.3 Substrattechnologien für Leistungsmodule 2.1.4 Verbindungstechniken in Leistungselektronikmodulen 2.1.4.1 Chipflächen- und Baugruppenkontaktierung 2.1.4.2 Chipanschlusskontaktierung 2.1.4.3 Kühlkörperanbindung 2.1.5 Verkapslungskonzepte 2.1.6 Kühlkonzepte in der Leistungselektronik 2.2 Typische Fehlermodi und -mechanismen 2.3 Lebensdauerbewertung von Leistungselektronik0 2.3.1 Globale Ansätze zur Produktqualifizierung und Zuverlässigkeitsbewertung0 2.3.2 Lebensdauertests in der Leistungselektronik 2.3.2.1 Überblick und Einordnung von Lastwechseltests 2.3.2.2 Testkonzepte und -strategien 2.3.3 Lebensdauermodellierung 3 Neue methodische Ansätze und Prüfstandsentwicklung 3.1 Überlagerung von aktiven Lastwechseln mit passiven Temperaturzyklen 3.2 Entwicklung und Aufbau eines Lastwechselprüfstandes zur Untersuchung von überlagerten Belastungstests 3.2.1 Konzeption 3.2.2 Kühlkörper-Design 3.2.3 Steuer- und Auswertesoftware 3.2.4 Lastwechselteststand 3.2.5 Messprozedur 3.2.6 Validierung der Tvj-basierten Temperaturmessung 3.3 Optisches In-situ-Monitoring während Lastwechseltests 3.3.1 Testaufbau und Probenpräparation 3.3.2 IR-Messungen an angeschliffenem Prüfling 4 Prüfgegenstände, Testplanung und Testdurchführung 4.1 Auswahl und Übersicht der Prüflinge 4.2 Testkonzeption und Versuchsplanung 4.2.1 Lastwechseltests 4.2.2 Temperaturschocktests 4.3 Testaufbau und -durchführung 4.3.1 Lastwechseltests 4.3.2 Temperaturschocktests 5 Testergebnisse 5.1 Messdatenanalyse und Auswerteprozedur 5.2 Statistische Testauswertung 5.2.1 Übersicht über Testergebnisse 5.2.2 Weibull-Verteilungen 5.3 Fehleranalytik 5.3.1 Bonddrahtausfälle 5.3.2 Lotdegradation 5.4 Optische In-situ-Analyse während aktiver Belastung 5.4.1 Methodik 5.4.2 Verschiebungsfelder in Abhängigkeit von ∆Tvj und Tvj,m 5.4.3 Einfluss der Einschaltzeit ton auf Verschiebungsfelder 5.4.4 Ableitung der Dehnungsfelder und Ergebnisdiskussion 6 Lebensdauermodellierung 6.1 Belastungsbasierte Lebensdauermodelle 6.1.1 Lebensdauerdiagramme und -einflussfaktoren 6.1.2 Multiple lineare Regression 6.1.3 Berücksichtigung der effektiven Temperatur T(v)j,eff 6.1.4 Vergleich der Lebensdauermodelle mit überlagerten Testergebnissen 6.1.5 Zusammenfassung 146 6.1.6 Einordnung der ermittelten Lebensdauermodelle 6.2 FE-Analyse zur Validierung der Ergebnisse aus der Lebensdauermodellierung 7 Zusammenfassung und Ausblick Literaturverzeichnis Abbildungsverzeichnis Tabellenverzeichnis