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1
Wei, Chi Pin, Zhao Lin Li, Hao Liu, and Zhi Xiang Chen. "Design of a Random Test Platform for DSP Serials Used in Embedded Systems." Advanced Materials Research 267 (June 2011): 98–103. http://dx.doi.org/10.4028/www.scientific.net/amr.267.98.
Повний текст джерелаАнотація:
Embedded systems with digital signal processor (DSP) become more and more popular for the increasing requirement of supercomputing these days. Efficient development of DSP serials used in embedded systems shortens the embedded system R&D cycle. Functional verification is one of the most complex and expensive tasks during DSP serials design process. A random test platform which is urged for DSP serials verification is proposed in this paper. The platform can automatically generate the random test program. The platform also realized the recording and checking of simulation results, which make the verification more effective. In order to improve the efficiency of DSP verification, a testing experience library has been generated through the testing procedure. This platform can be transplanted for different DSP models easily by updating few modules. According to the verification results, this platform has satisfactory coverage of DSP models.
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Sandi, Anuradha. "VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH." International Journal of Engineering Technologies and Management Research 6, no. 6 (March 25, 2020): 40–50. http://dx.doi.org/10.29121/ijetmr.v6.i6.2019.392.
Повний текст джерелаАнотація:
In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard & fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.
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Sharma, N., P. Kumar, N. Singh, and U. Mehta. "Digital energy monitor: design, simulations and prototype." South Pacific Journal of Natural and Applied Sciences 35, no. 2 (2017): 45. http://dx.doi.org/10.1071/sp17005.
Повний текст джерелаАнотація:
This paper demonstrates the design and implementation of a GSM based digital energy monitoring device. Firstly fuzzy based model is developed to replicate the characteristic of current and voltage sensors. The entire system is also studied and simulated in terms of utility side supply, load, microcontroller digitization and GSM communication. A virtual data sharing technic is also studied for the proposed system using state flow logic. A prototype system is verified real-time with its test and verification phase results. In this work, remote monitoring of electricity has been made easier for the utility. Demand side management is also presented as customers can instantly get their electricity consumptions when requested. Further, an effective overcurrent monitoring system has been embedded along with a backup battery source. Results obtained from the experiments prove that with this emerging technology it is possible to move towards a smarter grid at a rapid and cost effective way.
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Chen, Fu Long, Zhao Xia Zhu, and Xiao Ya Fan. "FPGA-Based In-Circuit Verification of Digital Systems." Advanced Materials Research 187 (February 2011): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amr.187.362.
Повний текст джерелаАнотація:
In general hardware designers design integrated circuit with hardware description languages or schematic diagram. However the growth of circuit complexity makes circuit design error prone and time consuming. The resulting descriptions tend to be lengthy and hard to reason about. Therefore functional simulation, timing simulation and in-circuit test are three essential steps to ensure that the designed circuit is correct. This paper presents a method of in-circuit verification on FPGA using UART communication between the computer and the FPGA board. Through UART, designers can convert the parallel input vector into a set of serial stimulus signals and send them to the FPGA board, and also can receive the feedback serial signals from the FPGA board and reconvert them into a parallel output vector. Given the input and output ports of the verified circuit component, a verification platform based on UART communication will be customized automatically by the in-circuit verification platform generator. This breaks the constraint of the FPGA board's limited pins and supports wide-scale input/output vectors and can be applied in in-circuit test of digital circuit.
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Zhang, Xu, Zhiguang Deng, Jun Li, Youwei Yang, Quan Ma, and Mingming Liu. "Design and Verification of Reactor Power Control Based on Stepped Dynamic Matrix Controller." Science and Technology of Nuclear Installations 2019 (November 3, 2019): 1–11. http://dx.doi.org/10.1155/2019/4973120.
Повний текст джерелаАнотація:
As key equipment in nuclear power plant, the reactor power control system is adopted to strictly control and regulate the reactor power of a PWR (pressurized water reactor) in a nuclear power plant. A well-optimized predictive control algorithm based on SDMC (stepped dynamic matrix controller) is developed and introduced in this paper and applied to the power regulation of a reactor power model. In addition, the test and verification of this application is conducted by two different methods and devices: the virtual verification platform and the physical DCS (digital control system). The result of the verification suggests that the application of SDMC gains a better performance in the maximum dynamic deviation, adjustment time, overshoot, and so on.
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Zhu, Pengcheng, and Haojie Li. "Design of Aeronautical Digital Video and Communication Bus Processing System." Journal of Physics: Conference Series 2252, no. 1 (April 1, 2022): 012044. http://dx.doi.org/10.1088/1742-6596/2252/1/012044.
Повний текст джерелаАнотація:
Abstract With the development of avionics systems, Avionics Digital Video Bus (ARINC 818) and Digital Information Transmission System (Arinc429) have become a new generation of aviation video transmission and communication bus standard respectively. Aiming at the characteristics of ARINC 818 and Arinc429, an aeronautical digital video and communication bus processing system is designed. First, the ARINC 818 aviation video transmission bus and the Arinc429 communication bus standard are introduced. Then, the design principles of the aeronautical digital video and communication bus processing system are described according to this standard, and the design scheme of each system component is introduced in detail. Finally, build a hardware test platform for testing and verification. The system development follows an integrated and modular design, with the Application Processing Unit (APU) main processor and Field Programmable Gate Array (FPGA) as the core, which realizes the superposition of 1-channel input ARINC 818 video with internally generated characters, and then outputs 1-channel ARINC 818 to the function displayed on the display. At the same time, it supports 7-channel Electronic Industries Association-422 (EIA-422) and 4-channel Arinc429 bus communication. In addition, the system supports the processing of 22 input discrete quantities and 7 input analog quantities. The design has been successfully used in a certain type of aircraft display control management system.
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Zhu, Pengcheng, and Haojie Li. "Design of Aeronautical Digital Video and Communication Bus Processing System." Journal of Physics: Conference Series 2252, no. 1 (April 1, 2022): 012044. http://dx.doi.org/10.1088/1742-6596/2252/1/012044.
Повний текст джерелаАнотація:
Abstract With the development of avionics systems, Avionics Digital Video Bus (ARINC 818) and Digital Information Transmission System (Arinc429) have become a new generation of aviation video transmission and communication bus standard respectively. Aiming at the characteristics of ARINC 818 and Arinc429, an aeronautical digital video and communication bus processing system is designed. First, the ARINC 818 aviation video transmission bus and the Arinc429 communication bus standard are introduced. Then, the design principles of the aeronautical digital video and communication bus processing system are described according to this standard, and the design scheme of each system component is introduced in detail. Finally, build a hardware test platform for testing and verification. The system development follows an integrated and modular design, with the Application Processing Unit (APU) main processor and Field Programmable Gate Array (FPGA) as the core, which realizes the superposition of 1-channel input ARINC 818 video with internally generated characters, and then outputs 1-channel ARINC 818 to the function displayed on the display. At the same time, it supports 7-channel Electronic Industries Association-422 (EIA-422) and 4-channel Arinc429 bus communication. In addition, the system supports the processing of 22 input discrete quantities and 7 input analog quantities. The design has been successfully used in a certain type of aircraft display control management system.
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Sun, Peng, Qi Shao, Ying Yu Liu, and Wei Ping Chen. "A New Method of Design and Verification of Digital Silicon Gyroscopes Closed-Loop Driving System Based on MicroBlaze." Key Engineering Materials 645-646 (May 2015): 771–76. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.771.
Повний текст джерелаАнотація:
The article brings out a digital silicon gyroscopes closed-loop driving system using the phase relationship of the input driving signal and the signal of the forced motion of the mass block in sensor structure based on analyzing the working principle and phase characters of digital silicon gyroscopes. We make a low-cost, simple and high precision measurement technique for resonant frequency of silicon micro-machinery gyroscopes by the whole digital locked loop system designed with MicroBlaze method. Dichotomy and Fourier transform spectrometry method constitute the algorithm of the system and the solution precision can be determined by the number of the times of approximation. Under the control of the MicroBlaze softcore, the system realizes the realization of the digital signal, the high speed frequency transformation, the acquisition of mass block response signal and the calculation of phase difference. Lastly, each module of the system and the whole system are simulated, the whole system is approved on the test broad.
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Rakic, Aleksandar, Sasa Zivanovic, Zoran Dimic, and Mladen Knezevic. "Digital twin control of multi-axis wood CNC machining center based on LinuxCNC." BioResources 16, no. 1 (December 18, 2020): 1115–30. http://dx.doi.org/10.15376/biores.16.1.1115-1130.
Повний текст джерелаАнотація:
This paper presents an application of an open architecture control system implemented on a multi-axis wood computer numerical control milling machining center, as a digital twin control. The development of the digital twin control system was motivated by research and educational requirements, especially in the field of configuring a new control system by “virtual commissioning”, enabling the validation of the developed controls, program verification, and analysis of the machining process and monitoring. The considered wood computer numerical control (CNC) machining system is supported by an equivalent virtual machine in a computer-aided design and computer-aided manufacturing (CAD/CAM) environment, as well as in the control system, as a digital twin. The configured virtual machines are used for the verification of the machining program and programming system via machining simulation, which is extremely important in multi-axis machining. Several test wood workpieces were machined to validate the effectiveness of the developed control system based on LinuxCNC.
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Hudson, Jeffrey A., Aernout Oudenhuijzen, and Gregory F. Zehner. "Digital Human Modelling Systems: A Procedure for Verification and Validation Using the F-16 Crew Station." Proceedings of the Human Factors and Ergonomics Society Annual Meeting 44, no. 38 (July 2000): 723–26. http://dx.doi.org/10.1177/154193120004403810.
Повний текст джерелаАнотація:
Digital Human Modelling Systems (HMS's) are considered a basic element in the cockpit design process. Their bio-fidelity has yet to be fully demonstrated, however. Currently, a joint project, undertaken by the Air Force Research Lab (AFRL/HECP) and the Netherlands (TNO HFRI), is addressing this issue. This effort will help improve methods for controlling and assuring anthropometric accommodation of crew systems in military aircraft. A verification and validation procedure is being developed as a part of this project and has been implemented for several commercially available HMS's. The two phases of the procedure are: 1. Anthropometric Verification: Quantify and compare a set of anthropometric values measured on 8 test subjects with the same set measured on their corresponding digital manikins (their human models), and 2. F-16 Cockpit Validation: Quantify and compare field test results (involving reaches, clearance, vision) of the same 8 test subjects in an F-16 cockpit, to the digital test results obtained with the HMS's using digital models of the subjects placed in an F-16 CAD drawing. The digital tests are conducted without knowledge of the field data results. The ultimate goal of this project is to set the standard for verification and validation of Human Modelling Systems to ensure their bio-fidelity. A complete discussion of the methods is provided below. The results, however, were not available at the time this manuscript was submitted, but will be covered in the oral presentation.
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Wen-xing, HE, and CHEN Chang-yu. "Research of Spacecraft Assembly Simulation with Ground Mechanical Equipments." MATEC Web of Conferences 179 (2018): 03017. http://dx.doi.org/10.1051/matecconf/201817903017.
Повний текст джерелаАнотація:
In order to overcome the shortcomings of the physical test conditions, research and development of the spacecraft container simulation verification platform to enhance the level of digital development of the spacecraft container. Based on the theory of rigid-flexible coupling dynamics, the dynamic model of the box system is established. The dynamic external excitation is determined by obtaining the track spectrum and identifying the condition of the line. Based on the computational fluid dynamics, the thermal model of the spacecraft container is established, and the container is realized by simulating the natural convection and air conditioning control spacecraft container thermal simulation. Using modular design, C/S architecture and navigation process to achieve the simulation platform architecture versatility, ease of maintenance and scalability and other needs. Finally, the mechanics and thermal performance verification of the spacecraft container and physical test are carried out. The results show that the simulation results of the box dynamic system and the thermal system are in good agreement with the experimental results.
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Kersten, T. P., D. Stallmann, and F. Tschirschwitz. "DEVELOPMENT OF A NEW LOW-COST INDOOR MAPPING SYSTEM – SYSTEM DESIGN, SYSTEM CALIBRATION AND FIRST RESULTS." ISPRS - International Archives of the Photogrammetry, Remote Sensing and Spatial Information Sciences XLI-B5 (June 15, 2016): 55–62. http://dx.doi.org/10.5194/isprs-archives-xli-b5-55-2016.
Повний текст джерелаАнотація:
For mapping of building interiors various 2D and 3D indoor surveying systems are available today. These systems essentially differ from each other by price and accuracy as well as by the effort required for fieldwork and post-processing. The Laboratory for Photogrammetry & Laser Scanning of HafenCity University (HCU) Hamburg has developed, as part of an industrial project, a lowcost indoor mapping system, which enables systematic inventory mapping of interior facilities with low staffing requirements and reduced, measurable expenditure of time and effort. The modelling and evaluation of the recorded data take place later in the office. The indoor mapping system of HCU Hamburg consists of the following components: laser range finder, panorama head (pan-tilt-unit), single-board computer (Raspberry Pi) with digital camera and battery power supply. The camera is pre-calibrated in a photogrammetric test field under laboratory conditions. However, remaining systematic image errors are corrected simultaneously within the generation of the panorama image. Due to cost reasons the camera and laser range finder are not coaxially arranged on the panorama head. Therefore, eccentricity and alignment of the laser range finder against the camera must be determined in a system calibration. For the verification of the system accuracy and the system calibration, the laser points were determined from measurements with total stations. The differences to the reference were 4-5mm for individual coordinates.
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Moon, Sangook, and Jongsu Park. "System Level Design of Reconfigurable Server Farms Using Elliptic Curve Cryptography Processor Engines." Journal of Applied Mathematics 2014 (2014): 1–8. http://dx.doi.org/10.1155/2014/390176.
Повний текст джерелаАнотація:
As today’s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the microarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design are not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a soft and advanced type of SystemVerilog at an electronic system level. We apply the concept of design-and-reuse with a high level of abstraction to implement elliptic curve crypto-processor server farms. With the concept of the superior level of abstraction to the RTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms as well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required error-prone Verilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software, sacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2m) serial multiplication architecture.
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Tokhi, M. O., and M. A. Hossain. "Self-Tuning Active Vibration Control in Flexible Beam Structures." Proceedings of the Institution of Mechanical Engineers, Part I: Journal of Systems and Control Engineering 208, no. 4 (November 1994): 263–78. http://dx.doi.org/10.1243/pime_proc_1994_208_339_02.
Повний текст джерелаАнотація:
This paper presents the design and performance evaluation of an adaptive active control mechanism for vibration suppression inflexible beam structures. A cantilever beam system in transverse vibration is considered. First-order central finite difference methods are used to study the behaviour of the beam and develop a suitable test and verification platform. An active vibration control algorithm is developed within an adaptive control framework for broadband cancellation of vibration along the beam using a single-input multi-output (SIMO) control structure. The algorithm is implemented on a digital processor incorporating a digital signal processing (DSP) and transputer system. Simulation results verifying the performance of the algorithm in the suppression of vibration along the beam, using single-input single-output and SIMO control structures, are presented and discussed.
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Shen, Yi, and Sixian Sun. "Design of International Chinese Education Promotion Platform Based on Artificial Intelligence and Facial Recognition Technology." Computational Intelligence and Neuroscience 2022 (July 13, 2022): 1–11. http://dx.doi.org/10.1155/2022/6424984.
Повний текст джерелаАнотація:
With the continuous development of today’s society, digital image processing technology has been applied in more and more fields, among which authentication in digital image processing technology has become a hot field. In the process of identity verification, the face is used as the basis of feature recognition because the method of using the face as a feature basis is more easily accepted by the public and the operation is simple and the feasibility is stronger. In the online education model, observing and comparing students’ facial emotions through the platform and analyzing students’ learning goals, learning effects, learning emotions, and contradictions and conflicts arising in the process of cooperation have become an effective teaching evaluation system. Up to now, China has developed into the second largest economy in the world. The global “Chinese fever” has brought China’s culture into a new stage of development. Countries in the world learn Chinese culture by developing Chinese language courses. By building a Chinese learning intelligent system with a B/S structure, this system can effectively evaluate the teaching process. It can be seen from the test results that the platform meets the basic requirements of functional design.
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Szplet, Ryszard, and Arkadiusz Czuba. "Two-Stage Clock-Free Time-to-Digital Converter Based on Vernier and Tapped Delay Lines in FPGA Device." Electronics 10, no. 18 (September 7, 2021): 2190. http://dx.doi.org/10.3390/electronics10182190.
Повний текст джерелаАнотація:
This article presents an idea, design and test results of a new time-to-digital converter (TDC) implemented in an FPGA device. The high resolution of 13 ps and measurement range of 3.4 ns are achieved based on a two-stage time interpolation (TI). In the first and second stages of the TI we have used the Vernier delay line and a single tapped delay line, respectively. This solution provides respectable metrological parameters without the need to use a clock signal, and significantly saves the logical resources of an integrated circuit (IC). The proposed method, generally based on two different variants of the discrete delay line, is easy to design and implement in digital ICs. For experimental verification, the TDC was implemented in a single programmable device from family Virtex-7 (Xilinx).
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Korkas, Christos, Asimina Dimara, Iakovos Michailidis, Stelios Krinidis, Rafael Marin-Perez, Ana Isabel Martínez García, Antonio Skarmeta, et al. "Integration and Verification of PLUG-N-HARVEST ICT Platform for Intelligent Management of Buildings." Energies 15, no. 7 (April 2, 2022): 2610. http://dx.doi.org/10.3390/en15072610.
Повний текст джерелаАнотація:
THe energy-efficient operation of microgrids—a localized grouping of consuming loads (domestic appliances, EVs, etc.) with distributed energy sources such as solar photovoltaic panels—suggests the deployment of Energy Management Systems (EMSs) that enable the actuation of controllable microgrid loads coupled with Artificial Intelligence (AI) tools. Such tools are capable of optimizing the aggregated performance of the microgrid in an automated manner, based on an extensive network of Advanced Metering Infrastructure (AMI). Modular adaptable/dynamic building envelope (ADBE) solutions have been proven an effective solution—exploiting free façade areas instead of roof areas—for extending the thermal inertia and energy harvesting capacity in existing buildings of different nature (residential, commercial, industrial, etc.). This study presents the PLUG-N-HARVEST holistic workflow towards the delivery of an automatically controllable microgrid integrating active ADBE technologies (e.g., PVs, HVACs). The digital platform comprises cloud AI services and functionalities for energy-efficient management, data healing/cleansing, flexibility forecasting, and the security-by-design IoT to efficiently optimize the overall performance in near-zero energy buildings and microgrids. The current study presents the effective design and necessary digital integration steps towards the PLUG-N-HARVEST ICT platform alongside real-life verification test results, validating the performance of the platform.
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Guo, Zhongjie, Yangle Wang, Ruiming Xu, and Ningmei Yu. "High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor." Sensors 23, no. 2 (January 4, 2023): 595. http://dx.doi.org/10.3390/s23020595.
Повний текст джерелаАнотація:
The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.
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Chen, Junxian, Jianhai Zhang, and Hongwei Zhao. "Development and Experimental Verification of a High-Temperature and In-Plane Biaxial Testing Apparatus." Machines 10, no. 11 (November 10, 2022): 1054. http://dx.doi.org/10.3390/machines10111054.
Повний текст джерелаАнотація:
Given the lack of primary data on heat-resistant composites under high-temperature conditions, the focus of this paper is the development of an in-plane biaxial apparatus under high temperatures and complex loads. Besides loading complex loads up to 80 kN, the apparatus can load under high-temperatures up to 2500 °C. A C/C tensile/compression test at 1700 °C illustrates the successful use of high-temperature digital speckle pattern technology to evaluate the in-plane mechanical properties of heat-resistant composites at 1700 °C under biaxial stress. A high-temperature impact test of a graphite specimen at 2500 °C shows that this apparatus can load at a high temperature in a vacuum and inert gas atmosphere. The yield characteristics of the Q235 steel sheet under in-plane stress show that the apparatus can conduct various mechanical loads, including tension–tension, tension–compression, and compression–compression loads. The proposed equipment can measure the in-plane mechanical properties of composite materials, particularly heat-resistant composites. The obtained results can be applied to structural design, life prediction, and reliability evaluation, as well as for the development, research, and design of aerospace instruments and critical materials.
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wang, Huan. "Construction and Application of a New Metal Random Matrix-Based Theory in a Numerical Phantom of the Metaverse NFT." Mathematical Problems in Engineering 2022 (September 9, 2022): 1–7. http://dx.doi.org/10.1155/2022/3429528.
Повний текст джерелаАнотація:
As the metaverse is hot, nonhomogenized tokens (NFT) as digital artwork identifiers present different characteristics and application values from other homogenized tokens, and their use for copyright verification will suffer from the problems of storage space limitation and data verification reliance on database, this study designs an NFT digital copyright authentication model for textual works. To cater for the uncontrollability of conventional Hash algorithms in stream matching due to the high conflict rate, a new random matrix theory is applied to propose a new Hash algorithm, which is used on the block structure of NFT credential authentication, while extending the block structure so that the data within the work is completely stored in the blockchain with NFT as the credential, allowing the database to store the work data in a relatively safe manner. The verification of the work data has the immutability and unique cryptographic solution of NFT. The NFT-based digital model collects TR information and conducts 30 tests, and the average test time for generating blocks is 0.53 s. Through the block query for detection, 248,655 words have exceeded the number of words of an article, and the consumption time is only 0.23s, to meet the customer's real-time query requirements for the system. According to the overhead ratio, the record storage expenditure is about 2-3 times of the text storage expenditure, the work storage expenditure, and the storage expenditure for storing 240,000 words for authentication is about 3720 KB.
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Irwanto, Irwanto, Bagus Dwi Cahyono, and Juanda Mitra Situmeang. "Development of Macromedia Flash 8-Based Learning Media in Simulation and Digital Communication Subjects in Vocational High School." Jurnal Pembelajaran Fisika 10, no. 2 (June 30, 2019): 207–18. http://dx.doi.org/10.23960/jpf.v10.n2.202205.
Повний текст джерелаАнотація:
Vocational education has a real goal, which is to prepare students to enter the world of work. The aims of this study were (1) to find out the planning stages of Macromedia flash-based learning media, and (2) to find out the feasibility of Macromedia flash-based learning media in simulation and digital communication subjects in vocational schools. This type of research is developed with the model used the V model or commonly called the verification and validation model. The system development process includes requirements analysis, requirements standards, design specifications, and program specifications. Based on the test results, it is known that the learning media based on Macromedia flash on simulation and digital communication subjects in SMKs that have been developed are suitable for use as learning media in SMKs. The average score obtained as a whole aspect of media experts was 3.58 in the very good category, material experts with a score of 3.62 in the very good category, and the student response score to Macromedia flash-based learning media was 3.89 very well. good category. good. So learning media based on Macromedia Flash 8 shows very feasible to be used as a learning medium in simulation and digital communication subjects in Vocational High Schools. Keywords: Macromedia Flash, Vocational Learning, Simulation, Digital Communication
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Mohan Kumar, B. N., and H. G. Rangaraju. "Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA." International Journal of Circuits, Systems and Signal Processing 15 (July 22, 2021): 700–712. http://dx.doi.org/10.46300/9106.2021.15.78.
Повний текст джерелаАнотація:
For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.
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Zhang, Jie, and Jiudong Zheng. "Prototype Verification of Self-Interference Suppression for Constant-Amplitude Full-Duplex Phased Array with Finite Phase Shift." Electronics 11, no. 3 (January 18, 2022): 295. http://dx.doi.org/10.3390/electronics11030295.
Повний текст джерелаАнотація:
In view of the strong self-interference problem when the practical phased array system is simultaneously applied for transmission and reception, under the constraints including limited quantization number, constant envelope amplitude, scanning mode, wideband signal mode, etc., this work studies it and proposes the amplitude-phase joint adjustment method and the phase-only method for beamforming optimization. Through digital simulation design, electromagnetic simulation evaluation and principle test verification, under the actual array system conditions, including 6-bit phase quantization or phase step size of 5.625° and amplitude 0.5 dB quantization step, when the transmitting beam is pointing (0°, 0°), the research has achieved a performance of 11.9~14.4 dB for self-interference suppression; at the same time, the optimized beam shape is maintained well, and the ratio of the main lobe to the side lobes does not change significantly, but the beam gain has a loss of about 2~3 dB. In addition, we studied the interference suppression performance and beam feature retention performance of the optimized beamforming weights in the case of array scanning and broadband signals, and analyzed the influence of the changes in the mutual coupling characteristics between elements caused by scanning and frequency changes on the cancellation performance. This provides a reference for the application research of the simultaneous transmitting and receiving self-interference suppression technology in the actual array system state.
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Paul, Shubhra Deb, and Swarup Bhunia. "SILVerIn: Systematic Integrity Verification of Printed Circuit Board Using JTAG Infrastructure." ACM Journal on Emerging Technologies in Computing Systems 17, no. 3 (June 25, 2021): 1–28. http://dx.doi.org/10.1145/3460232.
Повний текст джерелаАнотація:
A printed circuit board (PCB) provides necessary mechanical support to an electronic system and acts as a platform for connecting electronic components. Counterfeiting and in-field tampering of PCBs have become significant security concerns in the semiconductor industry as a result of increasing untrusted entities in the supply chain. These counterfeit components may result in performance degradation, profit reduction, and reputation risk for the manufacturers. While Integrated Circuit (IC) level authentication using physical unclonable functions (PUFs) has been widely investigated, countermeasures at the PCB level are scarce. These approaches either suffer from significant overhead issues, or opportunistic counterfeiters can breach them like clockwork. Besides, they cannot be extended to system-level (both chip and PCB together), and their applications are also limited to a specific purpose (i.e., either counterfeiting or tampering). In this article, we introduce SILVerIn , a novel systematic approach to verify the authenticity of all chips used in a PCB as well as the board for combating attacks such as counterfeiting, cloning, and in-field malicious modifications. We develop this approach by utilizing the existing boundary scan architecture (BSA) of modern ICs and PCBs. As a result, its implementation comes at a negligible (∼0.5%) hardware overhead. SILVerIn is integrated into a PCB design during the manufacturing phase. We implement our technique on a custom hardware platform consisting of an FPGA and a microcontroller. We incorporate the industry-standard JTAG (Joint Test Action Group) interface to transmit test data into the BSA and perform hands-on measurement of supply current at both chip and PCB levels on 20 boards. We reconstruct these current values to digital signatures that exhibit high uniqueness, robustness, and randomness features. Our approach manifests strong reproducibility of signatures at different supply voltage levels, even with a low-resolution measurement setup. SILVerIn also demonstrates a high resilience against machine learning-based modeling attacks, with an average prediction accuracy of ∼51%. Finally, we conduct intentional alteration experiments by replacing the on-board FPGA to replicate the scenario of PCB tampering, and the results indicate successful detection of in-field modifications in a PCB.
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Ramadan, Tarek. "SYSTEM-LEVEL, POST-LAYOUT ELECTRICAL ANALYSIS FOR HIGH-DENSITY ADVANCED PACKAGING." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000856–77. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_015.
Повний текст джерелаАнотація:
INTRODUCTION High-density advanced packaging (HDAP) continues to be the promising “More” in the “More than Moore” approach for improved form factor, functionality, and integration of multiple dies built using different technology nodes. HDAP offerings from outsourced assembly and test (OSAT) companies and foundries are continuously increasing. However, the full commercial productization of such offerings will require the assurance of both an acceptable yield and correct (as intended) functionality. This assurance, like that for integrated circuits (ICs), will come from the availability of proven and qualified electronic design automation (EDA) tools and flows that can be used by the design houses to build HDAPs with the confidence that they are compliant with the foundry/OSAT requirements and recommendations. The need for and general concept of assembly design kits (ADKs) that provide proven, qualified flows for HDAPs has been previously discussed in multiple white papers. In addition, there have been analyses of the need for assembly-level layout vs. schematic (LVS) verification for HDAPs. Best practices for an assembly-level LVS process have been proposed, including the required inputs (data, formats, etc.), and likely hurdles and potential errors have been highlighted. There has even been discussion of how parasitic extraction could be achieved for packages. However, as HDAP technologies and flows mature, system-level designers want to know if package design rule checking (DRC), assembly-level LVS, and layout vs. layout (LVL) verification (die-to-package alignment, scaling, orientation, etc.) are sufficient to guarantee correct functionality and successful manufacturing of the HDAP. While this question may depend on how complicated the HDAP is, in general, the answer (for now) is no. As HDAP technologies become more and more similar to IC technologies, it is clear that, although the physical verification steps for HDAP may be considered good progress, they are only part of a much more comprehensive flow, one that must account for a more in-depth, system-level electrical analysis. Of course, at the same time, expanded EDA tool support is required to ensure fast, accurate, automated flows that ensure package designers can meet their market schedules and expectations. HDAP POST-LAYOUT ELECTRICAL ANALYSIS In the case of an HDAP design, the foundry/OSAT expects that each component is designed and validated to meet the required HDAP constraints and specifications. For an analog-based flow, the designer must simulate the HDAP system circuitry, including parasitics, to ensure it meets the intended performance specifications. For a digital-based flow, the designer must run static timing analysis (STA) on the complete HDAP system, including parasitics, to ensure it meets the overall system timing budget. From an EDA perspective, building an automated flow to support these checks/analyses provides assurance that these processes can occur in a consistent, repeatable manner while ensuring accuracy and minimizing runtime. In general, EDA approaches take one of two paths. SINGLE COCKPIT In the cockpit approach, an EDA supplier builds a single simulator infrastructure to support HDAP circuit simulation, parasitic extraction (PEX), and static timing analysis (STA). Although a single interface seems convenient, it forces the designer to use the same design tool for all components at all levels (die and package). This approach may be too restrictive, given that HDAP design and verification typically require the involvement of multiple groups with varying backgrounds and tool preferences. Although this approach would be useful when building “fully live” heterogeneous HDAPs (i.e., both die and package are under development simultaneously, and can both be edited for performance), this is rarely the case. More commonly, known good dies (which have already been taped out) are used to build an HDAP. TOOL-AGNOSTIC In the tool-agnostic approach, an EDA supplier enables the user to construct the needed system-level connectivity of the HDAP (including parasitics), regardless of which design tools are used to build any one die or the package. Once the system-level connectivity is available, it can be exported in the required format to any circuit simulation/STA tool to simulate or analyze the entire HDAP system. This approach introduces minimum disruption to existing tools/methodologies used for die and package design. This paper discusses the implementation of a system-level parasitic netlist process for the HDAP using the tool-agnostic approach.
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Wang, Zhen-Ying, Zhi-Yun Liu, Ting-Wei Ma, Chen Sun, Liu Liu, Yu Huang, and Gang-Miao Guo. "The Implementation of Diverse Actuation System in ACPR1000 Nuclear Power Plants." Science and Technology of Nuclear Installations 2021 (September 6, 2021): 1–10. http://dx.doi.org/10.1155/2021/5529570.
Повний текст джерелаАнотація:
In order to improve the capability of dealing with software common cause failure (CCF) of digital reactor protection and monitoring system (RPMS), the diverse actuation system (DAS) is introduced for ACPR1000 nuclear power plants. From economic and feasibility point of view, the solution of DAS sharing with RPMS sensors and actuators is suggested; after capturing the function requirement of DAS, the automatic functions and manual functions assigned to it are determined based on transient analysis of design basic accidents concurrent with software CCF of RPMS. The independent verification proves that the reactor can be fallen back to and maintained at safety shutdown state, thanks to these DAS functions. Insight into probabilistic safety assessment proves significant reductions of risks are contributed. The critical technical issues while implementing DAS, such as measures to ensure its diversity from RPMS, precautions for preventing from its spurious actuation, isolation and independency from RPMS, and its testability and maintainability, are deliberately settled to improve its engineering reliability and alleviate the impact on RPMS as far as possible. Field programmable gate array technology that is diversified from RPMS is chosen to build DAS of ACPR1000 nuclear power plant, and the commissioning test verifies that it is capable of performing its designed functions. At last, a set of DAS-specific, paper-based, and event-oriented emergency operating procedure is developed, verified, and validated. Until now, the DAS system has always been successfully operating in all ACPR1000 nuclear power plants for several years.
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Shahriar Hazari, Shihab, and Qusay H. Mahmoud. "Improving Transaction Speed and Scalability of Blockchain Systems via Parallel Proof of Work." Future Internet 12, no. 8 (July 27, 2020): 125. http://dx.doi.org/10.3390/fi12080125.
Повний текст джерелаАнотація:
A blockchain is a distributed ledger forming a distributed consensus on a history of transactions, and is the underlying technology for the Bitcoin cryptocurrency. Its applications are far beyond the financial sector. The transaction verification process for cryptocurrencies is much slower than traditional digital transaction systems. One approach to scalability or the speed at which transactions are processed is to design a solution that offers faster Proof of Work. In this paper, we propose a method for accelerating the process of Proof of Work based on parallel mining rather than solo mining. The goal is to ensure that no more than two or more miners put the same effort into solving a specific block. The proposed method includes a process for selection of a manager, distribution of work and a reward system. This method has been implemented in a test environment that contains all the characteristics needed to perform Proof of Work for Bitcoin and has been tested, using a variety of case scenarios, by varying the difficulty level and number of validators. Experimental evaluations were performed locally and in a cloud environment, and experimental results demonstrate the feasibility the proposed method.
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Tamarkin, M. A., E. E. Tishchenko, and R. G. Tishchenko. "Technological support of digital production when processing parts using a ball-rod hardener." iPolytech Journal 26, no. 2 (July 4, 2022): 184–96. http://dx.doi.org/10.21285/1814-3520-2022-2-184-196.
Повний текст джерелаАнотація:
In this work, a module of an automated design system for machining using a multi-contact vibrating impact tool, namely a ball-rod hardener, was developed. The technological process of machining using such a hardener was studied. The performance and production cost of machining expressed as the duration and cost of achieving the specified hardening parameters were used to assess the efficiency. The specified geometric, physical and mechanical parameters of the surface layer of processed parts were used as restrictive functions. Residual stresses in samples were determined by Davydenko’s method. The Microsoft Visual Studio software and the C# programming language were used to automate process design. The studies established that the quality of the surface layer of parts is influenced by the main technological parameters (the impact energy of the indenter, the number of rods and grinding radius and tension in processing). The adequate theoretical models of developing various quality parameters of the surface layer of machined parts and processing time were obtained from the theoretical studies of the machining process using a ball-rod hardener. The obtained dependence was subjected to a comprehensive verification under the operating conditions at PJSC “Rostvertol” (Rostov-on-Don). Residual stresses in the surface layer of the BRH machined parts were measured using the ASCON-3-KI automated test stand produced by the Kazan Aviation Institute. The discrepancy between the theoretical and experimental results of the machining process was less than 15 %. The adequacy of the theoretical formulas was assessed by Fisher’s criterion. Based on the research findings, an algorithm and method of designing rational parameters for machining parts of complex geometry using a ball-rod hardener were developed. Using this software for the automated design of technological processes allowed the time of manufacturing preparation to be reduced and the stable quality of machined parts to be ensured. This offers manufacturing preparation in a digital production environment and ensures a significant increase in the useful life of manufactured products.
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Khan, Ayesha, Mujtaba Hussain Jaffery, Yaqoob Javed, Jehangir Arshad, Ateeq Ur Rehman, Rabia Khan, Mohit Bajaj, and Mohammed K. A. Kaabar. "Hardware-in-the-Loop Implementation and Performance Evaluation of Three-Phase Hybrid Shunt Active Power Filter for Power Quality Improvement." Mathematical Problems in Engineering 2021 (October 14, 2021): 1–23. http://dx.doi.org/10.1155/2021/8032793.
Повний текст джерелаАнотація:
The excessive use of nonlinear load causes electric current harmonics that ultimately downgrades the electrical power quality. If a failure exists due to internal integration of a power system in any one of the internal networks, it causes uncomplimentary consequences to the entire power system’s performance. This paper proposed a hybrid shunt active harmonic power filter (HSAHPF) design to reduce harmonic pollution. A digital controller HIL simulator has been modeled using a three-phase voltage source inverter to test the efficiency of HSAHPF and the performance of control algorithms. Moreover, the instantaneous active and reactive current theory (Id − Iq) and instantaneous active and reactive power theory (Pq0) control algorithms are implemented for the reference current generation in HSAHPF, resulting in reduced harmonic distortions, power factor improvement for a balanced nonlinear load. The control algorithms are further employed in Arduino MEGA to keep the factor of cost-effectiveness. The simulation of the proposed design has been developed in Simulink. The validation and testing of HSAHPF using controller HIL simulation prove the control algorithms’ ability to run in a portable embedded device. The statistical analysis of the proposed system response provides a minimum total harmonic distortion (THD) of 2.38 from 31.74 that lies in IEEE 519-1992 harmonic standards with an improved stability time of 0.04 s. The experimental verification and provided results of the HIL approach validate the proposed design. Significant mitigation of harmonics can be observed, consequently enhancing the power quality with power factor near unity.
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Tawadros, Peter, Mohamed Awadallah, Paul Walker, and Nong Zhang. "Using a low-cost bluetooth torque sensor for vehicle jerk and transient torque measurement." Proceedings of the Institution of Mechanical Engineers, Part D: Journal of Automobile Engineering 234, no. 2-3 (July 9, 2019): 423–37. http://dx.doi.org/10.1177/0954407019861613.
Повний текст джерелаАнотація:
This paper presents the use and development of a specific wireless torque measurement system that is used to obtain the transient torque performance of vehicle transmissions. The torque sensor is strain-based, using surface-mounted strain gauges on a prop shaft. The gauges are connected to a compact printed circuit board, which is clamped to the shaft next to the strain gauges using a three-dimensional printed housing. The printed circuit board contains an amplifier, low-pass filter, analog-to-digital converter, microcontroller and bluetooth transceiver. The printed housing is impact resistant carbon-reinforced nylon and securely retains the printed circuit board and the battery powering the device. The transmitted torque data are received by a transceiver, which is interfaced to a PC through an RS-232 connection. NI LabVIEW is used to process, display and save data. The wireless torque sensor was installed to the Unit Under Test at the output shaft of the five-speed manual transmission. The Unit Under Test was installed on a dynamometer for verification purposes and the transient torque was recorded under various operational conditions. The transient output torque of the manual transmission is measured and compared with results obtained from simulations performed under similar operating conditions. The two sets of transient responses show a good correlation with each other and hence demonstrate that the torque sensor meets the major design specifications. The data obtained will be used to enhance the fidelity of the software model.
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Hahanova, A., V. Hahanov, S. Chumachenko, E. Litvinova, and D. Rakhlis. "VECTOR-DRIVEN LOGIC AND STRUCTURE FOR TESTING AND DEDUCTIVE FAULT SIMULATION." Radio Electronics, Computer Science, Control, no. 3 (October 6, 2021): 69–85. http://dx.doi.org/10.15588/1607-3274-2021-3-7.
Повний текст джерелаАнотація:
Context. It is known that data structures are decisive for the creation of efficient parallel algorithms and high-performance computing devices. Therefore, the development of mathematically perfect and technologically simple data structures takes about 80 percent of the design time, when about 20 percent of time and material resources are spent on algorithms and their hardware-software coding. This lead to search for such primitives of data structures that will significantly simplify the parallel high-performance algorithms which are working on them. Models and methods for testing and simulation of digital systems are proposed, which containing certain advantages of quantum computing in terms of implementation of vector qubit data structures in technology of classical computational processes.
Objective. The goal of the work is development of an innovative technology for qubit-vector synthesis and deductive analysis of tests for their verification based on vector data structures that greatly simplify algorithms that can be embedded as BIST components in digital systems on chips.
Method. The deductive faults simulation is used to obtain analytical expressions focused on transporting fault lists through a functional or logical element based on the xor-operation, which serves as a measure of similarity-difference between a test, a function and faults which is specified in the same way in one of the formats − a table, graph, equation. A binary vector is proposed as the most technologically advanced primitive of data structures for setting logical functionality for the purpose of parallel synthesis and analysis of digital systems. The parallelism of solving combinatorial problems is a physical property of quantum computing, which in classical computing, for parallel simulation and faults diagnostics, is provided by unitary-coded data structures due to excess memory.
Results. 1) A method of analytical synthesis of deductive logic for functional elements on the gate level and register transfer level has been developed. 2) A deductive processor for faults simulation based on transporting input lists or faults vectors to external outputs of digital circuits was proposed. 3) The qubit-vector form of logic setting and methods of qubit synthesis of deductive equations for faults simulation were described. 4) A qubit-vector method for the tests’ synthesis which is using derivatives calculated by vector coverage of logic has been developed. 5) Models and methods verification is performed on test examples in the software implementation of structures and algorithms.
Conclusions. The scientific novelty lies in the new paradigm of the technology for the synthesis of deductive RTL logic based on metric test equation, which forms the. A vector form for structures description is introduced, which makes it possible to apply wellknown technologies for the synthesis and analysis of logical circuits tests to effectively solve the problems of graph structures testing and state machine models of digital devices. The practical significance is reflected in the examples of analytical synthesis of deductive logic for functional elements on gate level and register transfer level. A deductive processor for faults simulation which is focused on implementation as a BIST tool, which is used in online testing, simulation and fault diagnosis for digital systems on chips is proposed. A qubit-vector form of the digital systems description is proposed, which surpasses the existing methods of computing devices development in terms of the metric: manufacturability, compactness, speed and quality. A software application has been developed that implements the main testing, simulation and diagnostics services which are used in the educational process to study the advantages of qubit-vector data structures and algorithms. The computational complexity of synthesis processes and deductive formulas for logic and their usage in fault simulation are given.
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Chen, Lei, Lijun Wei, Yu Wang, Junshuo Wang, and Wenlong Li. "Monitoring and Predictive Maintenance of Centrifugal Pumps Based on Smart Sensors." Sensors 22, no. 6 (March 9, 2022): 2106. http://dx.doi.org/10.3390/s22062106.
Повний текст джерелаАнотація:
Centrifugal pumps have a wide range of applications in industrial and municipal water affairs. During the use of centrifugal pumps, failures such as bearing wear, blade damage, impeller imbalance, shaft misalignment, cavitation, water hammer, etc., often occur. It is of great importance to use smart sensors and digital Internet of Things (IoT) systems to monitor the real-time operating status of pumps and predict potential failures for achieving predictive maintenance of pumps and improving the intelligence level of machine health management. Firstly, the common fault forms of centrifugal pumps and the characteristics of vibration signals when a fault occurs are introduced. Secondly, the centrifugal pump monitoring IoT system is designed. The system is mainly composed of wireless sensors, wired sensors, data collectors, and cloud servers. Then, the microelectromechanical system (MEMS) chip is used to design a wireless vibration temperature integrated sensor, a wired vibration temperature integrated sensor, and a data collector to monitor the running state of the pump. The designed wireless sensor communicates with the server through Narrow Band Internet of Things (NB-IoT). The output of the wired sensor is connected to the data collector, and the designed collector can communicate with the server through 4G communication. Through cloud-side collaboration, real-time monitoring of the running status of centrifugal pumps and intelligent diagnosis of centrifugal pump faults are realized. Finally, on-site testing and application verification of the system was conducted. The test results show that the designed sensors and sensor application system can make good use of the centrifugal pump failure mechanism to automatically diagnose equipment failures. Moreover, the diagnostic accuracy rate is above 85% by using the method of wired sensor and collector. As a low-cost and easy-to-implement solution, wireless sensors can also monitor gradual failures well. The research on the sensors and pump monitoring system provides feasible methods and an effective means for the application of centrifugal pump health management and predictive maintenance.
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Qin, Feng, Ying Lin, and Diqiang Lu. "Hardware-in-the-loop simulation of high-speed maglev transportation five-segment propulsion system based on dSPACE." Transportation Systems and Technology 4, no. 2 (September 13, 2018): 62–72. http://dx.doi.org/10.17816/transsyst20184262-72.
Повний текст джерелаАнотація:
Aim: For exploring and testing the key technology of high-speed maglev transportation propulsion control system, this paper designs and establishes a hardware-in-the-loop (HIL) real-time simulation system of the high-speed maglev transportation five-segment propulsion system.
Materials and methods of the studies: According to the route conditions and propulsion segment division of Shanghai maglev demonstration and operation line, the real-time simulation platform based on dSPACE multiprocessor systems is implemented. The simulation system can achieve the functional simulation of all the high-power related equipment in the 5-segment area, including 8 sets of high-power converter units, 2 sets of medium-power converter units, 2 sets of low-power converter units, five-segment trackside switch stations and long-stator linear synchronous motors. The mathematical models of linear motors and converters are built in MATLAB/Simulink and System Generator, after compiling, they can be downloaded and executed in Field Programmable Logic Array (FPGA). All the interfaces connecting the simulation system to the propulsion control system physical equipment use real physical components as in the field, such as analog I/O, digital I/O, optical signals and Profibus.
Results: By using CPU+FPGA hardware configuration, the simulation steps are greatly shortened and the response speed and accuracy of real-time simulation system are improved. The simulation system can simulate multiple operating modes such as multi-segment, multi-vehicle, double-track, double-feeding, step-by-step stator section changeover, and so on. The simulation results show that the maximum speed of the simulation system can reach 500 km/h.
Conclusion: This HIL system can provide detailed real-time on-line test and verification of high speed maglev propulsion control system.
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Tenuta, Livia, and Susanna Testa. "Scientific method and creative process for wearable technologies from invention to innovation." Airea: Arts and Interdisciplinary Research, no. 1 (June 19, 2018): 35–46. http://dx.doi.org/10.2218/airea.2763.
Повний текст джерелаАнотація:
The aim of this paper is demonstrating how in the contemporary scene the boundaries between scientific method and creative process are increasingly blurred finding innovation as the point of intersection of this discursive separation. The analysis identifies the object of investigation in the emergent field of fashion wearables. In fact, the introduction of digital tools has had a significant impact on the fashion system, and wearable technologies represent the result of a new systemic interaction among diverse approaches belonging to different sectors. In this context, our purpose is to identify the moment when invention, seen as technological progress, becomes innovation, integrating and affecting people’s lives. To this end, the paper is firstly aimed in analyzing through case studies the different methods to design innovative fashion products. Both technology driven innovation and design driven innovation based methodologies are examined. The two strategies are compared and described in terms of phases, actors involved and validation of the obtained results, underlining the crucial stages of the process: the definition of the target and the scenario and the phase of product testing. This involves both traditional methods of data analysis for the technological functioning, based on numerically quantifiable parameters, and experimental verification based on the object-final user relationship. This test aims at “measuring” the effectiveness of the products in terms of comfort, usability, aesthetics and interaction. It is this methodological transdisciplinary practice that carries appreciable results concerning innovation. This approach leads to an emphasis of the designer’s cross role and it represents an opportunity for the academic research as well as for the market.
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Krishna Srinivasan, Mohan, Febin Daya John Lionel, Umashankar Subramaniam, Frede Blaabjerg, Rajvikram Madurai Elavarasan, G. M. Shafiullah, Irfan Khan, and Sanjeevikumar Padmanaban. "Real-Time Processor-in-Loop Investigation of a Modified Non-Linear State Observer Using Sliding Modes for Speed Sensorless Induction Motor Drive in Electric Vehicles." Energies 13, no. 16 (August 14, 2020): 4212. http://dx.doi.org/10.3390/en13164212.
Повний текст джерелаАнотація:
Tracking performance and stability play a major role in observer design for speed estimation purpose in motor drives used in vehicles. It is all the more prevalent at lower speed ranges. There was a need to have a tradeoff between these parameters ensuring the speed bandwidth remains as wide as possible. This work demonstrates an improved static and dynamic performance of a sliding mode state observer used for speed sensorless 3 phase induction motor drive employed in electric vehicles (EVs). The estimated torque is treated as a model disturbance and integrated into the state observer while the error is constrained in the sliding hyperplane. Two state observers with different disturbance handling mechanisms have been designed. Depending on, how they reject disturbances, based on their structure, their performance is studied and analyzed with respect to speed bandwidth, tracking and disturbance handling capability. The proposed observer with superior disturbance handling capabilities is able to provide a wider speed range, which is a main issue in EV. Here, a new dimension of model based design strategy is employed namely the Processor-in-Loop. The concept is validated in a real-time model based design test bench powered by RT-lab. The plant and the controller are built in a Simulink environment and made compatible with real-time blocksets and the system is executed in real-time targets OP4500/OP5600 (Opal-RT). Additionally, the Processor-in-Loop hardware verification is performed by using two adapters, which are used to loop-back analog and digital input and outputs. It is done to include a real-world signal routing between the plant and the controller thereby, ensuring a real-time interaction between the plant and the controller. Results validated portray better disturbance handling, steady state and a dynamic tracking profile, higher speed bandwidth and lesser torque pulsations compared to the conventional observer.
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Makhlouf Shabou, Basma. "Digital diplomatics and measurement of electronic public data qualities." Records Management Journal 25, no. 1 (March 16, 2015): 56–77. http://dx.doi.org/10.1108/rmj-01-2015-0006.
Повний текст джерелаАнотація:
Purpose – This paper aims to present a recent study on the definition and measurement of quality dimensions of public electronic records and archives (QADEPs: Qualités des archives et documents électroniques publics). It develops an original model and a complete method with tools to define and measure electronic public data qualities within public institutions. It highlights also the relationship between diplomatics principles and the measurement of trustworthiness of electronic data in particular. This paper presents a general overview of the main results of this study, with also illustrative examples to demonstrate the feasibility of measuring the qualities of electronic archives in the context of public institutions. Design/methodology/approach – This research was conducted in two phases. The first one was the conceptual phase in which the quality dimensions were identified and defined with specific sets of indicators and variables. The second phase was the empirical phase which involved the testing of the model on real electronic documents belonging to several public institutions to validate its relevance and applicability. These tests were performed at the Archives of the State of Wallis and the Archives of the State of Geneva, thanks to different measurement tools designed especially for this stage of the research. Findings – The QADEPs model analyzes the qualities of electronic records in public institutions through three dimensions: trustworthiness, exploitability and representativeness. These dimensions were divided into eight sub-dimensions comprising 17 indicators for a total of 46 variables. These dimensions and their variables tried to cover the main aspects of quality standards for electronic data and public documents. The study demonstrates that nearly 60 per cent of the measured variables could be automated. Research limitations/implications – The QADEPs model was defined and tested in a Swiss context on a limited sample of electronic public data to validate, essentially, its feasibility. It would be useful to extend this approach and test it on a broader sample in different contexts abroad. Practical implications – The decisionmaking of records retention in organizations and public institutions in particular is difficult to establish and justify because it is based generally on subjective and non-defendable practices. The QADEPs model offers specific metrics with their related measuring tools to evaluate and identify what is valuable and what is eliminable within the whole set of institutional electronic information. The model should reinforce the information governance of those institutions and help them control the risks related to information management. Originality/value – The current practice of archival appraisal does not yet invest in a meticulous examination of the nature of documents that should be preserved permanently. The lack of studies on the definition and measurement of the qualities of electronic and public electronic records prevents verification as to whether archival materials are significant. This paper fills in some of the gaps.
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Beal, Aubrey N., and Robert N. Dean. "A Random Stimulation Source for Evaluating MEMS Devices using an Exact Solvable Chaotic Oscillator." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 001594–625. http://dx.doi.org/10.4071/2015dpc-wp32.
Повний текст джерелаАнотація:
MEMS devices are nearly ubiquitous, with applications ranging from automobiles to toys, medical equipment to missiles, and cell phones to industrial equipment. At the microscale, fabrication tolerances are significantly less precise than at the scale of traditional machining techniques. This can result in significant differences in the operating characteristics between otherwise identical MEMS devices. A wide bandwidth random excitation source is ideal for evaluating these components, whether used as the forcing function for an electromechanical shaker employed to measure transmissibility, or as a voltage source to evaluate actuator structure resonances and instabilities. An electronic chaotic oscillator provides an ideal wide bandwidth voltage source which is provably random from first principles and may be simply integrated for the aforementioned MEMS testing. This type of system is easily integrated through standard Si MEMS processes and readily lends itself to application as a built-in-self test (BIST) component. These systems guarantee uniform frequency content from D.C. up to 100kHz due to their characteristically random behavior and serve as a strong candidate for providing uniform spectral density to a device under test. The proposed system is a simple, electronic circuit that creates a random, wideband excitation voltage for observing characteristics of MEMS devices. This functionality is achieved by the analog, digital or mixed signal computation of nonlinear differential equations that describe various exactly solvable chaotic systems. By creating Si microsystems which perform these computations, these test sources may be readily fabricated as integrated BIST components for MEMS devices or fabricated separately and integrated by flip chip assembly techniques. Furthermore, by considering the iterated map of this particular category of stimulation source, a direct and easy measurement of the stimulation entropy may be monitored and corrected. This work begins as a theoretical treatment involving the Nonlinear Dynamics of these types of systems including chaotic systems which permit closed form solutions. These systems are described classically through nonlinear differential equations and intuitively through iterated maps. These techniques reveal inherent methods for entropy measurement in these sources which may be implemented and controlled easily using electronic circuits. Subsequently, the simulation, circuit design methodology, circuit simulation, fabrication, testing and hardware verification of these wideband chaotic sources is presented. The development of this work delineates simple, wideband electronic testing circuits which may be fully integrated with MEMS devices using standard Si MEMS processes. The resulting microsystem may be used as the forcing function when measuring transmissibility of MEMS devices, or as a BIST element to evaluate MEMS microstructure characteristics through direct microelectronic fabrication or flip chip integration.
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Bozhko, I. V., G. G. Parkhomenko, A. V. Gromakov, V. A. Maksimenko, and S. I. Kambulov. "The experimental setup for the study of soil-working bodies." Traktory i sel hozmashiny 84, no. 6 (June 15, 2017): 37–42. http://dx.doi.org/10.17816/0321-4443-66332.
Повний текст джерелаАнотація:
The final verification of the performed calculations on the adequacy of the stated hypothesis on the phenomenon being studied is the experiment. Using the method of monographic examination of known bearing systems, the design of an experimental setup for conducting field experimental studies of the working organs of tillage machines was developed. When conducting experimental studies, methods of energy assessment, estimation of technical parameters in accordance with state standards, and methods of full-scale experiment using modern computer diagnostic tools and software are used. The experimental installation for studying the working organs of soil-cultivating machines of the proposed construction includes a frame, support wheels with the possibility of adjusting the depth of soil cultivation by means of a screw mechanism, the attachment mechanism, a hinged mechanism with the fastening of the test organ, the fixing mechanism of the measuring sensor and rigidly fixed to the frame of the apparatus working body to create conditions for the real technological process of functioning. When the system moves through the experimental section, the analog data of the traction resistance read from the measuring sensor is transmitted to the amplifier, from where it is fed through the channel to the analog-to-digital converter board, then the digitized data is fed to the personal computer. It is established that the relative error in the data of the experimental determination of the parameters and indices of the technological process of the working organs of soil-cultivating machines when using the proposed experimental installation with a measuring complex does not exceed 4 % of the results of theoretical studies. The experimental installation allows to carry out investigations in the field conditions with imitation of the real process of operation of the designed tiller machine.
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Ivanov, Hristo, Frank Marzano, Erich Leitgeb, and Pasha Bekhrad. "Testbed Emulator of Satellite-to-Ground FSO Downlink Affected by Atmospheric Seeing Including Scintillations and Clouds." Electronics 11, no. 7 (March 31, 2022): 1102. http://dx.doi.org/10.3390/electronics11071102.
Повний текст джерелаАнотація:
Free Space Optics (FSO) technology enabling next-generation near-Earth communication is prone to severe propagation losses due to atmospheric-turbulence-induced fading and Mie scattering (clouds). As an alternative to the real-time evaluation of the weather effects over optical signal, a state-of-the-art laboratory testbed for verification of slant APD-based (Avalanche Photodiode) FSO links in laboratory conditions is proposed. In particular, a hardware channel emulator representing an FSO channel by means of fiber-coupled Variable Optical Attenuator (VOA) controlled by driver board and software is utilized. While atmospheric scintillation data are generated based on Radiosonde Observation (RAOB) databases combined with a statistical design approach, cloud attenuation is introduced using Mie theory together with empirical Log-Normal modeling. The estimation of atmospheric-turbulence-induced losses within the emulated optical downlink is done with an FSO IM/DD prototype (Intensity Modulation/Direct Detection) relying on two different data throughputs using a transmitter with external and internal modulation. Moreover, the receiver under-test is a high-speed 10 Gbps APD photodetector with integrated Transimpedance Amplifier (TIA) typically installed in OGSs (Optical Ground Stations) for LEO/GEO satellite communication. The overall testbed performance is addressed by a BER tester and a digital oscilloscope, providing BER graphs and eye diagrams that prove the applied approach for testing APD-TIA in the presence of weather-based disruptions. Furthermore, the testbed benefits from the used beam camera that measures the quality of the generated FSO beam.
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Xiao, Da, Yue Fei Zhu, Sheng Li Liu, Dong Xia Wang, and You Qiang Luo. "Digital Hardware Design Formal Verification Based on HOL System." Applied Mechanics and Materials 716-717 (December 2014): 1382–86. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1382.
Повний текст джерелаАнотація:
This article selects HOL theorem proving systems for hardware Trojan detection and gives the symbol and meaning of theorem proving systems, and then introduces the symbol table, item and the meaning of HOL theorem proving systems. In order to solve the theorem proving the application of the system in hardware Trojan detection requirements, this article analyses basic hardware Trojan detection methods which applies for theorem proving systems and introduces the implementation methods and process of theorem proving about hardware Trojan detection.
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Wang, Xiao Feng. "XML Digital Signature Application in Network Test System." Applied Mechanics and Materials 513-517 (February 2014): 2016–19. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.2016.
Повний текст джерелаАнотація:
This paper describes the concept of XML digital signatures, analyzes the digital signature and the signature verification process, describes the W3C digital signature specification, and studies how to ensure data security in network exam in C #.NET environment. Experiments show that: XML digital signature in network test system ensures the integrity of network data transmission, the identity of verifiability and non-repudiation.
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Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (July 9, 2020): 1277–92. http://dx.doi.org/10.1007/s11265-020-01558-7.
Повний текст джерелаАнотація:
Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.
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Sanborn, J. W., J. E. Lenertz, and J. D. Johnson. "Advanced turbofan engine combustion system design and test verification." Journal of Propulsion and Power 5, no. 4 (July 1989): 502–9. http://dx.doi.org/10.2514/3.23182.
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KOBAYASHI, Toshio, Yukio NAITO, and Toshihisa ISHIBASHI. "SYSTEM DESIGN AND PERFORMANCE VERIFICATION TEST FOR VIBRATION ISOLATION SYSTEM (VIS)." Journal of Structural and Construction Engineering (Transactions of AIJ) 62, no. 498 (1997): 51–58. http://dx.doi.org/10.3130/aijs.62.51_2.
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Yao, Hong-Yu, Xiang-Jun Kong, Ya-Jie Shi, Xian-Bo Xiao, and Ning-Ning Le. "Aircraft test of engineered material arresting system." Aircraft Engineering and Aerospace Technology 90, no. 1 (January 2, 2018): 229–36. http://dx.doi.org/10.1108/aeat-05-2016-0082.
Повний текст джерелаАнотація:
Purpose Engineered material arresting systems (EMASs) are dedicated to stopping aircraft that overrun the runway before they enter dangerous terrain. The system consists of low-strength foamed concretes. The core component of the arresting system design is a reliable simulation model. Aircraft test verification is required before the practical application of the model. This study aims to propose a simulation model for the arresting system design and conducts serial verification tests. Design/methodology/approach Six verification tests were conducted using a Boeing 737 aircraft. The aircraft was equipped with an extra inertia navigation system and a strain gauge system to measure its motion and the forces exerted on the landing gears. The heights of the arrestor beds for these tests were either 240 or 310 mm, and the entering speeds of the aircraft ranged from 23.9 to 60.6 knots. Findings Test results revealed that both the aircraft and the pilots on board were safe after the tests. The maximum transient acceleration experienced by the dummies on board was 2.5 g, which is within the human tolerance. The model exhibited a satisfied accuracy to the field tests, as the calculation errors of the stopping distances were no greater than 7 per cent. Originality/value This study proposes a simulation model for the arresting system design and conducts serial verification tests. The model can be used in EMAS design.
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Xu, Mei Hua, Qin Yu, and Ai Ying Guo. "Design and Realization of Efficient Verification Platform Based on System Verilog." Advanced Materials Research 945-949 (June 2014): 1903–7. http://dx.doi.org/10.4028/www.scientific.net/amr.945-949.1903.
Повний текст джерелаАнотація:
Adopting the Verification Methodology Manual’s (VMM) hierarchical structure, this paper presents a design of available verification platform based on System Verilog adopted. The platform completed can implement constrained-random test, directed test, and error stimulus test with high efficiency; moreover, gain maximum code reuse. Using Direct Programming Interface (DPI), the verification platform can conveniently link C++ with the model that realized the function of Design Under Test (DUT), and then to test it. At last the paper shows the experiment results to prove the effectiveness and practicality of the platform by verification sample of HOG chip.
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Chen, Hao, Fu Sheng Chen, Jie Xiang, Li Man Shen, and E. Ying Li. "Research on the Digital Metering System and Verification Method of Digital Electrical Energy Meter." Advanced Materials Research 718-720 (July 2013): 715–20. http://dx.doi.org/10.4028/www.scientific.net/amr.718-720.715.
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The digital energy metering system applied in the smart substation are quite different from the traditional meter system, so its nessary to do some research on the digital metering system. With comparing the digital metering systems to traditional metering system, the application structure and characteristics of digital metering system is discussed, the traceability model of the digital electrical energy meter based on IEC 61850 protocol is also given.In the next part,we designed the verification system for digital energy meter, besides the standard digital power source in the test device, calibration device and the general controller are expounded. The performance of the verification system designed in this article shows that the method could be an effective solution to the verification and traceability of digital energy meter.
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Park, Dong-Myung, Yong-In Joung, Woo-Yong Moon, and Sung-Sun Park. "Design Verification of Environmental Control System by Flow Balance Test." Journal of the Korean Society for Aeronautical & Space Sciences 40, no. 7 (July 1, 2012): 608–15. http://dx.doi.org/10.5139/jksas.2012.40.7.608.
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Choi, Bumsuk, Suncheol Kim, Youngho Jeong, Jinwoo Hong, and Wondon Lee. "Metadata Design and Verification Test Bed System for Augmented Broadcasting." Journal of Broadcast Engineering 19, no. 5 (September 30, 2014): 736–45. http://dx.doi.org/10.5909/jbe.2014.19.5.736.
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Prokhorov, D. S., A. A. Grudin, and D. R. Yurgenson. "Automatic test design system for digital electronic equipment." Measurement Techniques 33, no. 8 (August 1990): 791–92. http://dx.doi.org/10.1007/bf00976157.
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