Дисертації з теми "Digital flesh"
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Ciacciulli, A. "FRUIT FLESH IN PEACH:CHARACTERIZATION OF THE 'SLOW SOFTENING' TEXTURE." Doctoral thesis, Università degli Studi di Milano, 2018. http://hdl.handle.net/2434/540666.
Повний текст джерелаMajidi, Rabeeh. "DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/275.
Повний текст джерелаPuig, Mailhol Vincent. "Le numérique et l'esprit. Prendre soin des technologies numériques de l'esprit à la lumière de Gilbert Simondon, Maurice Merleau-Ponty, Henri Bergson." Electronic Thesis or Diss., Poitiers, 2023. http://www.theses.fr/2023POIT5001.
Повний текст джерелаThis address to designers stems from an approach of anthropological decentering to think and take care of the digital as spiritual in the sense that Derrida designated the process of questioning but also the of technique in Heidegger. This route goes through a critique of the notion of information in Simondon to try to rethink "the soul of objects". It continues with an analysis of the question of the Flesh from Merleau-Ponty to propose the passage from a "digital suffering flesh" to an organology and a pharmacology of the digital gesture. Finally, it approaches what Bernard Stiegler called the technologies of the through the prism of Bergsonian intuition and Simondonian transduction to reintroduce analogical thought into the digital design of a dispositive benevolence, techno-estheú, cosmotechnic, ethical and political condiú)n for the development of the common good and of knowledge
Seto, Jim Carleton University Dissertation Engineering Electrical. "An 8 bit BiCMOS subranging flash analog to digital converter." Ottawa, 1991.
Знайти повний текст джерелаHassan, Raza Naqvi Syed. "1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8382.
Повний текст джерелаThe analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high performance ADCs.
Of all types of ADCs the flash ADC is not only famous for its data conversion rate but also it becomes the part of other types of ADC for example pipeline and multi bit Sigma Delta ADCs. The main problem with a flash ADC is its power consumption, which increases in number of bits. This thesis presents the comparison of power consumption of different blocks in 1Gbps flash ADCs for 2, 4 and 6 bits in a 90nm CMOS technology. We also investigate the impact on power consumption by changing the design of decoder block.
Sivakumar, Balasubramanian. "A 6-Bit Sub-Ranging High Speed Flash Analog To Digital Converter With Digital Speed And Power Control." The Ohio State University, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=osu1229631191.
Повний текст джерелаSäll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator Technology." Licentiate thesis, Linköping University, Linköping University, Electronics System, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.
Повний текст джерелаHigh speed analog-to-digital converters (ADCs) used in, e.g., read channel and ultra wideband (UWB) applications are often based on a flash topology. The read channel applications is the intended application of this work, where a part of the work covers the design of two different types of 6-bit flash ADCs. Another field of application is UWB receivers.
To optimize the performance of the whole system and derive the specifications for the sub-blocks of the system it is often desired to use a topdown design methodology. To facilitate the top-down design methodology the ADCs are modeled on behavioral level. The models are simulated in MATLAB®. The results are used to verify the functionality of the proposed circuit topologies and serve as a base to the circuit design phase.
The first flash ADC has a conventional topology. It has a resistor net connected to a number of latched comparators, but its thermometer-tobinary encoder is based on 2-to-1 multiplexers buffered with inverters. This gives a compact encoder with a regular structure and short critical path. The main disadvantage is the code dependent timing difference between the encoder outputs introduced by this topology. The ADC was simulated on schematic level in Cadence® using the foundry provided transistor models. The design obtained a maximum sampling frequency of 1 GHz, an effective resolution bandwidth of 390 MHz, and a power consumption of 170 mW.
The purpose of the second ADC is to demonstrate the concept of introducing dynamic element matching (DEM) into the reference net of a flash ADC. This design yields information about the performance improvements the DEM gives, and what the trade-offs are when introducing DEM. Behavioral level simulations indicate that the SFDR is improved by 11 dB when introducing DEM, but the settling time of the reference net with DEM will now limit the conversion speed of the converter. Further, the maximum input frequency is limited by the total resistance in the reference net, which gets increased in this topology. The total resistance is the total switch on-resistance plus the total resistance of the resistors. To increase the conversion speed and the maximum input frequency a new DEM topology is proposed in this work, which reduces the number of switches introduced into the reference net compared with earlier proposed DEM topologies. The transistor level simulations in Cadence® of the flash ADC with DEM indicates that the SFDR improves by 6 dB compared with when not using DEM, and is expected to improve more if more samples are used in the simulation. This was not possible in the current simulations due to the long simulation time. The improved SFDR is however traded for an increased chip area and a reduction of the maximum sampling frequency to 550 MHzfor this converter. The average power consumption is 92 mW.
A goal of this work is to evaluate a 130 nm partially depleted silicon-oninsulator (SOI) complementary metal oxide semiconductor (CMOS) technology with respect to analog circuit implementation. The converters are therefore implemented in this technology. When writing this the ADCs are still being manufactured. Since the technology evaluation will be based on the measurement results the final results of the evaluation are not included in this thesis. The conclusions regarding the SOI CMOS technology are therefore based on a literature study of published scientific papers in the SOI area, information extracted during the design phase of the ADCs, and from the transistor level circuit simulations. These inputs indicate that to fully utilize the potential performance advantages of the SOI CMOS technology the partially depleted SOI CMOS technology should be exchanged for a fully depleted SOI CMOS technology. The manufacturing difficulties regarding the control of the thin-film thickness must however first be solved before the exchange can be done.
Report code: LiU-Tek-Lic-2005:68.
Cicalo, James. "An embedded calibration technique for high-resolution flash time-to-digital converters." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/31637.
Повний текст джерелаApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Säll, Erik. "Implementation of flash analog-to-digital converters in silicon-on-insulator technology /." Linköping : Linköpings universitet, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5260.
Повний текст джерелаGuerrero, Maximiliano. "“3-1, shut your flash” : How shooter games convey agency." Thesis, Karlstads universitet, Institutionen för geografi, medier och kommunikation (from 2013), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kau:diva-80328.
Повний текст джерелаSheikhaei, Samad. "A 43mW single-channel 4GS/s 4-bit flash ADC IN 0.18um CMOS." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2746.
Повний текст джерелаSäll, Erik. "Implementation of Flash Analog-to-Digital Converters in Silicon-on-Insulator CMOS Technology." Doctoral thesis, Linköpings universitet, Elektroniksystem, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.
Повний текст джерелаSäll, Erik. "Implementation of flash analog-to-digital converters in silicon-on-insulator CMOS technology /." Linköping : Department of Electrical Engineering, Linköping University, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8712.
Повний текст джерелаCarter, Nathan R. "A 12-b 50Msample/s Pipeline Analog to Digital Converter." Digital WPI, 2000. https://digitalcommons.wpi.edu/etd-theses/749.
Повний текст джерелаFigueiredo, Michael. "Reference-free high-speed cmos pipeline analog-to-digital converters." Doctoral thesis, Faculdade de Ciências e Tecnologia, 2012. http://hdl.handle.net/10362/8776.
Повний текст джерелаMore and more signal processing is being transferred to the digital domain to profit from the technological enhancement of digital circuits. Where technology scaling enhances the capabilities of digital circuits, it degrades the performance of analog circuits. However, it is important to note that the impact that technology scaling has on digital circuits is becoming smaller and smaller, which means that, in nanotechnologies, to enhance energy and area efficiency, we can not simply depend on the benefits of this scaling. Although, a share of the efficiency can be obtained from the technology, new circuit architectures and techniques have to be developed to really push the limits of efficiency. In data converters, more specifically analog-to-digital converters (ADCs), a decision can be made: research energy and area efficient analog circuit techniques and architectures that cope with technological scaling issues, or design algorithms that use digital circuitry to assist the poor analog technological performance. The former option is the premise for the work developed in this thesis. The work reported in this thesis explores various design techniques with the purpose of enhancing the power and area efficiency of building blocks mainly to be used in multiplying digital-to-analog converter based ADCs. Therefore, novel analog techniques are developed for the three main blocks of an MDAC-based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. These techniques include self-biasing and inverter-based design for the flash quantizer and amplifier. Regarding the MDAC, it combines three techniques: unity feedback factor, insensitivity to capacitor mismatch, and current-mode reference shifting. In the second part of this work, the designed amplifier is implemented and experimentally characterized demonstrating its practical feasibility and performance. The final part of this work explores the design and implementation of a medium-low resolution high speed pipeline ADC incorporating all the developed circuits. Experimental results validate the feasibility of the techniques and demonstrate the attractiveness in terms of power dissipation and reduced area.
Brady, Philomena C. "Offset correction in flash ADCs using floating-gate circuits." Thesis, Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/14832.
Повний текст джерелаLindh, Lina, and Atena Ahmadi. "Digital presentation av Sunnerbogymnasiet : - En studie över hur VR kan användas för att locka nya elever." Thesis, University of Kalmar, School of Communication and Design, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hik:diva-2105.
Повний текст джерелаSyftet med detta arbete är att skapa en applikation som ska hjälpa och gynna Sunnerbogymnasiet när det gäller att locka till sig elever som går på högstadiet. För att göra detta har gruppen använt sig av bland annat VR (Virtual Reality) och Panorama som metoder till att göra applikationen attraktiv för målgruppen. För att få fram vad som kan locka elever till att använda applikationen utfördes enkätundersökningar på målgruppen som är elever i årskurs 8-9. Genom undersökningarna fick gruppen fram vad för information applikationen bör innehålla för att locka till sig elever. Med hjälp utav intervjuerna som utfördes på elever som går på Sunnerbogymnasiet, framkom det vilka platser som eleverna ansåg vara populärast på skolan. På dessa platser togs det bilder som sedan gjordes om till panorama filmer. Det finns en introduktionsdel där gruppen har visualiserat Sunnerbogymnasiets entré. Tanken bakom det är att elever ska känna igen sig när de besöker skolan. Resultatet blev en kompletterande applikation med en introduktionsfilm i 3D som föreställer skolans entré. För att visa upp populära platser på skolan finns det panorama filmer på dessa platser.
EL, RACHINI ALI. "Redundant analog to digital conversion architectures in CMOS technology." Doctoral thesis, Università degli Studi di Cagliari, 2015. http://hdl.handle.net/11584/266860.
Повний текст джерелаRitter, Philipp. "Design and optimization of high speed flash analog-to-digital converters in SiGe BiCMOS technologies." Thesis, Lyon, INSA, 2013. http://www.theses.fr/2013ISAL0052.
Повний текст джерелаHigh speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized
Savory, Fuller Rebecca. "Embodying 'new India' through remixed global performance : flash mobs redefined in contemporary urban India, 2003-15." Thesis, University of Exeter, 2018. http://hdl.handle.net/10871/33146.
Повний текст джерелаWang, Mingzhen. "High-speed Low-voltage CMOS Flash Analog-to-Digital Converter for Wideband Communication System-on-a-Chip." Wright State University / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=wright1189815482.
Повний текст джерелаRossoni, Mattos Diego. "Design and characterization of an 8gsps flash analog-to-digital converter for radio astronomy and cosmology applications." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14653/document.
Повний текст джерелаAn Analog-to-Digital Converter (ADC) has been developed for astrophysical and cosmological applications. This class of circuits demands, especially in the millimeter wavelength domain, ultra wide bandwidths, ultra high sampling frequencies and a low resolution. The “flash” architecture has been chosen for its speed and bandwidth. This ADC samples at 8Gsps and it has been fabricated in 65nm CMOS technology from STMicroelectornics.The design has been done in two steps. The first was the prototype of a track-and-hold circuit. The second was the ADC. Both circuits have been characterized and from these results some perspectives for further improvements have been proposed.In order to achieve the final goal of the multi-bit ADC (6-bit resolution) we have decided to design a first prototype with half the final resolution, namely a 3-bit resolution ADC. Our idea was, with this first prototype, to conduct a first analysis of the behavior of the integrated functional blocks and, consequently, find the correct improvements required for the ADC final version
Hennen, John Andrew. "Registration Algorithms for Flash Inverse Synthetic Aperture LiDAR." University of Dayton / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1576142937639181.
Повний текст джерелаAntonopoulou, Aikaterini. "From digital creations of space to analogous experiences of places : living in second life and acting in Flash Mob." Thesis, University of Newcastle upon Tyne, 2013. http://hdl.handle.net/10443/2316.
Повний текст джерелаKakizaki, Valter Eiji 1988. "Aspectos gerais e técnicos do violino/viola sob a perspectiva de Carl Flesch e Ivan Galamian : suas influências na era digital." [s.n.], 2014. http://repositorio.unicamp.br/jspui/handle/REPOSIP/285225.
Повний текст джерелаDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Artes
Made available in DSpace on 2018-08-26T08:41:14Z (GMT). No. of bitstreams: 1 Kakizaki_ValterEiji_M.pdf: 7721830 bytes, checksum: 6364af8be28879188712d29b477bdcc2 (MD5) Previous issue date: 2014
Resumo: Este trabalho tem por finalidade a compreensão e comparação dos pensamentos de dois dos mais importantes pedagogos do ensino de violino no século XX, Carl Flesch e Ivan Galamian, e averiguar suas influências nos dias de hoje em vídeos disponibilizados na internet. Inicialmente levantamos nos livros The Art of Violin Playing (Carl Flesch, 1923) e Principles of Violin Playing and Teaching (Ivan Galamian, 1962) as principais ideias desses autores sobre aspectos gerais, técnicos e interpretativos, fazendo uma comparação entre suas propostas pedagógicas. Em seguida analisamos os materiais pedagógicos postados na internet por professores de reconhecida competência, Todd Ehle e Kurt Sassmannshaus, observando os mesmos aspectos e parâmetros observados nos livros, verificando como as informações transmitidas por esses últimos se relacionam com as técnicas sugeridas por Carl Flesch e Ivan Galamian
Abstract: The purpose of this study is to understand and compare the thoughts of two of the most important violin pedagogues of the 20th Century, Carl Flesch and Ivan Galamian, and investigate their influences nowadays in videos available on the internet. Therefore, we summarized the main ideas presented by the two authors regarding general, technical and interpretative aspects in the books "The Art of Violin playing " (Carl Flesch, 1923) and "The Art of Violin Playing and Teaching" (Ivan Galamian, 1962), making a comparison between their pedagogical proposals. Then, we examined the pedagogical materials posted on the internet by professors of recognized competence, Todd Ehle e Kurt Sassmannshaus, observing the same aspects and parameters discussed in the two books, verifying how this more recent material relates to the techniques suggested by Carl Flesch and Ivan Galamian
Mestrado
Praticas Interpretativas
Mestre em Música
Hiremath, Vinayashree. "DESIGN OF ULTRA HIGH SPEED FLASH ADC, LOW POWER FOLDING AND INTERPOLATING ADC IN CMOS 90nm TECHNOLOGY." Wright State University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=wright1291391500.
Повний текст джерелаStefanou, Nikolaos. "A 1Gsample/s 6-bit flash A/D converter with a combined chopping and averaging technique for reduced distortion in 0.18(mu)m CMOS." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2469.
Повний текст джерелаGrillo, Kelly J. "An investigation of the effects of using digital flash cards to increase biology vocabulary knowledge in high school students with learning disabilities." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4907.
Повний текст джерелаID: 030423499; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 212-221).
Ph.D.
Doctorate
Education
Vaiho, :. Sara. "Konsten att döda en digital teknologi och tillvaron därefter : En kvalitativ studie om aktiviteter vid avvecklingen av ettinformationssystem." Thesis, Mittuniversitetet, Institutionen för data- och systemvetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41258.
Повний текст джерелаAtt sluta använda digitala teknologier sker genom en processsom forskningen benämner sominformationssystemsavveckling (IS-avveckling). Tidigareforskning har tagit fram faser och aktiviteter som kangenomföras i IS-avvecklingsprocessen, men denna kunskapär begränsad och har inte sammanställts. Denna studie syftarsåledes att skapa en modell av IS-avvecklingsprocessen och iden identifiera ytterligare aktiviteter. För att realisera dettahar en verklig IS-avvecklingsprocess studerats som haft ettannat förhållande och intressenter än i tidigare studier.Avvecklingen har skett hos en stor organisation somtillverkar fordon och studien har genomförts tillsammansmed dem. Avvecklingen harutförts på organisationens eLearning författarverktyg.Information om avvecklingen har samlats in genomsemistrukturerade personliga intervjuer med fem styckenrespondenter som är anställda hos organisationen. Deninsamlade datan har analyserats och tolkats i jämförelse meden framtagen teoretisk modell för IS-avvecklingsprocessensom innehåller faser och aktiviteter. Resultatet av analysenoch tolkningen blev en iterativ modellen för ISavvecklingsprocessen med faser och aktiviteter, varav 35stycken nya aktiviteter hittats. Stor del av dessa nyaaktiviteter kan kopplas till det nya förhållandet ochintressenterna i avvecklingen.
Josyula, Sai Prashanth. "On the Applicability of a Cache Side-Channel Attack on ECDSA Signatures : The Flush+Reload attack on the point multiplication in ECDSA signature generation process." Thesis, Blekinge Tekniska Högskola, Institutionen för datalogi och datorsystemteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-10820.
Повний текст джерелаKučerka, Daniel. "Návrh animace digitálního spojovacího pole." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217315.
Повний текст джерелаQueiroz, Alan Rômulo Silva. "Utilização de relés digitais para mitigação dos riscos envolvendo arco elétrico." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-30052012-124531/.
Повний текст джерелаThis dissertation aims to evaluate and propose the use of technological solutions that enable the reduction of risks caused by arc flash on the premises of an industrial unit with insulated system of electricity generation. It may be extremely damaging to the safety of people who interact with electrical installations and could cause significant damage to the equipment and facilities, the incident energy from an arc flash should be measured in accordance with existing standards, their risks must be controlled and attenuated, in order not to compromise the physical integrity of people and facilities. That way, this paper proposes changes into the system of protection and the insertion of devices dedicated to the identification of arc flashes inside panels of the unit concerned, contributing significantly to the reduction of incident energy released in the event of an arc flash. This reduction is obtained by lowering the time for the elimination of absence, requiring, therefore, devices and protective relays devoted exclusively to protect against electric arc.
Preston, Douglas. "Last Two Surface Range Detector for Direct Detection Multisurface Flash Lidar in 90nm CMOS Technology." Wright State University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=wright150392243439439.
Повний текст джерелаBojan, Vujičić. "Detekcija nule A/D konvertorom niske rezolucije." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2017. https://www.cris.uns.ac.rs/record.jsf?recordId=104132&source=NDLTD&language=en.
Повний текст джерелаThe main goal of this thesis was null-detection using a two-bit stochasticdigital measurement method (SDMM). Two methods of null-detection, usingtwo-bit SDMM, were formulated. Using the first method around 100 dB ofdynamic reserve was achieved and using the second one no less than160 dB. Both methods were theoretically, using simulation and experimentallyconfirmed. In addition to the solution of the main problem, several otherrelated problems were also solved. The hypothesis of this thesis – “two-bitSDMM in range from 0 % - 10 % FS is better than the standard samplingmethod (SSM)” has been fully confirmed in all considered cases.
Marjan, Urekar. "Prilog optimizaciji performansi digitalnih merenja." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2018. https://www.cris.uns.ac.rs/record.jsf?recordId=107133&source=NDLTD&language=en.
Повний текст джерелаThe thesis considers the criterion of optimality of the stochastic flash A/D converter (SFADC), which is the basis of the stochastic digital measurement method (SDMM). The mathematical and simulation model of the multibit SFADC was developed and the optimal number of bits of resolution was determined. A hardware prototype of a 4-bit stochastic measuring instrument (SMI) was made, tested in numerous experiments and compared with theoretically determined measurement performance values. The hypothesis of this thesis - that there is an optimal number of SMI resolution bits in which the maximum benefit of the measurement precision is achieved at the price of duplication of the required hardware - is fully confirmed
Sibanda, Phathisile. "Connection management applications for high-speed audio networking." Thesis, Rhodes University, 2008. http://hdl.handle.net/10962/d1006532.
Повний текст джерелаKobal, Damjan. "The use of technology to motivate, to present and to deepen the comprehension of math." Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-80412.
Повний текст джерелаHedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
Повний текст джерелаQC 20170905
Hancock, Amber N. "A Radical Approach to Syntheses and Mechanisms." Diss., Virginia Tech, 2011. http://hdl.handle.net/10919/77139.
Повний текст джерелаPh. D.
Huang, Chun-Cheng, and 黃鈞正. "Digitally-Calibrated Comparator and Its Application in Flash Analog-to-Digital Converters." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/60362296932435912652.
Повний текст джерела國立交通大學
電子研究所
98
This thesis presents a digital background calibration technique to trim the input-referred offsets of a comparator circuit. The calibration does not interrupt the normal operation of the comparator, hence is suitable for high speed and power efficient applications such as flash analog-to-digital converters(ADC). For a random-chopping comparator, the polarity of its offset is detected by observing the code density of its comparison results. A calibration loop is then used to adjust the comparator offset so that the offset is minimized. All procedures in the calibration loop are performed in digital domain. This arrangement ensures excellent reliability and high yields. The calibration performance is characterized by the converging speed of the calibration loop and the fluctuation noise imposed to the input signal. These two performance indexes of a background-calibrated comparator (BCC) are determined by three parameters: the probabilistic distribution of input signal, the quantized step size of offset adjustment, and the threshold of an internal bilateral peak detector. In flash ADCs, the offset fluctuation of a BCC can be drastically reduced by input windowing mechanism, which is accomplished by incorporating the thermometer-code edge detector(TCED) into the calibration loop. When introducing the TCED, uncorrelated random chopping for neighboring BCCs is used to avoid upward locking phenomenon which may lock calibration. A 2Gsample/s 6-bit ADC with the developed calibration technique is fabricated using 65 nm CMOS technology. A circuit architecture with no DC bias and small transistor sizes is selected for comparators used in the ADC. The comparator includes modifications for variable offset mechanism and high common-mode rejection capability. The parameters for the calibration loop are 1/4 LSB for the quantized offset adjustment step, and 16 for the bilateral peak detector threshold. The active area of the fabricated ADC is 0.21×0.66mm2. Drawing from 1.5V supply voltage, the ADC consumes 54mW. Before activating the calibration, the DNL is -1.0/+4.9 LSB and the INL is -4.3/+5.4 LSB. After activating the offset calibration, the DNL becomes -0.5/+0.6 LSB and the INL is reduced to -0.4/+0.7 LSB. The calibration improves the SNDR from 20.4dB to 31.0dB with an input frequency of 32MHz. When operating at 2GS/s, the effective resolution of bandwidth extends over the Nyquist frequency. The figure-of-merit of the ADC is 0.93pJ/conversion-step.
Maleki, Mohammad. "Current-mode flash analog-to-digital converter." Thesis, 1992. http://hdl.handle.net/1957/37347.
Повний текст джерелаGraduation date: 1993
Lin, Kaih-Ping, and 林凱評. "High Speed Flash Analog to Digital Converter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/12280330170131356783.
Повний текст джерела國立臺北科技大學
機電整合研究所
91
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, color, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. In this thesis, a flash ADC architecture is proposed to have 400 MHz samples rate with 6-bit resolution. We design the high speed architecture analog-to-digital converter by using two groups interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.80*1.10 mm2 with both powers of 3.3V and 2.5V. Experimentally, the chip can work up to 400 MHz as the input sample of 100 MHz sin-wave and has the differential nonlinearity is DNL<0.4 LSB, the integral nonlinearity is INL<1.0 LSB ,and the efficient number of 5.03 bits in practical applications. Moreover, we use two groups interleaved auto-zeroing technology for reducing the comparators capacitor value, so we can minimize the chip size and power consumption(152mA).
Sie, Ming-Jhou, and 謝明周. "4-Bit flash analog-to-digital converter." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60460902388790029068.
Повний текст джерела建國科技大學
電子工程系暨研究所
99
We use TSMC0.35μm2P 4M technology to design a positive feedback 3-bit 20MHz flash analog-to-digital converter and a 4-bit 1GHz flash analog-to-digital converter with hysteresis comparator. Reference potential was generated by resistor array, then compared with the input potential, and the resulting thermometer code pass through the pre-encoding circuit (1-out-of-N) and post-encoding circuit (Binary Code) after output. The 4-bit flash analog-to-digital-converter features working voltage range from 0.9 to 2.2 V, sampling rate of 1GHz, the power consumption is 5.158 mW and the chip layout area is 1.445×1.393mm . For 3-bit flash analog-to-digital converter, the working voltage ranges from 0 to 3.3 V, sampling rate of 20MHz, the power consumption is 2.2228mW and the chip layout area is 1.181 × 1.326 mm .
Lin, Kai-Chie, and 林凱琪. "High Speed Flash Analog to Digital Converter." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56085018306124426889.
Повний текст джерела國立臺北科技大學
電腦通訊與控制研究所
90
Applications of analog-to-digital converters (ADC) have become widespread as photoelectric devices, magnetic storages, and various sensors, such as light, colour, temperature, and signal detectors. Furthermore, specifications of analog-to-digital converters are more stringent as a result of the growing needs for wireless network and communications, as well as photoelectric convergence and conversion knowledge. The designs of analog to digital converter are innovative and versatile to have higher speed, more accuracy and stability, along with low operating potential and low power consumption. Various types of circuits such as flash、folding、feedback、parallel and pipe-line, are constructed according to match their specific characteristics. In this thesis, a flash ADC architecture is proposed to have 400 Mega-sample per second with 6-bit sample length. We design the architecture by using group interleaved auto-zeroing technology for shortening the time period in charging to zero for each comparator. The auto-zeroing process of a comparator would keep normally affect its comparing operation. Also, we revise the circuit of the series resistors used for generating voltage references by adding a post amplifier to avoid effectively the distortion in voltage floating. Moreover, we instigate the democracy circuit to over on traditional bubble errors. Thus, we have not only lower the number of MOS units, but also increase the ration of bubble errors correction. We implemental the ADC in TSMC 0.25 µm 1P5M technology. The chip occupied 0.60*0.66 mm2 with both powers of 3V and 2.5V, 8461 MOS units, 449 resistors, and 147 capacitors. Experimentally, the chip can work up to 400 MHz as the input sample of 10 MHz sin-wave and has the efficient number of 5.76 bits in practical applications.
Chang, Hsuan-Yu, and 張軒瑜. "Design of Low-Power Flash Analog-to-Digital Converters Using Digital Calibration." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/47809309624999322555.
Повний текст джерела國立中興大學
電機工程學系所
104
Flash-type ADCs have the inherent advantage on high-speed sampling rates. Although the flash ADC is superiority in sampling rate but its large power consumption makes itself bottleneck in many applications. Speed, power and accuracy are tradeoff in high-speed CMOS ADC design. Process technology scaling trends toward smaller transistor dimensions and low supply voltage, and thereby it leads to greatly reduce power consumption in flash ADCs. The never-ending story of CMOS technology trending toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Transistor size scaling results in significant offset voltage and supply voltage scaling makes it more difficult in higher accuracy design. In order to improving above design issues, many techniques have been proposed, such as resistor-averaging networks and digital calibrated techniques. Especially, the digital calibrated techniques are main solutions recently. In this thesis, the new idea of digital calibrated technique is proposed to realize high-speed ADCs. First chip, using tree-type metal layout and digital calibration, a 6-bit 2-GS/s flash ADC without track-and-hold is presented. Since large offset voltages caused by using small device sizes in front-end of high-speed ADCs usually result in nonlinearity in output, a digitally calibrated method is applied to improve the performance of the proposed ADC. In addition, no track-and-hold circuit used will cause dynamic error but tree-type metal layout will avoid it. Measurement results show the ADC achieves a SNDR of 35.6 dB for a low frequency input at 2 GS/s sampling frequency, and 32.7 dB for an ERBW input frequency. The power consumption is 28 mW at 2 GS/s from a 1.2-V supply. The core area is 0.56mm × 0.62mm and the figure of merit is 0.54pJ/conv. Second chip, a 6-bit flash ADC using reference-voltage- interpolated calibration to improve linearity and reduce power dissipation is presented. In the ADC, the digital calibration logic employs successive approximation algorithm and minimized residue algorithm to determine precise calibration levels. Implemented by 90-nm CMOS process, the proposed ADC can achieve a signal-to-noise-and-distortion ratio of 36 dB for a low input frequency and 33.5 dB for a Nyquist-rate input frequency at 2-GS/s sampling rate. The peaks of integral and differential nonlinearities after calibration are 0.36 LSB and 0.42 LSB, respectively. The power consumption is 25 mW at 2-GS/s from a 1.2-V supply. The core area is 0.32 mm × 0.62 mm, and the figure of merit is 0.34 pJ/conversion step. Finally, we compare the two chips design considerations and improvements. The first chip is suitable only in single ADC system application due to no track-and-hold circuit. The second chip is suitable in multi-sub ADCs system application, such as time-interleaved ultra-high speed ADCs. The second chip consumes less power comparing to the first chip due to wider calibration range. Transistor size of the comparator in flash ADC can be designed smaller due to wide calibration range, and it consumes less dynamic power. Performance summary and comparison table will be shown finally.
Hsu, Ying-Yu, and 徐瑛佑. "Ultra High-Speed Flash Analog-to-Digital Converter." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/9wam6k.
Повний текст джерела國立交通大學
電機與控制工程系所
93
Due to the advance process technologies, the operating frequency and circuit complexity of integrated circuit increase. The interfaces between the analog and the digital parts are required to operate at ultra high speed (over giga samples per second). The high-bit-rate applications include DVD read channel, multi level receiver, channel equalizer, jitter measurement system, and Ethernet need Analog-to-Digital Converters. There are two major topics in this thesis. First, we focus on the high speed ADC circuit design. Thus, we propose a 4-bit flash ADC typically operates at 3.125GSps and maximally at 4GSps. This 4-bit ADC achieves better than 3.1 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 2.3 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.45 LSB and 0.6 LSB, respectively. This ADC consumes 180mW from 1.8V power supply at 4GSps. The chip occupies 0.36- active area, implemented in TSMC 0.18-um 1P6M CMOS. Second, based on the circuits presented in the 4-bit flash ADC, and we propose two methods to improve the 4-bit accuracy to 5-bit accuracy. The methods are active averaging and active interpolation techniques. Using averaging technique can improve accuracy white using interpolation technique can reduce power consumption. The 5-bit flash ADC with averaging technique achieves better than 3.8 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 3 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.35 LSB and 0.8 LSB, respectively. This ADC consumes 270mW from 1.8V power supply at 4GSps. The 5-bit flash ADC with interpolation technique achieves better than 3.6 effective bits for input frequencies up to 1.55GHz at 3.125GSps, and 2.9 effective bits for 2GHz input at 4GSps. The peak DNL and INL are less than 0.5 LSB and 0.9 LSB, respectively. This ADC consumes 243mW from 1.8V power supply at 4GSps.
白薇詩. "Pipelined Encoding for a Flash Analog-to-Digital Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/40064734984142616238.
Повний текст джерела國立彰化師範大學
電機工程學系
96
In this research, fundamentals of power line signal sampling, quantization, and design of a pipelined encoder for flash analog to digital converter (Flash ADC) are presented. The current mode logic (CML) is applied because of lower voltage supply and faster processing time are considered. The second stage of this research is the analytical individual case of the electric power quality signal .The power quality has become an increasingly important topic due to rapid development of high-technology and precision instrument industries. Therefore, the quality of stable power supply is one of the main issues. The front-end device of power quality monitoring is an analog-to-digital converter, since the later processing of the power line signal is a key factor to the monitor or controller module.
Lien, Yu-Chang, and 連昱彰. "Low-Power High-Speed Flash Analog-to-Digital Converters." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/01613899949492304196.
Повний текст джерела國立成功大學
電機工程學系碩博士班
96
The performance and power consumption of analog-to-digital converters (ADCs) affect the efficiency of the ultra wideband (UWB) systems. In this thesis, we focus on the design techniques development of high speed ADCs, and propose a 6-bit high speed ADC design for the applications of UWB systems. In this design, a design methodology for pre-amplifier is used to achieve the maximum bandwidth while consuming the fixed power. Also, the non-ideality of comparators can be suppressed by improving the comparator’s timing. This proposed design adopts the offset cancellation, capacitive interpolation and distributed sample-and-hold techniques to solve the problems in designing flash ADCs. This proposed ADC is designed in TSMC 0.13�慆 process, and the experimental results show that the effective number of bit (ENOB) is 5.3 in the sampling frequency of 700MHz. The power consumption is 112mW, and the resolution bandwidth (ERBW) is 500MHz. Due to the high input bandwidth and low power consumption, this ADC is very suitable to UWB systems.
WANG, GUO-LONG, and 王國隆. "A new current-mode flash analog-to-digital converter." Thesis, 1991. http://ndltd.ncl.edu.tw/handle/27257510409184859270.
Повний текст джерелаSajjadian, Farnad. "A 10MHz flash analog-to-digital converter system for digital oscilloscope and signal processing applications." 1985. http://hdl.handle.net/2097/27577.
Повний текст джерела