Дисертації з теми "Delta sigma data converter"
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Gelhaar, B., K. Alvermann, and F. Dzaak. "A MULTICHANNEL DATA ACQUISITION SYSTEM BASED ON PARALLEL PROCESSOR ARCHITECTURES." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608884.
Повний текст джерелаFor research purposes on helicopter rotor acoustics a large data acquisition system called TEDAS (Transputer based Expandable Data Acquisition System) has been developed. The key features of this system are: unlimited expandability and sum data rate, local storage of data during operation, very simple analog anti aliasing filtering due to extensive digital filtering, and integrated computational power which scales with the number of channels. The sample rate is up to 50 kHz/channel, the resolution is 16 bit, 360 channels are realized now. TEDAS consists of blocks with 8 A/D converters which are controlled by one transputer T800. The size of the local memory is 4 Mbyte. Any number of blocks (IDAM = Intelligent Data Acquisition Module) can be combined to a complete system. Data preprocessing is done in parallel inside the IDAMs. As for 16 bit systems the analog antialiasing filtering becomes a dominant factor of the costs, delta sigma ADCs with oversampling and internal digital filtering are used. This produces an exact linear phase and a stop band rejection of -90 dB.
Vijjapu, Sudheer Paarmann Larry D. "RC implementation of an audio frequency band Butterworth MASH delta-sigma analog to digital data converter." Diss., The archival copy of this thesis can be found at SOAR (password protected), 2006. http://soar.wichita.edu/dspace/handle/10057/568.
Повний текст джерела"August 2006." Title from PDF title page (viewed on May 2, 2007). Thesis adviser: Larry D. Paarmann. Includes bibliographic references (leaves 41-43).
Baig, Shams Javid Paarmann Larry D. "RC implementation of an audio frequency band fourth-order Chebyshev type II Delta-Sigma analog to digital data converter." Diss., A link to full text of this thesis in SOAR, 2006. http://soar.wichita.edu/dspace/handle/10057/614.
Повний текст джерелаUMI Number: 1443931 "December 2006." Title from PDF title page (viewed on Sept. 18, 2007). Thesis adviser: Larry D. Paarmann. Includes bibliographic references (leaves 37-38).
Iuzzolino, Ricardo Javier [Verfasser], and Meinhard [Akademischer Betreuer] Schilling. "Josephson Waveforms Characterization of a Sigma-Delta Analog-to-Digital Converter for Data Acquisition in Metrology / Ricardo Javier Iuzzolino ; Betreuer: Meinhard Schilling." Braunschweig : Technische Universität Braunschweig, 2011. http://d-nb.info/1175824739/34.
Повний текст джерелаYu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
Повний текст джерелаKook, Se Hun. "Low-cost testing of high-precision analog-to-digital converters." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/41170.
Повний текст джерелаLiu, Xiyang. "Measurement of Delta-Sigma Converter." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-9701.
Повний текст джерелаLok, Chi Fung. "Multimode switched-capacitor delta-sigma analog-to-digital converter /." View abstract or full-text, 2007. http://library.ust.hk/cgi/db/thesis.pl?ECED%202007%20LOK.
Повний текст джерелаErtan, Sevgi 1976. "Comparison of two bandpass delta-sigma A/D converter architectures." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86435.
Повний текст джерелаPan, Yaobin, and Xizhuo Li. "Design and Implementation of Sigma-Delta Converter : in Oversampling frequency." Thesis, Linnéuniversitetet, Institutionen för fysik och elektroteknik (IFE), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:lnu:diva-53052.
Повний текст джерелаSigma-Delta Converter
McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter." Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.
Повний текст джерелаChen, Wei. "Asynchronous sigma delta modulators for data conversion." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/23651.
Повний текст джерелаZhao, Yixiang, and Hao Niu. "Measurement of dynamic parameters of Delta-Sigma ADC." Thesis, Högskolan i Gävle, Avdelningen för elektronik, matematik och naturvetenskap, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:hig:diva-12678.
Повний текст джерелаPěček, Lukáš. "Návrh Sigma Delta AD převodníku pro senzorové aplikace." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2017. http://www.nusl.cz/ntk/nusl-317221.
Повний текст джерелаAsibal, Romeo Lim. "Limitations of high speed sigma-delta A/D converter in GaAs technology." Diss., Georgia Institute of Technology, 1991. http://hdl.handle.net/1853/15445.
Повний текст джерелаGuyton, Matthew C. (Matthew Christopher). "A low-voltage zero-crossing-based delta-sigma analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/60147.
Повний текст джерелаCataloged from PDF version of thesis.
Includes bibliographical references (p. 179-183).
A zero-crossing-based (ZCB) switched-capacitor technique is presented for operation under low power supply voltages without gate boosting. Voltage ramp generators maintain common-mode level at each integrator output. Correlated level-shifting is used to increase the effective output impedance of gated current sources. The technique was used to design a single-bit 4th-order delta-sigma analog-to-digital converter for audio applications. The prototype ADC was implemented in 0.13 [mu]m CMOS and achieves 11.9 ENOB for 60 kHz input bandwidth while dissipating 1.2 mW power.
by Matthew C. Guyton.
Ph.D.
Huang, Li. "Calibration of a two-step Incremental Sigma-Delta Analog-to-Digital Converter." Thesis, université Paris-Saclay, 2020. http://www.theses.fr/2020UPAST041.
Повний текст джерелаIn the context of High Definition imagers, a trend is to integrate a bank of analogto-digital converters adjacent to the pixel matrix. The disadvantage is a constraint on the form factor of the converter. An incremental inverter-based Sigma-Delta converter was designed during previous work while respecting these constraints. But the post-layout of the circuit resulted in a performance degradation namely a resolution of 9 bits instead of the expected 14 bits. A calibration method was therefore necessary. This thesis proposes several correction methods implemented by digital filters applied on the output bits and on combinations of the output bits to take account of non-linear phenomena observed in post-layout simulation. The methods have been validated from the post-layout simulation results and achieve 14-bit resolution. To go further, the thesis also proposes a model of the circuit defects at the level of the integrators which are the most critical part of the circuit. This model, which implements parasitic capacitances, joins the post-layout simulation results with a very high precision, which makes it possible to consider ways of improvement for a future design
Early, Adrian Bruce. "A high-accuracy, DC-calibrated, monolithic, delta-sigma analog-to-digital converter." Diss., The University of Arizona, 1990. http://hdl.handle.net/10150/185072.
Повний текст джерелаZrilić, D., D. Skendzić, S. Pajavić, R. Ghorishi, F. Fu, and G. Kandus. "A Charge-Balancing Incremental Analog to Digital Converter for Instrumental Applications." International Foundation for Telemetering, 1988. http://hdl.handle.net/10150/615013.
Повний текст джерелаA switched-capacitor technique for realization of one bit serial A/D converter is presented. A conversion accuracy that is higher than 15 bits can be expected from its integrated realization. Results of simulation are presented. It is shown that arithmetic operations on bit serial signals are possible. Using arithmetic operations on delta-modulated signals, it is possible to build inexpensive options necessary in instrumentation.
Saleem, Jawad, and Abdul Mateen Malik. "REALIZATION OF CASCADE OF RESONATORS WITH DISTRBUTED FEED-BACK SIGMA-DELTA." Thesis, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20289.
Повний текст джерелаThe Sigma Delta Modulator (SDM) based analog to digital conversion is cost effective and have the advantages as higher reliability, increased functionality, and reduction in chip cost.
The thesis work includes the modeling of SDM with the signal flow graph in Matlab, optimization of the coefficients to improve the noise transfer function and signal transfer function. A procedure to find the maximum stable input range for the design. Scaling the inputs of the integrator so that the maximum output signal can be obtained according to the operational transconductance amplifier (OTA) output range. Further we derived error bound for the design. Then step by step realization of the SDM form the signal flow graph (SFG) to a fully differential switched-capacitor (SC) network is shown. The work also includes complete differential transistor level realization for 3-bit flash analog to digital converter (ADC), thermometric to binary encoder, a switch-capacitor digital to analog converter (DAC) circuit and an on-chip circuit realization of the non-overlapping clock generation circuitry.
Ng, Sheung Yan. "A continuous-time asynchronous Sigma Delta analog to digital converter for broadband wireless receiver with adaptive digital calibration technique." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1253559906.
Повний текст джерелаSaleem, Jawad, and Abdul Mateen Malik. "Realization of Cascade of Resonators with Distributed Feed-Back Sigma-Delta." Thesis, Linköpings universitet, Institutionen för systemteknik, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-20289.
Повний текст джерелаForejtek, Jiří. "Návrh a realizace sigma-delta převodníku AD v technice SC." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2008. http://www.nusl.cz/ntk/nusl-217731.
Повний текст джерелаSoukup, Luděk. "Návrh digitálně-analogového převodníku typu sigma-delta v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2012. http://www.nusl.cz/ntk/nusl-219761.
Повний текст джерелаJerng, Albert. "Delta-Sigma digital-RF modulation for high data rate transmitters." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/38675.
Повний текст джерелаIncludes bibliographical references (p. 157-162).
A low power, wideband wireless transmitter utilizing [Delta]-[Sigma] direct digital modulation of an RF carrier is presented. The transmitter architecture replaces high dynamic range analog circuits with high speed digital circuits and a passive LC bandpass filter, saving power and area compared to conventional IQ modulators for wideband systems. A prototype transmitter IC built in 0.13 pm CMOS demonstrates a data rate of 1.2 Gb/s using OFDM modulation in a bandwidth of 200 MHz centered at 5.25 GHz. The modulator consumes 187 mW and occupies a die area of 0.72 mm2. A quadrature digital-IF approach eliminates modulator LO feedthrough and image spurs from the output spectrum without requiring analog circuitry or system calibration, simplifying the design of the transmitter. The largest modulator spur is measured to be -47 dBc. Measured SNDR over a 200 MHz bandwidth is 43 dB. Successful implementation of the [Delta]-[Sigma] RF modulator requires the design of a high-Q, tunable RF bandpass filter, and a low power, high speed digital [Delta]-[Sigma] modulator. A 4th order passive LC bandpass filter with center frequency of 5.25 GHz is designed and implemented using differential coupled resonators.
(cont.) Variation of the filter response over process and temperature is removed through the design of an automatic self-tuning loop that calibrates the filter center frequency to the system LO. A 2.625 GS/s, 2nd order, 3-bit digital [Delta]-[Sigma] modulator is realized through the use of a pass-gate adder circuit optimized for low power and high speed. The digital modulator is software programmable to support multiple bandwidths, frequency channels, and modulation schemes. It can be used adaptively to transmit in selected channels with variable bit-rates, depending on channel conditions. It is envisioned that the [Delta]-[Sigma] digital-RF modulator can be used as a universal transmitter for wideband systems and applications that require high data rates and low power consumption.
by Albert Jerng.
Ph.D.
Štraus, Pavel. "Zvuková karta pro PC s obvodem FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-219090.
Повний текст джерелаHellman, Johan. "Implementation of a Low-Cost Analog-to-Digital Converter for Audio Applications Using an FPGA." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-96009.
Повний текст джерелаWang, Ting-Yang, and 王鼎洋. "Continuous-Time Incremental Delta Sigma Data Converter." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/81725051881955473970.
Повний текст джерела國立臺灣大學
電子工程學研究所
103
Incremental sigma-delta data converter (IDC) has many useful applications such as DC measurement, linear feet measurement, biomedical application, sensor array application, and is suitable for any multi-channel applications. Most of the IDC today is made by discrete-time (DT) structure. But continuous-time (CT) structure consumes much less power than DT one, since continuous ramping instead of discrete settling behavior is involved in CT loop-filters. This thesis use CT structure to make the modulator faster and consume less power. A third order 3-bit CT-IDC with OSR=64 fabricated in TSMC T18 1P6M technology is proposed in the thesis. The modulator is operated at 100MHz sampling clock. It achieves peak SNDR of 73.82dB within 737 kHz bandwidth. This chip dissipates 6.6 mA from a 3.3V supply. The core area of this modulator occupies smaller than 0.25mm2.
Hsieh, Yu-Lun, and 謝雨倫. "Continuous-Time Incremental Delta Sigma Data Converter." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/aeje7j.
Повний текст джерела國立臺灣大學
電子工程學研究所
106
Incremental delta-sigma data converter (IDC) has many useful applications including biomedical measurement and sensor array measurement, and is suitable for multi-channel platforms. This application for internet of things (IOT) always combine the characteristics of high-speed transmission and wireless network connectivity. Therefore, low power consumption is the first to be considered.This thesis presents a 3rd-order, 5-bit continuous-time incremental delta-sigma data converter (CTIDC). For low power consideration, we replace conventional FLASH ADC by power-efficient successive-approximation-register (SAR) ADC and utilizing the noise coupling (NC) technique to reduce the numbers of power-hungry op-amps for the same noise shaping effect. The excess loop delay compensation (ELDC) is also embedded in the SAR ADC without using additional DAC.Fabricated in TSMC 40 nm LP 1P6M technology, the proposed modulator is operated at 1.6MHz sampling clock. It achieves peak SNDR of 71.98 dB in IDC mode and 72.34 dB SNDR in SDM mode within 25 kHz signal bandwidth. This chip dissipates 225 μW from 1.2V/1.5V supply voltage. The active area of this modulator occupies less than 0.318mm2.
Caldwell, Trevor. "Delta-Sigma Modulators with Low Oversampling Ratios." Thesis, 2010. http://hdl.handle.net/1807/26352.
Повний текст джерелаHamoui, Anas A. "Delta-sigma data converters for broadband digital communications." 2004. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=94495&T=F.
Повний текст джерелаAkram, Waqas. "Tunable mismatch shaping for bandpass Delta-Sigma data converters." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-05-3575.
Повний текст джерелаtext
Bilhan, Erkan. "Very low power sigma delta modulator for WCDMA /." 2008. http://proquest.umi.com/pqdweb?did=1654494021&sid=1&Fmt=2&clientId=10361&RQT=309&VName=PQD.
Повний текст джерелаChen, Hongbo. "Integrated Circuit Blocks for High Performance Baseband and RF Analog-to-Digital Converters." Thesis, 2011. http://hdl.handle.net/1969.1/ETD-TAMU-2011-12-10522.
Повний текст джерелаVijjapu, Sudheer. "RC implementation of an audio frequency band Butterworth MASH delta-sigma analog to digital data converter -- FULL TEXT IS NOT AVAILABLE." Thesis, 2006. http://hdl.handle.net/10057/568.
Повний текст джерелаThesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
"August 2006."
Includes bibliographic references (leaves 41-43).
Lin, Jia-Ni, and 林佳霓. "A Delta-Sigma A/D Converter with Novel Data-Weighted Averaging Algorithm for Cochlear Prosthesis System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/98195844371113668602.
Повний текст джерела國立交通大學
電機工程學系
103
In recent years, with the rapid of development of biomedical electronic systems, low power consumption and low noise have become very important research topic. The ADC plays a very important role in biomedical electronic systems. In this thesis, the design of the delta-sigma A/D converter for applications of cochlear prosthesis has been implemented. A multi-bit delta-sigma ADC uses data weighted averaging (DWA) algorithm applied to the feedback DAC. DWA algorithm has been used to suppress the harmonic distortions. The pointer selection of DAC elements is used cyclically, which has resulted in some baseband tones. A novel DWA algorithm is proposed to further reduce baseband tones than the conventional DWA. The method randomly adds 0 or 1 during the pointer selection, which has improved the performance of SFDR and SNDR. In this thesis, the measurement results show that the peak signal to noise and distortion ratio is 50.1dB and the dynamic range is 58dB. The chip was fabricated by TSMC 0.18µm 1P6M CMOS mixed signal process. The chip area is 1.168 x 0.632 mm2 and power consumption is 452µW from a 1.8-V power supply.
Baig, Shams Javid. "RC implementation of an audio frequency band fourth order Chebyshev Type II delta-sigma analog to digital data converter -- FULL TEXT IS NOT AVAILABLE." Thesis, 2006. http://hdl.handle.net/10057/614.
Повний текст джерелаThesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
Includes bibliographical references (leaves 37-38)
"December 2006."
Hayward, Roger D. "Improving a sampled-data circuit simulator for Delta-Sigma modulator design." Thesis, 1992. http://hdl.handle.net/1957/36732.
Повний текст джерелаGraduation date: 1992
Gharbiya, Ahmed. "Architecture Alternatives for Time-interleaved and Input-feedforward Delta-Sigma Modulators." Thesis, 2008. http://hdl.handle.net/1807/11206.
Повний текст джерелаWang, Yan. "Design techniques for wideband low-power Delta-Sigma analog-to-digital converters." Thesis, 2009. http://hdl.handle.net/1957/13664.
Повний текст джерелаGraduation date: 2010
Yang, Yuqing Ph D. "System oriented delta sigma analog-to-digital modulator design for ultra high precisoin data acquisition applications." 2008. http://hdl.handle.net/2152/18176.
Повний текст джерелаtext
Reis, Luís Filipe Brochado. "CMOS RF Sigma-Delta Converter." Master's thesis, 2017. https://repositorio-aberto.up.pt/handle/10216/107273.
Повний текст джерелаReis, Luís Filipe Brochado. "CMOS RF Sigma-Delta Converter." Dissertação, 2017. https://repositorio-aberto.up.pt/handle/10216/107273.
Повний текст джерелаChuang, Bob, and 莊博智. "Sigma-Delta Analog to Digital Converter." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/22995366967144993753.
Повний текст джерела國立中興大學
電機工程學系所
98
A signal output with natural variations in energy retrieved by sensors is the analog type, while the subsequent circuit processing belongs to the digital type. Hence, to enable a smooth transition between analog and digital circuits requires A/D converters. Types of A/D converters are available for different applications. Practitioners regard Sigma-Delta A/D converters, which have been developed and improved for several decades, among the best converters available with wide applications in devices such as sphygmomanometers, ear thermometers, body weight scales, and audio frequency circuits. For mid to low speed, high bit A/D converter circuits, the advantage is that quantizer and digital filter processes can be completed using digital circuits. Current research has developed the integrator and comparator of the analog part with OP AMP, followed by creating the quantizer and decimation filter with a Complex-programmable Logic Device (CPLD), thus, obtaining a complete Sigma-Delta A/D digital converter. Finally, measuring instruments have evaluated important characteristics, such as integral non-linearity/differential non-linearity (INL/DNL) and the effective number of bits (ENOB).The measurement result: DNL is -1 to +0.9 LSB avg0.005 LSB, INL is -4 to +2 LSB avg-1.7 LSB, , ENOBAvg 5.4 bit.
Fonseca, Diogo Dinis da. "Low-pass CMOS Sigma-Delta Converter." Master's thesis, 2018. https://hdl.handle.net/10216/114123.
Повний текст джерелаThe growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption.
Fonseca, Diogo Dinis da. "Low-pass CMOS Sigma-Delta Converter." Dissertação, 2018. https://hdl.handle.net/10216/114123.
Повний текст джерелаThe growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance . Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution. This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption.
Fonseca, Diogo Dinis da. "Low-pass CMOS Sigma-Delta Converter." Dissertação, 2002. https://repositorio-aberto.up.pt/handle/10216/114123.
Повний текст джерелаThe growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance .Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution.This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption.
Chen, Shr-Lung, and 陳仕龍. "CMOS Delta Sigma Magnetic to Digital Converter." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/89670513080719273701.
Повний текст джерела國立臺灣大學
電機工程學研究所
89
In this thesis, we have proposed several magnetic to digital converters designed with MAGFET, and we have successfully transferred the magnetic signal into frequency domain, time domain, and voltage domain respectively. These application circuits are implemented in UMC 0.5mm DPDM CMOS process and SHARP 0.35mm DPDM CMOS process. In chapter2, the “double MOSFET method” has been applied to implement the linear resistor pairs in MOP, and this gives the possibility of implementing a fully integrated magnetic sensor interface. In chapter3, a magnetically controlled ring oscillator has been proposed. In particular, it exhibits the highest sensitivity/power ratio reported to date for a silicon magnetic field sensor based on oscillator. Another magnetic to pulse width digitizer has also been realized, which can reach a very small equivalent resolution. After off-line calibration, the offset can be reduced and gain error can be further minimized. Transferring the magnetic signal to frequency and time domain pave the way for the low voltage operation in the future. In chapter 4, We combined the MOP with the integrator of the modulator in the first order MDC, thus saving power and area because one opamp is spared. Combining this method with the pseudo two path technique, we presented a very compact second order MDC system using only opamp for low cost applications. In chapter5, the MAGFET offset canceling technique and differencing sampling technique are applied along with the design of MOP and integrator. The goal of reduced offset and gain factor enhancement are achieved. To sum up, we demonstrated the potential of oversampling techniques (in particular sigma-delta modulators and incremental A/D converters) for implementing very flexible, robust and performant sensor interface circuits. The measurement results have verified the correctness and feasibility of designed circuits. Such MDCs have the potential for low cost magnetic sensor applications.
Jen, Yung-Hsin, and 任永星. "An Integrated Sigma-Delta Noise-Spread Buck Converter." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/61695217339044281618.
Повний текст джерела國立成功大學
電機工程學系碩博士班
96
An integrated sigma.delta noise-spread buck converter using a discrete-time second order single.bit sigma-delta modulator (DT-SDM2) is presented. The DT-SDM2 buck converter and a compared PWM controller are designed and fabricated on a standard TSMC 0.35μm 3.3V CMOS process. Compared to a traditional PWM controller switching at 200 kHz, the DT-SDM2 sampling at 1M Hz suppresses the noise tone by 50dB at PWM switching frequency, spreads the noise floor by 53dB at DT-SDM2 sampling frequency,and decreases total noise power by 12.5% in 2M Hz with 95.6% efficiency and 0.83% output voltage ripple. The operating frequency of the proposed DT-SDM2 ranges from 400 KHz to 1 MHz. Simulation results show that DT-SDM2 has better noise performance than PWM and continuous.time SDM2 (CT-SDM2) buck converter.
Chuang, Chao-Hsun, and 莊肇勳. "The Delta-Sigma D/A converter of FPGA." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/23097676004884092553.
Повний текст джерела南台科技大學
電子工程系
99
The technique of low bandwidth, high resolution over-sampling interpolation delta-sigma modulator has been used extensively in digital to analog converter. The purpose of this thesis is to design a Delta-Sigma digital to analog converter which can be applied to voice signal. The architecture of this system is made up with an FIR filter and a 2nd order Delta-Sigma Modulator. This system focuses on the voice band signal with 10-bit digital data format, 20Hz to 3.4kHz frequency range, 8kHz input sampling rate and 32X over-sampling rate. The output is one digital bit to simplify the system circuit. Regarding to the design of this system, firstly, we use MATLAB to calculate the FIR coefficients and then simulate the whole system to confirm the feasibility and efficiency of this system. Secondly, we use verilog hardware description language to design the system circuits and also devise a test mechanism to verify the circuits.