Статті в журналах: "CONTINOUS TIME CIRCUITS"

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Califano, Alfonso Maria, Laurent Bitker, Ian Baldwin, Nigel Fealy, and Rinaldo Bellomo. "Circuit Survival during Continuous Venovenous Hemodialysis versus Continuous Venovenous Hemofiltration." Blood Purification 49, no. 3 (2020): 281–88. http://dx.doi.org/10.1159/000504037.

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Background: Continuous renal replacement therapy (CRRT) technique may affect circuit lifespan. A shorter circuit life may reduce CRRT efficacy and increase costs. Methods: In a before-and-after study, we compared circuit median survival time during continuous venovenous hemofiltration (CVVH) versus continuous venovenous hemodialysis (CVVHD). We performed log-rank mixed effects univariate analysis and Cox mixed effect regression modeling to define predictors of circuit lifespan. Results: We compared 197 CVVHD and 97 CVVH circuits in 39 patients. There was no overall difference in circuit lifespan. When no anticoagulation was used, median circuit survival time was shorter for CVVH circuits (5 h, 95% CI 3–7 vs. 10 h, 95% CI 8–13, p < 0.01). Moreover, CVVHD, lower platelets levels, and longer activated partial thromboplastin time independently predicted longer circuit median survival time. Conclusions: CVVHD is associated with longer circuit median survival time than CVVH when no anticoagulation is used and is an independent predictor of circuit survival.

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Bierer, P., A. W. Holt, A. D. Bersten, J. L. Plummer, and A. H. Chalmers. "Haemolysis Associated with Continuous Venovenous Renal Replacement Circuits." Anaesthesia and Intensive Care 26, no. 3 (June 1998): 272–75. http://dx.doi.org/10.1177/0310057x9802600307.

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Extracorporeal circuits can cause haemolysis resulting in an increase in plasma-free haemoglobin (PFHb). High pressures and clots within the circuit have been identified as factors increasing the likelihood of haemolysis. Continuous venovenous haemodiafiltration (CVVHD) is associated with high circuit pressures as the pump-driven circuit clots over a period of time. PFHb was measured during CVVHD to determine if circuit life, maximum circuit pressure or the clotting of the haemofilter was associated with evidence of haemolysis. Circuit life up to 50 hours, circuit pressures or haemofilter clotting had no significant effect on PFHb. There was a small rise in PFHb in the circuits lasting beyond 50 hours. CVVHD circuits can be run up to 50 hours without concern for haemolysis.

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PRAMOD, M., and T. LAXMINIDHI. "LOW POWER CONTINUOUS TIME COMMON MODE SENSING FOR COMMON MODE FEEDBACK CIRCUITS." Journal of Circuits, Systems and Computers 19, no. 03 (May 2010): 519–28. http://dx.doi.org/10.1142/s0218126610006268.

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Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.

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Kaczorek, Tadeusz. "SINGULAR FRACTIONAL CONTINUOUS-TIME AND DISCRETE-TIME LINEAR SYSTEMS." Acta Mechanica et Automatica 7, no. 1 (March 1, 2013): 26–33. http://dx.doi.org/10.2478/ama-2013-0005.

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Abstract New classes of singular fractional continuous-time and discrete-time linear systems are introduced. Electrical circuits are example of singular fractional continuous-time systems. Using the Caputo definition of the fractional derivative, the Weierstrass regular pencil decomposition and Laplace transformation the solution to the state equation of singular fractional linear systems is derived. It is shown that every electrical circuit is a singular fractional systems if it contains at least one mesh consisting of branches with only ideal supercondensators and voltage sources or at least one node with branches with supercoils. Using the Weierstrass regular pencil decomposition the solution to the state equation of singular fractional discrete-time linear systems is derived. The considerations are illustrated by numerical examples.

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5

Jiao, Su Min, Cai Hong Wang, and Xue Mei Wang. "Large-Scale Analog Circuit Evolutionary Design Using a Real-Coded Scheme." Applied Mechanics and Materials 220-223 (November 2012): 2036–39. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.2036.

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Analog circuits are of great importance in electronic system design. Recent evolutionary design results are usually small-scale analog circuits. This paper proposes a real-coded mechanism and uses it in the large-scale analog circuit evolutionary design. The proposed scheme evolves the circuit topology and size to a uniformed continuous space, in which the circuit representation is closed and of causality. Experimental results show that the proposed scheme can work successfully on many analog circuits with different kinds of characteristics. Comparing with other evolutionary methods before, the proposed scheme performs better on large-scale problems of circuit synthesis with higher search efficiency, lower computational complexity, and less computing time.

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Kaczorek, T. "Positive time-varying continuous-time linear systems and electrical circuits." Bulletin of the Polish Academy of Sciences Technical Sciences 63, no. 4 (December 1, 2015): 837–42. http://dx.doi.org/10.1515/bpasts-2015-0095.

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AbstractThe positivity of time-varying continuous-time linear systems and electrical circuits are addressed. Necessary and sufficient conditions for the positivity of the systems and electrical circuits are established. It is shown that there exists a large class of positive electrical circuits with time-varying parameters. Examples of positive electrical circuits are presented.

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7

Lu, Weijun, Ning Bao, Tangren Zheng, Xiaorui Zhang, and Yutong Song. "Memristor-Based Read/Write Circuit with Stable Continuous Read Operation." Electronics 11, no. 13 (June 27, 2022): 2018. http://dx.doi.org/10.3390/electronics11132018.

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In recent years, computation-intensive applications, such as artificial intelligence, video processing and encryption, have been developing rapidly. On the other hand, the problems of “storage wall” and “power consumption wall” for the traditional storage and computing separated architectures limit the computing performance. The computational circuits and memory cells based on nonvolatile memristors are unified and become a competitive solution to this problem. However, there are various problems that prevent memristor-based circuits from entering practical applications, one of which is the memristor state deviation problem caused by continuous reading. In this paper, we study some circuits studied by predecessors on read/write circuit, compare the experimental results, analyze the reason for the resistance state deviation of memristor, and put forward a new parallel structure of memristor based on opposite polarity. The logic “1” and logic “0” are represented by the positive and negative voltage difference of two memristors with opposite polarity, which can effectively alleviate the problem of the resistance state deviation caused by continuous reading. A reading voltage of 2 V is applied to the four circuits at the same time, and continuous reading is carried out until the output voltage becomes stable. The voltage offset of the optimized circuit when reading logic “0” is reduced to 78 mV, which is significantly smaller than that of other circuits. In addition, when reading logic “1”, it has the effect of enhancing the information stored in the memristor.

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Baryshev, I. V., К. А. Scherbina, E. P. Msallam, M. А. Vonsovitch, and A. V. Odokienko. "The experimental research of filtration quality of doppler signal spectral structure by modu-lated filter." Radiotekhnika, no. 191 (December 22, 2017): 150–57. http://dx.doi.org/10.30837/rt.2017.4.191.14.

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The comparative analysis of quantitative assessments of filtering by six performance indices of filter circuits of continuous-wave Doppler signal of 1st order PLL, 2nd order PLL, FLL with narrow-band filter circuit quadrature FM-detector based on synchronized oscillator with forced frequency tuning is carried out. The total average performance indices of the circuit with SG exceeded any of the compared indices by 1.5 times, with a tenfold increase in separate parameters. At the same time the method of indices calculation of filter circuits with SG is developed and simple calculation formulas are obtained.

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9

Tymoshchuk, Pavlo, and s. Shatny. "Hardware Implementation of Parallelized Fuzzy Adaptive Resonance Theory Neural Network." Computer Design Systems. Theory and Practice, no. 1 (2020): 1–11. http://dx.doi.org/10.23939/cds2019.01.001.

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A hardware implementation design of parallelized fuzzy Adaptive Resonance Theory neural network is described and simulated. Parallel category choice and resonance are implemented in the network. Continuous-time and discrete-time winner-take-all neural circuits identifying the largest of M inputs are used as the winner-take-all units. The continuous-time circuit is described by a state equation with a discontinuous right-hand side. The discrete-time counterpart is governed by a difference equation. Corresponding functional block-diagrams of the circuits include M feed-forward hard- limiting neurons and one feedback neuron, which is used to compute the dynamic shift of inputs. The circuits combine arbitrary finite resolution of inputs, high convergence speed to the winner-take-all operation, low computational and hardware implementation complexity, and independence of initial conditions. The circuits are also used for finding elements of input vector with minimal/maximal values to normalize them in the range [0,1].

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Maass, Wolfgang, Thomas Natschläger, and Henry Markram. "Real-Time Computing Without Stable States: A New Framework for Neural Computation Based on Perturbations." Neural Computation 14, no. 11 (November 1, 2002): 2531–60. http://dx.doi.org/10.1162/089976602760407955.

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A key challenge for neural modeling is to explain how a continuous stream of multimodal input from a rapidly changing environment can be processed by stereotypical recurrent circuits of integrate-and-fire neurons in real time. We propose a new computational model for real-time computing on time-varying input that provides an alternative to paradigms based on Turing machines or attractor neural networks. It does not require a task-dependent construction of neural circuits. Instead, it is based on principles of high-dimensional dynamical systems in combination with statistical learning theory and can be implemented on generic evolved or found recurrent circuitry. It is shown that the inherent transient dynamics of the high-dimensional dynamical system formed by a sufficiently large and heterogeneous neural circuit may serve as universal analog fading memory. Readout neurons can learn to extract in real time from the current state of such recurrent neural circuit information about current and past inputs that may be needed for diverse tasks. Stable internal states are not required for giving a stable output, since transient internal states can be transformed by readout neurons into stable target outputs due to the high dimensionality of the dynamical system. Our approach is based on a rigorous computational model, the liquid state machine, that, unlike Turing machines, does not require sequential transitions between well-defined discrete internal states. It is supported, as the Turing machine is, by rigorous mathematical results that predict universal computational power under idealized conditions, but for the biologically more realistic scenario of real-time processing of time-varying inputs. Our approach provides new perspectives for the interpretation of neural coding, the design of experiments and data analysis in neurophysiology, and the solution of problems in robotics and neurotechnology.

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11

Murali, K., Sudeshna Sinha, and William L. Ditto. "Implementation of NOR Gate by a Chaotic Chua's Circuit." International Journal of Bifurcation and Chaos 13, no. 09 (September 2003): 2669–72. http://dx.doi.org/10.1142/s0218127403008053.

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We report the experimental implementation of the most fundamental NOR gate with a chaotic Chua's circuit by a simple threshold mechanism. This provides a proof-of-principle experiment to demonstrate the universal computing capability of chaotic circuits in continuous time systems.

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12

Ramirez-Angulo, J., and A. J. Lopez. "MITE circuits: the continuous-time counterpart to switched-capacitor circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 1 (2001): 45–55. http://dx.doi.org/10.1109/82.913186.

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13

Singh, N. S. S. "Programmed Tool for Quantifying Reliability and Its Application in Designing Circuit Systems." Journal of Electrical and Computer Engineering 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/410758.

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As CMOS technology scales down to nanotechnologies, reliability continues to be a decisive subject in the design entry of nanotechnology-based circuit systems. As a result, several computational methodologies have been proposed to evaluate reliability of those circuit systems. However, the process of computing reliability has become very time consuming and troublesome as the computational complexity grows exponentially with the dimension of circuit systems. Therefore, being able to speed up the task of reliability analysis is fast becoming necessary in designing modern logic integrated circuits. For this purpose, the paper firstly looks into developing a MATLAB-based automated reliability tool by incorporating the generalized form of the existing computational approaches that can be found in the current literature. Secondly, a comparative study involving those existing computational approaches is carried out on a set of standard benchmark test circuits. Finally, the paper continues to find the exact error bound for individual faulty gates as it plays a significant role in the reliability of circuit systems.

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14

Abdulfatah, Azahar S., and Esraa K. Sae’d. "Modeling and Simulation Control of Buck Converter Applied to Solar Energy." Tikrit Journal of Engineering Sciences 23, no. 4 (December 31, 2016): 31–35. http://dx.doi.org/10.25130/tjes.23.4.04.

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The great difficulty in controlling the value of the continuous voltage and the inability to use electrical transformers because of constant produce flux by the direct current(DC) with time, therefore must be find other ways to control the continuous voltage value. The best methods used for this purpose are power electronics circuit, these circuits is buck converter, as a result of the output voltage becomes lower than from the input voltage. the renewable energies need to converter circuits to enable consumers to use and the circuit which represent the heart of the hybrid system (the sun /wind).This research addresses use modern methods in the control of buck converter used with the hybrid systems (solar energy / wind) as well as mathematically represented using the equations and computer simulation program and the famous (proteas (ISIS professional)) .

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15

Kumar, N., G. Cauwenberghs, and A. G. Andreou. "Auditory feature extraction using self-timed, continuous-time discrete-signal processing circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 44, no. 9 (1997): 723–28. http://dx.doi.org/10.1109/82.625002.

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16

Sabet, M. Amin, and Behnam Ghavami. "Statistical soft error rate estimation of combinational circuits using Bayesian networks." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 35, no. 5 (September 5, 2016): 1760–73. http://dx.doi.org/10.1108/compel-09-2015-0317.

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Purpose With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation. Design/methodology/approach In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated. Findings Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime. Originality/value The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.

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17

Green, Danielle J., Kevin M. Watt, Douglas N. Fish, Autumn McKnite, Walter Kelley, and Adam R. Bensimhon. "Cefepime Extraction by Extracorporeal Life Support Circuits." Journal of ExtraCorporeal Technology 54, no. 3 (September 2022): 212–22. http://dx.doi.org/10.1051/ject/202254212.

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Extracorporeal life support (ECLS) devices are lifesaving for critically ill patients with multi-organ dysfunction. Despite this, patients supported with ECLS are at high risk for ECLS-related complications, including nosocomial infections, and mortality rates are high in this patient population. The high mortality rates are suspected to be, in part, a result of significantly altered drug disposition by the ECLS circuit, resulting in suboptimal antimicrobial dosing. Cefepime is commonly used in critically ill patients with serious infections. Cefepime dosing is not routinely guided by therapeutic drug monitoring and treatment success is dependent upon the percentage of time of the dosing interval that the drug concentration remains above the minimum inhibitory concentration of the organism. This ex vivo study measured the extraction of cefepime by continuous renal replacement therapy (CRRT) and extracorporeal membrane oxygenation (ECMO) circuits. Cefepime was studied in four closed-loop CRRT circuit configurations and a single closed-loop ECMO circuit configuration. Circuits were primed with a physiologic human blood–plasma mixture and the drug was dosed to achieve therapeutic concentrations. Serial blood samples were collected over time and concentrations were quantified using validated assays. In ex vivo CRRT experiments, cefepime was rapidly cleared by dialysis, hemofiltration, and hemodiafiltration, with greater than 96% cefepime eliminated from the circuit by 2 hours. In the ECMO circuits, the mean recovery of cefepime was similar in both circuit and standard control. Mean (standard deviation) recovery of cefepime in the ECMO circuits (n = 6) was 39.2% (8.0) at 24 hours. Mean recovery in the standard control (n = 3) at 24 hours was 52.2% (1.5). Cefepime is rapidly cleared by dialysis, hemofiltration, and hemodiafiltration in the CRRT circuit but minimally adsorbed by either the CRRT or ECMO circuits. Dosing adjustments are needed for patients supported with CRRT.

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SHARKOVSKY, A. N. "IDEAL TURBULENCE IN AN IDEALIZED TIME-DELAYED CHUA’S CIRCUIT." International Journal of Bifurcation and Chaos 04, no. 02 (April 1994): 303–9. http://dx.doi.org/10.1142/s0218127494000216.

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By replacing the parallel LC “resonator” in Chua’s circuit by a lossless transmission line, terminated by a short circuit, we obtain a “time-delayed Chua’s circuit” whose time evolution is described by a pair of linear partial differential equations with a nonlinear boundary condition. If we neglect the capacitance across the Chua’s diode, described by a nonsymmetric piecewiselinear vR–iR characteristic, the resulting idealized time-delayed Chua’s circuit is described exactly by a scalar nonlinear difference equation with continuous time, which makes it possible to characterize its associated nonlinear dynamics and spatial chaotic phenomena. From a mathematical viewpoint, circuits described by ordinary differential equations can generate only temporal chaos, while the time-delayed Chua’s circuit can generate spatiotem poral chaos. Except for stepwise periodic oscillations, the typical solutions of the idealized time-delayed Chua’s circuit consist of either weak turbulence, or strong turbulence, which are examples of “ideal” (or “dry”) turbulence. In both cases, we can observe infinite processes of spatiotemporal coherent structure formations. Under weak turbulence, the graphs of the solution tend to limit sets which are fractals with a Hausdorff dimension between 1 and 3, and is therefore larger than the topological dimension (of sets). Under strong turbulence, the “limit” oscillations are oscillations whose amplitudes are random functions. This means that the attractor of the idealized time-delayed Chua’s circuit already contains random functions, and spatial self-stochasticity phenomenon can be observed.

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DOLEV, NOAM, AVNER KORNFELD, and AVINOAM KOLODNY. "COMPARISON OF SIGMA–DELTA CONVERTER CIRCUIT ARCHITECTURES IN DIGITAL CMOS TECHNOLOGY." Journal of Circuits, Systems and Computers 14, no. 03 (June 2005): 515–32. http://dx.doi.org/10.1142/s0218126605002507.

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Integration of analog-to-digital signal conversion circuits into digital submicron silicon chips is required for many applications. This is typically implemented by sigma–delta circuits, which can provide good resolution without requiring trimming of component values. This paper presents an analytical comparison of noise performance in four alternative sigma–delta circuit configurations which have been presented in the literature, consisting of discrete-time and continuous-time integration in voltage-mode and in current-mode. For high resolution, superiority of switched-capacitor circuits over the alternatives is shown, based on process technology considerations. Design guidelines are outlined for selecting oversampling rate and other key parameters, in order to obtain maximal data resolution.

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Singh, N. S. S., N. H. Hamid, and V. S. Asirvadam. "Reliability Programmed Tool and its Application for Fault Tolerance Computation." Advanced Materials Research 909 (March 2014): 397–404. http://dx.doi.org/10.4028/www.scientific.net/amr.909.397.

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With the continuous scaling of CMOS technology, reliability of nanobased electronic circuits is endlessly becoming a major concern. Due to this phenomenon, several computational approaches have been developed for the reliability assessment of modern logic integrated circuits. However, these analytical methodologies have a computational complexity that increases exponentially with the circuit dimension, making the whole reliability assessment process of large circuits becoming very time consuming and intractable. Therefore, to speed up the reliability assessment of large circuits, this paper firstly looks into the development of a programmed reliability tool. The Matlab-based tool is developed based on the generalization of Probabilistic Transfer Matrix (PTM) model as one of the existing reliability assessment approaches. Users have to provide description of the desired circuit in the form of Netlist that becomes the input to the programmed tool. For illustration purpose, in this paper, C17 has been used as the benchmark test circuit for its reliability computation. Secondly, reliability of a desired circuit does not only depend on its faulty gates, but it also depends on the maximum error threshold of these faulty gates above which no reliable computation is possible. For this purpose, the developed tool is employed again to find the exact error thresholds for faulty gates.

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Piotrowska, Ewa. "Positive continuous – time linear electrical circuit." Poznan University of Technology Academic Journals: Electrical Engineering, no. 93 (2018): 299–309. http://dx.doi.org/10.21008/j.1897-0737.2018.93.0025.

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22

Nedjah, Nadia, Jalber Dinelli Luna Galindo, Luiza de Macedo Mourelle, and Fernanda Duarte Vilela Reis de Oliveira. "Fault Diagnosis in Analog Circuits Using Swarm Intelligence." Biomimetics 8, no. 5 (August 25, 2023): 388. http://dx.doi.org/10.3390/biomimetics8050388.

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Open or short-circuit faults, as well as discrete parameter faults, are the most commonly used models in the simulation prior to testing methodology. However, since analog circuits exhibit continuous responses to input signals, faults in specific circuit elements may not fully capture all potential component faults. Consequently, diagnosing faults in analog circuits requires three key aspects: identifying faulty components, determining faulty element values, and considering circuit tolerance constraints. To tackle this problem, a methodology is proposed and implemented for fault diagnosis using swarm intelligence. The investigated optimization techniques are Particle Swarm Optimization (PSO) and the Bat Algorithm (BA). In this methodology, the nonlinear equations of the tested circuit are employed to calculate its parameters. The primary objective is to identify the specific circuit component that could potentially exhibit the fault by comparing the responses obtained from the actual circuit and the responses obtained through the optimization process. Two circuits are used as case studies to evaluate the performance of the proposed methodologies: the Tow–Thomas Biquad filter (case study 1) and the Butterworth filter (case study 2). The proposed methodologies are able to identify or at least reduce the number of possible faulty components. Four main performance metrics are extracted: accuracy, precision, sensitivity, and specificity. The BA technique demonstrates superior performance by utilizing the maximum combination of accessible nodes in the tested circuit, with an average accuracy of 95.5%, while PSO achieved only 93.9%. Additionally, the BA technique outperforms in terms of execution time, with an average time reduction of 7.95% reduction for the faultless circuit and an 8.12% reduction for the faulty cases. Compared to the machine-learning-based approach, using BA with the proposed methodology achieves similar accuracy rates but does not require any datasets nor any time-demanding training to proceed with circuit diagnostic.

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23

Hasler, P. "Continuous-time feedback in floating-gate MOS circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 48, no. 1 (2001): 56–64. http://dx.doi.org/10.1109/82.913187.

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Albertí, E. B. "Continuous-Time Adaptive Control of Consumer Electronic Circuits." IFAC Proceedings Volumes 25, no. 14 (July 1992): 335–40. http://dx.doi.org/10.1016/s1474-6670(17)50757-0.

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25

Beer, Randall D. "Parameter Space Structure of Continuous-Time Recurrent Neural Networks." Neural Computation 18, no. 12 (December 2006): 3009–51. http://dx.doi.org/10.1162/neco.2006.18.12.3009.

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A fundamental challenge for any general theory of neural circuits is how to characterize the structure of the space of all possible circuits over a given model neuron. As a first step in this direction, this letter begins a systematic study of the global parameter space structure of continuous-time recurrent neural networks (CTRNNs), a class of neural models that is simple but dynamically universal. First, we explicitly compute the local bifurcation manifolds of CTRNNs. We then visualize the structure of these manifolds in net input space for small circuits. These visualizations reveal a set of extremal saddle node bifurcation manifolds that divide CTRNN parameter space into regions of dynamics with different effective dimensionality. Next, we completely characterize the combinatorics and geometry of an asymptotically exact approximation to these regions for circuits of arbitrary size. Finally, we show how these regions can be used to calculate estimates of the probability of encountering different kinds of dynamics in CTRNN parameter space.

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Johansson, Susie, and John Dzarnoski. "Evaluation of Epoxy Flux for Use in Hearing Aid SMD Assemblies." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000152–57. http://dx.doi.org/10.4071/isom-2013-ta53.

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Miniaturization of everyday products has been driving sales for some time and continues to fuel the consumer market. Everyone expects size reduction with each new product generation [1], [2]. Almost everything has electronics inside that must get smaller. There is no market demanding smaller devices that are faster, more capable, more feature-rich than that of the hearing aid industry. While radios, Bluetooth wireless systems and other accessories are added to hearing instruments feature lists, the consumer nonetheless continues to wish for them to be even smaller. Advancements in circuit fabrication, component shrinkage and die consolidation have aided the industry in satisfying this need. However, as this demand continues and even intensifies, current surface mount device assembly materials are becoming inadequate and the limiting factor for overall circuit size reduction; specifically, the die attachment, protection and reinforcement process is limiting how small hearing aid circuits can be. For hearing aids, the addition of more features and connection to more accessories each require a number of integrated circuits and associated passives attached to a flexible circuit. These circuits are invariably bent and twisted during assembly, up to 180°, requiring the integrated circuit solder joints to be reinforced by underfilling to prevent detachment. Unfortunately, the underfilling process is time-consuming and the capillary action necessary for its success is finicky. Even more unfavorably, a designated “keep out” area for other components must surround the die to be underfilled to allow for the dispensing equipment to access the die, reducing the useable board space and limiting the overall possibility of circuit size reduction. Additionally, the underfill material must stay away from circuit board edges and areas to be bent during final assembly. In an attempt to increase useable circuit board space, decrease overall circuit board size, and reduce assembly steps, the application of two epoxy flux materials for die attach fluxing and underfilling of hearing aids was evaluated. Epoxy flux is a relatively new material, which combines the functionality of flux and underfill into a single step. Epoxy flux's application, while eliminating steps, would more significantly eliminate the necessary “keep out” areas around die and allow for more densely placed surface mount components. The epoxy flux materials were applied by both printing and dipping, and then evaluated using x-ray imaging, scanning acoustic microscope imaging, die peel testing, multiple reflow integrity testing and die shear testing.

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Cam Taskiran, Zehra Gulru, Murat Taşkıran, Mehmet Kıllıoğlu, Nihan Kahraman, and Herman Sedef. "A novel memristive true random number generator design." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 38, no. 6 (October 24, 2019): 1931–47. http://dx.doi.org/10.1108/compel-11-2018-0463.

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Purpose In this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals. Methodology A Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results. Originality It is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators. Findings Two new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

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28

Elliott, Conal. "Timely Computation." Proceedings of the ACM on Programming Languages 7, ICFP (August 30, 2023): 895–919. http://dx.doi.org/10.1145/3607861.

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This paper addresses the question “what is a digital circuit?” in relation to the fundamentally analog nature of actual (physical) circuits. A simple informal definition is given and then formalized in the proof assistant Agda. At the heart of this definition is the timely embedding of discrete information in temporally continuous signals. Once this embedding is defined (in constructive logic, i.e., type theory), it is extended in a generic fashion from one signal to many and from simple boolean operations (logic gates) to arbitrarily sophisticated sequential and parallel compositions, i.e., to computational circuits. Rather than constructing circuits and then trying to prove their correctness, a compositionally correct methodology maintains specification, implementation, timing, and correctness proofs at every step. Compositionality of each aspect and of their combination is supported by a single, shared algebraic vocabulary and related by homomorphisms. After formally defining and proving these notions, a few key transformations are applied to reveal the linearity of circuit timing (over a suitable semiring), thus enabling practical, modular, and fully verified timing analysis as linear maps over higher-dimensional time intervals. An emphasis throughout the paper is simplicity and generality of specification, minimizing circuit-specific definitions and proofs while highlighting a broadly applicable methodology of scalable, compositionally correct engineering through simple denotations and homomorphisms.

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29

Xiang, Changyuan, Zutao Xiang, Wenjia Xu, and Weihua Xiang. "Transient Characteristics Analysis of 500kV Parallel Circuit Breaker Based on Highly Coupled Split Reactor." E3S Web of Conferences 118 (2019): 02048. http://dx.doi.org/10.1051/e3sconf/201911802048.

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With the continuous expansion of power system capacity, parallel high-voltage circuit breakers with a Highly Coupled Split Reactor (HCSR) have a potential application for limitation of high short-circuit current. However, as the parallel circuit breakers open at different time, the residual voltage of the split reactor on the post-open circuit breaker is higher and the stray capacitors of HCSR form high-order oscillating circuits, which may lead to serious transient recovery voltage (TRV). Therefore, it is necessary to analyze and simulate the transient characteristics of 500kV HCSR. Firstly, the equivalent model of HCSR circuit breakers is built in EMTP simulation plat-form, and its TRV generation is analyzed. Then, the TRV of parallel circuit breakers under different operating conditions and fault types is simulated and calculated. Finally, according to the statistical calculation results, the protection measure of 0.2uF shunt capacitance to limit rise rate of TRV is proposed.

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30

Ren, Ming Yuan, Xiao Wei Liu, Hai Feng Zhang, and Zhi Gang Mao. "High Resolution Micro-Displacement Sensing Circuit for Rotor Micro-Gyroscope." Key Engineering Materials 645-646 (May 2015): 538–42. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.538.

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A novel CMOS interface circuit with high resolution is designed and realized to achieve the integration of interface circuit for liquid suspended rotor micro-gyroscope. The detecting circuit adopts continuous-time current sensing circuit for capacitance measurement. The equivalent output noise power spectral density of phase-sensitive demodulation is 120 nV/Hz1/2. The whole circuitry is realized with 0.5 μm 2P2M CMOS process and its testing results show the circuit has a relative capacitance resolution of 1×10-8, in which the power supply is 18 V and the power consumption is 30 mW. The area of the chip is merely 18.5 mm2.

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31

Lee, Changyeop, Gyuseong Cho, Troy Unruh, Seop Hur, and Inyong Kwon. "Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad." Sensors 20, no. 10 (May 12, 2020): 2765. http://dx.doi.org/10.3390/s20102765.

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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32

Justh, E. W., and F. J. Kub. "Analogue CMOS continuous-time tapped delay-line circuit." Electronics Letters 31, no. 21 (October 12, 1995): 1793–94. http://dx.doi.org/10.1049/el:19951285.

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33

Singireddy, A., K. R. McMillan, and D. W. Graham. "Compact and low-power continuous-time derivative circuit." Electronics Letters 47, no. 17 (2011): 956. http://dx.doi.org/10.1049/el.2011.1991.

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34

BODDHU, SANJAY K., JOHN C. GALLAGHER, and SARANYAN A. VIGRAHAM. "A COMMERCIAL OFF-THE-SHELF IMPLEMENTATION OF AN ANALOG NEURAL COMPUTER." International Journal on Artificial Intelligence Tools 17, no. 02 (April 2008): 241–58. http://dx.doi.org/10.1142/s021821300800387x.

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For most applications, analog electrical circuit implementations of continuous-valued neural networks have been abandoned in favor of digital simulations. This is not surprising, as both precision and accuracy can be more easily ensured in digital computers. Still, because they use far fewer transistors and support components, analog circuits can still be orders of magnitude smaller than their digital simulations. In some application, like micro-robotics and embedded control, one might be willing to tolerate less accuracy and precision for the size and power benefits. One would not under any condition, however, tolerate significant behavioral mismatches between the differential equation and electrical circuit forms of the neural networks in question. In this paper, we will present a design for an analog neural computer that embodies the commonly used continuous time recurrent neural network. We will show that the computer possesses excellent behavioral congruence to the differential equation form even in the presence of significant practical compromises. We will also discuss the implications of this work for both practical Commercial, Off-The-Shelf (COTS) and Application-Specific Integrated Circuit (ASIC) devices.

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35

Schreier, R., and B. Zhang. "Delta-sigma modulators employing continuous-time circuitry." IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications 43, no. 4 (April 1996): 324–32. http://dx.doi.org/10.1109/81.488811.

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36

LIU, LING, CHONGXIN LIU, and YANBIN ZHANG. "EXPERIMENTAL VERIFICATION OF A FOUR-DIMENSIONAL CHUA'S SYSTEM AND ITS FRACTIONAL ORDER CHAOTIC ATTRACTORS." International Journal of Bifurcation and Chaos 19, no. 08 (August 2009): 2473–86. http://dx.doi.org/10.1142/s0218127409024256.

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This paper introduces a modified Chua's system which is a smooth four-dimensional continuous-time autonomous chaotic system with a cubic nonlinearity. Some dynamical behaviors of this 4-D Chua's system are further investigated by means of Poincaré mapping, parameter phase portraits, equilibrium points, bifurcations and calculated Lyapunov exponents. Moreover, using RC-opamp and analog multiplier we describe a simple electronic circuit for hardware implementation of the 4-D Chua's system which differ from previously reported Chua's circuits. Various attractors of experimental results from this chaotic oscillator are in good agreement with theoretical analysis. In particular, based on the approximation theory of fractional-order operator, a relevant analog circuit diagram of this fractional-order modified Chua's system is designed with α = 0.9. Observation results demonstrate that chaos exists indeed in this fractional-order modified Chua's system with an order as low as 3.6. This fractional-order oscillation circuit, for the first time in the literature, realizes high-dimensional Chua's chaotic system.

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37

Tyurin, S. F., A. Yu Skornyakova, Y. A. Stepchenkov, and Y. G. Diachenko. "SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs." Radio Electronics, Computer Science, Control 1, no. 1 (March 24, 2021): 36–45. http://dx.doi.org/10.15588/1607-3274-2021-1-4.

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Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to create self-timed FPGAs do not stop. The article proposes a Self-Timed Lookup Table for the Self-Timed Uncommitted Logic Array and the Self-Timed FPGA, carried out either by constants or utilizing additional memory cells. Authors proposed 1,2 – Self-Timed Lookup Table and described simulation results. Objective. The work’s goal is the analysis and design of the Strictly Self-Timed universal logic element based on Uncommitted Logic Array cells and pass-transistors circuits. Methods. Analysis and synthesis of the Strictly Self-Timed circuits with Boolean algebra. Simulation of the proposed element in the CAD “ARC”, TRANAL program, system NI Multisim by National Instruments Electronics Workbench Group, and layout design by Microwind. The reliability theory and reliability calculations in PTC Mathcad. Results. Authors designed, analyzed, and proved the Self-Timed Lookup Table’s workability for the Uncommitted Logic Arrays and FPGAs. Layouts of the novel logic gates are ready for manufacturing. Conclusions. The conducted studies allow us to use proposed circuits in perspective digital devices.

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38

Salimi, K., F. Krummenacher, C. Dehollain, and M. Declercq. "Continuous-time CMOS circuits based on multi-tanh linearisation principle." Electronics Letters 38, no. 3 (2002): 103. http://dx.doi.org/10.1049/el:20020083.

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39

Udayanga, Nilan, S. I. Hariharan, Soumyajit Mandal, Leonid Belostotski, Len T. Bruton, and Arjuna Madanayake. "Continuous-Time Algorithms for Solving Maxwell’s Equations Using Analog Circuits." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 10 (October 2019): 3941–54. http://dx.doi.org/10.1109/tcsi.2019.2915200.

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40

KRASILENKO, VLADIMIR, YURCHUK NATALIYA, and ALEXANDER LAZAREV. "THE NEW BASIC REALIZATIONS OF OPERATIONS “EQUIVALENCE” OF NEURO-FUZZY AND BIOINSPIRED NEURO-LOGICS TO CREATE HARDWARE ACCELERATORS OF ADVANCED EQUIVALENTAL MODELS OF NEURAL STRUCTURES AND MACHINE VISION SYSTEMS." Herald of Khmelnytskyi National University 303, no. 6 (December 2021): 153–66. http://dx.doi.org/10.31891/2307-5732-2021-303-6-153-166.

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The perspective of neural networks equivalental models (EM) base on vector-matrix procedure with basic operations of continuous and neuro-fuzzy logic (equivalence, absolute difference) are shown. Capacity on base EMs exceeded the amount of neurons in 4-10 times. This is larger than others neural networks paradigms. Amount neurons of this neural networks on base EMs may be 10 – 100 thousand. The base operations in EMs are normalized equivalence operations. The family of new operations “equivalence” and “non-equivalence” of neuro-fuzzy logic’s, which we have elaborated on the based of such generalized operations of fuzzy-logic’s as fuzzy negation, t-norm and s-norm are shown. Generalized rules of construction of new functions (operations) “equivalence” which uses operations of t-norm and s-norm to fuzzy negation are proposed. Despite the wide variety of types of operations on fuzzy sets and fuzzy relations and the related variety of new synthesized equivalence operations based on them, it is possible and necessary to select basic operations, taking into account their functional completeness in the corresponding algebras of continuous logic, as well as their most effective circuitry implementations. Among these elements the following should be underlined: 1) the element which fulfills the operation of limited difference; 2) the element which algebraic product (intensifier with controlled coefficient of transmission or multiplier of analog signals); 3) the element which fulfills a sample summarizing (uniting) of signals (including the one during normalizing). The basic element of pixel cells for the construction of hardware accelerators EM NM is a node on the current-reflecting mirrors (CM), which implements the operation of a limited difference (LD) of continuous logic (CL). Synthesized structures which realize on the basic of these elements the whole spectrum of required operations: t-norm, s-norm and new operations – “equivalence” are shown. These realizations on the basic of CMOS transistors current mirror represent the circuit with analog and time-pulse optical input signals. Possibilities of “equivalence” circuits synthesis by such functions limited difference cells are shown. Such circuits consist of several dozen CMOS transistors, have low power supply voltage (1.8…3.3V), the range of an input photocurrent is 0.1…24 μA, the transformation time is less than 1 μs, low power consumption (microwatts). The circuits and the simulation results of their design with OrCAD are shown.

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41

Shokouhifar, Mohammad, and Ali Jalali. "Automatic Simplified Symbolic Analysis of Analog Circuits Using Modified Nodal Analysis and Genetic Algorithm." Journal of Circuits, Systems and Computers 24, no. 04 (March 4, 2015): 1550056. http://dx.doi.org/10.1142/s0218126615500565.

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In this paper, a hybrid methodology based on modified nodal analysis (MNA) and genetic algorithm (GA) is presented for simplified symbolic small-signal analysis of analog circuits containing semiconductor devices like MOSFETs. At first, the circuit is analyzed by the MNA, and the derived exact continuous-time transfer function is automatically simplified via GA. We propose a new multi-objective criterion for symbolic simplification of continuous-time transfer functions, which can be performed by such optimization algorithms as local-search algorithms, heuristic algorithms, swarm-intelligence algorithms, etc. In this paper, GA is used to validate the proposed simplification criterion. All processes including netlist text pre-processing, symbolic analysis via MNA, post-processing, and simplification via GA are consecutively run in an m-file MATLAB program. The comparison of obtained numeric results with HSPICE demonstrates the efficiency of the proposed methodology.

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42

Durham, A. M., J. B. Hughes, and W. Redman-White. "Circuit architectures for high linearity monolithic continuous-time filtering." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 39, no. 9 (1992): 651–57. http://dx.doi.org/10.1109/82.193320.

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43

Kotaka, Kazuya, Takahiro Inoue, and Kyoko Tsukano. "Realization and Analysis of Integrated Chua-Type Continuous-Time Chaos Circuits." IEEJ Transactions on Fundamentals and Materials 117, no. 6 (1997): 651–52. http://dx.doi.org/10.1541/ieejfms1990.117.6_651.

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44

Karel, Joël M. H., Sandro A. P. Haddad, Senad Hiseni, Ronald L. Westra, Wouter A. Serdijn, and Ralf L. M. Peeters. "Implementing Wavelets in Continuous-Time Analog Circuits With Dynamic Range Optimization." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 2 (February 2012): 229–42. http://dx.doi.org/10.1109/tcsi.2011.2162381.

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45

Comer, David J., Donald T. Comer, Bryan K. Casper, and Darren S. Korth. "A low-frequency, continuous-time notch filter using Gm-C circuits." International Journal of Electronics 86, no. 11 (November 1999): 1349–57. http://dx.doi.org/10.1080/002072199132635.

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46

Loke, T., and J. B. Wang. "Efficient quantum circuits for continuous-time quantum walks on composite graphs." Journal of Physics A: Mathematical and Theoretical 50, no. 5 (January 6, 2017): 055303. http://dx.doi.org/10.1088/1751-8121/aa53a9.

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47

Cardelli, Luca, Mirco Tribastone, and Max Tschaikowski. "From electric circuits to chemical networks." Natural Computing 19, no. 1 (September 16, 2019): 237–48. http://dx.doi.org/10.1007/s11047-019-09761-7.

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Abstract Electric circuits manipulate electric charge and magnetic flux via a small set of discrete components to implement useful functionality over continuous time-varying signals represented by currents and voltages. Much of the same functionality is useful to biological organisms, where it is implemented by a completely different set of discrete components (typically proteins) and signal representations (typically via concentrations). We describe how to take a linear electric circuit and systematically convert it to a chemical reaction network of the same functionality, as a dynamical system. Both the structure and the components of the electric circuit are dissolved in the process, but the resulting chemical network is intelligible. This approach provides access to a large library of well-studied devices, from analog electronics, whose chemical network realization can be compared to natural biochemical networks, or used to engineer synthetic biochemical networks.

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48

Itoh, Makoto, and Leon O. Chua. "Parasitic Effects on Memristor Dynamics." International Journal of Bifurcation and Chaos 26, no. 06 (June 15, 2016): 1630014. http://dx.doi.org/10.1142/s0218127416300147.

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In this paper, we show that parasitic elements have a significant effect on the dynamics of memristor circuits. We first show that certain [Formula: see text]-terminal elements such as memristors, memcapacitors, and meminductors can be used as nonvolatile memories, if the principle of conservation of state variables hold by open-circuiting, or short-circuiting, their terminals. We also show that a passive memristor with a strictly-increasing constitutive relation will eventually lose its stored flux when we switch off the power if there is a parasitic capacitance across the memristor. Similarly, a memcapacitor (resp., meminductor) with a positive memcapacitance (resp., meminductance) will eventually lose their stored physical states when we switch off the power, if it is connected to a parasitic resistance. We then show that the discontinuous jump that circuit engineers assumed to occur at impasse points of memristor circuits contradicts the principles of conservation of charge and flux at the time of the discontinuous jump. A parasitic element can be used to break an impasse point, resulting in the emergence of a continuous oscillation in the circuit. We also define a distance, a diameter, and a dimension, for each circuit element in order to measure the complexity order of the parasitic elements. They can be used to find higher-order parasitic elements which can break impasse points. Furthermore, we derived a memristor-based Chua’s circuit from a three-element circuit containing a memristor by connecting two parasitic memcapacitances to break the impasse points. We finally show that a higher-order parasitic element can be used for breaking the impasse points on two-dimensional and three-dimensional constrained spaces.

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49

Deep, Akash, Mohammad Zoha, and Pompa Dutta Kukreja. "Prostacyclin as an Anticoagulant for Continuous Renal Replacement Therapy in Children." Blood Purification 43, no. 4 (2017): 279–89. http://dx.doi.org/10.1159/000452754.

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Effective delivery of continuous renal replacement therapy (CRRT) depends on the longevity of the filter and circuit used in the CRRT machine. Safe and effective anticoagulation is crucial for maintaining the patency of these circuits. In children, heparin and citrate are the commonly used anticoagulants but they are limited by serious side effects and thus calls for meticulous monitoring. In conditions where neither of these can be used, prostacyclin can be an effective alternative. Prostacyclin is a platelet inhibitor that can be safely used as an efficient anticoagulant in CRRT. When combined with heparin, it induces a heparin-sparing effect, which can reduce the dosage and side effects of heparin. Furthermore, there is no need for performing time-consuming monitoring tests. Although prostacyclin seems to be an attractive option, there is scanty evidence about its use as an anticoagulant in CRRT in children. We review the evidence and practicalities, and propose a guideline for the use of prostacyclin as an anticoagulant in children requiring CRRT.

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50

Ma, Guilei, Menghua Man, Yongqiang Zhang, and Shanghe Liu. "Electromagnetic Interference Effects of Continuous Waves on Memristors: A Simulation Study." Sensors 22, no. 15 (August 3, 2022): 5785. http://dx.doi.org/10.3390/s22155785.

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As two-terminal passive fundamental circuit elements with memory characteristics, memristors are promising devices for applications such as neuromorphic systems, in-memory computing, and tunable RF/microwave circuits. The increasingly complex electromagnetic interference (EMI) environment threatens the reliability of memristor systems. However, various EMI signals’ effects on memristors are still unclear. This paper selects continuous waves (CWs) as EMI signals. It provides a deeper insight into the interference effect of CWs on the memristor driven by a sinusoidal excitation voltage, as well as a method for investigating the EMI effect of memristors. The optimal memristor model is obtained by the exhaustive traversing of the possible model parameters, and the interference effect of CWs on memristors is quantified based on this model and the proposed evaluation metrics. Simulation results indicate that CW interference may affect the switching time, dynamic range, nonlinearity, symmetry, time to the boundary, and variation of memristance. The specific interference effect depends on the operating mode of the memristor, the amplitude, and the frequency of the CW. This research provides a foundation for evaluating EMI effects and designing electromagnetic protection for memristive neuromorphic systems.

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