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Статті в журналах з теми "Compact clock"

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Автор: Grafiati

Опубліковано: 14 березня 2023

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1

Khabarova, Ksenia, Denis Kryuchkov, Alexander Borisenko, Ilia Zalivako, Ilya Semerikov, Mikhail Aksenov, Ivan Sherstov, Timur Abbasov, Anton Tausenev, and Nikolay Kolachevsky. "Toward a New Generation of Compact Transportable Yb+ Optical Clocks." Symmetry 14, no. 10 (October 20, 2022): 2213. http://dx.doi.org/10.3390/sym14102213.

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Optical atomic clocks are currently one of the most sensitive tools making it possible to precisely test the fundamental symmetry properties of spacetime and Einstein’s theory of relativity. At the same time, the extremely high stability and accuracy of compact transportable optical clocks open new perspectives in important fields, such as satellite navigation, relativistic geodesy, and the global time and frequency network. Our project aimed to develop a compact transportable optical clock based on a single ytterbium ion. We present the first prototype of the Yb+ clock (298 kg in 1 m3) and present several solutions aimed to improve the clock’s robustness to approach the demands of a space-qualified system. We present spectroscopic studies of a 435.5 nm quadrupole clock transition with Fourier-limited spectra of 25 Hz. The estimated instability of the output frequency at 1 GHz, which was down-converted with an optical frequency comb (OFC), is at the level of 9×10−15/τ, and the long-term instability and inaccuracy are at the level of 5×10−16. As the next steps, we present a new design for the clock laser and the OFC.

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2

Gellesch, Markus, Jonathan Jones, Richard Barron, Alok Singh, Qiushuo Sun, Kai Bongs, and Yeshpal Singh. "Transportable optical atomic clocks for use in out-of-the-lab environments." Advanced Optical Technologies 9, no. 5 (November 26, 2020): 313–25. http://dx.doi.org/10.1515/aot-2020-0023.

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AbstractRecently, several reports with a strong focus on compact, nonstationary optical atomic clocks have been published, including accounts of in-field deployment of these devices for demonstrations of chronometric levelling in different types of environments. We review recent progress in this research area, comprising compact and transportable neutral atom and single-ion optical atomic clocks. The identified transportable optical clocks strive for low volume, weight and power consumption while exceeding standard microwave atomic clocks in fractional frequency instability and systematic uncertainty. Some transportable clock projects additionally address requirements for metrology or serve the joint technology development between industrial and academic stakeholders. Based on the reviewed reports on nonstationary optical atomic clocks, we suggest definitions for transportable, portable and mobile optical atomic clocks. We conclude our article with an overview of possible future directions for developments of optical clock technology.

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3

Liu, Xiaochi, Ning Ru, Junyi Duan, Peter Yun, Minghao Yao, and Jifeng Qu. "High-performance coherent population trapping clock based on laser-cooled atoms." Chinese Physics B 31, no. 4 (March 1, 2022): 043201. http://dx.doi.org/10.1088/1674-1056/ac2d21.

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We present a coherent population trapping clock system based on laser-cooled 87Rb atoms. The clock consists of a frequency-stabilized CPT interrogation laser and a cooling laser as well as a compact magneto-optical trap, a high-performance microwave synthesizer, and a signal detection system. The resonance signal in the continuous wave regime exhibits an absorption contrast of ∼ 50%. In the Ramsey interrogation method, the linewidth of the central fringe is 31.25 Hz. The system achieves fractional frequency stability of 2.4 × 10 − 11 / τ , which goes down to 1.8 × 10−13 at 20000 s. The results validate that cold atom interrogation can improve the long-term frequency stability of coherent population trapping clocks and holds the potential for developing compact/miniature cold atoms clocks.

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4

Yun, Peter, Sinda Mejri, Francois Tricot, Moustafa Abdel Hafiz, Rodolphe Boudot, Emeric de Clercq, and Stéphane Guérandel. "Double-modulation CPT cesium compact clock." Journal of Physics: Conference Series 723 (June 2016): 012012. http://dx.doi.org/10.1088/1742-6596/723/1/012012.

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5

Pechoneri, R. D., S. T. Müller, C. Bueno, V. S. Bagnato, and D. V. Magalhães. "Portable compact cold atoms clock topology." Journal of Physics: Conference Series 733 (July 2016): 012049. http://dx.doi.org/10.1088/1742-6596/733/1/012049.

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6

Ahmed, Mushtaq, Daniel V. Magalhães, Aida Bebeachibuli, Stella T. Müller, Renato F. Alves, Tiago A. Ortega, John Weiner, and Vanderlei S. Bagnato. "The Brazilian time and frequency atomic standards program." Anais da Academia Brasileira de Ciências 80, no. 2 (June 2008): 217–52. http://dx.doi.org/10.1590/s0001-37652008000200002.

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Cesium atomic beam clocks have been the workhorse for many demanding applications in science and technology for the past four decades. Tests of the fundamental laws of physics and the search for minute changes in fundamental constants, the synchronization of telecommunication networks, and realization of the satellite-based global positioning system would not be possible without atomic clocks. The adoption of optical cooling and trapping techniques, has produced a major advance in atomic clock precision. Cold-atom fountain and compact cold-atom clocks have also been developed. Measurement precision of a few parts in 10(15) has been demonstrated for a cold-atom fountain clock. We present here an overview of the time and frequency metrology program based on cesium atoms under development at USP São Carlos. This activity consists of construction and characterization of atomic-beam, and several variations of cold-atom clocks. We discuss the basic working principles, construction, evaluation, and important applications of atomic clocks in the Brazilian program.

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7

LUO, ZHIHONG, YEUNG ON AU, BENJAMIN LAU, and HENRY LAW. "A 0.0052 mm2 COMPACT DIGITAL PLL IN 65 nm CMOS." Journal of Circuits, Systems and Computers 21, no. 08 (December 2012): 1240026. http://dx.doi.org/10.1142/s0218126612400269.

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A novel structure of digital phase locked loop (PLL) is presented in this paper. It uses digitally controlled oscillator (DCO) to generate the clock. At the beginning of each reference clock cycle, the DCO is fully reset and restarts to oscillate to prevent the long term jitter accumulation and increase the loop stability. It uses three types of digital delay control methods, including delay cell number adjust, delay cell load adjust and in cycle load adjust to digitally control the DCO output clock frequency, in order to get wider frequency range and smaller jitter. This digital PLL uses NAND gate as the basic delay cell of ring oscillator, which can completely reset DCO in a very short time. It uses binary search to achieve fast lock and uses shift chain to get better input clock jitter tolerance. This digital PLL has been silicon validated in GLOBALFOUNDRIES 65 nm Generic process. Its chip area is only 0.0052 mm2. In typical condition, DCO's frequency has a wide range between 550 MHz and 2.45 GHz. Its total power is around 1.4 mW when DCO's frequency is 1.8 GHz. This PLL can be locked very fast in 25 divided reference clock cycles, and its output clock jitter is around 18 ps.

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8

Gubin, M. A., A. N. Kireev, A. V. Konyashchenko, P. G. Kryukov, A. V. Tausenev, D. A. Tyurikov, and A. S. Shelkovnikov. "Realisation of a compact methane optical clock." Quantum Electronics 38, no. 7 (July 31, 2008): 613–14. http://dx.doi.org/10.1070/qe2008v038n07abeh013914.

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9

Kim, Seungjun, Junghoon Jin, and Jongsun Kim. "A Cost-Effective and Compact All-Digital Dual-Loop Jitter Attenuator for Built-Off-Test Applications." Electronics 11, no. 21 (November 7, 2022): 3630. http://dx.doi.org/10.3390/electronics11213630.

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Анотація:

A compact and low-power all-digital CMOS dual-loop jitter attenuator (DJA) for low-cost built-off-test (BOT) applications such as parallel multi-DUT testing is presented. The proposed DJA adopts a new digital phase interpolator (PI)-based clock recovery (CR) loop with an adaptive decimation filter (ADF) function to remove the jitter and phase noise of the input clock, and generate a phase-aligned clean output clock. In addition, by adopting an all-digital multi-phase multiplying delay-locked loop (MDLL), eight low-jitter evenly spaced reference clocks that are required for the PI are generated. In the proposed DJA, both the MDLL and PI-based CR are first-order systems, and so this DJA has the advantage of high system stability. In addition, the proposed DJA has the benefit of a wide operating frequency range, unlike general PLL-based jitter attenuators that have a narrow frequency range and a jitter peaking problem. Implemented in a 40 nm 0.9 V CMOS process, the proposed DJA generates cleaned programmable output clock frequencies from 2.4 to 4.7 GHz. Furthermore, it achieves a peak-to-peak and RMS jitter attenuation of –25.6 dB and –32.6 dB, respectively, at 2.4 GHz. In addition, it occupies an active area of only 0.0257 mm2 and consumes a power of 7.41 mW at 2.4 GHz.

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10

Hoang, Anh The, Ziyu Shen, Kuangchao Wu, An Ning, and Wenbin Shen. "Test of Determining Geopotential Difference between Two Sites at Wuhan Based on Optical Clocks’ Frequency Comparisons." Remote Sensing 14, no. 19 (September 28, 2022): 4850. http://dx.doi.org/10.3390/rs14194850.

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Applications of optical clocks in physical geodesy for determining geopotential are of increasing interest to scientists as the accuracy of optical clocks improves and the clock size becomes more and more compact. In this study, we propose a data processing method using the ensemble empirical mode decomposition technique to determine the geopotential difference between two sites in Wuhan based on the frequency comparison of two optical clocks. We use the frequency comparison record data of two Ca+ optical clocks based on the optical fiber frequency transfer method, provided by the Innovation Academy for Precision Measurement Science and Technology, Chinese Academy of Sciences (Wuhan, China). By optical clock comparisons we obtained a geopotential difference of 42.50 ± 1.03 m2∙s−2 (equivalent to height difference of 4.33 ± 0.11 m) between the two sites, which is excellent compared to the geopotential difference of 42.56 ± 0.29 m2∙s−2 (equivalent to height difference of 4.34 ± 0.03 m) measured by a spirit leveling. The results show that the optical fiber frequency transfer method is promising in determining the geopotential and potential for unifying the world height system.

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11

Kitching, J., L. Hollberg, S. Knappe, and R. Wynands. "Compact atomic clock based on coherent population trapping." Electronics Letters 37, no. 24 (2001): 1449. http://dx.doi.org/10.1049/el:20010959.

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12

Esnault, F. X., N. Rossetto, D. Holleville, J. Delporte, and N. Dimarcq. "HORACE: A compact cold atom clock for Galileo." Advances in Space Research 47, no. 5 (March 2011): 854–58. http://dx.doi.org/10.1016/j.asr.2010.12.012.

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13

Danet, Jean-Marie, Olga Kozlova, Peter Yun, Stéphane Guérande, and Emeric de Clercq. "Compact atomic clock prototype based on coherent population trapping." EPJ Web of Conferences 77 (2014): 00017. http://dx.doi.org/10.1051/epjconf/20147700017.

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14

Sivak, A. V., and S. A. Zibrov. "Development of the quantum discriminator for compact atomic clock." Bulletin of the Lebedev Physics Institute 38, no. 5 (May 2011): 131–36. http://dx.doi.org/10.3103/s1068335611050034.

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15

Elvin, Rachel, Michael W. Wright, Ben Lewis, Brendan L. Keliehor, Alan Bregazzi, James P. McGilligan, Aidan S. Arnold, Paul F. Griffin, and Erling Riis. "Towards a compact, optically interrogated, cold-atom microwave clock." Advanced Optical Technologies 9, no. 5 (November 26, 2020): 297–303. http://dx.doi.org/10.1515/aot-2020-0022.

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AbstractA compact platform for cold atoms opens a range of exciting possibilities for portable, robust and accessible quantum sensors. In this work, we report on the development of a cold-atom microwave clock in a small package. Our work utilises the grating magneto-optical trap and high-contrast coherent population trapping in the lin$\perp $lin polarisation scheme. We optically probe the atomic ground-state splitting of cold 87Rb atoms using a Ramsey-like sequence whilst the atoms are in free-fall. We have measured a short-term fractional frequency stability of $5{\times}{10}^{-11}/\sqrt{\tau }$ with a projected quantum projection noise limit at the ${10}^{-13}/\sqrt{\tau }$ level.

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16

Malav, Praveen, Bhushan Patil, and Rabinder Henry. "Compact CPLD Board Designing and Implemented for Digital Clock." International Journal of Computer Applications 3, no. 11 (July 10, 2010): 7–10. http://dx.doi.org/10.5120/783-1108.

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17

Rong, Wei, Qian Yong, Zhang Yu, and Wang Yu-Zhu. "Proposal of a Novel Compact Cold Atomic Fountain Clock." Chinese Physics Letters 21, no. 1 (January 2004): 57–60. http://dx.doi.org/10.1088/0256-307x/21/1/017.

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18

Ju, Bowen, Peter Yun, Qiang Hao, Shuai Nie, and Guobin Liu. "A low phase and amplitude noise microwave source for vapor cell atomic clocks." Review of Scientific Instruments 93, no. 10 (October 1, 2022): 104709. http://dx.doi.org/10.1063/5.0096589.

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A low-noise microwave source plays a key role in high-performance passive atomic clocks. Here, we propose and implement a microwave frequency synthesizer featuring a low phase and amplitude noise. With the help of a high-Q factor surface acoustic wave band-pass filter, we generate a microwave with targeted frequency by frequency multiplication of a low noise local oscillator at a radio frequency with the closest integer. At the frequency offset of 1 Hz, 10 Hz, 100 Hz, 1 kHz, and 10 kHz, the absolute phase noise of the output 3.417 GHz signal is −53.0, −83.3, −107.7, −119.2, and −124.0 dBc/Hz, respectively. After the microwave-to-optical conversion, the expected intermodulation effect contribution to the frequency stability of the coherent population trapping (CPT) atomic clock is 5.95 × 10−14 at an averaging time of 1 s. Meanwhile, with a feature of low fluctuation of this chain’s output microwave power at the level of 1.19 × 10−5 W at 1 s, its contribution to the frequency stability of the CPT atomic clock is 7.85 × 10−14 at the 1 s integration time. Our simple and low noise microwave chain is an ideal microwave source for high-performance, compact CPT clocks and could also be applied to cold atom or ion based microwave clocks.

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19

Zarschizky, H., CH Gerndt, M. Honsberg, H. W. Schneider, and A. Stemmer. "Optical clock distribution with a compact free space interconnect system." Optical and Quantum Electronics 26, no. 5 (May 1994): S471—S481. http://dx.doi.org/10.1007/bf00306218.

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20

Phelps, Gretchen, Nathan Lemke, Christopher Erickson, John Burke, and Kyle Martin. "Compact Optical Clock with 5×10−13Instability at 1 s." Navigation 65, no. 1 (March 2018): 49–54. http://dx.doi.org/10.1002/navi.215.

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21

Premananda, B. S., T. N. Dhanush, and Vaishnavi S. Parashar. "Area and Energy Efficient QCA Based Compact Serial Concatenated Convolutional Code Encoder." Journal of Physics: Conference Series 2161, no. 1 (January 1, 2022): 012025. http://dx.doi.org/10.1088/1742-6596/2161/1/012025.

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Abstract Quantum-dot Cellular Automata (QCA) is a transistor-less technology known for its low power consumption and higher clock rate. Serial Concatenated Convolutional Coding (SCCC) encoder is a class of forward error correction. This paper picturizes the implementation of the outer encoder as a (7, 4, 1) Bose Chaudhary Hocquenghem encoder that serves the purpose of burst error correction, a pseudo-random inter-leaver used for permuting of systematic code words and finally the inner encoder which is used for the correction of random errors in QCA. Two different architectures of the SCCC encoder have been proposed and discussed in this study. In the proposed two architectures, the first based on external clock signals whereas the second based on internal clock generation. The sub-blocks outer encoder, pseudo-random inter-leaver and inner encoder of the SCCC encoder are optimized, implemented and simulated using QCADesigner and then integrated to design a compact SCCC encoder. The energy dissipation is computed using QCADesigner-E. The proposed SCCC encoder reduced the total area by 46% and energy dissipation by 50% when compared to the reference SCCC encoder. The proposed encoders are more efficient in terms of cell count, energy dissipation and area occupancy respectively.

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22

Akanni, J., A. Abdulrasaq, A. A. Isa, and A. O. Ojo. "Development of a Compact and Accurate Auto-Update Digital Clock with Real-Time Location Display using Organic Light Emitting Diode and Crystal Oscillator." Journal of Applied Sciences and Environmental Management 26, no. 8 (August 31, 2022): 1391–96. http://dx.doi.org/10.4314/jasem.v26i8.11.

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Research has been going on for a lengthy time on digital clocks but with restraints to auto-updating based totally on location. The objective of the paper is to produce a portable and accurate auto-update digital watch (clock) that shows the real time and the current location of the user with the aid of crystal oscillator to generate clock pulses which interfaced with the GPS modules with organic light-emitting diode (OELD). The system was able to automatically update the co-ordinate of locations whenever the user moves from one place to another, It also auto-update time whenever the battery is removed and reinserted or when switched OFF and then switch ON after sometime. It also eliminate the stretch associated with time adjustment whenever the battery is down and replaced or when the watch is switched OFF and then ON. It performed satisfactorily and as a result, the system can be adapted and integrated to the new technology of modern watch as it can be adopted by the user to locate his/her position at any point in time.

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23

Pyrgas, Lampros, and Paris Kitsos. "Compact Hardware Architectures of Enocoro-128v2 Stream Cipher for Constrained Embedded Devices." Electronics 9, no. 9 (September 14, 2020): 1505. http://dx.doi.org/10.3390/electronics9091505.

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Lightweight cryptography is a vital and fast growing field in today’s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices.

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24

TAM, WING-SHAN, OI-YING WONG, KA-YAN MOK, CHI-WAH KOK, and HEI WONG. "AN ENERGY EFFICIENT HALF-STATIC CLOCK-GATING D-TYPE FLIP-FLOP." Journal of Circuits, Systems and Computers 19, no. 03 (May 2010): 635–54. http://dx.doi.org/10.1142/s0218126610006335.

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This paper presents a new design of half-static clock-gating D-type flip-flop (DFF). The proposed DFF consists of a dynamic master and a half-static slave built with a pass-transistor clock-gating circuitry. The new circuit has a very compact size, and can achieve low-power dissipation, especially in the case of low data activity. SPICE simulation results of the proposed DFF implemented with 0.18 μm CMOS technology are presented, which shows that the overall performance of the present design is better than most of the DFFs reported in literatures.

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25

Lee, Sangmin, Gyeong Won Choi, Hyun-Gue Hong, Taeg Yong Kwon, Sang-Bum Lee, Myoung-Sun Heo, and Sang Eon Park. "A compact cold-atom clock based on a loop-gap cavity." Applied Physics Letters 119, no. 6 (August 9, 2021): 064002. http://dx.doi.org/10.1063/5.0057150.

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26

Lacroûte, Clément, Maël Souidi, Pierre-Yves Bourgeois, Jacques Millo, Khaldoun Saleh, Emmanuel Bigler, Rodolphe Boudot, Vincent Giordano, and Yann Kersalé. "Compact Yb+optical atomic clock project: design principle and current status." Journal of Physics: Conference Series 723 (June 2016): 012025. http://dx.doi.org/10.1088/1742-6596/723/1/012025.

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27

Benedick, Andrew, Dmitry Tyurikov, Mikhail Gubin, Ruth Shewmon, Issac Chuang, and Franz X. Kärtner. "Compact, Ti:sapphire-based, methane-stabilized optical molecular frequency comb and clock." Optics Letters 34, no. 14 (July 10, 2009): 2168. http://dx.doi.org/10.1364/ol.34.002168.

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28

Santa, Fernando Martínez, Edwar Jacinto, and Holman Montie. "Hardware description of a simplified 4-bit softcore processor with BCD capabilities." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1570. http://dx.doi.org/10.11591/ijece.v10i2.pp1570-1576.

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The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.

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29

Silva, A., J. Dias, J. Santos, F. da Silva, and B. Gonçalves. "FM-CW compact reflectometer using DDS signal generation." Journal of Instrumentation 16, no. 11 (November 1, 2021): C11005. http://dx.doi.org/10.1088/1748-0221/16/11/c11005.

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Abstract A prototype of a compact coherent fast frequency sweeping RF back-end is being developed at IPFN-IST using commercial Monolithic Microwave Integrated Circuits (MMIC). On this work we present the usability of this concept of compact reflectometry associated with a Direct Digital Synthesis (DDS) source. Flexibility is one of the design goals for the back-end prototype, so that it can easily match the required frequency range. The backend alone covers the NATO J-band (10 GHz to 20 GHz) and is designed to drive external full band frequency multipliers, resulting in an ultra-wideband coverage of up to 140 GHz. FM-CW radar precision is strongly dependent on the probing source linearity. DDS nowadays plays an important role in signal generation in many fields of applications for communication systems as well as in radar technology. Modern DDSs are fully integrated, low-cost, single chip solutions that only need an external clock source for generating sinusoidal output signals up to several gigahertz. The DDS benefits from the totally digital generation of the output signal, which allows full control of the signal’s frequency and phase, both with very high precision and resolution. Recent implementations feature automatic sweeping capability, thus allowing the DDS to generate very linear and agile frequency chirps, assuming a high quality and constant frequency reference clock source. We propose to implement a DDS signal generation solution with the capability of a full band sweep in 1 μs. On the receiver side the IF and reference signals will be digitised allowing the use of high flexible data processing techniques. Input/output signals will allow the synchronisation of several systems.

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30

Semerikov, I. A., I. V. Zalivako, A. S. Borisenko, M. D. Aksenov, P. A. Vishnyakov, P. L. Sidorov, N. N. Kolachevskii, and K. Yu Khabarova. "Three-Dimensional Paul Trap with High Secular Frequency for Compact Optical Clock." Bulletin of the Lebedev Physics Institute 46, no. 9 (September 2019): 297–300. http://dx.doi.org/10.3103/s1068335619090070.

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31

Han, Min, and Wenbin Dou. "Compact Clock-Shaped Broadband Circularly Polarized Antenna Based on Characteristic Mode Analysis." IEEE Access 7 (2019): 159952–59. http://dx.doi.org/10.1109/access.2019.2951371.

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32

Ivanov, Anton E., Christoph Affolderbach, Gaetano Mileti, and Anja K. Skrivervik. "Design of atomic clock cavity based on a loop-gap geometry and modified boundary conditions." International Journal of Microwave and Wireless Technologies 9, no. 7 (June 27, 2017): 1373–86. http://dx.doi.org/10.1017/s1759078717000691.

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In this study, we investigate a concept that can be used to improve the magnetic field homogeneity in a microwave cavity applied in a novel, high-performance atomic frequency standard. We show that by modifying the boundary conditions in the case of a loop-gap geometry, a good improvement of the field homogeneity can be obtained. Such a design demonstrates high potential to improve the frequency stability; it is compact and hence suitable for a future generation of compact, high-precision frequency standards based on vapor cells and a pulsed optical pumping (POP) regime (POP atomic clocks).

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33

Yu, Zhijian, Zhijing Du, Yanyan Liu, Kemu Wang, Wenxiang Xue, and Shougang Zhang. "A Compact Laser System for the Pulsed Optically Pumped Rubidium Cell Atomic Clock." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 69, no. 3 (March 2022): 1137–46. http://dx.doi.org/10.1109/tuffc.2022.3140244.

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34

Schwarz, Roman, Sören Dörscher, Ali Al-Masoudi, Stefan Vogt, Ye Li, and Christian Lisdat. "A compact and robust cooling laser system for an optical strontium lattice clock." Review of Scientific Instruments 90, no. 2 (February 2019): 023109. http://dx.doi.org/10.1063/1.5063552.

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35

Jang, Jinwook, Olivier Franza, and Wayne Burleson. "Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 1 (January 2012): 66–79. http://dx.doi.org/10.1109/tvlsi.2010.2089706.

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36

Hoppner, Sebastian, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, and René Schuffny. "A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 3 (March 2013): 566–70. http://dx.doi.org/10.1109/tvlsi.2012.2187224.

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37

Xie, Tianjiao, Bo Li, Mao Yang, and Zhongjiang Yan. "Memory Compact High-Speed QC-LDPC Decoder Based on FPGA." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 37, no. 3 (June 2019): 515–22. http://dx.doi.org/10.1051/jnwpu/20193730515.

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In this paper, two compact memory strategies for partially parallel QC-LDPC decoder architecture are proposed. By compacting several adjacent rows hard decisions and extrinsic messages into one memory entry, which not only reduces the number of memory banks for hard decisions, but also facilitates multiple data accesses per clock cycle so as to increase the throughput of decoder. We demonstrate significant high speed and area efficient benefits of using the proposed techniques with an FPGA implementation of a CCSDS LDPC decoder on Xilinx XC5VLX330 device. The result shows that our new decoder can operate at a maximum frequency of 250 MHz after place and route, and achieve a throughput up to 2 Gb/s at 14 iterations.

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38

Sprenger, Alexander, and Sybille Hellebrand. "Divide and Compact — Stochastic Space Compaction for Faster-than-at-Speed Test." Journal of Circuits, Systems and Computers 28, supp01 (December 1, 2019): 1940001. http://dx.doi.org/10.1142/s0218126619400012.

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With shrinking feature sizes detecting small delay faults is getting more and more important. But not all small delay faults are detectable during at-speed test. By overclocking the circuit with several different test frequencies faster-than-at-speed test (FAST) is able to detect these hidden delay faults. If the clock frequency is increased, some outputs of the circuit may not have stabilized yet, and these outputs have to be considered as unknown ([Formula: see text]-values). These [Formula: see text]-values impede the test response compaction. In addition, the number and distribution of the [Formula: see text]-values vary with the clock frequency, and thus a very flexible [Formula: see text]-handling is needed for FAST. Most of the state-of-the-art solutions are not designed for these varying [Formula: see text]-profiles. Yet, the stochastic compactor by Mitra et al. can be adjusted to changing environments. It is easily programmable because it is controlled by weighted pseudo-random signals. But an optimal setup cannot be guaranteed in a FAST scenario. By partitioning the compactor into several smaller ones and a proper mapping of the scan outputs to the compactor inputs, the compactor can be better adapted to the varying [Formula: see text]-profiles. Finding the best setup can be formulated as a set partitioning problem. To solve this problem, several algorithms are presented. Experimental results show that independent from the scan chain configuration, the number of [Formula: see text]-values can be reduced significantly while the fault efficiency can be maintained. Additionally, it is shown that [Formula: see text]-reduction and fault efficiency can be adapted to user-defined goals.

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39

Ouyang, Xin-Chuan, Bo-Wen Yang, Jian-Liao Deng, Jin-Yin Wan, Ling Xiao, Hang-Hang Qi, Qing-Qing Hu, and Hua-Dong Cheng. "An effective pumping method for increasing atomic utilization in a compact cold atom clock*." Chinese Physics B 30, no. 8 (July 1, 2021): 083202. http://dx.doi.org/10.1088/1674-1056/abfccd.

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40

Boudot, Rodolphe, Xiaochi Liu, Philippe Abbe, Ravinder Chutani, Nicolas Passilly, Serge Galliou, Christophe Gorecki, and Vincent Giordano. "A high-performance frequency stability compact CPT clock based on a Cs-Ne microcell." IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 59, no. 11 (November 2012): 2584–87. http://dx.doi.org/10.1109/tuffc.2012.2493.

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41

Bakopoulos, P., D. Tsiokos, O. Zouraraki, H. Avramopoulos, G. Maxwell, and A. Poustie. "Compact all-optical packet clock and data recovery circuit using generic integrated MZI switches." Optics Express 13, no. 17 (2005): 6401. http://dx.doi.org/10.1364/opex.13.006401.

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42

Park, Sungkyung, and Chester Sungchung Park. "High-Speed CMOS Frequency Dividers with Symmetric In-Phase and Quadrature Waveforms." Journal of Circuits, Systems and Computers 25, no. 10 (July 22, 2016): 1630006. http://dx.doi.org/10.1142/s0218126616300063.

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Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.

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43

Cao, Jian, Jinbo Yuan, Shaomao Wang, Ping Zhang, Yi Yuan, Daoxin Liu, Kaifeng Cui, et al. "A compact, transportable optical clock with 1×10−17 uncertainty and its absolute frequency measurement." Applied Physics Letters 120, no. 5 (January 31, 2022): 054003. http://dx.doi.org/10.1063/5.0079432.

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44

Shang, Haosen, Tongyun Zhang, Jianxiang Miao, Tiantian Shi, Duo Pan, Xingwen Zhao, Qiang Wei, Lin Yang, and Jingbiao Chen. "Laser with 10−13 short-term instability for compact optically pumped cesium beam atomic clock." Optics Express 28, no. 5 (February 24, 2020): 6868. http://dx.doi.org/10.1364/oe.381147.

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45

Cappellini, G., P. Lombardi, M. Mancini, G. Pagano, M. Pizzocaro, L. Fallani, and J. Catani. "A compact ultranarrow high-power laser system for experiments with 578 nm ytterbium clock transition." Review of Scientific Instruments 86, no. 7 (July 2015): 073111. http://dx.doi.org/10.1063/1.4927165.

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46

Shang, Junjuan, Jian Cao, Kaifeng Cui, Shaomao Wang, Ping Zhang, Jinbo Yuan, Sijia Chao, Hualin Shu, and Xueren Huang. "A compact, sub-Hertz linewidth 729 nm laser for a miniaturized 40 Ca + optical clock." Optics Communications 382 (January 2017): 410–14. http://dx.doi.org/10.1016/j.optcom.2016.08.027.

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47

Pagnacco, Maja C., Jelena P. Maksimović, Marko Daković, Bojana Bokic, Sébastien R. Mouchet, Thierry Verbiest, Yves Caudano, and Branko Kolaric. "Spontaneous Symmetry Breaking: The Case of Crazy Clock and Beyond." Symmetry 14, no. 2 (February 19, 2022): 413. http://dx.doi.org/10.3390/sym14020413.

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In this work, we describe the crazy-clock phenomenon involving the state I (low iodide and iodine concentration) to state II (high iodide and iodine concentration with new iodine phase) transition after a Briggs–Rauscher (BR) oscillatory process. While the BR crazy-clock phenomenon is known, this is the first time that crazy-clock behavior is linked and explained with the symmetry-breaking phenomenon, highlighting the entire process in a novel way. The presented phenomenon has been thoroughly investigated by running more than 60 experiments, and evaluated by using statistical cluster K-means analysis. The mixing rate, as well as the magnetic bar shape and dimensions, have a strong influence on the transition appearance. Although the transition for both mixing and no-mixing conditions are taking place completely randomly, by using statistical cluster analysis we obtain different numbers of clusters (showing the time-domains where the transition is more likely to occur). In the case of stirring, clusters are more compact and separated, revealed new hidden details regarding the chemical dynamics of nonlinear processes. The significance of the presented results is beyond oscillatory reaction kinetics since the described example belongs to the small class of chemical systems that shows intrinsic randomness in their response and it might be considered as a real example of a classical liquid random number generator.

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48

Kwon, Hyeokdong, Young Beom Kim, Seog Chung Seo, and Hwajeong Seo. "High-Speed Implementation of PRESENT on AVR Microcontroller." Mathematics 9, no. 4 (February 13, 2021): 374. http://dx.doi.org/10.3390/math9040374.

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We propose the compact PRESENT on embedded processors. To obtain high-performance, PRESENT operations, including an add-round-key, a substitute layer and permutation layer operations are efficiently implemented on target embedded processors. Novel PRESENT implementations support the Electronic Code Book (ECB) and Counter (CTR). The implementation of CTR is improved by using the pre-computation for one substitute layer, two diffusion layer, and two add-round-key operations. Finally, compact PRESENT on target microcontrollers achieved 504.2, 488.2, 488.7, and 491.6 clock cycles per byte for PRESENT-ECB, 16-bit PRESENT-CTR (RAM-based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively. Compared with former implementation, the execution timing is improved by 62.6%, 63.8%, 63.7%, and 63.5% for PRESENT-ECB, 16-bit PRESENT-CTR (RAM based implementation), 16-bit PRESENT-CTR (ROM-based implementation), and 32-bit PRESENT-CTR (ROM-based implementation) modes of operation, respectively.

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49

Tan, Yung Sern, Kiat Seng Yeo, Chirn Chye Boon, and Manh Anh Do. "A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector." IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 6 (June 2012): 1156–67. http://dx.doi.org/10.1109/tcsi.2011.2173387.

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50

Ozalevli, Erhan. "A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24, no. 9 (September 2016): 2960–69. http://dx.doi.org/10.1109/tvlsi.2016.2541166.

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