Статті в журналах з теми "Coarse Grained Reconfigurable arrays"
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Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis, and Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays." Microprocessors and Microsystems 33, no. 2 (March 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.
Повний текст джерелаTheocharis, Panagiotis, and Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays." ACM Transactions on Architecture and Code Optimization 13, no. 2 (June 27, 2016): 1–26. http://dx.doi.org/10.1145/2893475.
Повний текст джерелаAnsaloni, Giovanni, Kazuyuki Tanimura, Laura Pozzi, and Nikil Dutt. "Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 12 (December 2012): 1803–16. http://dx.doi.org/10.1109/tcad.2012.2209886.
Повний текст джерелаEgger, Bernhard, Eunjin Song, Hochan Lee, and Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs." ACM SIGPLAN Notices 53, no. 6 (December 7, 2018): 76–88. http://dx.doi.org/10.1145/3299710.3211342.
Повний текст джерелаFilho, J. O., S. Masekowsky, T. Schweizer, and W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.
Повний текст джерелаDimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays." Journal of Supercomputing 48, no. 2 (May 16, 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.
Повний текст джерелаQu, Tongzhou, Zibin Dai, Yanjiang Liu, and Lin Chen. "A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays." Electronics 11, no. 19 (September 30, 2022): 3144. http://dx.doi.org/10.3390/electronics11193144.
Повний текст джерелаLopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.
Повний текст джерелаDe Sutter, Bjorn, Paul Coene, Tom Vander Aa, and Bingfeng Mei. "Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays." ACM SIGPLAN Notices 43, no. 7 (June 27, 2008): 151–60. http://dx.doi.org/10.1145/1379023.1375678.
Повний текст джерелаKissler, Dmitrij, Daniel Gran, Zoran Salcic, Frank Hannig, and Jürgen Teich. "Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays." IEEE Embedded Systems Letters 3, no. 2 (June 2011): 58–61. http://dx.doi.org/10.1109/les.2011.2124438.
Повний текст джерелаYang, Chen, Leibo Liu, Yansheng Wang, Shouyi Yin, Peng Cao, and Shaojun Wei. "Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array." Journal of Circuits, Systems and Computers 24, no. 03 (February 10, 2015): 1550043. http://dx.doi.org/10.1142/s0218126615500437.
Повний текст джерелаChoi, Kiyoung. "Coarse-Grained Reconfigurable Array: Architecture and Application Mapping." IPSJ Transactions on System LSI Design Methodology 4 (2011): 31–46. http://dx.doi.org/10.2197/ipsjtsldm.4.31.
Повний текст джерелаDöbrich, Stefan, and Christian Hochberger. "Low-Complexity Online Synthesis for AMIDAR Processors." International Journal of Reconfigurable Computing 2010 (2010): 1–15. http://dx.doi.org/10.1155/2010/953693.
Повний текст джерелаHartmann, Matthias, Vasileios (Vassilis) Pantazis, Tom Vander Aa, Mladen Berekovic, and Christian Hochberger. "Still Image Processing on Coarse-Grained Reconfigurable Array Architectures." Journal of Signal Processing Systems 60, no. 2 (December 11, 2008): 225–37. http://dx.doi.org/10.1007/s11265-008-0309-0.
Повний текст джерелаFerreira, Ricardo S., João M. P. Cardoso, Alex Damiany, Julio Vendramini, and Tiago Teixeira. "Fast placement and routing by extending coarse-grained reconfigurable arrays with Omega Networks." Journal of Systems Architecture 57, no. 8 (September 2011): 761–77. http://dx.doi.org/10.1016/j.sysarc.2011.03.006.
Повний текст джерелаZhou, Li, Dongpei Liu, Jianfeng Zhang, and Hengzhu Liu. "Application-specific coarse-grained reconfigurable array: architecture and design methodology." International Journal of Electronics 102, no. 6 (August 8, 2014): 897–910. http://dx.doi.org/10.1080/00207217.2014.942885.
Повний текст джерелаBae, Inpyo, Barend Harris, Hyemi Min, and Bernhard Egger. "Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 11 (November 2018): 2301–10. http://dx.doi.org/10.1109/tcad.2018.2857278.
Повний текст джерелаVranjković, Vuk S., Rastislav J. R. Struharik, and Ladislav A. Novak. "Reconfigurable Hardware for Machine Learning Applications." Journal of Circuits, Systems and Computers 24, no. 05 (April 8, 2015): 1550064. http://dx.doi.org/10.1142/s0218126615500644.
Повний текст джерелаMunaf, S., Dr A. Bharathi, and Dr A. N. Jayanthi. "Double Pumping Low Power Technique for Coarse - Grained Reconfigurable Architecture." International Journal of Electrical and Electronics Research 4, no. 1 (March 31, 2016): 10–15. http://dx.doi.org/10.37391/ijeer.040103.
Повний текст джерелаHannig, Frank, Hritam Dutta, and Jurgen Teich. "Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology." International Journal of Embedded Systems 2, no. 1/2 (2006): 114. http://dx.doi.org/10.1504/ijes.2006.010170.
Повний текст джерелаKissler, Dmitrij, Frank Hannig, and Jürgen Teich. "Efficient Evaluation of Power/Area/Latency Design Trade-Offs for Coarse-Grained Reconfigurable Processor Arrays." Journal of Low Power Electronics 7, no. 1 (February 1, 2011): 29–40. http://dx.doi.org/10.1166/jolpe.2011.1114.
Повний текст джерелаKIM, YOONJIN. "POWER-EFFICIENT CONFIGURATION CACHE STRUCTURE FOR COARSE-GRAINED RECONFIGURABLE ARCHITECTURE." Journal of Circuits, Systems and Computers 22, no. 03 (March 2013): 1350001. http://dx.doi.org/10.1142/s0218126613500011.
Повний текст джерелаPatel, Kunjan, Séamas McGettrick, and C. J. Bleakley. "Rapid functional modelling and simulation of coarse grained reconfigurable array architectures." Journal of Systems Architecture 57, no. 4 (April 2011): 383–91. http://dx.doi.org/10.1016/j.sysarc.2011.02.006.
Повний текст джерелаQu, Tongzhou, Zibin Dai, Chen Lin, and Anqi Yin. "Adaptive loop pipeline control mechanism for Coarse-Grained Reconfigurable Block Cipher Array." Journal of Physics: Conference Series 1971, no. 1 (July 1, 2021): 012051. http://dx.doi.org/10.1088/1742-6596/1971/1/012051.
Повний текст джерелаYang, Chen, LeiBo Liu, ShouYi Yin, and ShaoJun Wei. "Efficient and flexible memory architecture to alleviate data and context bandwidth bottlenecks of coarse-grained reconfigurable arrays." Science China Physics, Mechanics & Astronomy 57, no. 12 (October 21, 2014): 2214–27. http://dx.doi.org/10.1007/s11433-014-5610-2.
Повний текст джерелаRouson, Damian W. I., and Yi Xiong. "Design Metrics in Quantum Turbulence Simulations: How Physics Influences Software Architecture." Scientific Programming 12, no. 3 (2004): 185–96. http://dx.doi.org/10.1155/2004/910505.
Повний текст джерелаPatel, Kunjan, and Chris J. Bleakley. "Coarse Grained Reconfigurable Array Based Architecture for Low Power Real-Time Seizure Detection." Journal of Signal Processing Systems 82, no. 1 (March 7, 2015): 55–68. http://dx.doi.org/10.1007/s11265-015-0981-9.
Повний текст джерелаLiu, Leibo, Chen Yang, Shouyi Yin, and Shaojun Wei. "CDPM: Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained Reconfigurable Array Performance." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, no. 6 (June 2018): 1171–84. http://dx.doi.org/10.1109/tcad.2017.2748026.
Повний текст джерелаYang, Chen, Leibo Liu, Kai Luo, Shouyi Yin, and Shaojun Wei. "CIACP: A Correlation- and Iteration- Aware Cache Partitioning Mechanism to Improve Performance of Multiple Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Parallel and Distributed Systems 28, no. 1 (January 1, 2017): 29–43. http://dx.doi.org/10.1109/tpds.2016.2554278.
Повний текст джерелаWeinhardt, Markus, Mohamed Messelka, and Philipp Käsgen. "CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor." Electronics 10, no. 21 (October 23, 2021): 2590. http://dx.doi.org/10.3390/electronics10212590.
Повний текст джерелаLu, Yanan, Leibo Liu, Yangdong Deng, Jian Weng, Shouyi Yin, Yiyu Shi, and Shaojun Wei. "Triggered-Issuance and Triggered-Execution: A Control Paradigm to Minimize Pipeline Stalls in Distributed Controlled Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Parallel and Distributed Systems 29, no. 10 (October 1, 2018): 2360–72. http://dx.doi.org/10.1109/tpds.2018.2822708.
Повний текст джерелаLi, Zeyu, Junjie Wang, Zhao Huang, Nan Luo, and Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware." Applied Sciences 12, no. 13 (June 29, 2022): 6601. http://dx.doi.org/10.3390/app12136601.
Повний текст джерелаMehta, Dinesh P., Carl Shetters, and Donald W. Bouldin. "Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on an Array of Reconfigurable FPGAs." VLSI Design 2013 (December 25, 2013): 1–13. http://dx.doi.org/10.1155/2013/249592.
Повний текст джерелаLiu, LeiBo, YanSheng Wang, ShouYi Yin, Min Zhu, Xing Wang, and ShaoJun Wei. "Row-based configuration mechanism for a 2-D processing element array in coarse-grained reconfigurable architecture." Science China Information Sciences 57, no. 10 (September 6, 2014): 1–18. http://dx.doi.org/10.1007/s11432-013-4973-8.
Повний текст джерелаMudza, Zbigniew, and Rafał Kiełbik. "Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions." Electronics 11, no. 8 (April 16, 2022): 1261. http://dx.doi.org/10.3390/electronics11081261.
Повний текст джерелаHo, H., V. Szwarc, and T. Kwasniewski. "A Reconfigurable Systolic Array Architecture for Multicarrier Wireless and Multirate Applications." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/529512.
Повний текст джерелаZhao, Zhongyuan, Weiguang Sheng, Jinchao Li, Pengfei Ye, Qin Wang, and Zhigang Mao. "Similarity-Aware Architecture/Compiler Co-Designed Context-Reduction Framework for Modulo-Scheduled CGRA." Electronics 10, no. 18 (September 9, 2021): 2210. http://dx.doi.org/10.3390/electronics10182210.
Повний текст джерелаTehre, Vaishali, and Ravindra Kshirsagar. "Survey on Coarse Grained Reconfigurable Architectures." International Journal of Computer Applications 48, no. 16 (June 30, 2012): 1–7. http://dx.doi.org/10.5120/7429-0104.
Повний текст джерелаJong-eun Lee, Kiyoung Choi, and N. D. Dutt. "Compilation approach for coarse-grained reconfigurable architectures." IEEE Design & Test of Computers 20, no. 1 (January 2003): 26–33. http://dx.doi.org/10.1109/mdt.2003.1173050.
Повний текст джерелаPaek, Jong Kyung, Kiyoung Choi, and Jongeun Lee. "Binary acceleration using coarse-grained reconfigurable architecture." ACM SIGARCH Computer Architecture News 38, no. 4 (September 14, 2010): 33–39. http://dx.doi.org/10.1145/1926367.1926374.
Повний текст джерелаAnsaloni, Giovanni, Paolo Bonzini, and Laura Pozzi. "EGRA: A Coarse Grained Reconfigurable Architectural Template." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, no. 6 (June 2011): 1062–74. http://dx.doi.org/10.1109/tvlsi.2010.2044667.
Повний текст джерелаWang, Xing, Lei Bo Liu, Shou Yi Yin, Min Zhu, and Shao Jun Wei. "H.264/AVC Intra Predictor on a Coarse-Grained Reconfigurable Multi-Media System." Advanced Materials Research 546-547 (July 2012): 469–74. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.469.
Повний текст джерелаYIN, Shouyi, Chongyong YIN, Leibo LIU, Min ZHU, and Shaojun WEI. "Configuration Context Reduction for Coarse-Grained Reconfigurable Architecture." IEICE Transactions on Information and Systems E95-D, no. 2 (2012): 335–44. http://dx.doi.org/10.1587/transinf.e95.d.335.
Повний текст джерелаWang, Chao, Peng Cao, and Jun Yang. "Efficient AES cipher on coarse-grained reconfigurable architecture." IEICE Electronics Express 14, no. 11 (2017): 20170449. http://dx.doi.org/10.1587/elex.14.20170449.
Повний текст джерелаHussain, Shaik Rizwan, and Jahangir Badashah Syed. "Design and Applications of Coarse-Grained Reconfigurable Architectures." International Journal of Scientific Research 2, no. 12 (June 1, 2012): 198–201. http://dx.doi.org/10.15373/22778179/dec2013/61.
Повний текст джерелаAtak, Oguzhan, and Abdullah Atalar. "BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 7 (July 2013): 1285–98. http://dx.doi.org/10.1109/tvlsi.2012.2207748.
Повний текст джерелаAkbari, Omid, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, and Muhammad Shafique. "Toward Approximate Computing for Coarse-Grained Reconfigurable Architectures." IEEE Micro 38, no. 6 (November 1, 2018): 63–72. http://dx.doi.org/10.1109/mm.2018.2873951.
Повний текст джерелаSim, Hyeonuk, Hongsik Lee, Seongseok Seo, and Jongeun Lee. "Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, no. 7 (July 2016): 1092–104. http://dx.doi.org/10.1109/tcad.2015.2504918.
Повний текст джерелаSeveso, Luigi, Dardo Goyeneche, and Karol Życzkowski. "Coarse-grained entanglement classification through orthogonal arrays." Journal of Mathematical Physics 59, no. 7 (July 2018): 072203. http://dx.doi.org/10.1063/1.5006890.
Повний текст джерелаKOJIMA, Takuya, and Hideharu AMANO. "A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures." IEICE Transactions on Information and Systems E102.D, no. 7 (July 1, 2019): 1247–56. http://dx.doi.org/10.1587/transinf.2018edp7336.
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