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Опубліковано: 6 вересня 2023

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Статті в журналах з теми "Coarse Grained Reconfigurable arrays"

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Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis, and Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays." Microprocessors and Microsystems 33, no. 2 (March 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.

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2

Theocharis, Panagiotis, and Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays." ACM Transactions on Architecture and Code Optimization 13, no. 2 (June 27, 2016): 1–26. http://dx.doi.org/10.1145/2893475.

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3

Ansaloni, Giovanni, Kazuyuki Tanimura, Laura Pozzi, and Nikil Dutt. "Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 12 (December 2012): 1803–16. http://dx.doi.org/10.1109/tcad.2012.2209886.

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4

Egger, Bernhard, Eunjin Song, Hochan Lee, and Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs." ACM SIGPLAN Notices 53, no. 6 (December 7, 2018): 76–88. http://dx.doi.org/10.1145/3299710.3211342.

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5

Filho, J. O., S. Masekowsky, T. Schweizer, and W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.

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Dimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays." Journal of Supercomputing 48, no. 2 (May 16, 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.

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7

Qu, Tongzhou, Zibin Dai, Yanjiang Liu, and Lin Chen. "A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays." Electronics 11, no. 19 (September 30, 2022): 3144. http://dx.doi.org/10.3390/electronics11193144.

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Анотація:
Shift transformations are the fundamental operation of cryptographic algorithms, and the arithmetic unit implementing different types of shift transformations are utilized in the coarse-grain reconfigurable cryptographic architectures (CGRCA) to meet the different cryptographic algorithms. In this paper, a reconfigurable shift transformation unit (RSTU) is proposed to meet the complicated shift requirement of CGRCA, which achieves high flexibility and a good cost–performance ratio. The mathematical properties of shift transformation are analyzed, and several theorems are introduced to design a reconfigurable shifter. Furthermore, the reconfigurable data path of the proposed unit is presented to implement the random combination of shift operations in different granularity, and configuration word and routing algorithms are proposed to generate control information for RSTU. Moreover, the control information generation module is designed to invert the configuration word into the control information, according to the routing algorithms. As a proof-of-concept, the proposed RSTU is built using the CMOS 65 nm technology. The experimental results show that RSTU supports more shift operations, increases 18.2% speed at most, and reduces 13% area occupation, compared to the existing shifters.
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8

Lopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.

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Анотація:
Reconfigurable computing architectures allow the adaptation of the underlying datapath to the algorithm. The granularity of the datapath elements and data width determines the granularity of the architecture and its programming flexibility. Coarse-grained architectures have shown the right balance between programmability and performance. This paper provides an overview of coarse-grained reconfigurable architectures and describes Versat, a Coarse-Grained Reconfigurable Array (CGRA) with self-generated partial reconfiguration, presented as a case study for better understanding these architectures. Unlike most of the existing approaches, which mainly use pre-compiled configurations, a Versat program can generate and apply myriads of on-the-fly configurations. Partial reconfiguration plays a central role in this approach, as it speeds up the generation of incrementally different configurations. The reconfigurable array has a complete graph topology, which yields unprecedented programmability, including assembly programming. Besides being useful for optimising programs, assembly programming is invaluable for working around post-silicon hardware, software, or compiler issues. Results on core area, frequency, power, and performance running different codes are presented and compared to other implementations.
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De Sutter, Bjorn, Paul Coene, Tom Vander Aa, and Bingfeng Mei. "Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays." ACM SIGPLAN Notices 43, no. 7 (June 27, 2008): 151–60. http://dx.doi.org/10.1145/1379023.1375678.

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Kissler, Dmitrij, Daniel Gran, Zoran Salcic, Frank Hannig, and Jürgen Teich. "Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays." IEEE Embedded Systems Letters 3, no. 2 (June 2011): 58–61. http://dx.doi.org/10.1109/les.2011.2124438.

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Дисертації з теми "Coarse Grained Reconfigurable arrays"

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Lee, Jong-Suk Mark. "FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/77094.

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High computing power and flexibility are important design factors for multimedia and wireless communication applications due to the demand for high quality services and frequent evolution of standards. The ASIC (Application Specific Integrated Circuit) approach provides an area efficient, high performance solution, but is inflexible. In contrast, the general purpose processor approach is flexible, but often fails to provide sufficient computing power. Reconfigurable architectures, which have been introduced as a compromise between the two extreme solutions, have been applied successfully for multimedia and wireless communication applications. In this thesis, we investigated a new coarse-grained reconfigurable architecture called FleXilicon which is designed to execute critical loops efficiently, and is embedded in an SOC with a host processor. FleXilicon improves resource utilization and achieves a high degree of loop level parallelism (LLP). The proposed architecture aims to mitigate major shortcomings with existing architectures through adoption of three schemes, (i) wider memory bandwidth, (ii) adoption of a reconfigurable controller, and (iii) flexible wordlength support. Increased memory bandwidth satisfies memory access requirement in LLP execution. New design of reconfigurable controller minimizes overhead in reconfiguration and improves area efficiency and reconfiguration overhead. Flexible word-length support improves LLP by increasing the number of processing elements executable. The simulation results indicate that FleXilicon reduces the number of clock cycles and increases the speed for all five applications simulated. The speedup ratios compared with conventional architectures are as large as two orders of magnitude for some applications. VLSI implementation of FleXilicon in 65 nm CMOS process indicates that the proposed architecture can operate at a high frequency up to 1 GHz with moderate silicon area.
Ph. D.
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Saraswat, Rohit. "A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/689.

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Scheduling, placement, and routing are important steps in Very Large Scale Integration (VLSI) design. Researchers have developed numerous techniques to solve placement and routing problems. As the complexity of Application Specific Integrated Circuits (ASICs) increased over the past decades, so did the demand for improved place and route techniques. The primary objective of these place and route approaches has typically been wirelength minimization due to its impact on signal delay and design performance. With the advent of Field Programmable Gate Arrays (FPGAs), the same place and route techniques were applied to FPGA-based design. However, traditional place and route techniques may not work for Coarse-Grained Reconfigurable Architectures (CGRAs), which are reconfigurable devices offering wider path widths than FPGAs and more flexibility than ASICs, due to the differences in architecture and routing network. Further, the routing network of several types of CGRAs, including the Field Programmable Object Array (FPOA), has deterministic timing as compared to the routing fabric of most ASICs and FPGAs reported in the literature. This necessitates a fresh look at alternative approaches to place and route designs. This dissertation presents a finite domain constraint-based, delay-aware placement and routing methodology targeting an FPOA. The proposed methodology takes advantage of the deterministic routing network of CGRAs to perform a delay aware placement.
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Das, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.

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La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion. Les accélérateurs programmables fournissent le bon compromis efficacité et flexibilité. Les architectures reconfigurables à gros grains (CGRA) sont composées d'éléments de calcul au niveau mot et constituent un choix prometteur d'accélérateurs programmables. Cette thèse propose d'exploiter le potentiel des architectures reconfigurables à gros grains et de pousser le matériel aux limites énergétiques dans un flot de conception complet. Les contributions de cette thèse sont une architecture de type CGRA, appelé IPA pour Integrated Programmable Array, sa mise en œuvre et son intégration dans un système sur puce, avec le flot de compilation associé qui permet d'exploiter les caractéristiques uniques du nouveau composant, notamment sa capacité à supporter du flot de contrôle. L'efficacité de l'approche est éprouvée à travers le déploiement de plusieurs applications de traitement intensif. L'accélérateur proposé est enfin intégré à PULP, a Parallel Ultra-Low-Power Processing-Platform, pour explorer le bénéfice de ce genre de plate-forme hétérogène ultra basse consommation
Emerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
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Dogan, Rabia. "System Level Exploration of RRAM for SRAM Replacement." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.

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Recently an effective usage of the chip area plays an essential role for System-on-Chip (SOC) designs. Nowadays on-chip memories take up more than 50%of the total die-area and are responsible for more than 40% of the total energy consumption. Cache memory alone occupies 30% of the on-chip area in the latest microprocessors. This thesis project “System Level Exploration of RRAM for SRAM Replacement” describes a Resistive Random Access Memory (RRAM) based memory organizationfor the Coarse Grained Reconfigurable Array (CGRA) processors. Thebenefit of the RRAM based memory organization, compared to the conventional Static-Random Access Memory (SRAM) based memory organization, is higher interms of energy and area requirement. Due to the ever-growing problems faced by conventional memories with Dynamic Voltage Scaling (DVS), emerging memory technologies gained more importance. RRAM is typically seen as a possible candidate to replace Non-volatilememory (NVM) as Flash approaches its scaling limits. The replacement of SRAMin the lowest layers of the memory hierarchies in embedded systems with RRAMis very attractive research topic; RRAM technology offers reduced energy and arearequirements, but it has limitations with regards to endurance and write latency. By reason of the technological limitations and restrictions to solve RRAM write related issues, it becomes beneficial to explore memory access schemes that tolerate the longer write times. Therefore, since RRAM write time cannot be reduced realistically speaking we have to derive instruction memory and data memory access schemes that tolerate the longer write times. We present an instruction memory access scheme to compromise with these problems. In addition to modified instruction memory architecture, we investigate the effect of the longer write times to the data memory. Experimental results provided show that the proposed architectural modifications can reduce read energy consumption by a significant frame without any performance penalty.
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Zain-ul-Abdin. "Programming of coarse-grained reconfigurable architectures." Doctoral thesis, Örebro universitet, Akademin för naturvetenskap och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-15246.

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Анотація:
Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet not only the increased computational demands of high-performance embedded systems, but also to fulfill the need of adaptability to functional requirements of the application. This thesis focuses on the programming aspects of such coarse-grained reconfigurable computing devices, including the relevant computation models that are capable of exposing different kinds of parallelism inherent in the application and the ability of these models to capture the adaptability requirements of the application. The thesis suggests the occam-pi language for programming of a broad class of coarse-grained reconfigurable architectures as an intermediate language; we call it intermediate, since we believe that the applicationprogramming is best done in a high-level domain-specific language. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessorcommunication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language, and backends were developed to target two different coarse-grained reconfigurable architectures. XPP and Ambric. The results on XPP reveal that the occam-pi based implementations produce comparable throughput to those of NML programs, while programming at a much higher level of abstraction than that of NML. Similarly the two occam-pi implementations of autofocus criterion calculation targeted to the Ambric platform outperform the CPU implementation by factors of 11-23. Thus, the results of the implemented case-studies suggest that the occam-pi language based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.
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Ul-Abdin, Zain. "Programming of Coarse-Grained Reconfigurable Architectures." Doctoral thesis, Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-15050.

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Анотація:
Coarse-grained reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet not only the increased computational demands of high-performance embedded systems, but also to fulfill the need of adaptability to functional requirements of the application. This thesis focuses on the programming aspects of such coarse-grained reconfigurable computing devices, including the relevant computation models that are capable of exposing different kinds of parallelism inherent in the application and the ability of these models to capture the adaptability requirements of the application. The thesis suggests the occam-pi language for programming of a broad class of coarse-grained reconfigurable architectures as an intermediate language; we call it intermediate, since we believe that the applicationprogramming is best done in a high-level domain-specific language. The salient properties of the occam-pi language are explicit concurrency with built-in mechanisms for interprocessorcommunication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the occam-pi language, and backends were developed to target two different coarse-grained reconfigurable architectures. XPP and Ambric. The results on XPP reveal that the occam-pi based implementations produce comparable throughput to those of NML programs, while programming at a much higher level of abstraction than that of NML. Similarly the two occam-pi implementations of autofocus criterion calculation targeted to the Ambric platform outperform the CPU implementation by factors of 11-23. Thus, the results of the implemented case-studies suggest that the occam-pi language based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits.
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7

Guo, Yuanqing. "Mapping applications to a coarse-grained reconfigurable architecture." Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/57121.

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8

Bag, Zeki Ozan. "Energy-Aware Coarse Grained Reconfigurable Architectures Using Dynamically Reconfigurable Isolation Cells." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-108217.

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This thesis presents a self adaptive power management system to improve energy efficiency of coarse-grained reconfigurable architectures (CGRAs). CGRAs can host multiple applications on a single platform. Moreover, a single application may have multiple versions which have different degree of parallelism (fully serial, partially serial, fully parallel etc.). Selection of the optimum application version depends on runtime conditions such as resource availability on the platform. A traditional worst case design to satisfy its specifications results in undesirable power efficiency. Existing solutions to this problem offer costly hardware to mainly employ dynamic voltage and frequency scaling (DVFS). We propose exploiting reconfiguration of available resources on CGRA. Our solution makes use of dynamically reconfigurable isolation cells (DRICs) instead of dedicated hardware. We also introduce autonomous parallelism, voltage and frequency selection (APVFS) to realize DVFS functionality and to select the optimum version. Three applications are used for simulations, namely; matrix multiplication, finite impulse response filter (FIR) and fast Fourier transform (FFT). Results show that up to 72 % and 55 % power and energy can be saved respectively. Synthesis of the fabric shows considerable reduction in area overheads compared to existing designs employing DVFS.
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Plessl, Christian [Verfasser]. "Hardware Virtualization on a Coarse-Grained Reconfigurable Processor / Christian Plessl." Aachen : Shaker, 2006. http://d-nb.info/1166513963/34.

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Yadav, Anil. "Exploration Of Energy And Area Efficient Techniques For Coarse-grained Reconfigurable Fabrics." Thesis, University of North Texas, 2011. https://digital.library.unt.edu/ark:/67531/metadc103413/.

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Coarse-grained fabrics are comprised of multi-bit configurable logic blocks and configurable interconnect. This work is focused on area and energy optimization techniques for coarse-grained reconfigurable fabric architectures. In this work, a variety of design techniques have been explored to improve the utilization of computational resources and increase energy savings. This includes splitting, folding, multi-level vertical interconnect. In addition to this, I have also studied fully connected homogeneous and heterogeneous architectures, and 3D architecture. I have also examined some of the hybrid strategies of computation unit’s arrangements. In order to perform energy and area analysis, I selected a set of signal and image processing benchmarks from MediaBench suite. I implemented various fabric architectures on 90nm ASIC process from Synopsys. Results show area improvement with energy savings as compared to baseline architecture.
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Книги з теми "Coarse Grained Reconfigurable arrays"

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1964-, Soudris Dimitrios, and Vassiliadis Stamatis, eds. Fine- and coarse-grain reconfigurable computing. [New York?]: Springer, 2007.

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2

Plessl, Christian. Hardware virtualization on a coarse-grained reconfigurable processor. Aachen: Shaker, 2006.

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3

Wijtvliet, Mark, Henk Corporaal, and Akash Kumar. Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79774-4.

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N, Mahapatra Rabi, ed. Design of low-power coarse-grained reconfigurable architectures. Boca Raton, FL: CRC Press, 2011.

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(Foreword), Y. Patt, J. Smith (Foreword), M. Valero (Foreword), Stamatis Vassiliadis (Editor), and Dimitrios Soudris (Editor), eds. Fine- and Coarse-Grain Reconfigurable Computing. Springer, 2007.

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6

Patt, Y., J. Smith, M. Valero, Dimitrios Soudris, and Stamatis Vassiliadis. Fine- and Coarse-Grain Reconfigurable Computing. Springer London, Limited, 2007.

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Patt, Y., J. Smith, M. Valero, Dimitrios Soudris, and Stamatis Vassiliadis. Fine- and Coarse-Grain Reconfigurable Computing. Springer Netherlands, 2014.

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8

Mahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Mahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2017.

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Mahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.

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Частини книг з теми "Coarse Grained Reconfigurable arrays"

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Sousa, Éricles, Frank Hannig, and Jürgen Teich. "Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays." In System Level Design from HW/SW to Memory for Embedded Systems, 218–29. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-90023-0_18.

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2

De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures." In Handbook of Signal Processing Systems, 553–92. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6859-2_18.

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De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures." In Handbook of Signal Processing Systems, 449–84. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6345-1_17.

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Sutter, Bjorn De, Praveen Raghavan, and Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures." In Handbook of Signal Processing Systems, 427–72. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91734-4_12.

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Kim, Yongjoo, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon, and Yunheung Paek. "Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays." In High Performance Embedded Architectures and Compilers, 171–85. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11515-8_14.

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Niedermeier, A., Jan Kuper, and Gerard J. M. Smit. "A Dataflow Inspired Programming Paradigm for Coarse-Grained Reconfigurable Arrays." In Lecture Notes in Computer Science, 275–82. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05960-0_29.

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Miyasaka, Yukio, Masahiro Fujita, Alan Mishchenko, and John Wawrzynek. "SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays." In VLSI-SoC: Design Trends, 113–31. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81641-4_6.

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Patel, Kunjan, and C. J. Bleakley. "Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures." In Lecture Notes in Computer Science, 351–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12133-3_33.

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9

Ristimäki, T., and J. Nurmi. "Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array." In Field Programmable Logic and Application, 1130–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_146.

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10

Bouwens, Frank, Mladen Berekovic, Bjorn De Sutter, and Georgi Gaydadjiev. "Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array." In High Performance Embedded Architectures and Compilers, 66–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-77560-7_6.

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Тези доповідей конференцій з теми "Coarse Grained Reconfigurable arrays"

1

Tan, Cheng, Nicolas Bohm Agostini, Jeff Zhang, Marco Minutoli, Vito Giovanni Castellana, Chenhao Xie, Tong Geng, Ang Li, Kevin Barker, and Antonino Tumeo. "OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays." In 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2021. http://dx.doi.org/10.1109/asap52443.2021.00029.

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2

Ansaloni, G., L. Pozzi, K. Tanimura, and N. Dutt. "Slack-aware scheduling on Coarse Grained Reconfigurable Arrays." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763323.

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3

Dimitroulakos, Gregory, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration for coarse grained reconfigurable arrays." In the 17th great lakes symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1228784.1228827.

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4

Van Essen, Brian, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, and Scott Hauck. "Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272293.

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5

Sousa, Ericles, Alexandru Tanase, Frank Hannig, and Jurgen Teich. "A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays." In 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2017. http://dx.doi.org/10.1109/reconfig.2017.8279768.

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6

Jian, Liu, Leibo Liu, Yanan Lu, Jianfeng Zhu, and Shaojun Wei. "Comparing Branch Predictors for Distributed-Controlled Coarse-Grained Reconfigurable Arrays." In 2019 IEEE 11th International Conference on Communication Software and Networks (ICCSN). IEEE, 2019. http://dx.doi.org/10.1109/iccsn.2019.8905283.

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7

Egger, Bernhard, Eunjin Song, Hochan Lee, and Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs." In LCTES '18: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2018. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3211332.3211342.

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8

Stock, Florian, and Andreas Koch. "Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311194.

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9

Heyse, Karel, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, and Dirk Stroobandt. "Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS." In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2013. http://dx.doi.org/10.1109/fpl.2013.6645516.

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10

Kim, Hee-Seok, Minwook Ahn, John A. Stratton, and Wen-mei W. Hwu. "Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays." In 2012 International Conference on Field-Programmable Technology (FPT). IEEE, 2012. http://dx.doi.org/10.1109/fpt.2012.6412155.

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