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Статті в журналах з теми "Coarse Grained Reconfigurable arrays"
Dimitroulakos, Grigorios, Stavros Georgiopoulos, Michalis D. Galanis, and Costas E. Goutis. "Resource aware mapping on coarse grained reconfigurable arrays." Microprocessors and Microsystems 33, no. 2 (March 2009): 91–105. http://dx.doi.org/10.1016/j.micpro.2008.07.002.
Повний текст джерелаTheocharis, Panagiotis, and Bjorn De Sutter. "A Bimodal Scheduler for Coarse-Grained Reconfigurable Arrays." ACM Transactions on Architecture and Code Optimization 13, no. 2 (June 27, 2016): 1–26. http://dx.doi.org/10.1145/2893475.
Повний текст джерелаAnsaloni, Giovanni, Kazuyuki Tanimura, Laura Pozzi, and Nikil Dutt. "Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, no. 12 (December 2012): 1803–16. http://dx.doi.org/10.1109/tcad.2012.2209886.
Повний текст джерелаEgger, Bernhard, Eunjin Song, Hochan Lee, and Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs." ACM SIGPLAN Notices 53, no. 6 (December 7, 2018): 76–88. http://dx.doi.org/10.1145/3299710.3211342.
Повний текст джерелаFilho, J. O., S. Masekowsky, T. Schweizer, and W. Rosenstiel. "CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (September 2009): 1247–59. http://dx.doi.org/10.1109/tvlsi.2008.2002429.
Повний текст джерелаDimitroulakos, Grigorios, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays." Journal of Supercomputing 48, no. 2 (May 16, 2008): 115–51. http://dx.doi.org/10.1007/s11227-008-0208-y.
Повний текст джерелаQu, Tongzhou, Zibin Dai, Yanjiang Liu, and Lin Chen. "A High Flexible Shift Transformation Unit Design Approach for Coarse-Grained Reconfigurable Cryptographic Arrays." Electronics 11, no. 19 (September 30, 2022): 3144. http://dx.doi.org/10.3390/electronics11193144.
Повний текст джерелаLopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto, and José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture." Electronics 10, no. 6 (March 12, 2021): 669. http://dx.doi.org/10.3390/electronics10060669.
Повний текст джерелаDe Sutter, Bjorn, Paul Coene, Tom Vander Aa, and Bingfeng Mei. "Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays." ACM SIGPLAN Notices 43, no. 7 (June 27, 2008): 151–60. http://dx.doi.org/10.1145/1379023.1375678.
Повний текст джерелаKissler, Dmitrij, Daniel Gran, Zoran Salcic, Frank Hannig, and Jürgen Teich. "Scalable Many-Domain Power Gating in Coarse-Grained Reconfigurable Processor Arrays." IEEE Embedded Systems Letters 3, no. 2 (June 2011): 58–61. http://dx.doi.org/10.1109/les.2011.2124438.
Повний текст джерелаДисертації з теми "Coarse Grained Reconfigurable arrays"
Lee, Jong-Suk Mark. "FleXilicon: a New Coarse-grained Reconfigurable Architecture for Multimedia and Wireless Communications." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/77094.
Повний текст джерелаPh. D.
Saraswat, Rohit. "A Finite Domain Constraint Approach for Placement and Routing of Coarse-Grained Reconfigurable Architectures." DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/689.
Повний текст джерелаDas, Satyajit. "Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.
Повний текст джерелаEmerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
Dogan, Rabia. "System Level Exploration of RRAM for SRAM Replacement." Thesis, Linköpings universitet, Elektroniksystem, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-92819.
Повний текст джерелаZain-ul-Abdin. "Programming of coarse-grained reconfigurable architectures." Doctoral thesis, Örebro universitet, Akademin för naturvetenskap och teknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:oru:diva-15246.
Повний текст джерелаUl-Abdin, Zain. "Programming of Coarse-Grained Reconfigurable Architectures." Doctoral thesis, Högskolan i Halmstad, Centrum för forskning om inbyggda system (CERES), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-15050.
Повний текст джерелаGuo, Yuanqing. "Mapping applications to a coarse-grained reconfigurable architecture." Enschede : University of Twente [Host], 2006. http://doc.utwente.nl/57121.
Повний текст джерелаBag, Zeki Ozan. "Energy-Aware Coarse Grained Reconfigurable Architectures Using Dynamically Reconfigurable Isolation Cells." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-108217.
Повний текст джерелаPlessl, Christian [Verfasser]. "Hardware Virtualization on a Coarse-Grained Reconfigurable Processor / Christian Plessl." Aachen : Shaker, 2006. http://d-nb.info/1166513963/34.
Повний текст джерелаYadav, Anil. "Exploration Of Energy And Area Efficient Techniques For Coarse-grained Reconfigurable Fabrics." Thesis, University of North Texas, 2011. https://digital.library.unt.edu/ark:/67531/metadc103413/.
Повний текст джерелаКниги з теми "Coarse Grained Reconfigurable arrays"
1964-, Soudris Dimitrios, and Vassiliadis Stamatis, eds. Fine- and coarse-grain reconfigurable computing. [New York?]: Springer, 2007.
Знайти повний текст джерелаPlessl, Christian. Hardware virtualization on a coarse-grained reconfigurable processor. Aachen: Shaker, 2006.
Знайти повний текст джерелаWijtvliet, Mark, Henk Corporaal, and Akash Kumar. Blocks, Towards Energy-efficient, Coarse-grained Reconfigurable Architectures. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-79774-4.
Повний текст джерелаN, Mahapatra Rabi, ed. Design of low-power coarse-grained reconfigurable architectures. Boca Raton, FL: CRC Press, 2011.
Знайти повний текст джерела(Foreword), Y. Patt, J. Smith (Foreword), M. Valero (Foreword), Stamatis Vassiliadis (Editor), and Dimitrios Soudris (Editor), eds. Fine- and Coarse-Grain Reconfigurable Computing. Springer, 2007.
Знайти повний текст джерелаPatt, Y., J. Smith, M. Valero, Dimitrios Soudris, and Stamatis Vassiliadis. Fine- and Coarse-Grain Reconfigurable Computing. Springer London, Limited, 2007.
Знайти повний текст джерелаPatt, Y., J. Smith, M. Valero, Dimitrios Soudris, and Stamatis Vassiliadis. Fine- and Coarse-Grain Reconfigurable Computing. Springer Netherlands, 2014.
Знайти повний текст джерелаMahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.
Знайти повний текст джерелаMahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2017.
Знайти повний текст джерелаMahapatra, Rabi N., and Yoonjin Kim. Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis Group, 2010.
Знайти повний текст джерелаЧастини книг з теми "Coarse Grained Reconfigurable arrays"
Sousa, Éricles, Frank Hannig, and Jürgen Teich. "Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays." In System Level Design from HW/SW to Memory for Embedded Systems, 218–29. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-90023-0_18.
Повний текст джерелаDe Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures." In Handbook of Signal Processing Systems, 553–92. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-6859-2_18.
Повний текст джерелаDe Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures." In Handbook of Signal Processing Systems, 449–84. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6345-1_17.
Повний текст джерелаSutter, Bjorn De, Praveen Raghavan, and Andy Lambrechts. "Coarse-Grained Reconfigurable Array Architectures." In Handbook of Signal Processing Systems, 427–72. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-91734-4_12.
Повний текст джерелаKim, Yongjoo, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon, and Yunheung Paek. "Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays." In High Performance Embedded Architectures and Compilers, 171–85. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-11515-8_14.
Повний текст джерелаNiedermeier, A., Jan Kuper, and Gerard J. M. Smit. "A Dataflow Inspired Programming Paradigm for Coarse-Grained Reconfigurable Arrays." In Lecture Notes in Computer Science, 275–82. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05960-0_29.
Повний текст джерелаMiyasaka, Yukio, Masahiro Fujita, Alan Mishchenko, and John Wawrzynek. "SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays." In VLSI-SoC: Design Trends, 113–31. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81641-4_6.
Повний текст джерелаPatel, Kunjan, and C. J. Bleakley. "Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures." In Lecture Notes in Computer Science, 351–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-12133-3_33.
Повний текст джерелаRistimäki, T., and J. Nurmi. "Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array." In Field Programmable Logic and Application, 1130–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30117-2_146.
Повний текст джерелаBouwens, Frank, Mladen Berekovic, Bjorn De Sutter, and Georgi Gaydadjiev. "Architecture Enhancements for the ADRES Coarse-Grained Reconfigurable Array." In High Performance Embedded Architectures and Compilers, 66–81. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-77560-7_6.
Повний текст джерелаТези доповідей конференцій з теми "Coarse Grained Reconfigurable arrays"
Tan, Cheng, Nicolas Bohm Agostini, Jeff Zhang, Marco Minutoli, Vito Giovanni Castellana, Chenhao Xie, Tong Geng, Ang Li, Kevin Barker, and Antonino Tumeo. "OpenCGRA: Democratizing Coarse-Grained Reconfigurable Arrays." In 2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP). IEEE, 2021. http://dx.doi.org/10.1109/asap52443.2021.00029.
Повний текст джерелаAnsaloni, G., L. Pozzi, K. Tanimura, and N. Dutt. "Slack-aware scheduling on Coarse Grained Reconfigurable Arrays." In 2011 Design, Automation & Test in Europe. IEEE, 2011. http://dx.doi.org/10.1109/date.2011.5763323.
Повний текст джерелаDimitroulakos, Gregory, Nikos Kostaras, Michalis D. Galanis, and Costas E. Goutis. "Compiler assisted architectural exploration for coarse grained reconfigurable arrays." In the 17th great lakes symposium. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1228784.1228827.
Повний текст джерелаVan Essen, Brian, Aaron Wood, Allan Carroll, Stephen Friedman, Robin Panda, Benjamin Ylvisaker, Carl Ebeling, and Scott Hauck. "Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays." In 2009 International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2009. http://dx.doi.org/10.1109/fpl.2009.5272293.
Повний текст джерелаSousa, Ericles, Alexandru Tanase, Frank Hannig, and Jurgen Teich. "A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays." In 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2017. http://dx.doi.org/10.1109/reconfig.2017.8279768.
Повний текст джерелаJian, Liu, Leibo Liu, Yanan Lu, Jianfeng Zhu, and Shaojun Wei. "Comparing Branch Predictors for Distributed-Controlled Coarse-Grained Reconfigurable Arrays." In 2019 IEEE 11th International Conference on Communication Software and Networks (ICCSN). IEEE, 2019. http://dx.doi.org/10.1109/iccsn.2019.8905283.
Повний текст джерелаEgger, Bernhard, Eunjin Song, Hochan Lee, and Daeyoung Shin. "Verification of coarse-grained reconfigurable arrays through random test programs." In LCTES '18: SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2018. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3211332.3211342.
Повний текст джерелаStock, Florian, and Andreas Koch. "Architecture Exploration and Tools for Pipelined Coarse-Grained Reconfigurable Arrays." In 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006. http://dx.doi.org/10.1109/fpl.2006.311194.
Повний текст джерелаHeyse, Karel, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, and Dirk Stroobandt. "Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS." In 2013 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2013. http://dx.doi.org/10.1109/fpl.2013.6645516.
Повний текст джерелаKim, Hee-Seok, Minwook Ahn, John A. Stratton, and Wen-mei W. Hwu. "Design evaluation of OpenCL compiler framework for Coarse-Grained Reconfigurable Arrays." In 2012 International Conference on Field-Programmable Technology (FPT). IEEE, 2012. http://dx.doi.org/10.1109/fpt.2012.6412155.
Повний текст джерела