Статті в журналах: "CNTFETs"

1

Kimbrough, Joevonte, Lauren Williams, Qunying Yuan, and Zhigang Xiao. "Dielectrophoresis-Based Positioning of Carbon Nanotubes for Wafer-Scale Fabrication of Carbon Nanotube Devices." Micromachines 12, no. 1 (December 25, 2020): 12. http://dx.doi.org/10.3390/mi12010012.

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In this paper, we report the wafer-scale fabrication of carbon nanotube field-effect transistors (CNTFETs) with the dielectrophoresis (DEP) method. Semiconducting carbon nanotubes (CNTs) were positioned as the active channel material in the fabrication of carbon nanotube field-effect transistors (CNTFETs) with dielectrophoresis (DEP). The drain-source current (IDS) was measured as a function of the drain-source voltage (VDS) and gate-source voltage (VGS) from each CNTFET on the fabricated wafer. The IDS on/off ratio was derived for each CNTFET. It was found that 87% of the fabricated CNTFETs was functional, and that among the functional CNTFETs, 30% of the CNTFETs had an IDS on/off ratio larger than 20 while 70% of the CNTFETs had an IDS on/off ratio lower than 20. The highest IDS on/off ratio was about 490. The DEP-based positioning of carbon nanotubes is simple and effective, and the DEP-based device fabrication steps are compatible with Si technology processes and could lead to the wafer-scale fabrication of CNT electronic devices.

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2

GUO, JING, SIYURANGA O. KOSWATTA, NEOPHYTOS NEOPHYTOU, and MARK LUNDSTROM. "CARBON NANOTUBE FIELD-EFFECT TRANSISTORS." International Journal of High Speed Electronics and Systems 16, no. 04 (December 2006): 897–912. http://dx.doi.org/10.1142/s0129156406004077.

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This paper discusses the device physics of carbon nanotube field-effect transistors (CNTFETs). After reviewing the status of device technology, we use results of our numerical simulations to discuss the physics of CNTFETs emphasizing the similarities and differences with traditional FETs. The discussion shows that our understanding of CNTFET device physics has matured to the point where experiments can be explained and device designs optimized. The paper concludes with some thoughts on challenges and opportunities for CNTFET electronics.

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3

Crippa, Paolo, Giorgio Biagetti, Claudio Turchetti, Laura Falaschetti, Davide Mencarelli, George Deligeorgis, and Luca Pierantoni. "A High-Gain CNTFET-Based LNA Developed Using a Compact Design-Oriented Device Model." Electronics 10, no. 22 (November 18, 2021): 2835. http://dx.doi.org/10.3390/electronics10222835.

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Recently, carbon nanotube field-effect transistors (CNTFETs) have attracted wide attention as promising candidates for components in the next generation of electronic devices. In particular CNTFET-based RF devices and circuits show superior performance to those built with silicon FETs since they are able to obtain higher power-gain and cut-off frequency at lower power dissipation. The aim of this paper is to present a compact, design-oriented model of CNTFETs that is able to ease the development of a complete amplifier. As a case study, the detailed design of a high-gain CNTFET-based broadband inductorless LNA is presented.

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4

Ding, Hongyu, Jiangwei Cui, Qiwen Zheng, Haitao Xu, Ningfei Gao, Mingzhu Xun, Gang Yu, Chengfa He, Yudong Li, and Qi Guo. "Effect of Trapped Charge Induced by Total Ionizing Dose Radiation on the Top-Gate Carbon Nanotube Field Effect Transistors." Electronics 12, no. 4 (February 17, 2023): 1000. http://dx.doi.org/10.3390/electronics12041000.

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The excellent performance and radiation-hardness potential of carbon nanotube (CNT) field effect transistors (CNTFETs) have attracted wide attention. However, top-gate structure CNTFETs, which are often used to make high-performance devices, have not been studied enough. In this paper, the total ionizing dose (TID) effect of the top-gate structure CNTFETs and the influence of the substrate on top-gate during irradiation are studied. The parameter degradation caused by the irradiation- and radiation-damage mechanisms of the top-gate P-type CNTFET were obtained by performing a Co-60 γ-ray irradiation test. The results indicate that the transfer curves of the top-gate P-type CNTFETs shift negatively, the threshold voltage and the transconductance decrease when TID increases, and the subthreshold swing decreases first and then increases with the increase in TID. The back-gate transistor is constructed by using the substrate as a back-gate, and the influence of back-gate bias on the characteristics of the top-gate transistor is tested. We also test the influence of TID irradiation on the characteristics of back-gate transistors, and reveal the effect of trapped charge introduced by radiation on the characteristics of top-gate transistors. In addition, the CNTFETs that we used have obvious hysteresis characteristics. After irradiation, the radiation-induced trapped charges generated in oxide and the OH groups generated by ionization of the CNT adsorbates aggravate the hysteresis characteristics of CNTFET, and the hysteresis window increases with the increase in TID.

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5

Park, Junsung, Xueqing Liu, Trond Ytterdal, and Michael Shur. "Carbon Nanotube Detectors and Spectrometers for the Terahertz Range." Crystals 10, no. 7 (July 10, 2020): 601. http://dx.doi.org/10.3390/cryst10070601.

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We present the compact unified charge control model (UCCM) for carbon nanotube field-effect transistors (CNTFETs) to enable the accurate simulation of the DC characteristics and plasmonic terahertz (THz) response in the CNTFETs. Accounting for the ambipolar nature of the carrier transport (n-type and p-type conductivity at positive and negative gate biases, respectively), we use n-type and p-type CNTFET non-linear equivalent circuits connected in parallel, representing the ambipolar conduction in the CNTFETs. This allows us to present a realistic non-linear model that is valid across the entire voltage range and is therefore suitable for the CNTFET design. The important feature of the model is that explicit equations for gate bias, current, mobility, and capacitance with smoothing parameters accurately describe the device operation near the transition from above- to below-threshold regimes, with scalability in device geometry. The DC performance in the proposed compact CNTFET model is validated by the comparison between the SPICE simulation and the experimental DC characteristics. The simulated THz response resulted from the validated CNTFET model is found to be in good agreement with the analytically calculated response and also reveals the bias and power dependent sub-THz response and relatively wide dynamic range for detection that could be suitable for THz detectors. The operation of CNTFET spectrometers in the THz frequency range is further demonstrated using the present model. The simulation exhibits that the CNT-based spectrometers can cover a broad THz frequency band from 0.1 to 3.08 THz. The model that has been incorporated into the circuit simulators enables the accurate assessment of DC performance and THz operation. Therefore, it can be used for the design and performance estimation of the CNTFETs and their integrated circuits operating in the THz regime.

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6

Cho, Gookbin, Eva Grinenval, Jean-Christophe P. Gabriel, and Bérengère Lebental. "Intense pH Sensitivity Modulation in Carbon Nanotube-Based Field-Effect Transistor by Non-Covalent Polyfluorene Functionalization." Nanomaterials 13, no. 7 (March 24, 2023): 1157. http://dx.doi.org/10.3390/nano13071157.

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We compare the pH sensing performance of non-functionalized carbon nanotubes (CNT) field-effect transistors (p-CNTFET) and CNTFET functionalized with a conjugated polyfluorene polymer (labeled FF-UR) bearing urea-based moieties (f-CNTFET). The devices are electrolyte-gated, PMMA-passivated, 5 µm-channel FETs with unsorted, inkjet-printed single-walled CNT. In phosphate (PBS) and borate (BBS) buffer solutions, the p-CNTFETs exhibit a p-type operation while f-CNTFETs exhibit p-type behavior in BBS and ambipolarity in PBS. The sensitivity to pH is evaluated by measuring the drain current at a gate and drain voltage of −0.8 V. In PBS, p-CNTFETs show a linear, reversible pH response between pH 3 and pH 9 with a sensitivity of 26 ± 2.2%/pH unit; while f-CNTFETs have a much stronger, reversible pH response (373%/pH unit), but only over the range of pH 7 to pH 9. In BBS, both p-CNTFET and f-CNTFET show a linear pH response between pH 5 and 9, with sensitivities of 56%/pH and 96%/pH, respectively. Analysis of the I–V curves as a function of pH suggests that the increased pH sensitivity of f-CNTFET is consistent with interactions of FF-UR with phosphate ions in PBS and boric acid in BBS, with the ratio and charge of the complexed species depending on pH. The complexation affects the efficiency of electrolyte gating and the surface charge around the CNT, both of which modify the I–V response of the CNTFET, leading to the observed current sensitivity as a function of pH. The performances of p-CNTFET in PBS are comparable to the best results in the literature, while the performances of the f-CNTFET far exceed the current state-of-the-art by a factor of four in BBS and more than 10 over a limited range of pH in BBS. This is the first time that a functionalization other than carboxylate moieties has significantly improved the state-of-the-art of pH sensing with CNTFET or CNT chemistors. On the other hand, this study also highlights the challenge of transferring this performance to a real water matrix, where many different species may compete for interactions with FF-UR.

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7

Zhang, Ji, Sheng Chang, Hao Wang, Jin He, and Qi Jun Huang. "Artificial Neural Network Based CNTFETs Modeling." Applied Mechanics and Materials 667 (October 2014): 390–95. http://dx.doi.org/10.4028/www.scientific.net/amm.667.390.

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Based on artificial neural network (ANN), a new method of modeling carbon nanotube field effect transistors (CNTFETs) is developed. This paper presents two ANN CNTFET models, including P-type CNTFET (PCNTFET) and N-type CNTFET (NCNTFET). In order to describe the devices more accurately, a segmentation voltage of the voltage between gate and source is defined for each type of CNTFET to segment the workspace of CNTFET. With the smooth connection by a quasi-Fermi function for, the two segmented networks of CNTFET are integrated into a whole device model and implemented by Verilog-A. To validate the ANN CNTFET models, quantitative test with different device intrinsic parameters are done. Furthermore, a complementary CNTFET inverter is designed using these NCNTFET and PCNTFET ANN models. The performances of the inverter show that our models are both efficient and accurate for simulation of nanometer scale circuits.

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8

Prasad, Vikash, and Debaprasad Das. "A Review on MOSFET-Like CNTFETs." Science & Technology Journal 4, no. 2 (July 1, 2016): 124–29. http://dx.doi.org/10.22232/stj.2016.04.02.06.

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Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

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9

Zahoor, Furqan, Fawnizu Azmadi Hussin, Farooq Ahmad Khanday, Mohamad Radzi Ahmad, and Illani Mohd Nawi. "Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)." Micromachines 12, no. 11 (October 21, 2021): 1288. http://dx.doi.org/10.3390/mi12111288.

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Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

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10

Marani, R., and A. G. Perri. "Study of CNTFETs as Memory Devices." ECS Journal of Solid State Science and Technology 11, no. 3 (March 1, 2022): 031001. http://dx.doi.org/10.1149/2162-8777/ac5846.

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In this paper we propose a procedure for the study of CNTFETs as memory devices. In particular we analyze the design of a 6-T SRAM, in order to evaluate the writing and reading times, in single and double supplies, the static noise margin, the static power consumption and the power-delay product. For these goals, we use a CNTFET model, already proposed by us. Then we apply the same procedure using the Stanford model in order to compare the obtained results. At last we apply the proposed analysis for the design of a 6-T SRAM in CMOS technology, showing the improvements obtained with CNTFET technology.

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11

Hamieh, S. "Improving the RF Performance of Carbon Nanotube Field Effect Transistor." Journal of Nanomaterials 2012 (2012): 1–7. http://dx.doi.org/10.1155/2012/724121.

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Compact model of single-walled semiconducting carbon nanotube field-effect transistors (CNTFETs) implementing the calculation of energy conduction subband minima under VHDLAMS simulator is used to explore the high-frequency performance potential of CNTFET. The cutoff frequency expected for a MOSFET-like CNTFET is well below the performance limit, due to the large parasitic capacitance between electrodes. We show that using an array of parallel nanotubes as the transistor channel combined in a finger geometry to produce a single transistor significantly reduces the parasitic capacitance per tube and, thereby, improves high-frequency performance.

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12

Zahoor, Furqan, Fawnizu Azmadi Hussin, Farooq Ahmad Khanday, Mohamad Radzi Ahmad, Illani Mohd Nawi, Chia Yee Ooi, and Fakhrul Zaman Rokhani. "Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits." Electronics 10, no. 1 (January 4, 2021): 79. http://dx.doi.org/10.3390/electronics10010079.

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The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

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13

Naderi, Ali, S. Mohammad Noorbakhsh, and Hossein Elahipanah. "Temperature Dependence of Electrical Characteristics of Carbon Nanotube Field-Effect Transistors: A Quantum Simulation Study." Journal of Nanomaterials 2012 (2012): 1–7. http://dx.doi.org/10.1155/2012/532625.

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By developing a two-dimensional (2D) full quantum simulation, the attributes of carbon nanotube field-effect transistors (CNTFETs) in different temperatures have been comprehensively investigated. Simulations have been performed by employing the self-consistent solution of 2D Poisson-Schrödinger equations within the nonequilibrium Green's function (NEGF) formalism. Principal characteristics of CNTFETs such as current capability, drain conductance, transconductance, and subthreshold swing (SS) have been investigated. Simulation results present that as temperature raises from 250 to 500 K, the drain conductance and on-current of the CNTFET improved; meanwhile the on-/off-current ratio deteriorated due to faster growth in off-current. Also the effects of temperature on short channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off have been studied. Results show that the subthreshold swing and DIBL parameters are almost linearly correlated, so the degradation of these parameters has the same origin and can be perfectly influenced by the temperature.

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14

Pourfath, Mahdi, Hans Kosina, and Siegfried Selberherr. "Tunneling CNTFETs." Journal of Computational Electronics 6, no. 1-3 (January 18, 2007): 243–46. http://dx.doi.org/10.1007/s10825-006-0099-1.

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15

FAEZ, RAHIM, and SEYED EBRAHIM HOSSEINI. "NOVEL STRUCTURES FOR CARBON NANOTUBE FIELD EFFECT TRANSISTORS." International Journal of Modern Physics B 23, no. 19 (July 30, 2009): 3871–80. http://dx.doi.org/10.1142/s0217979209052911.

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A carbon nanotube field effect transistor (CNTFET) has been studied based on the Schrödinger–Poisson formalism. To improve the saturation range in the output characteristics, new structures for CNTFETs are proposed. These structures are simulated and compared with the conventional structure. Simulations show that these structures have a wider output saturation range. With this, larger drain-source voltage (Vds) can be used, which results in higher output power. In the digital circuits, higher Vds increases noise immunity.

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16

SundaramK, Mohana, P. Prakash, S. Angalaeswari, T. Deepa, L. Natrayan, and Prabhu Paramasivam. "Influence of Process Parameter on Carbon Nanotube Field Effect Transistor Using Response Surface Methodology." Journal of Nanomaterials 2021 (December 15, 2021): 1–9. http://dx.doi.org/10.1155/2021/7739359.

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Carbon nanotube field-effect transistor (CNTFET) is a good option to replace silicon for low power consumption application. Recent research shows that CN-FET thermal and electrical properties alter with length, diameter, and gate parameters. Optimization of CNTFET design parameters helps control some of the factors. Double gate and cylindrical gate layouts are introduced to overcome these facts. Carbon nanotubes have an intercapacitance between them that increases as their diameter increases. Total capacitance and inductance of CNTFETs increase with nanotube count. In order to reduce the voltage drop between semiconducting and metallic terminals, the diameter and pitch must be raised. This study employs response surface methodology and ANOVA technique that were used to optimize CNTFET process parameters. Thickness, voltage, delay, and power were all considered. The most affecting parameter was investigated.

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17

Dudina, Alexandra, Urs Frey, and Andreas Hierlemann. "Carbon-Nanotube-Based Monolithic CMOS Platform for Electrochemical Detection of Neurotransmitter Glutamate." Sensors 19, no. 14 (July 12, 2019): 3080. http://dx.doi.org/10.3390/s19143080.

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We present a monolithic biosensor platform, based on carbon-nanotube field-effect transistors (CNTFETs), for the detection of the neurotransmitter glutamate. We used an array of 9′216 CNTFET devices with 96 integrated readout and amplification channels that was realized in complementary metal-oxide semiconductor technology (CMOS). The detection principle is based on amperometry, where electrochemically active hydrogen peroxide, a product of the enzymatic reaction of the target analyte and an enzyme that was covalently bonded to the CNTFET, modulated the conductance of the CNTFET-based sensors. We assessed the performance of the CNTs as enzymatic sensors by evaluating the minimal resolvable concentration change of glutamate in aqueous solutions. The minimal resolvable concentration change amounted to 10 µM of glutamate, which was one of the best values reported for CMOS-based systems so far.

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18

Farmer, Damon B. "Metallization considerations for carbon nanotube device optimization." Journal of Applied Physics 132, no. 10 (September 14, 2022): 104301. http://dx.doi.org/10.1063/5.0098970.

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As a one-dimensional structure with atomically thin sidewalls, charge transport in carbon nanotubes can be regarded as a surface phenomenon. As such, perturbations from the surrounding environment can have a dramatic impact on transport and consequently on the device behavior of carbon nanotube field-effect transistors (CNTFETs). Importantly, this includes effects from device fabrication processes like contact metallization. With this as motivation, several aspects of contact metallization are investigated herein. First, it is found that ON current in n-type CNTFETs is enhanced to the level of p-type CNTFETs through the utilization of titanium as an adhesion layer, a result of improved wetting. Effects of different metallization techniques, namely, thermal and electron-beam evaporation, are also explored in p-type devices using titanium/palladium/gold contacts. It is found that thermal metallization consistently produces devices with higher ON current. In-depth analysis of the transfer characteristics reveals that this is due to radiation effects encountered during electron-beam processing, resulting in channel scattering and a decreased transconductance in the devices. This effect is particularly severe upon gold processing, and attempts to heal this device degradation through annealing proved unsuccessful. All studies presented here are conducted through the analysis of a large number of nanotube devices, giving a degree of confidence to the average results. Additionally, only device parameters that can be directly extracted from the transfer characteristics are analyzed. Assumptions including nanotube diameter, capacitance, and nanotube number per device are not made. Results from this study provide recommendations for optimizing CNTFET performance as it relates to contact metallization.

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19

., Gudala Konica, and Sreenivasulu Mamilla . "Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling." Volume 4,Issue 5,2018 4, no. 5 (January 5, 2019): 575–79. http://dx.doi.org/10.30799/jnst.187.18040530.

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Анотація:

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

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20

Dinh, Hien Sy, Tuan Tran Anh Thi, and Luong Thi Nguyen. "SIMULATING CHARACTERISTICS OF CARBON NANOTUBE FIELD- EFFECT TRANSISTOR (CNTFET)." Science and Technology Development Journal 13, no. 2 (June 30, 2010): 15–27. http://dx.doi.org/10.32508/stdj.v13i2.2123.

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Анотація:

We provide a model of coaxial CNTFET, using single wall nanotube. These devices would exhibit wrap-around gates that maximize capacitive coupling between the gate electrode and the nanotube channel. The results of simulations of I-V characteristics for CNTFETs are presented. Here we use non-equilibrium Green’s function (NEGF) to perform simulation for CNTFET. This simulator also includes a graphic user interface (GUI) of Matlab that enables parameter entry, calculation control, display of calculation results. In this work, we review the capabilities of the simulator, summarize the theoretical approach and experimental results. Current-voltage characteristics are a function of the variables such as: diameter of CNT, the length of CNT, the gate oxide thickness, gate voltage of Vg, types of materials of Source-Drain, Gate, and temperature. The obtained I-V characteristics of the CNTFET are also presented by analytical equations.

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21

Naderi, Ali. "Numerical study of carbon nanotube field effect transistors in presence of carbon–carbon third nearest neighbor interactions." International Journal of Modern Physics B 28, no. 24 (August 5, 2014): 1450167. http://dx.doi.org/10.1142/s0217979214501677.

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Анотація:

In this paper, for the first time, we have used a more precise Hamiltonian matrix based on first nearest neighbor (1NN) and third nearest neighbor (3NN) carbon–carbon interactions to simulate carbon nanotube field effect transistors (CNTFETs). By taking the interactions with more distant neighbors into account, an improvement in tight-binding picture is gained. A self-consistent solution of Schrodinger equation based on nonequilibrium Green's function (NEGF) formalism coupled to a two-dimensional Poisson's equation for treating the electrostatics of the device has been employed to simulate CNTFETs. A tight-binding Hamiltonian with an atomistic (pz orbitals) mode space basis in the ballistic limits has been used to describe the carbon nanotube (CNT) region. Simulations show that in the presence of 3NN, the energy bandgap of the CNT decreases and consequently the simulated device has lower threshold voltage compared to a simulated device with just 1NN. Short channel effects study demonstrates that neglecting 3NN underestimates the subthreshold swing and overestimates ON/OFF current ratio. All these investigations show that for simulating a CNTFET more precisely, the 3NN interactions can be taken into account in addition to the 1NN.

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22

Shahangian, Maryam, Seied Ali Hosseini, and Reza Faghih Mirzaee. "A Universal Method for Designing Multi-Digit Ternary to Binary Converter Using CNTFET." Journal of Circuits, Systems and Computers 29, no. 12 (February 19, 2020): 2050196. http://dx.doi.org/10.1142/s0218126620501960.

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Анотація:

Ternary logic can reduce the number of interconnections, chip area and power dissipation. In addition, one of the important features of carbon nanotube field effect transistors (CNTFETs) is the capability of adjusting threshold voltage. As a result, the design complexity of ternary circuits can be decreased. The structure of a mixed radix system which is based on multi-valued and binary logic is more appropriate compared to only multiple-valued logic (MVL). Therefore, ternary-to-binary and binary-to-ternary converters are the essential components for the ternary signaling on the bus and the binary logic processing circuits. It is also important for the creation of compatibility between the binary and ternary logic. This study is about a multi-digit binary-to-ternary converter by using CNTFET. At first, the algorithm used for the multi-digit conversion from ternary to binary logic is addressed in this paper. Then, the paper proposes a block diagram suitable for designing the multi-digit ternary-to-binary converter. Some new gates including One-Active Gate and Two-Active Gate, as well as two types of binary half-and full-adders, are designed for the purpose of implementing the proposed block diagram. This is done by adjusting the proper threshold voltage for CNTFETs. The proposed algorithm can also be applied to any desired number of bits. The proper operation and high efficiency of the proposed converter are confirmed by HSPICE simulation results and 32[Formula: see text]nm CNTFET technology from the Stanford University.

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23

Rahman, Fahim, Prodyut Das, Md Forhad Hossain, Sazzaduzzaman Khan, and Rajib Chowdhury. "Design and Performance Evaluation of a 10GHz 32nm-CNTFET IR-UWB Transmitter for Inter-Chip Wireless Communication." Advanced Materials Research 646 (January 2013): 228–34. http://dx.doi.org/10.4028/www.scientific.net/amr.646.228.

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In this paper, we have presented the design and performance evaluation of a 10GHz 32nm-CNTFET IR-UWB transmitter for inter-chip wireless transmission. We have designed the transmitter using a VCO-based high speed clock generator and a positive and a negative monocycle Gaussian pulse generator. RF compatible Carbon Nano-Tube Field Effect Transistors (CNTFETs) have been used as the building blocks of the oscillator and the logic gates. The final design has resulted to a 7-channel-SWNT CNTFET-based transmitter for optimum 10GHz data rate with a promising 650mV pulse amplitude and only 1.069mW power consumption with a -32.27dB output. This transmitter can also operate satisfactorily upto 15GHz. The results show promising superiority over existing transmitters regarding high data rate, low power loss and high pulse amplitude.

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24

Uchino, Takashi, Greg Ayre, David Smith, John Hutchison, C. de Groot, and Peter Ashburn. "The Effects of Hydrogen Annealing on Carbon Nanotube Field-Effect Transistors." Nanomaterials 11, no. 10 (September 23, 2021): 2481. http://dx.doi.org/10.3390/nano11102481.

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We have systematically investigated the effects of hydrogen annealing on Ni- and Al-contacted carbon nanotube field-effect transistors (CNTFETs), whose work functions have not been affected by hydrogen annealing. Measured results show that the electronic properties of single-walled carbon nanotubes are modified by hydrogen adsorption. The Ni-contacted CNTFETs, which initially showed metallic behavior, changed their p-FET behavior with a high on-current over 10 µA after hydrogen annealing. The on-current of the as-made p-FETs is much improved after hydrogen annealing. The Al-contacted CNTFETs, which initially showed metallic behavior, showed unipolar p-FET behavior after hydrogen annealing. We analyzed the energy band diagrams of the CNTFETs to explain experimental results, finding that the electron affinity and the bandgap of single-walled carbon nanotubes changed after hydrogen annealing. These results are consistent with previously reported ab initio calculations.

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25

Marani, R., and A. G. Perri. "Analysis of Noise in Current Mirror Circuits Based on CNTFET and MOSFET." ECS Journal of Solid State Science and Technology 11, no. 3 (March 1, 2022): 031006. http://dx.doi.org/10.1149/2162-8777/ac5eb1.

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In this paper we present a comparative analysis of noise performance of Carbon Nanotube Field Effect Transistors (CNTFETs) and MOSFET, through the design of two circuits: a basic current mirror and self-bias current mirror, each time with different current values. For this aim we use a semi-empirical compact CNTFET model, already proposed by us, including noise source contributions, and the BSIM4 model for MOS device. Then we analyze and discuss the spectral density of output noise current, comparing the two considered technology. The software used is Advanced Design System (ADS), compatible with the Verilog A programming language.

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26

Falaschetti, Laura, Davide Mencarelli, Nicola Pelagalli, Paolo Crippa, Giorgio Biagetti, Claudio Turchetti, George Deligeorgis, and Luca Pierantoni. "A Compact and Robust Technique for the Modeling and Parameter Extraction of Carbon Nanotube Field Effect Transistors." Electronics 9, no. 12 (December 20, 2020): 2199. http://dx.doi.org/10.3390/electronics9122199.

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Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

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27

Yao, Xuesong, Yalei Zhang, Wanlin Jin, Youfan Hu, and Yue Cui. "Carbon Nanotube Field-Effect Transistor-Based Chemical and Biological Sensors." Sensors 21, no. 3 (February 2, 2021): 995. http://dx.doi.org/10.3390/s21030995.

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Chemical and biological sensors have attracted great interest due to their importance in applications of healthcare, food quality monitoring, environmental monitoring, etc. Carbon nanotube (CNT)-based field-effect transistors (FETs) are novel sensing device configurations and are very promising for their potential to drive many technological advancements in this field due to the extraordinary electrical properties of CNTs. This review focuses on the implementation of CNT-based FETs (CNTFETs) in chemical and biological sensors. It begins with the introduction of properties, and surface functionalization of CNTs for sensing. Then, configurations and sensing mechanisms for CNT FETs are introduced. Next, recent progresses of CNTFET-based chemical sensors, and biological sensors are summarized. Finally, we end the review with an overview about the current application status and the remaining challenges for the CNTFET-based chemical and biological sensors.

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28

Haji-Nasiri, Saeed, and Mohammad Kazem Moravvej-Farshi. "Stability Analysis in CNTFETs." IEEE Electron Device Letters 34, no. 2 (February 2013): 301–3. http://dx.doi.org/10.1109/led.2012.2235136.

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29

Pourfath, Mahdi, Hans Kosina, and Siegfried Selberherr. "Dissipative transport in CNTFETs." Journal of Computational Electronics 6, no. 1-3 (January 26, 2007): 321–24. http://dx.doi.org/10.1007/s10825-006-0113-7.

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30

JAMALABADI, ZAHRA, PARVIZ KESHAVARZI, and ALI NADERI. "SDC-CNTFET: STEPWISE DOPING CHANNEL DESIGN IN CARBON NANOTUBE FIELD EFFECT TRANSISTORS FOR IMPROVING SHORT CHANNEL EFFECTS IMMUNITY." International Journal of Modern Physics B 28, no. 07 (February 20, 2014): 1450048. http://dx.doi.org/10.1142/s0217979214500489.

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A novel carbon nanotube field-effect transistor with stepwise doping profile channel (SDC-CNTFET) is introduced for short-channel effects (SCEs) improvement. In SDC-CNTFET, the channel is divided into five sections of equal length. Impurity concentration was reduced from 0.8 nm-1 to zero from the source side to the drain side of the channel, with stepwise profile. The devices have been simulated by the self-consistent solution of two-dimensional (2D) Poisson–Schrödinger equations, within the nonequilibrium Green's function (NEGF) formalism. We demonstrate that the proposed structure for CNTFETs shows considerable improvement in device performance focusing on leakage current and ON–OFF current ratio. In addition, the investigation of SCEs for the proposed structure shows the improved drain-induced barrier lowering (DIBL) and subthreshold swing (SS). Moreover, we will prove that the proposed structure has acceptable performance at different values of channel impurity concentration in terms of delay and power-delay product (PDP). All these investigations introduce SDC-CNTFET as a more reliable device structure in short-channel regime.

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31

Reddy Eamani, Ramakrishna, Vinodhkumar Nallathambi, and Sasikumar Asaithambi. "A low-power high speed full adder cell using carbon nanotube field effect transistors." Indonesian Journal of Electrical Engineering and Computer Science 31, no. 1 (July 1, 2023): 134. http://dx.doi.org/10.11591/ijeecs.v31.i1.pp134-142.

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The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

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32

KORDROSTAMI, ZOHEIR, M. HOSSEIN SHEIKHI, and ABBAS ZARIFKAR. "DESIGN DEPENDENT CUTOFF FREQUENCY OF NANOTRANSISTORS NEAR THE ULTIMATE PERFORMANCE LIMIT." International Journal of Modern Physics B 26, no. 32 (December 11, 2012): 1250196. http://dx.doi.org/10.1142/s0217979212501962.

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We have studied the effect of different structural designs of double gate MOSFETs (DG–MOSFETs) and carbon nanotube field effect transistors (CNTFETs) on the cutoff frequency (fT). The effects of metallic contacts with Schottky barriers, gate work function, dual material gate (DMG), halo doped channel and lightly doped drain and source (LDDS) architectures on the fT have been investigated for DG–MOSFETs and CNTFETs and the design dependent fT for both types of transistors has been studied for the first time. The simulations are based on the Schrödinger–Poisson solvers developed for each nanotransistor separately. The ballistic limit has been studied as the ultimate performance limit of the DG–MOSFETs and CNTFETs. The results of this paper, for the first time, show how some designations used for modification of short channel effects or current–voltage characteristics affect the fT. The results revealed that the cutoff frequencies of both types of the transistors exhibit the same behavior with changing design parameters. We have shown that the Schottky barriers, parasitic capacitances and halo doping reduce the fT and have proposed the DMG and LDDS artchitectures as ways to increase the fT for DG–MOSFETs and CNTFETs for the first time.

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33

Saini, Jitendra Kumar, Avireni Srinivasulu, and Renu Kumawat. "High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology." International Journal of Sensors, Wireless Communications and Control 9, no. 4 (September 17, 2019): 462–67. http://dx.doi.org/10.2174/2210327909666190206144601.

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Background: The advent of High Performance Computing (HPC) applications and big data applications has made it imparitive to develop hardware that can match the computing demands. In such high performance systems, the high speed multipliers are the most sought after components. A compressor is an important part of the multiplier; it plays a vital role in the performance of multiplier, also it contributes to the efficiency enhancement of an arithmetic circuit. The 5:2 compressor circuit design proposed here improves overall performance and efficiency of the arithmetic circuits in terms of power consumption, delay and power delay product. The proposed 5:2 compressor circuit was implemented using both CMOS and Carbon Nano Tube Field Effect Transistor (CNTFET) technologies and it was observed that the proposed circuit has yielded better results with CNTFETs as compared to MOSFETs. Methods/Results: The proposed 5:2 compressor circuit was designed with CMOS technology simulated at 45 nm with voltage supply 1.0 V and compared it with the existing 5:2 compressor designes to validate the improvements. Thereafter, the proposed design was implemented with CNTFET technology at 32 nm and simulated with voltage supply 0.6 V. The comparision results of proposed 5:2 compressor with existing designs implemented using CMOS. The results also compare the proposed design on CMOS and CNTFET technologies for parameters like power, delay, power delay product. Conclusion: It can be concluded that the proposed 5:2 compressor gives better results as compared to the existing 5:2 compressor designs implemeted using CMOS. The improvement in power, delay and power delay product is approx 30%, 15% and 40% respectively. The proposed circuit of 5:2 compressor is also implemented using CNTFET technology and compared, which further enhances the results by 30% (power consumption and PDP). Hence, the proposed circuit implemented using CNTFET gives substantial improvements over the existing circuits.

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34

LI, HONG, QING ZHANG, and JINGQI LI. "CHARGE STORAGE IN CARBON NANOTUBE FIELD-EFFECT TRANSISTORS." International Journal of Nanoscience 05, no. 04n05 (August 2006): 553–57. http://dx.doi.org/10.1142/s0219581x06004784.

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Very significant hysteresis characteristics are found in single wall carbon nanotubes field-effect transistors (CNTFET) fabricated using AC dielectrophoresis method. The CNTFETs show ambipolar characteristics. Two clear hysteresis loops are observed when the gate voltage is forward and backward swept. The hysteresis characteristics are studied from room temperature down to 16 K. It is found that the hysteresis loops become smaller as temperature is decreased. We suggested that the hysteresis is caused by charge trapping in foreign species covering the single wall carbon nanotube. It is more difficult for charges to transfer into and out of the trapping center at a lower temperature; as a result, the hysteresis loops become much smaller at low temperature.

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35

Hou, Zhenfei, Yiwei Liu, Gang Niu, Yanxiao Sun, Jie Li, Jinyan Zhao, and Shengli Wu. "Carbon nanotube network film-based field-effect transistor interface state optimization by ambient air annealing." Journal of Applied Physics 133, no. 12 (March 28, 2023): 125303. http://dx.doi.org/10.1063/5.0135500.

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Carbon nanotube field-effect transistors (CNTFETs) have been considered a strong candidate for post-Si era electronics due to the virtues of higher speed, lower power consumption, and multiple functionalities. The interface analysis based on the top gate structure has made little progress and lacks a reliable charge trap characterization model suitable for carbon tube devices. Quantitative extraction and analysis of the interface state are crucial for the integration of top-gate devices. Herein, a 5 nm thick Y2O3 thin film was selected as the gate dielectric layer in the top-gate CNTFETs device, and a post-annealing process in air ambience was utilized to optimize the Y2O3-CNT interface. A series of device performance evaluation results indicated that the post-annealing process in air ambience can effectively improve the on-state current and reduce the threshold voltage and subthreshold swing of the device, which are derived from diffusion of oxygen atom in the Y2O3 layer and optimization of the interface of Y2O3-CNT. Specifically, the maximum mobility, subthreshold swing, and threshold voltage are calculated to be 29 cm2/V s, 103 mV/dec, and −0.1 V, respectively, and the interface state density is reduced from 2.68 × 1012 to 1.51 × 1012 cm−2 in the gate insulator. These results not only are important to understand the dielectric impact on CNTFET devices but also are useful for future materials’ development and device optimization for high-performance CNT-based electronics.

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36

Bejenari, Igor, and Martin Claus. "Electron Back Scattering in CNTFETs." IEEE Transactions on Electron Devices 63, no. 3 (March 2016): 1340–45. http://dx.doi.org/10.1109/ted.2015.2512180.

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37

Hellkamp, Daniel, and Kundan Nepal. "True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors." Journal of Circuits, Systems and Computers 28, no. 05 (May 2019): 1950085. http://dx.doi.org/10.1142/s0218126619500853.

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Carbon nanotube-based transistors (CNTFETs) have been shown to exhibit ambipolar field-effect transistor behavior, allowing circuit designers to easily choose between [Formula: see text]- and [Formula: see text]-conduction channels by applying correct voltages at a polarity gate. In this paper, we explore this ambipolar behavior of the CNTFET to design both binary and ternary content addressable memory (AM) cells. Using SPICE simulation, we show the designs of a traditional ternary CAM (TCAM) and a true three-valued TCAM (T3-CAM) functionality of the proposed cells and show that the ambipolar design can lead to a savings of up to 31% in terms of transistor count over a traditional design. We also explore issues related to matchline leakage, cell stability and design in the presence of metallic tubes.

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38

Selvan, S. Tamil. "Comparison analysis of three value logic 8T CNTFET SRAM Cell with 6 CMOS SRAM CELL at 32nm technology." International Journal of Reconfigurable and Embedded Systems (IJRES) 8, no. 2 (July 1, 2019): 107. http://dx.doi.org/10.11591/ijres.v8.i2.pp107-113.

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This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.

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39

Arul, P., and K. Helen Prabha. "A Comprehensive Analysis of Short Channel Effects on Carbon Nano Tube Field Effect Transistors." Journal of Nanoelectronics and Optoelectronics 16, no. 12 (December 1, 2021): 1905–12. http://dx.doi.org/10.1166/jno.2021.3144.

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As the direction of World health organization (WHO) report the diseases like male infertility, brain tumor, hearing impairment, fetus issues, effect on eyes and other various parts of the human body caused by harmful radiations released by portable electronic devices. To reduce radiation and size, a deep scaling has been applied on MOSFETs. Due to this aggressive scaling MOSFET devices are affected by Short Channel Effects (SCE) in Nanometer regime (<10 nm). The Short Channel Effects Such as Subthreshold Swing (SS), Drain Induced barrier Lowering (DIBL) and threshold voltage roll-off (VT), plays a key role in determining the performance of CMOS devices. At Nano-meter scale Carbon Nano Tube FETs (CNTFETs) devices might be furnished with good control on leakage current and power consumption. The comparative analysis of Subthreshold Swing (SS), Drain Induced Barrier Lowering (DIBL) and Ion/Ioff ratio on Conventional Single Gate MOSFET (C-MOSFET), Double Gate MOSFET (DG-MOSFET) and CNTFET devices are presented in this paper. The results of comparative analysis show that CNTFET exhibits 133% times more Ion/Ioff ratio than MOSFET and very less change in Subthreshold swing and DIBL.

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40

Yasir, Mohd, and Naushad Alam. "Design of CNTFET-Based CCII Using gm/ID Technique for Low-Voltage and Low-Power Applications." Journal of Circuits, Systems and Computers 29, no. 09 (November 27, 2019): 2050143. http://dx.doi.org/10.1142/s0218126620501431.

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This paper introduces for the first time all the steps required in the optimal design of carbon nanotube field-effect transistor (CNTFET)-based second generation current conveyor (CCII) using transconductance-to-drain current ratio ([Formula: see text]) technique for low-voltage (LV) and low-power (LP) applications. The [Formula: see text] technique is a well-established methodology for CMOS analog IC design. However, the difference between CMOS and CNTFET is that CMOS has continuous width while the width of CNTFET is discrete and depends on different parameters like the number of tubes, pitch and diameter ([Formula: see text]) of the carbon nanotube (CNT). Therefore, there is a need for a design technique by which one can easily design analog circuits using CNTFETs. The CCII is based on two-stage op-amp and two inverters used as class AB amplifiers. The performance of CCII has been extensively examined in terms of DC, AC and transient responses of node voltages, branch currents and node impedances using HSPICE simulations. The CCII operates at [Formula: see text]0.5[Formula: see text]V and has 172[Formula: see text][Formula: see text]W of power consumption. The designed CCII provides very high 3-dB bandwidth (BW) for current gain ([Formula: see text][Formula: see text]GHz as well as voltage gain ([Formula: see text][Formula: see text]GHz.

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41

Mothes, Sven, Martin Claus, and Michael Schroter. "Toward Linearity in Schottky Barrier CNTFETs." IEEE Transactions on Nanotechnology 14, no. 2 (March 2015): 372–78. http://dx.doi.org/10.1109/tnano.2015.2397696.

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42

Pacheco-Sanchez, Anibal, Florian Fuchs, Sven Mothes, Andreas Zienert, Jorg Schuster, Sibylle Gemming, and Martin Claus. "Feasible Device Architectures for Ultrascaled CNTFETs." IEEE Transactions on Nanotechnology 17, no. 1 (January 2018): 100–107. http://dx.doi.org/10.1109/tnano.2017.2774605.

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43

YOUSEFI, REZA, and SEYYED SALEH GHOREISHI. "A COMPUTATIONAL STUDY OF STRAIN EFFECTS IN THE BAND-TO-BAND-TUNNELING CARBON NANOTUBE FIELD-EFFECT TRANSISTORS." International Journal of Modern Physics B 26, no. 29 (September 27, 2012): 1250155. http://dx.doi.org/10.1142/s021797921250155x.

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In this paper, the transport properties of the band-to-band-tunneling carbon nanotube field-effect transistors (BTBT-CNTFETs) under uniaxial strain are studied, with the nonequilibrium Green's function (NEGF) formalism. The effects of the uniaxial strain on the electrical properties, such as the ON current (I ON ), OFF current (I OFF ), I ON /I OFF ratio, subthreshold swing and intrinsic delay are evaluated. It was observed that the uniaxial strain has strong effects on the transport properties of these transistors. The results show that appropriate uniaxial strain, although degrades the ON current and the intrinsic delay, it also decreases the power consumption of the BTBT-CNTFETs and as a result can be used for low-power applications.

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44

Ding, Li, Zhiyong Zhang, Jun Su, Qunqing Li, and Lian-Mao Peng. "Exploration of yttria films as gate dielectrics in sub-50 nm carbon nanotube field-effect transistors." Nanoscale 6, no. 19 (2014): 11316–21. http://dx.doi.org/10.1039/c4nr03475a.

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45

Masoumi, Saeid, Hassan Hajghassem, Alireza Erfanian, and Ahmad Molaei Rad. "Design and manufacture of TNT explosives detector sensors based on CNTFET." Sensor Review 36, no. 4 (September 19, 2016): 414–20. http://dx.doi.org/10.1108/sr-01-2016-0014.

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Purpose Miniaturized smart sensors that can perform sensitive and selective real-time monitoring of target analytes are tremendously valuable for various sensing applications. So, the purpose of this paper is to provide details of sensors based on selective nanocoatings by combining trinitrotoluene (TNT) receptors bound to conjugated polydiacetylene (PDA) polymers with single-walled carbon nanotube field-effect transistors (CNTFETs) for detecting explosives TNT. Design/methodology/approach Following an introduction, this paper describes the way of creating an FET with CNTs, which are functionalized by the peptide based on TNT molecule recognition elements and PDA, to offer a system which has the capability of answering the presence of related target molecules (TNT). Finally, brief conclusions are drawn. Findings Single-wall nanotubes and reduced graphene oxide are interesting materials for creating biosensors of FETs at nanoscale because of unique electrical, mechanical, geometrical and biocompatible properties. Therefore, this sensor is designed and manufactured, and the results of applying TNT to sensor show good sensitivity and selectivity response. Originality/value In this timeframe of history, sensors based on CNTFET are required for different uses, including clinical diagnosis technologies, environmental tests and bioterrorism recognition technologies, that correspond to the military conflicts and terrorism. So, CNTFET sensor design provides real-time detection of TNT explosives.

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46

Ghabri, Houda, Dalenda Ben Issa, and Hekmet Samet. "New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2019): 189. http://dx.doi.org/10.11591/ijres.v7.i3.pp189-196.

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The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.

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47

Ghabri, Houda, Dalenda Ben Issa, and Hekmet Samet. "New Optimized Reconfigurable ALU Design Based on DG-CNTFET Nanotechnology." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2019): 195. http://dx.doi.org/10.11591/ijres.v7.i3.pp195-202.

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Анотація:

The heart of the microprocessor and responsible for the execution of logical and arithmetic operations, the arithmetic and logical unit is constantly optimized. The performance is improved to allow the development of more powerful and smaller circuits. This paper describes simple ALU but contains the essentials functions. It is a reconfigurable ALU based on double-gate carbon nanotube field effect transistor (DG-CNTFETs). This transistor has an interesting property, it can switch from p- to n- type behavior and vice-versa dynamically. This opens the opportunity for building novel and complex functions in fine-grain reconfigurable logic inaccessible to MOSFETs and reaching a good performance levels. In literature there are several problems related to signal quality. In this paper, we will propose a new solution that allows us to improve the quality of the output signal without affecting the number of transistors used. This improves the overall performance of ALU. We will show the improvement in signal level and quality. First, an overview of carbon nanotube field-effect transistor (CNTFET) and state of the art Reconfigurable ALU based on DG-CNTFET is given. Then an explication of signal integrity issues of the actual Reconfigurable DG-CNTFET cell is done. After we will present and explain the proposed solution. The solution is first applied on the cnt_9T circuit then will show its effect on the ALU. Finally, a performance comparison is made.

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48

Kumar, Nandhaiahgari Dinesh, Rajendra Prasad Somineni, and CH Raja Kumari. "Design and analysis of different full adder cells using new technologies." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 2 (July 1, 2020): 116. http://dx.doi.org/10.11591/ijres.v9.i2.pp116-124.

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Анотація:

CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.

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49

Marani, R., G. Gelao, and A. G. Perri. "A Compact Noise Model for C-CNTFETs." ECS Journal of Solid State Science and Technology 6, no. 4 (2017): M44—M49. http://dx.doi.org/10.1149/2.0341704jss.

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50

Fediai, Artem, Dmitry A. Ryndyk, Gotthard Seifert, Sven Mothes, Martin Claus, Michael Schröter, and Gianaurelio Cuniberti. "Towards an optimal contact metal for CNTFETs." Nanoscale 8, no. 19 (2016): 10240–51. http://dx.doi.org/10.1039/c6nr01012a.

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