Дисертації з теми "CMOS interface"

The objective of this thesis is to introduce an alternative temperature sensor in CMOS technology with small area, low power consumption, and high resolution that can be easily interfaced. A novel temperature sensor utilizing the interface–trap charge pumping phenomenon and the temperature sensitivity of generation current is proposed. This thesis presents the design and characterization of the proposed temperature sensor fabricated in 0.18µm CMOS technology. The prototype sensor is characterized for the temperature range of 27oC–120oC. It has frequency output and exhibits linear transfer characteristics, high sensitivity, and high resolution. This temperature sensor is proposed for microprocessor thermal management applications.

The high-performance accelerometers with micro-gravity resolution and large dynamic range at very low frequencies are not only used in GPS-augmented inertial navigation, monitoring of aircrafts and space station, but also used in monitoring wind turbines for green energy. This dissertation presents the design and development of a mixed-signal, low-noise, and fourth-order sigma-delta interface circuit for the MEMS capacitive micro-gravity accelerometer. A fully-differential switched-capacitor (SC) amplifier architecture is developed with the low-frequency noise reduction through the integration of chopper-stabilization technique with lateral BJT at input stage. The effectiveness of different noise reduction techniques is also compared and verified. The application of fourth-order SC sigma-delta modulation concept to the inertial-grade accelerometer is to achieve the benefits of the digitization of the accelerometer output without compromising the resolution of the analog front-end. This open-loop interface provides 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power dissipation and maximum dynamic range. The micromechanical accelerometers are fabricated in thick silicon-on-insulator (SOI) substrates. The accelerometer operates in air and is designed for non-peaking response with a bandwidth of 500 Hz.

This thesis reports the development and analysis of high performance CMOS readout electronics for increasing the performance of MEMS gyroscopes developed at Middle East Technical University (METU). These readout electronics are based on unity gain buffers implemented with source followers. High impedance node biasing problem present in capacitive interfaces is solved with the implementation of a transistor operating in the subthreshold region. A generalized fully differential gyroscope model with force feedback electrodes has been developed in order to simulate the capacitive interfaces with the model of the gyroscope. This model is simplified for the single ended gyroscopes fabricated at METU, and simulations of resonance characteristics are done. Three gyroscope interfaces are designed by considering the problems faced in previous interface architectures. The first design is implemented using a single ended source follower biased with a subthreshold transistor. From the simulations, it is observed that biasing impedances up to several gigaohms can be achieved. The second design is the fully differential version of the first design with the addition of a self biasing scheme. In another interface, the second design is modified with an instrumentation amplifier which is used for fully differential to single ended conversion. All of these interfaces are fabricated in a standard 0.6 µ
m CMOS process. Fabricated interfaces are characterized by measuring their ac responses, noise response and transient characteristics for a sinusoidal input. It is observed that, biasing impedances up to 60 gigaohms can be obtained with subthreshold transistors. Self biasing architecture eliminates the need for biasing the source of the subthreshold transistor to set the output dc point to 0 V. Single ended SOG gyroscopes are characterized with the single ended capacitive interfaces, and a 45 dB gain improvement is observed with the addition of capacitive interface to the drive mode. Minimum resolvable capacitance change and displacement that can be measured are found to be 58.31 zF and 38.87 Fermi, respectively. The scale factor of the gyroscope is found to be 1.97 mV/(°
/sec) with a nonlinearity of only 0.001% in ±
100 °
/sec measurement range. The bias instability and angle random walk of the gyroscope are determined using Allan variance method as 2.158 °
/&
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hr and 124.7 °
/hr, respectively.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
Includes bibliographical references (p. 95-98).
A carbon nanotube is considered as a candidate for a next-generation chemical sensor. CNT sensors are attractive as they allow room-temperature sensing of chemicals. From the system perspective, this signifies that the sensor system does not require any micro hotplates, which are one of the major sources of power dissipation in other types of sensor systems. Nevertheless, a poor control of the CNT resistance poses a constraint on the attainable energy efficiency of the sensor platform. An investigation on the CNT sensors shows that the dynamic range of the interface should be 17 bits, while the resolution at each base resistance should be 7 bits. The proposed CMOS interface extends upon the previously published work to optimize the energy performance through both the architecture and circuit level innovations. The 17-bit dynamic range is attained by distributing the requirement into a 10-bit Analog-to-Digital Converter (ADC) and a 8-bit Digital-to-Analog Converter (DAC). An extra 1-bit leaves room for any unaccounted subblock performance error. Several system-level all-digital calibration schemes are proposed to account for DAC nonlinearity, ADC offset voltage, and a large variation in CNT base resistance. Circuit level techniques are employed to decrease the leakage current in the sensitive frontend node, to decrease the energy consumption of the ADC, and to efficiently control the DAC. The interface circuit is fabricated in 0.18 /m CMOS technology, and can operate at 1.83 kS/s sampling rate at 32 pW worst case power. The resistance measurement error across the whole dynamic range is less than 1.34% after calibration. A functionality of the full chemical sensor system has been demonstrated to validate the concepts introduced in this thesis.
by Taeg Sang Cho.
S.M.

With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC. In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation. Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent. With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%. As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result. With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.

Negli ultimi anni i dispositivi mobili sono molto complessi e ricchi di funzionalità che consumano molta energia. Per questo motivo, l'industria elettronica sta spingendo verso la riduzione del consumo di energia e corrente nei dispositivi elettronici per aumentare la durata della batteria. Tutto va fatto mantenendo le stesse prestazioni o migliorandole. Questa tesi presenta un accurato generatore di riferimento di tensione per interfaccia audio in tecnologia CMOS a 65/55nm e particolare attenzione è stata posta al consumo di corrente. Il riferimento è costituito da un riferimento di tensione Bandgap e da un regolatore Low Dropout. La topologia scelta per il bandgap è un bandgap in modalità di corrente con resistore di uscita regolabile. Ciò garantisce una tensione di riferimento inferiore a 1.2V grazie alla somma di due correnti invece di due tensioni. È stato scelto un doppio circuito per il regolatore LDO per garantire una rapida risposta ai transitori. Innanzitutto, il generatore di riferimento di tensione è stato simulato in tecnologia CMOS a 65nm. Nelle simulazioni a 65 nm tutte le specifiche mirate sono state raggiunte con successo. Per BG, il consumo di corrente è inferiore a 5uA, DC PSR inferiore a -60dB e un coefficiente di temperatura di circa 5ppm/°C. L'LDO ha un tempo di assestamento inferiore a 150ns, un PSR inferiore a -70dB nella banda audio ([20, 20K]Hz) e un consumo energetico inferiore a 10uA. Quindi, è stato simulato e misurato con la tecnologia CMOS a 55nm e sono stati sviluppati e testati tre diversi prototipi. I risultati non sono buoni come quelli a 65nm perché questa è stata la prima volta che la tecnologia è stata utilizzata. Quindi, i tre chip di test sviluppati sono stati utilizzati per comprendere il comportamento della tecnologia e per confrontare le simulazioni con le misurazioni, ma ogni chip di test rappresenta un miglioramento rispetto al precedente. L'ultimo chip di prova presenta un PSR molto vicino alle specifiche sia per il BG che per l’LDO e un consumo di corrente di 5uA per il BG, 10uA per l’LDO NM e 5uA per l’LDO LP.
In recent years, mobile devices are very complex and feature-rich that consume a lot of energy. For this reason, the electronics industry is pushing towards reducing power and current consumption in electronic devices to increase battery life. Everything has to be done while maintaining the same performance or improving it. This thesis presents an accurate voltage reference generator for audio interface in CMOS technology at 65/55nm and particular attention has been paid to current consumption. The reference is made up of a Bandgap voltage reference and a Low Dropout regulator. The topology chosen for the bandgap is a current mode bandgap with adjustable output resistor. This guarantees a reference voltage of less than 1.2V thanks to the sum of two currents instead of two voltages. A double loop was chosen for the LDO regulator to ensure rapid transient response. First, the voltage reference generator was simulated in CMOS technology at 65nm. In the 65nm simulations all targeted specifications were successfully achieved. For BG, power consumption is less than 5uA, DC PSR lower than -60dB and a temperature coefficient around 5ppm/°C. The LDO has a fast settling time lower 150ns, a PSR of less than -70dB in the audio band ([20, 20K]Hz) and a power consumption of less than 10uA. Then, it was simulated and measured with 55nm CMOS technology and three different prototypes were developed and tested. The results are not as good as the 65 nm results because this was the first time the technology was used. Then, the three developed test chips were used to understand the behavior of the technology and to compare simulations with measurements, but each test chip is an improvement on the previous one. The latest test chip features PSR very close to specifications for BG and LDO and power consumption of 5uA for the BG, 10uA for the LDO NM and 5uA for the LDO LP.

MEMS accelerometers are quickly approaching navigation grade performance and navigation market for MEMS accelerometer systems are expected to grow in the recent years. Compared to conventional accelerometers, these micromachined sensors are smaller and more durable but are generally worse in terms of noise and dynamic range performance. Since MEMS accelerometers are already dominant in the tactical and consumer electronics market, as they are in all modern smart phones today, there is significant demand for MEMS accelerometers that can reach navigation grade performance without significantly altering the developed process technologies. This research aims to improve the performance of previously fabricated and well-known MEMS capacitive closed loop &Sigma
&Delta
accelerometer systems to navigation grade performance levels. This goal will be achieved by reducing accelerometer noise level through significant changes in the system architecture and implementation of a new electronic interface readout ASIC. A flexible fourth order &Sigma
&Delta
modulator was chosen as the implementation of the electro-mechanical closed loop system, and the burden of noise shaping in the modulator was shifted from the mechanical sensor to the programmable electronic readout. A novel operational transconductance amplifier (OTA) was also designed for circuit implementation of the electronic interface readout. Design and fabrication of the readout was done in a standard 0.35 µ
m CMOS technology. With the newly designed and fabricated readout, single-axis accelerometers were implemented and tested for performance levels in 1g range. The implemented system achieves 5.95 µ
g/sqrt Hz, 6.4 µ
g bias drift, 131.7 dB dynamic range and up to 37.2 g full scale range with previously fabricated dissolved epitaxial wafer process (DEWP) accelerometers in METU MEMS facilities. Compared to a previous implementation with the same accelerometer element reporting 153 µ
g/sqrtHz, 50 µ
g bias drift, 106.8 dB dynamic range and 33.5 g full scale range
this research reports a 25 fold improvement in noise, 24 dB improvement in dynamic range and removal of the deadzone region.

O desenvolvimento de tecnologias de integração para circuitos integrados junto com a demanda de cada vez mais processamento digital de sinais, como em sistemas de telecomunicações e aplicações SOC, resultaram na crescente necessidade de circuitos mistos em tecnologia CMOS integrados em um único chip. Em um trabalho anterior, a arquitetura de uma interface analógica para ser usada em aplicações SOC mistas foi desenvolvida e implementada. Basicamente esta interface é composta por uma célula analógica fixa (fixed analog cell – FAC), que translada o sinal de entrada para uma freqüência de processamento fixa, e por um bloco digital que processa este sinal. Primeiramente, as especificações de sistema foram determinadas considerando o processamento de sinais de três bandas de freqüência diferentes: FM, vídeo e celular, seguido por simulações de alto-nível do sistema da FAC. Então, uma arquitetura heteródina integrada CMOS para o front-end que integrará a FAC, composto por 2 mixers ativos e um amplificador de ganho variável, foi apresentada, enumerando-se e propondo-se soluções para os desafios de projeto e metodologia. Os blocos analógicos/RF, juntamente com o front-end, foram projetados e implementados em tecnologia CMOS IBM 0.18μm, apresentando-se simulações e medidas de um protótipo físico.
The development of IC technologies coupled with the demand for more digital signal processing integrated in a single chip has created an increasing need for design of mixed-signal systems in CMOS technology. Previously, a general analog interface architecture targeted to mixed-signal systems on-chip applications was developed and implemented, which is composed by a fixed analog cell (FAC), that translates the input signal to a processing frequency, and a digital block, that processes the signal. The focus of this thesis is to analyze, design and implement analog/RF building blocks suitable for this system. First, a set of system specifications is developed and verified through system level simulations for the FAC system, aiming the signal processing of three target applications: FM, video and digital cellular frequency bands. Then, a fully CMOS integrated dual-conversion heterodyne front-end architecture with 2 active mixers and a variable-gain amplifier is presented, enumerating and proposing solutions for the design challenges and methodology. The stand-alone building blocks and the front-end system are designed and implemented in IBM 0.18μm CMOS process, presenting simulations and experimental data from an actual physical prototype.

This work investigates the interface between a video sensor and a low bandwidth radio transmitter. In the context of a low-cost low-power radio video link, it outlines a hardware minimal solution. To solve the bandwidth conflict between the low power radio links and even a modest image sequence quality, a broad range of digital coding techniques are evaluated. Aspects of the coding methods other than the compression ratios they offer and the ability to implement them using minimal hardware are considered (in particular how vulnerable they leave the coded data to corruption through transmission errors). Through software simulation, implementations of the two most promising compression techniques: color quantisation with error-diffusion and localised differential predictive coding (DPCM) are further investigated. Particular emphasis is placed on implementation of the software algorithms using architectures close to those of the simplest hardware implementations. Implementation of the localised DPCM scheme is dropped on the grounds that its lossless implementation cannot offer sufficient compression, and that a lossy implementation would be too expensive in terms of the required memory. Colour quantisation with error diffusion is further pursued in the hardware implementation of two algorithms in the form of a field-programmable gate-array (FPGA). Results from the FPGA offer subjective analysis of the algorithms output at higher frame rate and the successful implementation of the architecture demonstrates the suitability to hardware implementation. A framework that was developed to allow comprehensive subjectivity testing of image processing algorithms is described and results, although statistically insignificant, are given. In evaluating the importance of the colour quantisation with error diffusion amongst other compression and coding techniques, this work concludes that where hardware is at a premium and strict viewing requirements can be met, there are applications where it can be applied profitably, offering results comparable with much more complicated solutions.

L'amélioration continue des performances, de la sécurité et de l'économie d'énergie exige la présence de capteurs de plus en plus nombreux. Cette thèse propose un système de mesure dédié aux capteurs capacitifs dans les domaines de l'automobile et du grand public. Elle se base sur un modulateur sigma delta d'ordre deux associé à un capteur de température et un calibrage en deux points par PROM. La linéarisation de la caractéristique du capteur est assurée par un CNA de retour multibits. Un circuit a été conçu en technologie CMOS standard pour la réalisation d'une sonde de mesure d'humidité relative à partir d'un capteur commercial discret
The continous improvement of performences, secutity and power efficiency lead to the growth of sensors interaction in many applications. This thesis reports on a capacitive sensor interaction for automotive and public applications. It is based on a two-points calibration by PROM while the linear behaviour of the sensor characteristics is achieved thanks to a modular multibits technology to build a relative humidity probe from a commercial discret sensor

Nesta dissertação, é apresentado o projeto de uma interface que permite o controle e monitoramento de cargas de alta tensão alimentadas na faixa de 8,5V a 35V. A interface fornece duas funções básicas: a primeira é permitir que circuitos alimentados no domínio dos 5V controlem o chaveamento de transistores de potência PMOS com uma tensão de porta 5V abaixo da tensão de alimentação; a segunda é realizar o monitoramento de sobrecorrentes na carga de alta tensão, alertando, com um sinal de baixa tensão, estas ocorrências. A interface foi projetada e fabricada no processo CMOS XC06 - 0,6µm da XFAB, com a inclusão de módulos que permitem o uso de transistores de alta tensão. Como parte da solução proposta, foi analisado, implementado e caracterizado um regulador de tensão flutuante que gera uma tensão de saída 5V abaixo da tensão de alimentação. A área de silício do regulador é de 599µm x 330µm, e as medidas da tensão de saída gerada apresentam variações menores que 10%. Também foi projetado e integrado no mesmo circuito integrado um sensor para medir o nível da tensão flutuante do regulador e comunicar seu estado com um sinal de 5V, este bloco ocupa uma área de 599µm x µm. Este sensor apresentou um desvio padrão de 7% nas medidas da sua tensão limiar. A interface foi integrada em um sensor de proximidade indutivo, permitindo o chaveamento de uma carga de 430pF a 1,2kHz em toda a faixa de alimentação.
This work presents the design of an interface that allow to control and monitoring high voltage loads in the range of 8,5V to 35V. The interface provides two main features, the first one is to allow low voltage circuits supplied with 5V to control the switching of power PMOS transistors with a gate voltage 5V bellow the supply voltage. The second one is monitoring overcurrents on the high voltage load alerting with a low voltage signal these occurences. The interface was designed and fabricated on the CMOS XC06 - 0,6µm process from XFAB with the inclusion of modules that allow the use of high voltage transistors. As part of the proposed solution it was analyzed, implemented and measured a floating voltage regulator wich provides an output voltage 5V bellow the supply voltage. The area of the regulator is 599µm x 330µm and the measures of the output voltage presents variations under the 10%. Also it was designed and integrates in the same integrated circuit a sensor to measure the output level of the floating regulator and communicate the state of this output with a 5V signal, this block occupies an area of 599µm x 579µm. This sensor presented a 7% standard desviation on the measured voltage threashold. The interface was integrated on an inductive proximity sensor allowing the switching of a 430pF load at 1,2kHz for the entire all supply range.

This thesis presents the development of high resolution, wide dynamic range sigma-delta type readout circuits for capacitive MEMS accelerometers. Designed readout circuit employs fully differential closed loop structure with digital output, achieving high oversampling ratio and high resolution. The simulations of the readout circuit together with the accelerometer sensor are performed using the models constructed in Cadence and Matlab Simulink environments. The simulations verified the stability and proper operation of the accelerometer system. The sigma-delta readout circuit is implemented using XFab 0.6 µ
m CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 µ
g/&
#61654
Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed ±
18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 µ
g/&
#61654
Hz of noise level and 74 µ
g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/º
C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.

Thesis (M.S.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Dept. of Electrical and Computer Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

During the last years, material science has been focused on the exploration of the material characteristics at nanoscale. In fact, some materials show different properties only if they are designed with a nanometer structure. Even if they can be used to build macro devices (e.g., tactile surface, strain sensors), the nanostructured materials can reach high sensitivity or accuracy. Thin films [1], nanoparticles [2] and nanowires composites [3] have been widely used thanks to their sensitivity to mechanical strengths [4] or light stimuli [5–7]. In these cases, a large number of nanostructured elements have been merged in a single device to transduce macro-phenomena (e.g., strain, bending, pressure, temperature). Although nanomaterials can be used for standard sensor applications, the aim of nanotechnology is to exploit the dimension of the basic elements (e.g., nanoparticles) to conceive innovative applications at nanoscale. In order to exploit the ultra-small dimension of these materials, researchers addressed the development of nanodevices including only a single nanostructured element to increase sensitivity and accuracy. Nanomaterials, such as nanowires (NWs), bridging molecules or nanoparticles, are considered the basis for a new generation of bio-sensors able to interact with gases [8, 9], molecules (e.g., DNA molecules) or other bio-substances at nanoscale. Some examples are the lab-on-chip designed to implement drug detection using functionalized CNT [10] and the Electronic Nose able to identify different gas molecules [11]. The fabrication process of a nanosensor (or nanodevice) mainly consists in the integration of nanomaterials (previously synthesized for achieving the desired functionality) with metal electrodes. The fabrication process is actually complex and implies high costs. Different techniques can be used to connect nanomaterial with metal electrodes and, then, to the custom electronic interface. The most used methods for integration involve a stochastic deposition upon interdigitated electrodes [12] or chemical processes to directly grow the nanomaterials in-situ [13] or an electrically controlled deposition of nanomaterials dissolved in liquid solution [14]. The fabricated nanodevice is a passive component and it needs to be connected to a measurement system, involving long cables and therefore high parasitics. Fundamentally, when a nanomaterial is exposed to specific molecules or physical phenomena, its resistance or capacitance changes proportionally to the sensed quantity. Thus, the larger the variation of the resistance or capacitance of nanomaterials, the higher the sensitivity to specific phenomena. The electronic interface for passive nanosensors should be able to stimulate the nanomaterial and convert the large variation of its electrical characteristics to analog or digital signals compliant with commercial electronics. The nanomaterial signal is usually a current in the pA-μA range and the noise coupling, due to long interconnections, can easily affect the whole nanodevice sensitivity. Hence, a new approach for the nanosensor fabrication and for the read-out is strictly required to cut fabrication costs and improve measurement accuracy. The electronic interface needs to be placed as close as possible to avoid interferences at the interconnection cables. Anyway, the read-out system has also to overcome flicker-noise effects during DC or low-frequency measurements. In addition to the issues related to the measurement accuracy, a single nanosensor is not sufficient to produce reliable results because of the process variation in nanomaterial synthesis and nanodevice fabrication. Thus, an array of nanosensors is strongly suggested because a large number of nanodevices compensates the defects in single nanosensor fabrication. The measurement system provides the final results performing an average calculation of the nanosensor outputs. Actually, if the final aim is a complex system as the Electronic Nose [15] (i.e., an integrated multi-sensors system) or a bio-sensors for blood analysis [16], an array of nanosensors is strictly required given that different molecules have to be detected and average measurements are mandatory. This PhD thesis reports about a flexible platform implemented in CMOS technology for conceiving a Micro-for-Nano (M4N) system where nanosensors and microelectronics coexist on the same chip. The nanomaterial integration process (Chapter 2, Chapter 3), the read-out circuits for nanosensor interface (Chapter 4, Chapter 5) and the architecture to handle large number of integrated nanosensors (Chapter 6) will be described in the following chapters. The M4N project has been developed in collaboration with the Italian Institute of Tecnology (IIT@PoliTO), which has supported all the experiments needed to set-up the integration process and to characterize the designed CMOS circuits.

As one of the major building blocks in a wireless receiver, the Analog-to-Digital Interface (ADI) provides link and transition between the analog Radio Frequency (RF) frontend and the baseband Digital Signal Processing (DSP) module. The rapid development of the radio technologies raises new design challenges for the receiver ADI implementation. Requirements, such as power consumption optimization, multi-standard compatibility, fast settling capability and wide signal bandwidth capacity, are often encountered in a low voltage ADI design environment. Previous research offers ADI design schemes that emphasize individual merit. A systematic ADI design methodology is, however, not suffciently studied. In this work, the ADI design for two receiver systems are employed as research vehicles to provide solutions for different ADI design issues. A zero-crossing demodulator ADI is designed in the 0.35µm CMOS technology for the Bluetooth receiver to provide fast settling. Architectural level modification improves the process variation and the Local Oscillation (LO) frequency offset immunity of the demodulator. A 16.2dB Signal-to-Noise Ratio (SNR) at 0.1% Bit Error Rate (BER) is achieved with less than 9mW power dissipation in the lab measurement. For ADI in the 802.11b/Bluetooth dual-mode receiver, a configurable time-interleaved pipeline Analog-to-Digital-Converter (ADC) structure is adopted to provide the required multi-standard compatibility. An online digital calibration scheme is also proposed to compensate process variation and mismatching. The prototype chip is fabricated in the 0.25µm BiCMOS technology. Experimentally, an SNR of 60dB and 64dB are obtained under the 802.11b and Bluetooth receiving modes, respectively. The power consumption of the ADI is 20.2mW under the 802.11b receiving mode and 14.8mW under the Bluetooth mode. In this dissertation, each step of the receiver ADI design procedure, from system level optimization to the transistor level implementation and lab measurement, is illustrated in detail. The observations are carefully studied to provide insight on receiver ADI design issues. The ADI design for the Ultra-Wide Band (UWB) receiver is also studied at system level. Potential ADI structure is proposed to satisfy the wide signal bandwidth and high speed requirement for future applications.

L’ingénierie neuromorphique est un nouveau champ disciplinaire en plein essor qui fait appel à des compétences en électronique, mathématiques, informatique et en ingénierie biomorphique dans le but de produire des réseaux de neurones artificiels capables de traiter les informations à la manière du cerveau humain. Ainsi, les systèmes neuromorphiques offrent non seulement des solutions plus performantes et efficientes que les technologies actuelles de traitement de l’information mais permettent également d’envisager le développement de stratégies thérapeutiques inédites dans le cadre de dysfonctionnements cérébraux pathologiques. Le groupe Circuits Systèmes Applications des Micro-ondes (CSAM) de l’Institut d’Electronique, de Microélectronique et de Nanotechnologies (IEMN) dans lequel ces travaux de thèse ont été effectués a contribué à l’émergence de ces systèmes neuromorphiques en développant une boîte à outils complète de neurones et synapses artificiels. Pour intégrer l’ingénierie neuromorphique dans la prise en charge de dysfonctionnements neuronaux pathologiques, il convient d’interfacer les neurones artificiels et les neurones vivants afin d’assurer une communication réelle entre ces différents composants. Dans ce contexte, et en utilisant les outils innovants développés par le groupe CSAM, l’objectif de ce travail de thèse a été de concevoir et réaliser une interface fonctionnelle permettant d’établir une boucle de communication bidirectionnelle entre des neurones artificiels et des neurones vivants. Les neurones artificiels développés par le groupe CSAM sont réalisés en technologie CMOS et capables d’émettre des signaux électriques biomimétiques. Les neurones vivants sont issus de cellules PC12 différenciées. Une première étape de ce travail a consisté à modéliser et à simuler cette interface entre neurones artificiels et vivants ; une deuxième partie de la thèse a été dédiée à la fabrication et à la caractérisation d’interfaces neurobiohybrides, ainsi qu’à la croissance et à la caractérisation de neurones vivants, avant d’étudier leur capacité à communiquer avec des neurones artificiels. Ainsi, un modèle de membrane neuronale représentant un neurone vivant interfacé avec une électrode métallique planaire a été développé. L’exploitation de ce modèle a permis de montrer qu’il est possible de stimuler des neurones vivants en utilisant les signaux biomimétiques issus du modèle de neurones artificiels tout en conservant des tensions d’excitation faibles. L’utilisation de faibles tensions d’excitation permettrait d’améliorer l’efficacité énergétique des systèmes neurobiohybrides intégrant des neurones artificiels et d’amoindrir le risque d’endommager les tissus vivants. Ensuite, le neurobiohybride permettant d’interfacer les neurones vivants et les neurones artificiels a été conçu et réalisé. Une caractérisation expérimentale de cette interface a permis de valider l’approche consistant à exciter un neurone vivant au travers d’une électrode métallique planaire. Enfin, des cellules neuronales vivantes issues de cellules PC-12 ont été cultivées et différenciées dans les neurobiohybrides. Une preuve expérimentale de la capacité des signaux électriques biomimétiques produits par les neurones artificiels a ainsi pu être apportée par la technique d’imagerie calcique. En conclusion, les travaux présentés dans ce manuscrit établissent clairement la preuve de concept de l’excitation de neurones vivants par un signal biomimétique dans nos conditions expérimentales et étayent ainsi la première partie de la boucle de communication bidirectionnelle entre neurones artificiels et neurones vivants
Neuromorphic engineering is an exciting emerging new field, which combines skills in electronics, mathematics, computer sciences and biomorphic engineering with the aim of developing artificial neuronal networks capable of reproducing the brain’s data processing. Thus, neuromorphic systems not only offer more effective and energy efficient solutions than current data processing technologies, but also set the bases for developing novel original therapeutic strategies in the context of pathological brain dysfunctions. The research group Circuits Systèmes Applications des Micro-ondes (CSAM) of the Institute for Electronics, Microelectronics and Nanotechnologies (IEMN) in Lille, in which this thesis work was carried out, has contributed to the generation of such neuromorphic systems by developing a toolbox constituted of artificial neurons and synapses. In order to implement neuromorphic engineering in the therapeutic arsenal for treating neurologic disorders, we need to interface living and artificial neurons to ensure real communication between these different components. In this context and using the original tools developed by the CSAM group, the main goal of this thesis work was to design and produce a functional interface allowing a bidirectional communication loop to be established between living and artificial neurons. These artificial neurons have been developed by the CSAM group using CMOS technology and are able to emit biomimetic electrical signals. Living neurons were obtained from differentiated PC-12 cells. A first step in this work consisted in modeling and simulating this interface between artificial and living neurons; a second part of the thesis was dedicated to the fabrication and characterization of neurobiohybrid interfaces, and to the growth and characterization of living neurons before studying their capacities to communicate with artificial neurons. First, a model of neuronal membrane representing a living neuron interfaced with a metallic planar electrode has been developed. We thus showed that it is possible to excite neurons using biomimetic signals produced by artificial neurons while maintaining a low excitation voltage. Low voltage excitation would improve energy efficiency of neurobiohybrid systems integrating artificial neurons and reduce the impact of harmful electrical signals on living neurons. Then, the neurobiohybrid interfacing living and artificial neurons has been designed and produced. The results obtained by experimental characterization of this interface validate the approach consisting in exciting living neurons through a metallic planar electrode. Finally, living neurons from PC-12 cells were grown and differentiated directly onto neurobiohybrids. Then, an experimental proof of the ability of biomimetic electrical signals to excite living neurons was obtained using calcium imaging. To conclude, the work presented in this manuscript clearly establishes a proof of concept for the excitation of living neurons using a biomimetic signal in our experimental conditions and thus substantiates the first part of the bidirectional communication loop between artificial neurons and living neurons

This dissertation reports a high-speed wideband wireless transmission solution for the tight power constraints of cortical interface application. The proposed system deploysImpulse Radio Ultra-wideband (IR-UWB) technique to achieve very high-rate communication. However, impulse radio signals suffer from significant attenuation within the body,and power limitations force the use of very low-power receiver circuits which introduce additional noise and jitter. Moreover, the coils’ self-resonance has to be suppressed to minimize the pulse distortion and inter-symbol interference, adding significant attenuation. To compensate these losses, an Error correction code (ECC) layer is added for functioning reliably to the system. The performance evaluation is made by modeling a pair of physically fabricated coils, and the results show that the ECC is essential to obtain the system’s reliability. Furthermore, the gm/ID methodology, which is based on the complete exploration ofall inversion regions that the transistors are biased, is studied and explored for optimizingthe system at the circuit-level. Specific focuses are on the RF blocks: the low noise am-plifier (LNA) and the injection-locked voltage controlled oscillator (IL-VCO). Through the analytical deduction of the circuit’s features as the function of the gm/ID for each transistor, it is possible to select the optimum operating region for the circuit to achieve the target specification. Other circuit blocks, including the phase shifter, frequency divider,mixer, etc. are also described and analyzed. The prototype is fabricated in a 65-nm CMOS(Complementary Metal-Oxide-Semiconductor) process.

La réglementation mondiale, pour des appareils de courte portée, permet l’utilisation sans licence de plusieurs Gigahertz de bande autour de 60 GHz. La bande des 60 GHz répond aux besoins des applications telles que les réseaux de capteurs très haut débit autonome en énergie,ou les transmissions à plusieurs Gbit/s avec des contraintes de consommation d’énergie. Il y a encore peu de temps, les interfaces radios fonctionnant dans la bande millimétrique n’étaient réalisables qu’en utilisant des technologies III-V couteuses. Aujourd’hui, les avancées des technologies CMOS nanométriques permettent la conception et la production en masse des circuits intégrées radiofréquences (RFIC) à faible coût.Cette thèse s’inscrit dans des travaux de recherches dédiés à la réalisation d’un système dans un boîtier (SiP, System in Package) à 60 GHz contenant à la fois l’interface radio (bande de base et circuits RF) ainsi qu’un réseau d’antennes. La première partie de cette thèse est dédiée la conception de la tête RF de l’émetteur-récepteur à faible consommation pour l’interface radio. Les blocs clefs de cette tête RF (amplificateurs, mélangeurs et un oscillateur commandé en tension) sont conçus, réalisés et mesurés en utilisant la technologie CMOS 65 nm de ST Microelectronics. Des éléments actifs et passifs sont développés spécifiquement pour l’utilisation au sein de ces blocs. Une étape importante vers l’intégration de la tête RF complète de l’émetteur-récepteur est l’assemblage de ces blocs de base afin de réaliser une puce émetteur et une puce récepteur. A ce but, une tête RF pour le récepteur a été réalisée. Ce circuit présent une consommation et un encombrement plus réduit que l’état de l’art.La deuxième partie de cette thèse présente le développement des modèles comportementaux des blocs de base conçus. Ces modèles au niveau système sont nécessaires afin de simuler le comportement du SIP, qui devient trop complexe si des modèles détaillés du niveau circuitsont utilisés. Dans cette thèse, une nouvelle technique modélisant le comportement en régime transitoire et régime permanent ainsi que le bruit de phase des oscillateurs commandés en tension est proposée. Ce modèle est implémenté dans le langage de description de matérielVHDL-AMS. La technique proposée utilise des réseaux de neurones artificiels pour approximer la caractéristique non linéaire du circuit. La dynamique est décrite dans l’espace d’état. Grâce à ce modèle, il est possible de réduire d’une façon drastique le temps de calcul des simulations système tout en conservant une excellente précision
Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs)at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form basic transmitter and receiver chips. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished.The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemented. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy

This dissertation presents the design and development of a mixed-signal low noise second-order integrated circuit (IC) for the open-loop and closed-loop operation of integrated capacitive micro- and nano-gravity accelerometers. The micromechanical accelerometers are fabricated in thick (less than 100 m) silicon-on-insulator (SOI) substrates. The IC provides the 1-bit digital output stream and has the versatility of interfacing sensors with different sensitivities while maintaining minimum power consumption (less than 5 mW) and maximum dynamic range (90 dB). A fully-differential sampled-data scheme is deployed with the ability of low-frequency noise reduction through the use of correlated double sampling (CDS) scheme. In this work, the measured resolution of the closed-loop CMOS-SOI accelerometer system, in the presence of high background accelerations, is in the micro-g (g: gravity) range. In this design, a second-order SC modulator is cascaded with the accelerometer and the front-end amplifier. The accelerometer operates in air and is designed for non-peaking response with a BW-3dB of 500 Hz. A 22 dB improvement in noise and hence dynamic range is achieved with a sampling clock of 40 kHz corresponding to a low oversampling ratio (OSR) of 40. The interface IC consumed a current of 1.5 mA from a supply of 3 V.

Neuronal networks are at the base of information processing in the brain. They are series of interconnected neurons whose activation defines a recognizable linear pathway. The main goal of studying neural ensembles is to characterize the relationship between the stimulus and the individual or general neuronal responses and the relation amongst the electrical activities of neurons within the network, also understanding how topology and connectivity relates to their function. Many techniques have been developed to study these complex systems: single-cell approaches aim to investigate single neurons and their connections with a limited number of other nerve cells; on the opposite side, low-resolution large-scale approaches, such as functional MRI (Magnetic Resonance Imaging) or electroencephalography (EEG), record signal changes in the brain that are generated by large populations of cells. More recently, multisite recording techniques have been developed to overcome the limitations of previous approaches, allowing to record simultaneously from huge neuronal ensembles with high spatial resolution and in different brain regions, i.e. by using implantable semiconductor chips. Local Field Potentials (LFPs), the part of electrophysiological signals that has frequencies below 500 Hz, capture key integrative synaptic processes that cannot be measured by analyzing the spiking activity of few neurons alone. Several studies have used LFPs to investigate cortical network mechanisms involved in sensory processing, motor planning and higher cognitive processes, like memory and perception. LFPs are also promising signals for steering neuroprosthetic devices and for monitoring neural activity even in human beings, since they are more easily and stably recorded in chronic settings than neuronal spikes. In this work, LFP profiles recorded in the rat barrel cortex through high-resolution CMOS-based needle chips are presented and compared to those obtained by means of conventional Ag/AgCl electrodes inserted into glass micropipettes, which are widely used tools in electrophysiology. The rat barrel cortex is a well-known example of topographic mapping where each of the whiskers on the snout of the animal is mapped onto a specific cortical area, called a barrel. The barrel cortex contains the somatosensory representation of the whiskers and forms an early stage of cortical processing for tactile information, along with the trigeminal ganglion and the thalamus. It is an area of great importance for understanding how the cerebral cortex works, since the cortical columns that form the basic building blocks of the neocortex can be actually seen within the barrel. Moreover, the barrel cortex has served as a test-bed system for several new methodologies, partly because of its unique and instantly identifiable form, and partly because the species that have barrels, i.e. rodents, are the most commonly used laboratory mammal. The barrel cortex, the whiskers that activate it and the intervening neural pathways have been increasingly the subject of focus by a growing number of research groups for quite some time. Nowadays, studies (such this one) are directed not only at understanding the barrel cortex itself but also at investigating issues in related fields using the barrel cortex as a base model. In this study, LFP responses were evoked in the target barrel by repeatedly deflecting the corresponding whisker in a controlled fashion, by means of a specifically designed closed-loop piezoelectric bending system triggered by a custom LabView acquisition software. Evoked LFPs generated in the barrel cortex by many consecutive whiskers' stimulations show large variability in shapes and timings. Moreover, anesthetics can deeply affect the profile of evoked responses. This work presents preliminary results on the variability and the effect of commonly used anesthetics on these signals, by comparing the distributions of evoked responses recorded from rats anesthetized with tiletamine-xylazine, which mainly blocks the excitatory NMDA receptors, and urethane, which conversely affects both the excitatory and inhibitory system, in a complex and balanced way yet preserving the synaptic plasticity. Representative signal shape characteristics (e.g., latencies and amplitude of events) extracted from evoked responses acquired from different cortical layers are analyzed and discussed. Statistical distributions of these parameters are estimated for all the different depths, in order to assess the variability of LFPs generated by individual mechanical stimulations of single whiskers along the entire cortical column. Preliminary results showed a great variability in cortical responses, which varied both in latency and amplitude across layers. We found significant difference in the latency of the first principal peak of the responses: under tiletamine-xylazine anesthetic, the responses or events of the evoked LFPs occurred later than the ones recorded while urethane was administered. Furthermore, the distributions of this parameter in all cortical layers were narrower in case of urethane. This behavior should be attributed to the different effects of these two anesthetics on specific synaptic receptors and thus on the encoding and processing of the sensory input information along the cortical pathway. The role of the ongoing basal activity on the modulation of the evoked response was also investigated. To this aim, spontaneous activity was recorded in different cortical layers of the rat barrel cortex under the two types of anesthesia and analyzed in the statistical context of neuronal avalanches. A neuronal avalanche is a cascade of bursts of activity in neural networks, whose size distribution can be approximated by a power law. The event size distribution of neuronal avalanches in cortical networks has been reported to follow a power law of the type P(s)= s^-a, with exponent a close to 1.5, which represent a reflection of long-range spatial correlations in spontaneous neuronal activity. Since negative LFP peaks (nLFPs) originates from the sum of synchronized Action Potentials (AP) from neurons within the vicinity of the recording electrode, we wondered if it were possible to model single nLFPs recorded in the basal activity traces by means of only one electrode as the result of local neuronal avalanches, and thus we analyzed the size (i.e. the amplitude in uV) distribution of these peaks so as to identify a suitable power-law distribution that could describe also these single-electrode records. Finally, the results of the first ever measurements of evoked LFPs within an entire column of the barrel cortex obtained by means of the latest generation of CMOS-based implantable needles, having 256 recording sites arranged into two different array topologies (i.e. 16 x 16 or 4 x 64, pitches in the x- and y-direction of 15 um and 33 um respectively), are presented and discussed. A propagation dynamics of the LFP can be already recognized in these first cortical profiles. In the next future, the use of these semiconductor devices will help, among other things, to understand how degenerating syndromes like Parkinson or Alzheimer evolve, by coupling detected behaviors and symptoms of the disease to neuronal features. Implantable chips could then be used as 'electroceuticals', a newly coined term that describes one of the most promising branch of bioelectronic medicine: they could help in reverting the course of neurodegenerative diseases, by constituting the basis of neural prostheses that physically supports or even functionally trains impaired neuronal ensembles. High-resolution extraction and identification of neural signals will also help to develop complex brain-machine interfaces, which can allow intelligent prostheses to be finely controlled by their wearers and to provide sophisticated feedbacks to those who have lost part of their body or brain functions.
Le reti neuronali sono alla base della codifica dell'informazione cerebrale. L'obiettivo principale dello studio delle popolazioni neuronali è quello di caratterizzare la relazione tra uno stimolo e la risposta individuale o globale dei neuroni e di studiare il rapporto tra le varie attività elettriche dei neuroni appartenenti ad una particolare rete, comprendendo anche come la topologia e la connettività della rete neuronale influiscano sulla loro funzionalità. Fino ad oggi, molte tecniche sono state sviluppate per studiare questi sistemi complessi: studi a singola cellula mirano a studiare singoli neuroni e le loro connessioni con un numero limitato di altre cellule; sul lato opposto, approcci su larga scala e a bassa risoluzione, come la risonanza magnetica funzionale o l'elettroencefalogramma, registrano segnali elettrofisiologici generati nel cervello da vaste popolazioni di cellule. Più recentemente, sono state sviluppate tecniche di registrazione multisito che mirano ad abbattere le limitazioni dei precedenti approcci, rendendo possibile la misurazione ad alta risoluzione di segnali generati da grandi ensamble neuronali e da diverse regioni del cervello simultaneamente, ad esempio mediante l'uso di chip impiantabili a semiconduttore. I potenziali di campo locali (LFP) catturano processi sinaptici chiave che non possono essere estratti dall'attività di spiking di qualche neurone isolato. Numerosi studi hanno utilizzato gli LFP per studiare i meccanismi corticali coinvolti nei processi sensoriali, motori e cognitivi, come la memoria e la percezione. Gli LFP rappresentano anche dei segnali interessanti nell'ambito delle applicazioni neuroprotesiche e per monitorare l'attività cerebrale negli esseri umani, dal momento che possono essere registrati più stabilmente e facilmente in impianti cronici rispetto agli spike neuronali. In questo studio, sono riportati dei profili LFP registrati dalla barrel cortex di ratto tramite chip ad ago ad alta risoluzione basati su tecnologia CMOS e confrontati con quelli ottenuti tramite elettrodi convenzionali in Ag/AgCl inseriti in micropipette di vetro, strumenti comunemente usati in elettrofisiologia. La barrel cortex di ratto è un esempio ben noto di mapping topografico, nel quale ogni baffo sul muso dell'animale è mappato in una specifica area corticale, chiamata barrel. La barrel cortex contiene la rappresentazione sensoriale dei baffi dell'animale e rappresenta uno dei primi stadi di elaborazione dell'informazione tattile, insieme al ganglio del trigemino e al talamo. Essa è un'area di primaria importanza per lo studio del funzionamento della corteccia cerebrale, visto che le colonne corticali che formano i blocchi di base della neocorteccia possono essere visualizzati facilmente all'interno della barrel cortex. La barrel cortex inoltre è utilizzata come sistema di test in numerose metodologie innovative, grazie alla sua struttura unica ed istantaneamente identificabile, e grazie anche al fatto che le specie dotate di barrel, i roditori, sono gli animali da laboratorio più comuni. La barrel cortex e le sue interconnessioni neuronali sono stati oggetto delle ricerche più disparate in questi ultimi decenni. Attualmente, alcuni studi (come questo) non mirano solamente a comprendere meglio la barrel cortex, ma anche ad analizzare problematiche in campi scientifici collegati, utilizzando la barrel cortex come modello base. In questo lavoro, sono stati evocati segnali LFP nella barrel cortex tramite deflessioni ripetute dei baffi dell'animale, realizzate in modo controllato tramite un sistema di deflessione piezoelettrica a closed-loop innescato da un sistema di acquisizione LabView. Le risposte evocate generate nella barrel dalla stimolazione ripetuta dei baffi presentano elevata variabilità nella forma e nelle latenze temporali. Inoltre, il tipo di anestesia utilizzata può influenzare profondamente il profilo della risposta evocata. Questo studio riporta i risultati preliminari sulla variabilità della risposta neuronale e sull'effetto di due anestetici di uso comune su questi segnali, confrontando le distribuzioni delle risposte evocate in ratti anestetizzati con tiletamina-xylazina (il quale agisce prevalentemente sui recettori eccitatori di tipo NMDA) e uretano (che agisce in modo più bilanciato e complesso su entrambi i sistemi eccitatori ed inibitori, preservando la plasticità sinaptica). Sono state analizzate e discusse alcune caratteristiche rappresentative del segnale evocato (ad esempio, le latenze temporali e l'ampiezza degli eventi), registrato a varie profondità corticali. Per tutte le prondità corticali acquisite, sono state stimate le distribuzioni statistiche di tali parametri, in modo da valutare la variabilità degli LFP evocati dalle stimolazioni meccaniche individuali delle vibrisse del ratto lungo l'intera colonna corticale. I primi risultati presentano una grande variabilità nelle risposte corticali, sia in latenza che in ampiezza. Inoltre, è stata riscontrata una differenza significativa nella latenza del primo picco principale delle risposte evocate: gli LFP evocati in animali anestetizzati con tiletamina-xylazina presentavano una latenza più lunga di quelli registrati in ratti anestetizzati con uretano. Inoltre, le distribuzioni dei parametri analizzati erano più strette e piccate in uretano, in corrispondenza di tutte le profondità corticali. Questo comportamento è sicuramente da attribuire al differente meccanismo d'azione dei due anestetici su specifici recettori sinaptici, e quindi nell'elaborazione e nella trasmissione dell'informazione sensoriale lungo tutto il percorso corticale. E' stato inoltre discusso il ruolo della attività basale nella modulazione della risposta evocata. A questo proposito, è stata registrata l'attività spontanea in corrispondenza dei vari layer corticali ed analizzata nel contesto statistico delle 'valanghe neuronali'. Una valanga neuronale è una cascata di attività elettrica in una rete neuronale, la cui distribuzione statistica dei parametri principali (dimensione e vita media) può essere approssimata da una legge di potenza. La distribuzione delle dimensioni di una valanga in una rete neuronale segue una legge di potenza del tipo P(s)=s^-a, con a=1.5. Tale esponente è un riflesso delle correlazioni spaziali a lungo raggio nell'attività neuronale spontanea. Dal momento che i picchi negativi (nLFPs) nelle tracce elettrofisiologiche originano dalla somma di potenziali d'azione sincronizzati generati da neuroni posti nelle vicinanze dell'elettrodo di registrazione, ci siamo chiesti se fosse possibile modellizare i singoli nLFP registrati nell'attività basale tramite un singolo elettrodo come il risultato di valanghe neuronali locali. Pertanto, abbiamo analizzato la distribuzione della dimensione (cioè l'ampiezza in uV) di tali picchi, in modo da identificare una distribuzione power-law appropriata, che potesse descrivere anche le registrazioni a singolo elettrodo. Infine, sono presentate e discusse le prime registrazioni in assoluto degli LFP evocati lungo un'intera colonna corticale ottenute tramite l'ultima generazione di chip impiantabili a tecnologia CMOS. Questi ultimi presentano una matrice di 256 siti di registrazione, organizzata secondo due possibili topologie, 16 x 16 o 4 x 64, e avente una distanza tra gli elettrodi pari a 15 um o 33 um rispettivamente. Una precisa dinamica di propagazione dei potenziali evocati può già essere riconosciuta in questi primissimi profili corticali. Nel prossimo futuro, l'uso di questi dispositivi a semiconduttore potrà aiutare a comprendere il decorso di sindromi neurodegerative come il Parkinson o l'Alzheimer, associando sintomi e comportamenti tipo della malattia a specifiche caratteristiche neuronali. I chip impiantabili potranno anche essere utilizzati come 'electroceuticals', ossia potranno aiutare a rallentare (o addirittura a capovolgere) il decorso delle malattie neurogenerative, costituendo le basi di protesi neuronali in grado di sostenere fisicamente o allenare funzionalmente le popolazioni neuronali danneggiate. L'identificazione e il rilevamento di segnali neuronali ad alta risoluzione aiuterà anche a sviluppare complesse interfacce cervello-macchina, che consentiranno il controllo di protesi intelligenti e che forniranno sofisticati meccanismi di feedback a chi ha perso l'uso di alcune parti del proprio corpo o determinate funzioni cerebrali.

The improvement of devices provided by Nanotechnology has put forward new classes of sensors, called bio-nanosensors, which are very promising for the detection of biochemical molecules in a large variety of applications. Their use in lab-on-a-chip could gives rise to new opportunities in many fields, from health-care and bio-warfare to environmental and high-throughput screening for pharmaceutical industry. Bio-nanosensors have great advantages in terms of cost, performance, and parallelization. Indeed, they require very low quantities of reagents and improve the overall signal-to-noise-ratio due to increase of binding signal variations vs. area and reduction of stray capacitances. Additionally, they give rise to new challenges, such as the need to design high-performance low-noise integrated electronic interfaces. This thesis is related to the design of high-performance advanced CMOS interfaces for electrochemical bio-nanosensors. The main focus of the thesis is: 1) critical analysis of noise in sensing interfaces, 2) devising new techniques for noise reduction in discrete-time approaches, 3) developing new architectures for low-noise, low-power sensing interfaces. The manuscript reports a multi-project activity focusing on low-noise design and presents two developed integrated circuits (ICs) as examples of advanced CMOS interfaces for bio-nanosensors. The first project concerns low-noise current-sensing interface for DC and transient measurements of electrophysiological signals. The focus of this research activity is on the noise optimization of the electronic interface. A new noise reduction technique has been developed so as to realize an integrated CMOS interfaces with performance comparable with state-of-the-art instrumentations. The second project intends to realize a stand-alone, high-accuracy electrochemical impedance spectroscopy interface. The system is tailored for conductivity-temperature-depth sensors in environmental applications, as well as for bio-nanosensors. It is based on a band-pass delta-sigma technique and combines low-noise performance with low-power requirements.

The improvement of devices provided by Nanotechnology has put forward new classes of sensors, called bio-nanosensors, which are very promising for the detection of biochemical molecules in a large variety of applications. Their use in lab-on-a-chip could gives rise to new opportunities in many fields, from health-care and bio-warfare to environmental and high-throughput screening for pharmaceutical industry. Bio-nanosensors have great advantages in terms of cost, performance, and parallelization. Indeed, they require very low quantities of reagents and improve the overall signal-to-noise-ratio due to increase of binding signal variations vs. area and reduction of stray capacitances. Additionally, they give rise to new challenges, such as the need to design high-performance low-noise integrated electronic interfaces. This thesis is related to the design of high-performance advanced CMOS interfaces for electrochemical bio-nanosensors. The main focus of the thesis is: 1) critical analysis of noise in sensing interfaces, 2) devising new techniques for noise reduction in discrete-time approaches, 3) developing new architectures for low-noise, low-power sensing interfaces. The manuscript reports a multi-project activity focusing on low-noise design and presents two developed integrated circuits (ICs) as examples of advanced CMOS interfaces for bio-nanosensors. The first project concerns low-noise current-sensing interface for DC and transient measurements of electrophysiological signals. The focus of this research activity is on the noise optimization of the electronic interface. A new noise reduction technique has been developed so as to realize an integrated CMOS interfaces with performance comparable with state-of-the-art instrumentations. The second project intends to realize a stand-alone, high-accuracy electrochemical impedance spectroscopy interface. The system is tailored for conductivity-temperature-depth sensors in environmental applications, as well as for bio-nanosensors. It is based on a band-pass delta-sigma technique and combines low-noise performance with low-power requirements.

This dissertation demonstrates the feasibility of three novel low-power and low-noise schemes for the readout interfaces of MEMS Capacitive Microphones (MCM) by presenting their detailed design descriptions and measurement results as application-specific ICs (ASIC) in CMOS technology developed to exploit their application scope in consumer electronics and hearing aids. MCMs are a new generation of acoustic sensors, which offer a significant scope to improve miniaturization, integration and cost of the acoustic systems by leveraging the MEMS technology. Electret-Condenser-Microphones (ECM) are the current market solution for acoustic applications; however, MCMs are being considered as the future microphone-of-choice for mobile phones in consumer electronics and for hearing aids in medical applications. The readout interface of MCM in an acoustic system converts the output of the MEMS sensor into an appropriate electrical representation (analog or digital). The output of a MCM is in the form of capacitive-variations in femto-Farad range, which necessitates a low-noise signal-translation employed by the readout interface together with a low-power profile for its portable applications. The main focus of this dissertation is to develop novel readout schemes that are low-noise, low-power, low-cost and batch-producible, targeting the domains of consumer electronics and hearing-aids. The presented readout interfaces in this dissertation consist of a front-end, which is a preamplifier, and a backend which converts the output of the preamplifier into a digital representation. The first interface presents a bootstrapped preamplifier and a third-order sigma-delta modulator (SDM) for analog-to-digital conversion. The preamplifier is bootstrapped to the MCM by tying its output to the sensor’s substrate. This bootstrapping technique boosts the MCM signal by ~17dB and also makes the readout insensitive to the parasitic capacitors in MCM electro-mechanical structure, achieving 55dBA/Pa of SNDR. The third-order low-power SDM converts output of the PAMP into an over-sampled digital bitstream demonstrating a dynamic-range (DR) of 80dBA. This ASIC operates at 1.8V single-supply and 460uA of total current consumption; thus, highlighting the feasibility of low-power integrated MCM readout interface. This ASIC is also acoustically characterized with a MCM, bonded together in a single package, demonstrating a reasonable agreement with the expected performance. The second interface presents a readout scheme with force-feedback (FFB) for the MCM. The force-feedback is used to enhance the linearity of the MCM and minimize the impact of drift in sensor mechanical parameters. Due to the unavailability of the sensor, the effect of FFB could not be measured with an MCM; however, the presented results point out a significant performance improvement through FFB. The preamplifier in this ASIC utilizes a high-gain OTA in a capacitive-feedback configuration to achieve parasitic insensitive readout in an area and power-efficient way, achieving 40dBA/Pa of SNDR. The digital output of the third-order SDM achieved 76dBA of DR and was also used to apply the electrostatic FFB by modulating the bias voltage of the MCM. A dummy-branch with dynamic matching converted the single-ended MCM into a pseudo-differential sensor to make it compatible with force-feedback. This interface operates at 3.3V supply and consumes total current of 300uA. The third interface presents a chopper-stabilized multi-function preamplifier for MCM. Unlike typical MCM preamplifiers, this preamplifier employs chopper-stabilization to mitigate low-frequency noise and offset and it also embeds extra functionalities in the preamplifier core such as controllable gain, controllable offset and controllable high-pass filtering. This preamplifier consists of two stages; the first stage is a source-follower buffering the MCM output into a voltage signal and the second-stage is a chopper-stabilized controllable capacitive gain-stage. This preamplifier employs MΩ bias resistors to achieve consistent readout sensitivity over the audio band by utilizing the miller effect, avoiding the conditionally-linear GΩ bias resistors. The offset control functionality of this preamplifier can be used to modulate idle tones in the subsequent sigma-delta modulator out of the audio-band. The high-pass filtering functionality can be used to filter-out low-frequency noises such as wind-hum. This preamplifier operates at 1.8V and consumes total current of 50u with SNDR of 44dB/PA, demonstrating the feasibility of a low-power low-noise multifunction preamplifier for the MCM sensor.

This dissertation demonstrates the feasibility of three novel low-power and low-noise schemes for the readout interfaces of MEMS Capacitive Microphones (MCM) by presenting their detailed design descriptions and measurement results as application-specific ICs (ASIC) in CMOS technology developed to exploit their application scope in consumer electronics and hearing aids. MCMs are a new generation of acoustic sensors, which offer a significant scope to improve miniaturization, integration and cost of the acoustic systems by leveraging the MEMS technology. Electret-Condenser-Microphones (ECM) are the current market solution for acoustic applications; however, MCMs are being considered as the future microphone-of-choice for mobile phones in consumer electronics and for hearing aids in medical applications. The readout interface of MCM in an acoustic system converts the output of the MEMS sensor into an appropriate electrical representation (analog or digital). The output of a MCM is in the form of capacitive-variations in femto-Farad range, which necessitates a low-noise signal-translation employed by the readout interface together with a low-power profile for its portable applications. The main focus of this dissertation is to develop novel readout schemes that are low-noise, low-power, low-cost and batch-producible, targeting the domains of consumer electronics and hearing-aids. The presented readout interfaces in this dissertation consist of a front-end, which is a preamplifier, and a backend which converts the output of the preamplifier into a digital representation. The first interface presents a bootstrapped preamplifier and a third-order sigma-delta modulator (SDM) for analog-to-digital conversion. The preamplifier is bootstrapped to the MCM by tying its output to the sensor’s substrate. This bootstrapping technique boosts the MCM signal by ~17dB and also makes the readout insensitive to the parasitic capacitors in MCM electro-mechanical structure, achieving 55dBA/Pa of SNDR. The third-order low-power SDM converts output of the PAMP into an over-sampled digital bitstream demonstrating a dynamic-range (DR) of 80dBA. This ASIC operates at 1.8V single-supply and 460uA of total current consumption; thus, highlighting the feasibility of low-power integrated MCM readout interface. This ASIC is also acoustically characterized with a MCM, bonded together in a single package, demonstrating a reasonable agreement with the expected performance. The second interface presents a readout scheme with force-feedback (FFB) for the MCM. The force-feedback is used to enhance the linearity of the MCM and minimize the impact of drift in sensor mechanical parameters. Due to the unavailability of the sensor, the effect of FFB could not be measured with an MCM; however, the presented results point out a significant performance improvement through FFB. The preamplifier in this ASIC utilizes a high-gain OTA in a capacitive-feedback configuration to achieve parasitic insensitive readout in an area and power-efficient way, achieving 40dBA/Pa of SNDR. The digital output of the third-order SDM achieved 76dBA of DR and was also used to apply the electrostatic FFB by modulating the bias voltage of the MCM. A dummy-branch with dynamic matching converted the single-ended MCM into a pseudo-differential sensor to make it compatible with force-feedback. This interface operates at 3.3V supply and consumes total current of 300uA. The third interface presents a chopper-stabilized multi-function preamplifier for MCM. Unlike typical MCM preamplifiers, this preamplifier employs chopper-stabilization to mitigate low-frequency noise and offset and it also embeds extra functionalities in the preamplifier core such as controllable gain, controllable offset and controllable high-pass filtering. This preamplifier consists of two stages; the first stage is a source-follower buffering the MCM output into a voltage signal and the second-stage is a chopper-stabilized controllable capacitive gain-stage. This preamplifier employs MΩ bias resistors to achieve consistent readout sensitivity over the audio band by utilizing the miller effect, avoiding the conditionally-linear GΩ bias resistors. The offset control functionality of this preamplifier can be used to modulate idle tones in the subsequent sigma-delta modulator out of the audio-band. The high-pass filtering functionality can be used to filter-out low-frequency noises such as wind-hum. This preamplifier operates at 1.8V and consumes total current of 50u with SNDR of 44dB/PA, demonstrating the feasibility of a low-power low-noise multifunction preamplifier for the MCM sensor.

Worldwide regulations for short range communication devices allow the unlicensed use of several Gigahertz of bandwidth in the frequency band around 60 GHz. This 60GHz band is ideally suited for applications like very high data rate, energy-autonomous wireless sensor networks or Gbit/s multimedia links with low power constraints. Not long ago, radio interfaces that operate in the millimeter-wave frequency range could only be realized using expensive compound semiconductor technologies. Today, the latest sub-micron CMOS technologies can be used to design 60GHz radio frequency integrated circuits (RFICs) at very low cost in mass production. This thesis is part of an effort to realize a low power System in Package (SiP) including both the radio interface (with baseband and RF circuitry) and an antenna array to directly transmit and receive a 60GHz signal. The first part of this thesis deals with the design of the low power RF transceiver front-end for the radio interface. The key building blocks of this RF front-end (amplifiers, mixers and a voltage controlled oscillator (VCO)) are designed, realized and measured using the 65nm CMOS technology of ST Microelectronics. Full custom active and passive devices are developed and characterized for the use within these building blocks. An important step towards the full integration of the RF transceiver front-end is the assembly of these building blocks to form a basic receiver chip. Circuits with small chip size and low power consumption compared to the state of the art have been accomplished. The second part of this thesis concerns the development of behavioral models for the designed building blocks. These system level models are necessary to simulate the behavior of the entire SiP, which becomes too complex when using detailed circuit level models. In particular, a novel technique to model the transient, steady state and phase noise behavior of the VCO in the hardware description language VHDL-AMS is proposed and implemente d. The model uses a state space description to describe the dynamic behavior of the VCO. Its nonlinearity is approximated by artificial neural networks. A drastic reduction of simulation time with respect to the circuit level model has been achieved, while at the same time maintaining a very high level of accuracy.

Il rilevamento di gas tossici e pericolosi è sempre stato necessario per motivi di sicurezza. Negli ultimi anni, in particolare, l’attenzione per lo sviluppo di sistemi portatili e a basso costo per il rilevamento dei gas è aumentata notevolmente. Questa tesi presenta circuiti CMOS versatili, veloci, ad alta precisione e basso consumo per applicazioni portatili di rilevamento di gas. I sensori target sono i Metal Oxide Semiconductor (MOX). Questi sensori sono ampiamente utilizzati per la loro intrinseca compatibilità con le tecnologie MEMS integrate. Le tipologie di lettura scelte sono basate su un oscillatore controllato dalla resistenza del sensore stessa, in modo da ottenere una conversione resistenza-tempo. Ciò garantisce un ampio range dinamico, una buona precisione e la capacità di far fronte alle grandi variazioni di resistenza del sensore MOX. Quattro diversi prototipi sono stati sviluppati e testati con successo. Sono state anche eseguite misurazioni chimiche con un vero sensore SnO2 MOX, validando i risultati ottenuti. Le misure hanno mostrato come il sensore e l’interfaccia sia in grado di rilevare fino a 5ppm di CO in aria. Gli ASIC sono in grado di coprire 128 dB di DR a 4Hz di output data rate digitale, o 148 dB a 0.4Hz, garantendo un errore relativo percentuale sempre migliore dello 0,4% (SNDR> 48 dB). Le prestazioni target sono state raggiunte con aggressive strategie di progettazione e ottimizzazione a livello di sistema. È stata utilizzata una tecnologia CMOS a 130nm fornita da Infineon Technologies AG. La scelta di un nodo tecnologico così scalato (rispetto alle tipiche implementazioni in questo settore) ha consentito di ridurre ulteriormente i consumi fino a circa 450 μA. Inoltre, questo lavoro introduce la possibilità di utilizzare la stessa architettura basata su oscillatore per eseguire la lettura di sensori capacitivi. I risultati delle misurazioni con sensori capacitivi MEMS hanno mostrato 116 dB di DR, con un SNR di 74 dB a 10Hz di velocità di trasmissione dati digitale. Le architetture sviluppate in questa tesi sono compatibili con gli standard moderni nel settore del rilevamento del gas per dispositivi portatili.
Detection of toxic and dangerous gases has always been a need for safety purpose and, in recent years, portable and low-cost gas sensing systems are becoming of main interest. This thesis presents fast, high precision, low-power, versatile CMOS interface circuits for portable gas sensing applications. The target sensors are Metal Oxide Semiconductor (MOX) sensors which are widely used due to their inherent compatibility with integrated MEMS technologies. The chosen readout typologies are based on the time-domain Resistor-Controlled Oscillator. This guarantees wide dynamic range, good precision and the ability to cope with the large MOX sensor resistance variations. Four different prototypes have been successfully developed and tested. Chemical measurements with a real SnO2 MOX sensor have also been performed to validate the results, showing a minimum CO detection capability in ambient air of 5 ppm. The ASICs are able to cover 128 dB of DR at 4 Hz of digital output data rate, or 148 dB at 0.4 Hz, while providing a relative error always better than 0.4% (SNDR >48 dB). Target performances have been achieved with aggressive design strategies and system-level optimization, and using a scaled (compared to typical implementations in this field) 130nm CMOS technology provided by Infineon Technologies AG. Power consumption is about 450 μA. Moreover, this work introduces the possibility to use the same oscillator-based architecture to perform capacitive sensors readout. Measurement results with capacitive MEMS sensors have shown 116 dB of DR in CSENS mode, with an SNR of 74 dB at 10 Hz of digital output data rate. The architectures developed in this thesis are compatible with the modern standards in the portable gas sensing industry.

The adaptation of standard integrated circuit (IC) technology for biosensors in drug discovery pharmacology, neural interface systems, environmental sensors and electrophysiology requires electrodes to be electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous IC technology, complementary metal oxide semiconductor (CMOS), does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved by others. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. The scope of this work was to develop post-processing methods that meet the electrochemical and biocompatibility requirements but within the low-cost constraint. Several approaches were appraised with the two most promising designs taken forward for further investigation. Firstly, a process was developed whereby the corrodible aluminium is anodised to form nanoporous alumina and further processed to optimise its impedance. A second design included a noble metal in the alumina pores to enhance further the electrical characteristics of the electrode. Experiments demonstrated for the first time the ability to anodise CMOS metallisation to form the desired electrodes. Tests showed the electrode addressed the problems of corrosion and presented a surface that was biocompatible with the NG108-15 neuronal cell line. Difficulties in assessing the influence of alumina porosity led to the development of a novel cell adhesion assay that showed for the first time neuronal cells adhere preferentially to large pores rather than small pores or planar aluminium. It was also demonstrated that porosity can be manipulated at room temperature by modifying the anodising electrolyte with polyethylene glycol. CMOS ICs were designed as multiple electrode arrays and optimised for neuronal recordings. This utilised the design incorporating a noble metal deposited into the porous alumina. Deposition of platinum was only partially successful, with better results using gold. This provided an electrode surface suitable for electric cell-substrate impedance sensors (ECIS) and many other sensor applications. Further processing deposited platinum black to improve signal-to-noise ratio for neuronal recordings. The developed processes require no specialised semiconductor fabrication equipment and can process CMOS ICs on laboratory or factory bench tops in less than one hour. During the course of electrode development, new methods for biosensor packaging were assessed: firstly, a biocompatible polyethylene glycol mould process was developed for improved prototype assembly. Secondly, a commercial ‘partial encapsulation’ process (Quik-Pak, U.S.) was assessed for biocompatibility. Cell vitality tests showed both methods were biocompatible and therefore suitable for use in cell-based biosensors. The post-processed CMOS electrode arrays were demonstrated by successfully recording neuronal cell electrical activity (action potentials) and by ECIS with a human epithelial cell line (Caco2). It is evident that these developments may provide a missing link that can enable commercialisation of CMOS biosensors. Further work is being planned to demonstrate the technology in context for specific markets.

Arrays of micron sized light-emitting diodes (micro-LEDs) allow high-frequency spatial and temporal modulation of an optical signal. Contacting micro-LED arrays to complementary metal-oxide-semiconductor (CMOS) electronics provides a mm-chip-scale device with a high level of control over the optical emission through digital input. Such devices enable novel forms of optical communication and imaging to be investigated. This thesis first demonstrates the use of CMOS controlled micro-LEDs in multi-level intensity modulated optical communications. By generating signals in a discrete fashion with weighted groups of pixels in an array, the non-linearity issues of single LED elements can be avoided and the device functions as a digital-to-light converter. Pulse amplitude modulation and discrete orthogonal frequency division multiplexing were performed, yielding data rates up to 200 Mb/s, and spectral efficiencies up to 3.96 bits/s/Hz. A novel form of optical communications is introduced where data is sent through modulation of the temporal correlation of a pulsed optical signal. Utilising single-photon detection at the receiver enables transmission at low received power levels, on the order of picowatts. While data rates prove to be modest, the scheme is robust to both constant and modulated background signals. Additionally, the implementation requires only simple semiconductor components, exhibits low electrical power consumption, and has been demonstrated under power from a nanosatellite simulation testbed. The pulse correlation approach also presents opportunities in imaging. Received signals are dependent on optical power; therefore, if relative emitted power from multiple transmitters is known, information on the reectance or absorption of an intermediate material can be obtained. This potentially enables colour or hyperspectral imaging with single-photon detectors by temporally structuring light sources. Proof-of-principle experiments have been performed using commercially available LEDs of 10 different wavelengths and printed colour targets.

The emergence of miniaturized electronic sensors for recording neural activity is opening up new opportunities for better health care and understanding brain function. The precise instrumentation for sensing these signals has been developed extensively, but no implantable system available today is capable of providing a high density recording structures that can be scaled to accommodate the large number of electrodes and processing neuroprosthetics need for functional limb replacement. The design of these systems is complicated by micro-volt levels of signal that contain convoluted mixtures of information. This demands highly accurate signal quantization and exhaustive processing that is constrained by the scarce power availability. The resulting difficulty in realizing viable solutions for chronic implants necessitates cutting-edge fabrication technologies and state-of-the-art circuit optimization techniques. This thesis presents the understanding behind optimizing these instrumentation systems in order to maximize the simultaneous sensing capabilities of brain machine interfaces that can be implanted wirelessly into living systems. These analytics enabled this work to outperform state of the art in terms of delivering high precision at 56 dB SINAD with a sub 0.01mm^2 silicon footprint and a 800 nW power budget by employing novel time-domain circuit techniques. This advancement will enable BMIs to be integrated & minimutrized using nanometre CMOS with extensive digital processing capabilities that are capable of decoding neural signals without supervision such that therapy in a fully implanted fashion. Moreover by introducing distributed processing architecture this work is the first to allows scalable fully reconfigurable functionality at the instrumentation interface for complex algorithmic operations while maintaining a power efficiency of 2.7μW per MIPS.

L’avenir de la recherche sur les maladies du cerveau repose sur le développement de nouvelles technologies qui permettront de comprendre comment cet organe si complexe traite, intègre et transfère l’information. Parmi celles-ci, l’optogénétique est une technologie révolutionnaire qui permet d’utiliser de la lumière afin d’activer sélectivement les neurones du cortex d’animaux transgéniques pour observer leur effet dans un vaste réseau biologique. Ce cadre expérimental repose typiquement sur l’observation de l’activité neuronale de souris transgéniques, car elles peuvent exprimer une grande variété de gènes et de maladies et qu’elles sont peu couteuses. Toutefois, la plupart des appareils de mesure ou de stimulation optogénétique disponible ne sont pas appropriés, car ils sont câblés, trop lourds et/ou trop simplistes. Malheureusement, peu de systèmes sans fil existent, et ces derniers sont grandement limités par la bande passante requise pour transmettre les données neuronales, et ils ne fournissent pas de stimulation optogénétique multicanal afin de stimuler et observer plusieurs régions du cerveau. Dans les dispositifs actuels, l’interprétation des données neuronales est effectuée ex situ, alors que la recherche bénéficierait grandement de systèmes sans fil assez intelligents pour interpréter et stimuler les neurones en boucle fermée, in situ. Le but de ce projet de recherche est de concevoir des circuits analogiques-numériques d’acquisition et de traitement des signaux neuronaux, des algorithmes d’analyse et de traitement de ces signaux et des systèmes electro-optiques miniatures et sans fil pour : i) Mener des expériences combinant l’enregistrement neuronal et l’optogénétique multicanal haute résolution avec des animaux libres de leurs mouvements. ii) Mener des expériences optogénétiques synchronisées avec l’observation, c.-à-d. en boucle fermée, chez des animaux libres de leurs mouvements. iii) Réduire la taille, le poids et la consommation énergétique des systèmes optogénétiques sans fil afin de minimiser l’impact de la recherche chez de petits animaux. Ce projet est en 3 phases, et ses principales contributions ont été rapportées dans dix conférences internationales (ISSCC, ISCAS, EMBC, etc.) et quatre articles de journaux publiés ou soumis, ainsi que dans un brevet et deux divulgations. La conception d’un système optogénétique haute résolution pose plusieurs défis importants. Notamment, puisque les signaux neuronaux ont un contenu fréquentiel élevé (_10 kHz), le nombre de canaux sous observation est limité par la bande passante des transmetteurs sans fil (2-4 canaux en général). Ainsi, la première phase du projet a visé le développement d’algorithmes de compression des signaux neuronaux et leur intégration dans un système optogénétique sans fil miniature et léger (2.8 g) haute résolution possédant 32 canaux d’acquisition et 32 canaux de stimulation optique. Le système détecte, compresse et transmet les formes d’onde des potentiels d’action (PA) produits par les neurones avec un field programmable gate array (FPGA) embarqué à faible consommation énergétique. Ce processeur implémente un algorithme de détection des PAs basé sur un seuillage adaptatif, ce qui permet de compresser les signaux en transmettant seulement les formes détectées. Chaque PA est davantage compressé par une transformée en ondelette discrète (DWT) de type Symmlet-2 suivie d’une technique de discrimination et de requantification dynamique des coefficients. Les résultats obtenus démontrent que cet algorithme est plus robuste que les méthodes existantes tout en permettant de reconstruire les signaux compressés avec une meilleure qualité (SNDR moyen de 25 dB _ 5% pour un taux de compression (CR) de 4.2). Avec la détection, des CR supérieurs à 500 sont rapportés lors de la validation in vivo. L’utilisation de composantes commerciales dans des systèmes optogénétiques sans fil augmente
la taille et la consommation énergétique, en plus de ne pas être optimisée pour cette application. La seconde phase du projet a permis de concevoir un système sur puce (SoC) complementary metal oxide semiconductor (CMOS) pour faire de l’enregistrement neuronal et de optogénétique multicanal, permettant de réduire significativement la taille et la consommation énergétique comparativement aux alternatives commerciales. Ceci est une contribution importante, car c’est la première puce à être doté de ces deux fonctionnalités. Le SoC possède 10 canaux d’enregistrement et 4 canaux de stimulation optogénétique. La conception du bioamplificateur inclut une bande passante programmable (0.5 Hz - 7 kHz) et un faible bruit referré à l’entré (IRN de 3.2 μVrms), ce qui permet de cibler différents types de signaux biologiques (PA, LFP, etc.). Le convertisseur analogique numérique (ADC) de type Delta- Sigma (DS) MASH 1-1-1 est conçu pour fonctionner de faibles taux de sur-échantillonnage (OSR _50) pour réduire sa consommation et possède une résolution programmable (ENOB de 9.75 Bits avec un OSR de 25). Cet ADC exploite une nouvelle technique réduisant la taille du circuit en soustrayant la sortie de chaque branche du DS dans le domaine numérique, comparativement à la méthode analogique classique. La consommation totale d’un canal d’enregistrement est de 11.2 μW. Le SoC implémente un nouveau circuit de stimulation optique basé sur une source de courant de type cascode avec rétroaction, ce qui permet d’accommoder une large gamme de LED et de tensions de batterie comparativement aux circuits existants. Le SoC est intégré dans un système optogénétique sans fil et validé in vivo. À ce jour et en excluant ce projet, aucun système sans-fil ne fait de l’optogénétique en boucle fermée simultanément au suivi temps réel de l’activité neuronale. Une contribution importante de ce travail est d’avoir développé le premier système optogénétique multicanal qui est capable de fonctionner en boucle fermée et le premier à être validé lors d’expériences in vivo impliquant des animaux libres de leurs mouvements. Pour ce faire, la troisième phase du projet a visé la conception d’un SoC CMOS numérique, appelé neural decoder integrated circuit (ND-IC). Le ND-IC et le SoC développé lors de la phase 2 ont été intégrés dans un système optogénétique sans fil. Le ND-IC possède 3 modules : 1) le détecteur de PA adaptatif, 2) le module de compression possédant un nouvel arbre de tri pour discriminer les coefficients, et 3) le module de classement automatique des PA qui réutilise les données générées par le module de détection et de compression pour réduire sa complexité. Un lien entre un canal d’enregistrement et un canal de stimulation est établi selon l’association de chaque PA à un neurone, grâce à la classification, et selon l’activité de ce neurone dans le temps. Le ND-IC consomme 56.9 μW et occupe 0.08 mm2 par canal. Le système pèse 1.05 g, occupe un volume de 1.12 cm3, possède une autonomie de 3h, et est validé in vivo.
The future of brain research lies in the development of new technologies that will help understand how this complex organ processes, integrates and transfers information. Among these, optogenetics is a recent technology that allows the use of light to selectively activate neurons in the cortex of transgenic animals to observe their effect in a large biological network. This experimental setting is typically based on observing the neuronal activity of transgenic mice, as they express a wide variety of genes and diseases, while being inexpensive. However, most available neural recording or optogenetic devices are not suitable, because they are hard-wired, too heavy and/or too simplistic. Unfortunately, few wireless systems exist, and they are greatly limited by the required bandwidth to transmit neural data, while not providing simultaneous multi-channel neural recording and optogenetic, a must for stimulating and observing several areas of the brain. In current devices, the analysis of the neuronal data is performed ex situ, while the research would greatly benefit from wireless systems that are smart enough to interpret and stimulate the neurons in closed-loop, in situ. The goal of this project is to design analog-digital circuits for acquisition and processing of neural signals, algorithms for analysis and processing of these signals and miniature electrooptical wireless systems for: i) Conducting experiments combining high-resolution multi-channel neuronal recording and high-resolution multi-channel optogenetics with freely-moving animals. ii) Conduct optogenetic experiments synchronized with the neural recording, i.e. in closed loop, with freely-moving animals. iii) Increase the resolution while reducing the size, weight and energy consumption of the wireless optogenetic systems to minimize the impact of research with small animals. This project is in 3 phases, and its main contributions have been reported in ten conferences (ISSCC, ISCAS, EMBC, etc.) and four published journal papers, or submitted, as well as in a patent and two disclosures. The design of a high resolution optogenetic system poses several challenges. In particular, since the neuronal signals have a high frequency content (10 kHz), the number of chanv nels under observation is limited by the bandwidth of the wireless transmitters (2-4 channels in general). Thus, the first phase of the project focused on the development of neural signal compression algorithms and their integration into a high-resolution miniature and lightweight wireless optogenetics system (2.8g), having 32 recording channels and 32 optical stimulation channels. This system detects, compresses and transmits the waveforms of the signals produced by the neurons, i.e. action potentials (AP), in real time, via an embedded low-power field programmable gate array (FPGA). This processor implements an AP detector algorithm based on adaptive thresholding, which allows to compress the signals by transmitting only the detected waveforms. Each AP is further compressed by a Symmlet-2 discrete wavelet transform (DWT) followed dynamic discrimination and requantification of the DWT coefficients, making it possible to achieve high compression ratios with a good reconstruction quality. Results demonstrate that this algorithm is more robust than existing approach, while allowing to reconstruct the compressed signals with better quality (average SNDR of 25 dB 5% for a compression ratio (CR) of 4.2). With detection, CRs greater than 500 are reported during the in vivo validation. The use of commercial components in wireless optogenetic systems increases the size and power consumption, while not being optimized for this application. The second phase of the project consisted in designing a complementary metal oxide semiconductor (CMOS) system-on-chip (SoC) for neural recording and multi-channel optogenetics, which significantly reduces the size and energy consumption compared to commercial alternatives. This is important contribution, since it’s the first chip to integrate both features. This SoC has 10 recording channels and 4 optogenetic stimulation channels. The bioamplifier design includes a programmable bandwidth (0.5 Hz -7 kHz) and a low input-referred noise (IRN of 3.2 μVrms), which allows targeting different biological signals (AP, LFP, etc.). The Delta-Sigma (DS) MASH 1-1-1 low-power analog-to-digital converter (ADC) is designed to work with low OSR (50), as to reduce its power consumption, and has a programmable resolution (ENOB of 9.75 bits with an OSR of 25). This ADC uses a new technique to reduce its circuit size by subtracting the output of each DS branch in the digital domain, rather than in the analog domain, as done conventionally. A recording channel, including the bioamplifier, the DS and the decimation filter, consumes 11.2 μW. Optical stimulation is performed with an on-chip LED driver using a regulated cascode current source with feedback, which accommodates a wide range of LED parameters and battery voltages. The SoC is integrated into a wireless optogenetic platform and validated in vivo.
To date and excluding this project, no wireless system is making closed-loop optogenetics simultaneously to real-time monitoring of neuronal activity. An important contribution of this work is to have developed the first multi-channel optogenetic system that is able to work in closed-loop, and the first to be validated during in vivo experiments involving freely-moving animals. To do so, the third phase of the project aimed to design a digital CMOS chip, called neural decoder integrated circuit (ND-IC). The ND-IC and the SoC developed in Phase 2 are integrated within a wireless optogenetic system. The ND-IC has 3 main cores: 1) the adaptive AP detector core, 2) the compression core with a new sorting tree for discriminating the DWT coefficients, and 3 ) the AP automatic classification core that reuses the data generated by the detection and compression cores to reduce its complexity. A link between a recording channel and a stimulation channel is established according to the association of each AP with a neuron, thanks to the classification, and according to the bursting activity of this neuron. The ND-IC consumes 56.9 μW and occupies 0.08 mm2 per channel. The system weighs 1.05 g, occupies a volume of 1.12 cm3, has an autonomy of 3h, and is validated in vivo.

Au cours de ces travaux de thèse, nous avons étudié la redistribution atomique de contaminantsmétalliques dans le silicium et au voisinage d'une interface SiO2/Si. Pour mener à bien cetteétude, trois techniques de caractérisation complémentaires ont été utilisées (TEM,APT,SIMS).Nous avons dans un premier temps étudié la diffusion ainsi que la ségrégation d'équilibre de contaminants à une interface SiO2/Si, et plus particulièrement, la diffusion du W et du Mo. Le Wprésente une cinétique de diffusion extrêmement lente. Les caractérisations réalisées par TEM et APT nous ont permis de discuter les profils de concentrations mesurés par SIMS et nous ont guidés dans le choix du modèle de diffusion proposé. L'étude de la diffusion du Mo révéle que cette espèce présente une limite de solubilité faible dans le silicium et une forte interaction avec des défauts d'irradiation, provoquant sa précipitation.Dans un second volet, nous nous sommes intéressés à l'effet d'une interface mobile, lors d'une réaction, sur la redistribution atomique des contaminants proches de cette interface. Nous avons ainsiréalisé une étude comparative des comportements du Fe et W lors de procédés d'oxydation.Le tungstène précipite dans le volume et est progressivement rejeté par l'oxydation. Le ferprécipite à l'interface SiO2/Si, provoquant un effet de masquage dont nous avons montré qu'il étaitresponsable de la formation de défauts pyramidaux d'interface, caractéristiques d'une contaminationen fer du silicium. Le procédé de germano-siliciuration de nickel, réalisé à basses températures a également été investigué. Cette réaction provoque le rejet 3D du germanium à l'interface NiSiGe/SiGe
During this thesis work, we studied the atomic redistribution of metallic contaminantsin silicon and near a SiO2/Si interface. To conduct this study, we used three complementary characterisation techniques : transmission electron microscopy (TEM), atomic probe tomography (APT) and secondary ion mass spectrometry (SIMS).We first studied the diffusion and equilibrium segregation of various contaminants at a SiO2/Si interface, and more particularly, the diffusion of W and Mo. W exhibits a very slow diffusion kinetic.Physico-chemical characterizations performed by TEM and APT allowed discussing the concentrationprofiles obtained by SIMS leading to the diffusion model that we proposed. The study of Mo diffusionrevealed that this specy exhibits a low solubility limit in silicon and strongly interacts with irradiation-induced defects, leading to its precipitation.In a second phase, we studied the effect of a mobile interface, during a reaction, on the atomic redistribution of contaminants near this interface. We performed a comparative study of the behaviourof Fe and W during oxidation processes. W precipitates in the silicon substrate and is progressivelyrejected (snowplow) by the oxidation. Fe preferentially precipitates at the SiO2/Si interface. Theseprecipitates mask a part of the silicon substrate and thus hinder its oxidation, leading to the formation of characteristics pyramidal-shaped defects at the interface. Low temperature nickel germano-silicide formation have also been investigated. This reaction leads to the 3D snowplow of germanium atoms at the NiSiGe/SiGe interface

L'approche du role du comportement mecanique des interphases dans les composites sic/sic a ete menee en utilisant diverses techniques experimentales: microindentation, nanoindentation et essais de traction sur composites modeles (microcomposites) et composites 2d. Des interphases de carbone et des interphases moins oxydables, tels que bn et des sequences c/sic, ont ete etudiees a temperature ambiante. La rupture, de type adhesive et cohesive, puis la fissuration et enfin le frottement des surfaces deliees ont ete analyses. Les proprietes interfaciales determinees ont permis d'expliquer les differences de comportements macro-mecaniques des divers composites. Le champ des contraintes residuelles d'origine thermique dans des couches minces a ete calcule par la methode des elements finis. Les conditions d'elaboration cvd/cvi pour obtenir du nitrure de bore a structure anisotrope ont ete identifiees. L'augmentation du degre de cristallisation des depots de nitrure de bore a ete reliee a des changements dans les regimes cinetiques de depot. La degradation mecanique et chimique du renfort fibreux lors du depot de l'interphase bn et l'adherence des depots sur les fibres ont ete caracterisees ; les modifications de compositions de surface expliquent l'affaiblissement de la liaison substrat/depot

Os Sistemas Digitais de Múltiplas Tensões exploram o conceito de dimensionamento da tensão de alimentação através da aplicação de diferentes fontes para regiões específicas do chip. Cada uma destas regiões pertence a um domínio de energia e pode ter duas ou mais configurações de voltagens. Independentemente dos distintos níveis de energia em diferentes domínios de tensão, os blocos devem processar sinais com níveis lógicos coerentes. Nestes sistemas, os Conversores de Nível (LS do inglês Level Shifters) são componentes essenciais que atuam como interfaces de escalonamento da tensão entre domínios de energia, garantindo a correta transmissão dos sinais. Com a apropriada interface de escalonamento de tensão e sua correta implementação, pode-se evitar o consumo excessivo de potência dinâmica e estática. Portanto, a concepção e implementação de conversores de nível deve ser um processo consciente que garanta o menor sobrecusto no tamanho, consumo de energia, e tempo de atraso. Neste trabalho estudam-se as principais características das interfaces de escalonamento de tensão e se introduce um conversor de tensão com eficiência energética e área reduzida, adequado para a conversão de baixo a alto nível. Apresentam-se os conversores de nível com o melhor desempenho encontrados na literatura, os quais são categorizados em dois principais grupos: Dois trilhos (Dual-rail) e Único trilho (Single-rail), de acordo ao número de linhas de alimentação necessárias. O circuito proposto foi comparado com a topologia tradicional de cada grupo, o Differential Cascode Voltage Switch (DCVS) e o conversor de Puri respectivamente. Simulações na tecnologia CMOS 130nm da IBMTM mostram que a topologia proposta requer até 93,79% menos energia em determinadas condições. Esta apresentou 88,03% menor atraso e uma redução de 39,6% no Produto Potência-Atraso (PDP), quando comparada com a topologia DCVS. Em contraste com o conversor Puri, obteve-se uma redução de 32,08% no consumo de energia, 13,26% diminuição no atraso e 15,37% inferior PDP. Além disso, o conversor de nível proposto foi o único capaz de trabalhar a 35% da tensão nominal de alimentação.
Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different supplies to particular regions of the chip. Each of those regions belongs to a power domain and may have two or more supply voltage configurations. Regardless of distinct energy levels on different power domains, the blocks shall process signals with coherent logic levels. In these systems, the Level Shifters (LS) are essential components that act as voltage scaling interfaces between power domains, guaranteeing the correct signal transmission. With the appropriate voltage scaling interface and its proper implementation, we can avoid excessive static and dynamic power consumption. Therefore, the design and implementation of level shifters should be a conscientious process and must guarantee the lowest overhead in size, energy consumption, and delay time. In this work, we study the main characteristics of voltage scaling interfaces and introduce an energy-efficient level shifter with reduced area, and suitable for low-to-high level conversion. We present the level shifters with the best performance that we found in the literature and categorize them into two main groups: Dual-rail and Single-rail, according to the number of power rails required. The proposed circuit was compared to the traditional topology of each group, Differential Cascode Voltage Switch (DCVS) and Puri’s level shifter respectively. Simulations on an IBMTM 130nm CMOS technology show that the proposed topology requires up to 93.79% less energy under certain conditions. It presented 88.03% smaller delay and 39.6% less Power-Delay Product (PDP) when compared to the DCVS topology. In contrast with the Puri’s level shifter, we obtained a reduction of 32.08% in power consumption, 13.26% smaller delay and 15.37% lower PDP. Besides, our level shifter was the only one capable of working at 35% of the nominal supply voltage.

L’intégration des oscillateurs dans les microcontrôleurs est aujourd’hui un enjeu industriel majeur suscitant une forte concurrence entre les principaux acteurs du marché. En effet, les oscillateurs sinusoïdaux sont des circuits indispensables, et sont majoritairement basés sur l’utilisation d’un résonateur à quartz ou MEMS externe. De plus en plus d’investigations sont menées afin d’intégrer des dispositifs résonants dans les boîtiers et éviter ainsi toutes les contraintes extérieures limitant les performances de l’oscillateur. En ce sens, nous avons étudié dans ce travail le comportement électrique, et notamment inductif, des liaisons filaires permettant de connecter une puce à son boîtier de protection. L’avantage d’utiliser ce composant passif est principalement son faible coût. Ce composant a été caractérisé en utilisant plusieurs méthodologies de modélisations et de mesures sur une large plage fréquentielle. Cette étude propose un modèle permettant aux concepteurs d’utiliser une caractéristique électrique équivalente dans une technologie CMOS standard. L’intégration du composant dans une cellule résonante est démontrée au sein d’un prototype
Nowadays, the integration of oscillators into microcontrollers is a major industrial challenge which involves a large competition between the main actors of this market. Indeed, sine wave oscillators are essential circuits, and are fore the most part based on external crystal or MEMs resonators. More and more investigations are carried out in order to integrate the resonant structure into the package, and avoid all external constraints able to restrict the performances of the oscillator. With this in mind, we studied in this work the electrical behavior, in particular the inductive behavior of bond wires which are electrical connections between a die and its package. The main advantage to use this type of component is its low cost of manufacturing. This passive component has been characterized using several measurement tools on a wide range of frequencies. A RLC model has been presented, allowing analogue designers to use an electrical equivalent circuit in standard CMOS technology. The integration of the passive component in a resonant cell has been demonstrated in a prototype

O registro de sinais neurais através de matrizes de microeletrodos implantáveis no meio extracelular do córtex cerebral tem-se tornado um paradigma experimental para a neurociência. Por outro lado, a pesquisa recente sobre neuropróteses motoras tem mostrado que é possível decodificar comandos motores a partir dos sinais registrados no meio extracelular do córtex cerebral. Em ambos os contextos, neurociência experimental e desenvolvimento de neuropróteses motoras, um dos aspectos encontrados no estado da arte ´e a utilização de circuitos integrados (chips) implantados no cérebro. Nesses chips, os sinais neurais medidos com os microeletrodos são amplificados, filtrados, processados e transmitidos a um computador externo mediante fios que atravessam o crânio. Existe o interesse em desenvolver chips implantáveis que transmitam os sinais ao computador externo sem a necessidade de fios que atravessem o crânio. Na pesquisa do estado da arte tem-se encontrado a utilização de tais chips implantáveis sem fio em ratos e macacos, porém até a data da elaboração deste texto não foram encontrados relatos da aplicação em humanos. Um dos aspectos que deve se levar em consideração no desenvolvimento de interfaces neurais implantáveis sem fio é a largura de banda do canal de comunicação. Quanto maior a quantidade de dados a serem transmitidos, maior a largura de banda necessária e maior o aquecimento do chip devido à dissipação de potência. Esta tese aborda sistemas de processamento de sinais neurais extracelulares que tem como objetivo reduzir a quantidade de dados a serem transmitidos e assim viabilizar a transmissão sem fio. Para poder ser integrados dentro do chip implantável, esses sistemas de processamento devem estar otimizados em termos de área e consumo de potência. Dois processamentos encontrados na pesquisa de interfaces neurais implantáveis são a detecção de impulsos elétricos e a separação de impulsos elétricos (Spike Sorting). Nesta tese apresentam-se soluções para esses tipos de processamentos visando a implementação mediante tecnologia CMOS (Complementary Metal Oxide Semiconductor). Para o caso da detecção de impulsos elétricos (spikes), nesta tese apresenta-se uma alternativa de implementação em hardware de um operador matemático conhecido como operador não linear de energia (NEO do inglês Nonlinear Energy Operator) ou operador Teager. Através da aplicação desse operador a um sinal neural evidencia-se a presença de spikes e atenua-se o ruído. Uma das características inovadoras da implementação apresentada nesta tese é a utilização de um circuito elevador ao quadrado que consiste de apenas três transistores, como bloco funcional básico para a realização da operação NEO. O circuito NEO desenvolvido consome 300 pJ no processamento de um spike e foi caracterizado por simulação até em 30 kHz, frequência que é compatível com as taxas de amostragem encontradas na literatura. O outro processamento abordado nesta tese, conhecido como separação de impulsos elétricos ou Spike Sorting, consiste no agrupamento dos impulsos elétricos registrados por um eletrodo em categorias, de maneira que em uma categoria estejam os impulsos gerados por um mesmo neurônio. Em outras palavras, o objetivo é reconhecer quais dos impulsos elétricos medidos pelo eletrodo pertencem a um mesmo neurônio, sendo possível que vários neurônios influenciem na medida realizada por um único eletrodo. Uma solução para a separação de impulsos, apropriada no contexto de sistemas implantáveis, é o template matching. Essa técnica baseia-se na geração de modelos (templates) durante uma fase inicial ao final da qual o número de templates gerados corresponde ao número de neurônios identificados pelo eletrodo. Numa fase seguinte, o sistema associa cada impulso elétrico detectado a um dos modelos inicialmente gerados. Nesta tese propõe-se um sistema de classificação que executa essa segunda fase do processo de spike sorting. Nesta tese apresenta-se o projeto de um sistema de classificação de spikes baseado na t écnica template matching, implementado com tecnologia CMOS. A implementação proposta nesta tese baseia-se na representação de amostras analógicas mediante o tempo. Esse tipo de representação de sinais analógicos mediante atrasos de pulsos digitais está sendo muito utilizado como alternativa à representação no domínio da tensão, da corrente ou da carga elétrica. A vantagem desse tipo de representação é que não se vê severamente afetada pela redução da tensão de alimentação dos circuitos integrados fabricados em tecnologias submicrométricas. A taxa de acerto na classificação do sistema desenvolvido é maior que 99% inclusive considerando um offset de até 20mV no comparador de saída. Os circuitos apresentados neste trabalho foram projetados considerando dispositivos da tecnologia TSMC de 90nm.
Neural signals recording through implantable microelectrode arrays in cortex extracellular medium has become an experimental paradigm for neuroscience. Moreover, recent research about motor neuroprostheses has shown that it is possible to decode motor commands from the signals recorded in the cerebral cortex extracellular medium. In both situations, experimental neuroscience and motor neuroprostheses development, one of the issues encountered in the state-of-the-art is the use of integrated circuits (chips) implanted in the brain. In these chips, neural signals measured with microelectrodes are amplified, filtered, processed, and transmitted to an external computer through wires that run through the skull. There is interest in developing implantable chips that transmit signals to the external computer without the need for wires passing through the skull. In the survey of the state-of-the-art it has found the use of such implantable wireless chips in rats and monkeys, but until the date of this writing we have not found reports of application in humans. One of the aspects that must be taken into account in the development of wireless implantable neural interfaces is the bandwidth of the communication channel. The greater the amount of data to be transmitted, the greater the bandwidth required and higher chip heating due to power dissipation. This thesis deals with extracellular neural signals processing systems that aim to reduce the amount of data to be transmitted and in this way to enable wireless transmission. In order to integrate them into an implantable chip, those processing systems must be optimized in terms of area and power consumption. Two processes found in the research of implantable neural interfaces are spike detection and spike sorting. In this thesis solutions for these types of processing are presented considering their implementation by CMOS (Complementary Metal Oxide Semiconductor). For the case of spike detection in this thesis it is presented an alternative for the hardware implementation of a mathematical operator known as NEO (Nonlinear Energy Operator). Through the application of this operator to a neural signal the presence of spikes becomes evident and the noise is attenuated. One of the innovative characteristics of the implementation presented in this thesis is the use of a squarer circuit which consists of only three transistors, as a basic function block for performing operation of NEO. NEO circuit consumes 300 pJ in processing a spike, and was characterized by simulation up to 30 kHz, frequency which is compatible with sampling rates found in the literature. The other processing discussed in this thesis, known as Spike Sorting, is the grouping of electrical impulses recorded by an electrode into categories so that the spikes belonging to the same category were generated by a single neuron. In other words, the goal is to recognize which of the spikes measured by the electrode belong to the same neuron, given that it is possible that several neurons influence the measure performed by a single electrode. A solution for the Spike Sorting suitable in the context of implantable systems, is the template matching. This technique is based on generating templates during an initial phase at the end of which the number of generated templates corresponds to the number of neurons identified by the electrode. In the next phase, the system associates each detected spike to one of the templates generated initially. In this thesis it is proposed a classification systems which performs that second phase of the spike sorting process. This thesis presents the design of a spike classification system based on template matching technique, implemented in CMOS technology. The processing proposed in this work is based on the time-based representation of the analog samples. This kind of representation of analog signals by delays of digital pulses is being widely used as an alternative to the classical representation of samples by voltage, current or electric charge. The advantage of this time-mode representation is that it is not severely affected by reduced supply voltage of integrated circuits manufactured in sub-micrometer technologies. The classification hit rate of the developed system is greater than 99% even when an offset of 20 mV is assumed for the output comparator. All the circuits presented in this work were designed using devices from TSMC 90nm technology.

Several critical issues in the mechanics of the interface between the fibers and matrix in ceramic matrix composites (CMCs) are studied. The first issue is the competition between crack deflection and penetration at the fiber/matrix interface. When a matrix crack, the first fracture mode in a CMC, reaches the interface, two different crack modes are possible; crack deflection along the interface and crack penetration into the fibers. A criterion based on strain energy release rates is developed to determine the crack propagation at the interface. The Axisymmetric Damage Model (ADM), a newly-developed numerical technique, is used to obtain the strain energy in the cracked composite. The results are compared with a commonly-used analytic solution provided by He and Hutchinson (HH), and also with experimental data on a limited basis. The second issue is the stress distribution near the debond/sliding interface. If the interface is weak enough for the main matrix crack to deflect and form a debond/sliding zone, then the stress distribution around the sliding interface is of interest because it provides insight into further cracking modes, i.e. multiple matrix cracking or possibly fiber failure. The stress distributions are obtained by the ADM and compared to a simple shear-lag model in which a constant sliding resistance is assumed. The results show that the matrix axial stress, which is responsible for further matrix cracking, is accurately predicted by the shear-lag model. Finally, the third issue is multiple matrix cracking. We present a theory to predict the stress/strain relations and unload/reload hysteresis behavior during the evolution of multiple matrix cracking. The random spacings between the matrix cracks as well as the crack interactions are taken into account in the model. The procedure to obtain the interfacial sliding resistance, thermal residual stress, and matrix flaw distribution from the experimental stress/strain data is discussed. The results are compared to a commonly-used approach in which uniform crack spacings are assumed. Overall, we have considered various crack modes in the fiber-reinforced CMCs; from a single matrix crack to multiple matrix cracking, and have suggested models to predict the microscopic crack behavior and to evaluate the macroscopic stress/strain relations. The damage tolerance or toughening due to the inelastic strains caused by matrix cracking phenomenon is the key issue of this study, and the interfacial mechanics in conjunction with the crack behavior is the main issue discussed here. The models can be used to interpret experimental data such as micrographs of crack surface or extent of crack damage, and stress/strain curves, and in general the models can be used as guidelines to design tougher composites.
Ph. D.

Afin de poursuivre la miniaturisation des dispositifs CMOS, l'empilement HfO2/Métal a remplacé l'empilement SiO2/polySi. Cependant, la diffusion incontrôlée des espèces chimiques dans ces nouveaux empilements fabriqués avec un fort budget thermique compromet l'obtention des travaux de sortie (EWF) et des épaisseurs d'oxyde équivalent (EOT) définis par l'ITRS. Une solution consiste à utiliser une intégration à plus bas budget thermique. Avec cette nouvelle approche, l'objectif de ce travail de thèse était de comprendre les paramètres physiques permettant d'obtenir une EOT<1nm et des EWF permettant une co-intégration nMOS et pMOS pour des nœuds futurs CMOS 20-14 nm. En nous appuyant sur différents méthodes d'analyse physico-chimique (STEM EDX, TOF-SIMS et XPS), la distribution spatiale des éléments et leurs liaisons chimiques au sein d'empilements de taille nanométrique ont été discutées et, sur la base de considérations thermodynamiques, corrélées aux valeurs mesurées de l'EOT et EWF. Nous avons démontré pour la première fois un écart de ~0. 8eV entre une électrode TiAlNx déficitaire et riche en azote, déposée sur HfO2. Ces résultats ont été obtenus après avoir identifié les mécanismes qui contrôlent l'EWF et l'EOT dans des empilements plus simples TiN/Ti, Al et TiAl. Les grilles HfO2/TiAlNx ne sont cependant pas stables thermiquement. Nous avons alors proposé deux systèmes métalliques plus simples et plus stables utilisant des alliages TaNix et NiTix obtenus par interdiffusion dans les empilements HfO2/Ta/Ni et de HfO2/Ni/Ti. Ces structures de grilles à base de Ni apparaissent prometteuses pour une co-intégration CMOS à bas budget thermique
To continue CMOS scaling, the HfO2/metal gate stack replaced the historical SiO2/PolySi gate stack. But the uncontrolled interdiffusion and reactivities of the new gate materials integrated with the classical high thermal budget approach appear to be a roadblock to reach the effective work function (EWF) and equivalent oxide thickness (EOT) ITRS targets. One solution consisted in implementing an approach with a lower thermal budget. Using this new approach, the aim of this thesis work was to understand the physical mechanisms, which enable to reach an EOT<1nm and an EWF relevant for nMOS and pMOS co-integration as required for the next 20-14nm CMOS nodes. Using spatially resolved TEM/EDX analyses and macroscopic TOF-SIMS and XPS techniques, elemental distributions and chemical bonds across nanometric-sized stacks were discussed and, based on thermodynamic considerations, correlated with the measured EWF and EOT. We showed for the first time that the modulation of nitrogen during TiAlN deposition on HfO2 results in a ~0. 8eV EWF shift between the N-poor and N-rich HfO2/TiAlNx electrodes. The TiAlN complex system was understood after the identification of the EWF and EOT modulation mechanisms in the simple gate stacks TiN/Ti, Al or TiAl. Although TiAlNx electrodes define the best compromise for a variable EWF with a sub-nm EOT, it exhibits a low thermal stability. Therefore, we investigated two simpler metallic and stable systems using TaNix and NiTix alloys resulting from thermally assisted Ni-Ta and Ni-Ti interdiffusion in HfO2/Ta/Ni and HfO2/Ni/Ti stacks, respectively. These Ni-based electrodes are shown to be promising for a low thermal budget CMOS co-integration

La tecnología microelectrónica esta entrando a formar parte de la vida cotidiana. Así, además del ordenador PC, tanto en los vehículos, como en las viviendas es difícil encontrar equipos o subsistemas eléctricos que no incluyan algún tipo de circuito integrado para su control.
Aspectos como la automatización de viviendas y edificios se empieza a considerar una cuestión clave para la industria informática. Los cuales se basan en buses de campo. Estos precisan de sensores que le informen del estado de la vivienda, industria, vehículo... que se desea controlar, y actuadores que permitan modificar dicho estado.
Sin embargo, los sensores y actuadores son, en general, sistemas analógicos, con salidas difícilmente estandarizables si no se les incluye una electrónica que acondicione la señal, la convierta en digital, y la adapte a dicho estándar.
La respuesta a esta necesidad la han dado los microsistemas, que permiten incluir en una oblea de silicio sensores, actuadores y la electrónica de control necesaria dando lugar a los llamados sensores y actuadores inteligentes.
Sin embargo, la fabricación de estos microsistemas suele precisar de procesos tecnológicos complejos y costosos, que requieren de etapas que normalmente no se realizan en los procesos CMOS estándar. Esto puede implicar la necesidad de realizar el sensor/actuador en una oblea distinta de la del circuito, por problemas de compatibilidad entre procesos.
Esta tesis también se enmarca dentro de este campo, y busca el diseño de un circuito de interfaz para sensores capacitivos micromecanizados en silicio.
Teniendo en cuenta la posible utilización posterior, se ha impuesto que el diseño debe ser compatible con una tecnología CMOS de bajo coste. Esto lleva a realizar el diseño en tecnologías concebidas inicialmente para la implementación de circuitos digitales.
La salida del interfaz debe ser digital, para poder ser conectado fácilmente a un bus digital. Por este motivo, se ha realizado un estudio de las posibles metodologías de conversión.
Por último, se ha buscado un diseño siguiendo una metodología Top-Down, acorde con las utilizadas en las tecnologías digitales. Esto simplifica el proceso de diseño cuando se hacen sistemas mixtos, ya que se pueden realizar los diferentes pasos en paralelo.
A la hora de escribir esta tesis también se ha seguido este esquema, organizando los capítulos en el mismo orden.
Medida de Microsensores Capacitivos: Describe el problema de la medida, haciendo hincapié en los problemas que se pueden encontrar con un microsensor capacitivo. También realiza el estudio de un microsensor concreto, un acelerómetro xyz para el automovil.
Diseño Funcional: En este capítulo se estudian las posibles opciones para el diseño de la interfaz. Y posteriormente se analiza la estabilidad del sistema sensor-interfaz.
Diseño Estructural: A partir de las decisiones tomadas en el diseño funcional, se baja al nivel de bloques y se estudia que componentes y dispositivos son más adecuados para el diseño a partir de la modelización y simulaciones realizadas.
Diseño Físico: Se explica todo el proceso seguido para el diseño de las máscaras de la interfaz. Para ello se presenta una explicación más detallada de aquellos dispositivos que por sus características son más dependientes de las condiciones de las máscaras.
Test: Este último capítulo presenta la metodología seguida para la caracterización de los circuitos, así como los resultados obtenidos

Aim of this master’s thesis was design of front-end and back-end interfaces of electronic shopping system. Design consists of completing individual use-case and workflow diagrams. Next it was explored possible security risks, designed security actions against these risks, explored payment methods usable in electronic shopping systems and methods of its implementation. There was chosen PHP programming language in combination with MySQL relation database management system to be used for development of final application. As result of this work was development of electronic shopping system final application with extended user options, ability of placement at any business type and possibilities that present-day internet user expects from electronic shopping system. To accomplishment the aim of this work contributed implementation of extended user options as advanced catalog items sorting, multi level catalog structure and advanced search options. It succeeded in choosing and implementing designed security prevention and implementing of template engine into final application. Whole system is described in detail using data modeling and class diagrams.

Ultra low power wireless sensors and sensor systems are of increasing interest in a variety of applications ranging from structural health monitoring to industrial process control. Electrochemical batteries have thus far remained the primary energy sources for such systems despite the finite associated lifetimes imposed due to limitations associated with energy density. However, certain applications (such as implantable biomedical electronic devices and tire pressure sensors) require the operation of sensors and sensor systems over significant periods of time, where battery usage may be impractical and add cost due to the requirement for periodic re-charging and/or replacement. In order to address this challenge and extend the operational lifetime of wireless sensors, there has been an emerging research interest on harvesting ambient vibration energy. Vibration energy harvesting is a technology that generates electrical energy from ambient kinetic energy. Despite numerous research publications in this field over the past decade, low power density and variable ambient conditions remain as the key limitations of vibration energy harvesting. In terms of the piezoelectric transducers, the open-circuit voltage is usually low, which limits its power while extracted by a full-bridge rectifier. In terms of the interface circuits, most reported circuits are limited by the power efficiency, suitability to real-world vibration conditions and system volume due to large off-chip components required. The research reported in this thesis is focused on increasing power output of piezoelectric transducers and power extraction efficiency of interface circuits. There are five main chapters describing two new design topologies of piezoelectric transducers and three novel active interface circuits implemented with CMOS technology. In order to improve the power output of a piezoelectric transducer, a series connection configuration scheme is proposed, which splits the electrode of a harvester into multiple equal regions connected in series to inherently increase the open-circuit voltage generated by the harvester. This topology passively increases the rectified power while using a full-bridge rectifier. While most of piezoelectric transducers are designed with piezoelectric layers fully covered by electrodes, this thesis proposes a new electrode design topology, which maximizes the raw AC output power of a piezoelectric harvester by finding an optimal electrode coverage. In order to extract power from a piezoelectric harvester, three active interface circuits are proposed in this thesis. The first one improves the conventional SSHI (synchronized switch harvesting on inductor) by employing a startup circuitry to enable the system to start operating under much lower vibration excitation levels. The second one dynamically configures the connection of the two regions of a piezoelectric transducer to increase the operational range and output power under a variety of excitation levels. The third one is a novel SSH architecture which employs capacitors instead of inductors to perform synchronous voltage flip. This new architecture is named as SSHC (synchronized switch harvesting on capacitors) to distinguish from SSHI rectifiers and indicate its inductorless architecture.