Статті в журналах: "CMOS device"

1

Yedukondalu, Udara, Vinod Arunachalam, Vasudha Vijayasri Bolisetty, and Ravikumar Guru Samy. "Fully synthesizable multi-gate dynamic voltage comparator for leakage reduction and low power application." Indonesian Journal of Electrical Engineering and Computer Science 28, no. 2 (November 1, 2022): 716. http://dx.doi.org/10.11591/ijeecs.v28.i2.pp716-723.

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The paper presents the implementation of a standard cell multigate fully synthesizable rail-to-rail dynamic voltage comparator. The dynamic voltage comparator works on deep sub-threshold supply voltage VDD =0.3 V with common mode inputs. The common-mode input range is VDD/2 with minimum input offset voltage ranging between 8mV to 28mV. Thus the circuit is simulated at 180nm Complementary Metal-Oxide Semiconductor (CMOS) process. Hence the dynamic voltage comparator has measured and tabulated by corresponding output voltage, power dissipation. But the performance of CMOS device is not good when compared with Fin Field-Effect Transistor (FinFET) device. The leakage current is more in CMOS devices while in FinFET device due to the control of multi-Gates on the channel, the leakage current is reduced. This will improve the power consumption in the FinFET device when compared to CMOS devices. The comparator results shows that CMOS device is inferior when compared with FinFET device comparator. For the implementation of the comparator Spice model were used in this work. The software used in the project is synopsis Hspice.

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2

Xiong, Qi, Shao Hua Zhou, and Jiang Ping Zeng. "The Analysis of Device Model in CMOS Integrated Temperature Sensor." Advanced Materials Research 986-987 (July 2014): 1600–1605. http://dx.doi.org/10.4028/www.scientific.net/amr.986-987.1600.

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According to the requirement of the CMOS integrated temperature sensor on the device, we analyzed the sub-threshold model of MOS device and the bipolar device under MOS technology. We found the latter is more suitable for a components of CMOS integrated temperature sensor devices. Therefore, we analyzed the influence of the substrate PNP tube’s piezoelectric effect on temperature sensor and compared different types of resistance that lays a theoretical basis for the design of CMOS integrated temperature sensor.

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3

Chiovetti, Bob. ""Chip Wars" Heat Up On The Digital Imaging Front." Microscopy Today 7, no. 2 (March 1999): 3–4. http://dx.doi.org/10.1017/s1551929500063847.

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Although the Charge-Coupled Device (CCD) imaging chip is the standard in today's video and digital cameras, things may change during the coming year. The CCD chip is being challenged by a competing device, the CMOS ("C-moss") chip.CMOS is the most widely used type of integrated circuit for memory and digital processing, virtually everything in computers is CMOS based. The economies of scale and production of CMOS devices are the main reasons why computer prices have continued to drop during the past few years. If a device or an instrument has a microprocessor in it, chances are it includes CMOS technology..

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4

Shawkat, Mst Shamim Ara, Mohammad Habib Ullah Habib, Md Sakib Hasan, Mohammad Aminul Haque, and Nicole McFarlane. "Perimeter Gated Single Photon Avalanche Diodes in Sub-Micron and Deep-Submicron CMOS Processes." International Journal of High Speed Electronics and Systems 27, no. 03n04 (September 2018): 1840018. http://dx.doi.org/10.1142/s0129156418400189.

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A perimeter gated SPAD (PGSPAD), a SPAD with an additional gate terminal, prevents premature perimeter breakdown in standard CMOS SPADs. At the same time, a PGSPAD takes advantage of the benefits of standard CMOS. This includes low cost and high electronics integration capability. In this work, we simulate the effect of the applied voltage at the perimeter gate to develop a consistent electric field distribution at the junction through physical device simulation. Additionally, the effect of the shape of the device on the electric field distribution has been examined using device simulation. Simulations show circular shape devices provide a more uniform electric field distribution at the junction compared to that of rectangular and octagonal devices. We fabricated PGSPAD devices in a sub-micron process (0.5 μm CMOS process and 0.5 μm high voltage CMOS process) and a deep-submicron process (180 nm CMOS process). Experimental results show that the breakdown voltage increases with gate voltage. The breakdown voltage increases by approximately 1.5 V and 2.5 V with increasing applied gate voltage magnitude from 0 V to 6 V for devices fabricated in 0.5 μm and 180 nm standard CMOS process respectively.

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5

Wong, Hei. "Abridging CMOS Technology." Nanomaterials 12, no. 23 (November 29, 2022): 4245. http://dx.doi.org/10.3390/nano12234245.

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6

FOSSUM, JERRY G. "A SIMULATION-BASED PREVIEW OF EXTREMELY SCALED DOUBLE-GATE CMOS DEVICES AND CIRCUITS." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 563–72. http://dx.doi.org/10.1142/s0129156402001460.

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This paper gives a simulation-based preview of device-design issues and performance of extremely scaled DG CMOS. A suite of simulation tools, including a 2D numerical device simulator, a 1D numerical Poisson-Schrödinger solver, and a generic, physics/process-based DG MOSFET compact model in Spice, is applied to both asymmetrical-and symmetrical-gate DG CMOS devices and circuits to provide physical insight at the device and circuit levels. The results give added motivation as well as preliminary guidance for the development of DG CMOS.

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7

MOONEY, P. M. "MATERIALS FOR STRAINED SILICON DEVICES." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 305–14. http://dx.doi.org/10.1142/s0129156402001265.

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Strained Si devices exhibit enhanced carrier mobility compared to that of standard Si CMOS devices of the same dimensions. Recent strained Si CMOS device results are reviewed. Materials issues related to the strained Si/relaxed SiGe heterostructures required for a strained Si CMOS technology are discussed.

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8

Birla, Shilpi, Sudip Mahanti, and Neha Singh. "Leakage reduction technique for nano-scaled devices." Circuit World 47, no. 1 (May 29, 2020): 97–104. http://dx.doi.org/10.1108/cw-12-2019-0195.

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Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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9

Won, Jongun, Youngchae Roh, Minseung Kang, Yeaji Park, Jaehyeon Kang, Hyeongjun Seo, Changhoon Joe, and SangBum Kim. "A Capacitor-Based Synaptic Device with IGZO Access Transistors for Neuromorphic Computing." ECS Transactions 111, no. 2 (May 19, 2023): 133–36. http://dx.doi.org/10.1149/11102.0133ecst.

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Analog in-memory computing synaptic devices have been widely studied for efficient implementation of deep learning. As a candidate for a synaptic device, Si-CMOS and capacitor-based synaptic devices have been proposed. However, due to Si-CMOS leakage currents, it is difficult to achieve sufficient retention time. In our research, we verified IGZO TFT with low leakage current and capacitor-based synapses can show linear and symmetric weight update characteristics as well as excellent device variation characteristics. We also verified that IGZO TFT has a leakage current per channel width of 1μm of ~10-17A, which is much lower than the Si-CMOS, resulting in higher accuracy in deep neural network training.

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10

Tang, L., S. Latif, and D. A. B. Miller. "Plasmonic device in silicon CMOS." Electronics Letters 45, no. 13 (2009): 706. http://dx.doi.org/10.1049/el.2009.0839.

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11

David Theodore, N., Sophie Verdonckt-Vandebroek, C. Barry Carter, and S. Simon Wong. "Characterization of lateral bipolar transistor structures." Proceedings, annual meeting, Electron Microscopy Society of America 48, no. 4 (August 1990): 628–29. http://dx.doi.org/10.1017/s0424820100176277.

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Semiconductor devices are being scaled down into the submicron regime in order to meet technological demands for increased device-packing densities. Other factors considered for device design include low power dissipation, noise immunity, speed and high driving capability. Of these factors, high packing densities and low power dissipation can be derived using Coinplementary-Metal-Oxide-Semiconductor (CMOS) schemes. Bipolar-Junction-Transistor (BJT) schemes on the other hand provide driving capability, low noise performance and speed, at the expense however of greater device power- consumption. Combining CMOS and BJT technologies, a compromise can be struck between devicespeed and power dissipation. Most such combinations have resulted in vertical BJT requiring complex fabrication sequences. Recently, simpler lateral BJTs have been proposed for use in Bipolar CMOS processes. The viability of such semiconducting devices depends in part on the absence or controlled presence of structural defects. Diagnostic techniques are therefore required that are capable of high spatial resolution, for investigating the origin, behavior and possible elimination of fabrication-process-induced defects. Transmission electron microscopy (TEM) of device cross-sections can be effectively used for this purpose. In this study, lateral BJT structures are characterized using cross-section TEM and the results are correlated with electrical device-behavior.

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12

Kogut, Igor T., Victor I. Holota, Anatoly Druzhinin, and V. V. Dovhij. "The Device-Technological Simulation of Local 3D SOI-Structures." Journal of Nano Research 39 (February 2016): 228–34. http://dx.doi.org/10.4028/www.scientific.net/jnanor.39.228.

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This paper presents the device-technological simulation of local 3D SOI structures. These structures are created by use microcavities under surface of silicon wafer. Is shown that proposed microcavities could be use as a constructive material for CMOS transistor array on the bulk silicon and 3D SOI-CMOS transistor array, as well as the sensitive elements and their combinations. Such structures allow creation and monolithic integration the CMOS, SOI-CMOS circuits and sensitive elements for IC and SoC.

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13

Dhar, Subhra, Manisha Pattanaik, and Poolla Rajaram. "Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications." VLSI Design 2011 (May 26, 2011): 1–19. http://dx.doi.org/10.1155/2011/178516.

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In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.

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14

GABARA, THAD. "PULSED LOW POWER CMOS." International Journal of High Speed Electronics and Systems 05, no. 02 (June 1994): 159–77. http://dx.doi.org/10.1142/s0129156494000097.

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A simple CMOS circuit technique called PPS (Pulsed Power Supply) CMOS is used to reduce the power dissipation of Conventional 0.9 μm CMOS by 10X when operated at 32 MHz. Combinational and sequential logic can utilize this technique including the I/O (input/output) buffers. Thus, PPS CMOS offers a full chip solution for low power dissipation CMOS. In addition, several advantages occur in this new circuit technique: (1) low power signal propagation through several gates in series can occur during each evaluation cycle; (2) crowbar current does not occur; (3) additional placed devices, i.e. bipolar, diodes, JFETs are not required to generate this low power capability; (4) the Conventional CMOS process is used to fabricate the circuit; (5) the same physical layout can be used either as a PPS CMOS circuit or as a Conventional CMOS circuit; (6) the device count is the same as that of Conventional CMOS; (7) PPS CMOS uses quasistatic logic levels; (8) capacitive coupling is used to store and restore the contents of a memory cell; (9) the parasitic diodes of the MOS devices are used to improve the noise margin of the circuit; (10) PPS CMOS can easily hold a static state and have the same low power dissipation properties of data inactive Conventional CMOS.

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15

Poehls, L. M. Bolzani, M. C. R. Fieback, S. Hoffmann-Eifert, T. Copetti, E. Brum, S. Menzel, S. Hamdioui, and T. Gemmeke. "Review of Manufacturing Process Defects and Their Effects on Memristive Devices." Journal of Electronic Testing 37, no. 4 (August 2021): 427–37. http://dx.doi.org/10.1007/s10836-021-05968-8.

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AbstractComplementary Metal Oxide Semiconductor (CMOS) technology has been scaled down over the last forty years making possible the design of high-performance applications, following the predictions made by Gordon Moore and Robert H. Dennard in the 1970s. However, there is a growing concern that device scaling, while maintaining cost-effective production, will become infeasible below a certain feature size. In parallel, emerging applications including Internet-of-Things (IoT) and big data applications present high demands in terms of storage and computing capability, combined with challenging constraints in terms of size, power consumption and response latency. In this scenario, memristive devices have become promising candidates to complement the CMOS technology due to their CMOS manufacturing process compatibility, great scalability and high density, zero standby power consumption and their capacity to implement high density memories as well as new computing paradigms. Despite these advantages, memristive devices are also susceptible to manufacturing defects that may cause unique faulty behaviors that are not seen in CMOS, increasing significantly the complexity of test procedures. This paper provides a review about the manufacturing process of memristives devices, focusing on Valence Change Mechanism (VCM)-based memristive devices, and a comparative analysis of the CMOS and memristive device manufacturing processes. Moreover, this paper identifies possible manufacturing failure mechanisms that may affect these novel devices, completing the list of the already known mechanisms, and provides a discussion about possible faulty behaviors. Note that the identification of these mechanisms provides insights regarding the possible memristive devices’ defective behaviors, enabling to derive more accurate fault models and consequently, more suitable test procedures.

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16

Wimmer-Teubenbacher, Robert, Florentyna Sosada-Ludwikowska, Anton Köck, Stephan Steinhauer, Mukhles Sowwan, and Vidyadhar Singh. "Optimization of SnO2-Based CMOS-Integrated Gas Sensors by Mono-, Bi- and Trimetallic Nanoparticles." Proceedings 56, no. 1 (January 20, 2021): 43. http://dx.doi.org/10.3390/proceedings2020056043.

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In this paper, we report on the optimization of SnO2-based thin film gas sensor devices by mono-, bi- and trimetallic nanoparticles. Ag, AgRu, and AgRuPd nanoparticles are sputter deposited on CMOS-integrated SnO2-thin film gas sensor devices. The CMOS device is a worldwide unique chip containing an array of eight microhotplates. The response towards the target gas CO was dramatically increased from 10% to more than 70% by using trimetallic AgRuPd nanoparticles.

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17

Prasad, Vikash, and Debaprasad Das. "A Review on MOSFET-Like CNTFETs." Science & Technology Journal 4, no. 2 (July 1, 2016): 124–29. http://dx.doi.org/10.22232/stj.2016.04.02.06.

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Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

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18

Punjiya, Meera, Chung Hee Moon, Zimple Matharu, Hojatollah Rezaei Nejad, and Sameer Sonkusale. "A three-dimensional electrochemical paper-based analytical device for low-cost diagnostics." Analyst 143, no. 5 (2018): 1059–64. http://dx.doi.org/10.1039/c7an01837a.

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19

Krupar, Joerg, Heiko Hauswald, and Ronny Naumann. "A Substrate Current Less Control Method for CMOS Integration of Power Bridges." Advances in Power Electronics 2010 (September 23, 2010): 1–11. http://dx.doi.org/10.1155/2010/909612.

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Modern electronical devices use high integration to decrease device size and cost and to increase reliability. More and more devices appear that integrate even power devices into VLSI circuits. When driving inductive loads, this is a critical step because freewheeling at a power device appears. In these applications usually special technologies with extra wells for the power devices, SOI technologies, or BiCMOS technologies are required to suppress any substrate current. However, the use of these technologies results in higher production cost for the device. We present a method to control the freewheeling actively. Using this approach we are able to integrate the power devices using a normal CMOS technology.

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20

Sanchez Esqueda, Ivan, Hugh J. Barnaby, Keith E. Holbert, and Younes Boulghassoul. "Modeling Inter-Device Leakage in 90 nm Bulk CMOS Devices." IEEE Transactions on Nuclear Science 58, no. 3 (June 2011): 793–99. http://dx.doi.org/10.1109/tns.2010.2101616.

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21

Chen, An. "(Invited, Digital Presentation) Emerging Materials and Devices for Energy-Efficient Computing." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1073. http://dx.doi.org/10.1149/ma2022-01191073mtgabs.

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As the CMOS scaling driven by the Moore’s Law approaching the fundamental limits, high energy consumption and heat dissipation have been recognized as the most critical device challenges. Novel switching devices with significantly lower power based on unconventional mechanisms have been explored to replace CMOS in various research programs, e.g., Nanoelectronics Research Initiative (NRI). The major categories of these devices include steep-slope transistors, spintronic devices, ferroelectric devices, and van der Waals devices [1]. These devices are often implemented on emerging materials with unique properties. As the foundation of nanoelectronic devices and systems, novel materials (including dielectrics) present both great challenges and promising opportunities. For example, dielectric layers for gating and electrical insulation are critical for low-dimension devices; magnetic insulators are promising for low-power high-efficiency spintronic devices; ferroelectric materials have been utilized to realize “negative-capacitance” transistors with steep subthreshold slope. Despite abundant scientific breakthroughs achieved on these emerging devices, comprehensive benchmarking has revealed that most of them do not outperform CMOS for Boolean logic and von Neumann architectures [2]. Therefore, the focus of emerging materials and devices has increasingly shifted toward novel computing paradigms. Novel computing paradigms beyond Boolean logic and von Neumann architectures may provide solutions for energy-efficient computing. For example, in-memory computing reduces data movement between computing and memory units, and exploits the intrinsic parallelism in memory arrays. Neural-inspired computing implements cognitive and intelligent functions through a wide range of approaches, e.g., deep neural network, spiking neural network, hyperdimensional computing, probabilistic network, dynamic systems, etc. Although many of these approaches can be implemented in CMOS technologies, more efficient solutions may originate from the engineering and optimization of materials and devices that could enable native implementations of novel computing paradigms. For example, ferroelectric materials, binary and complex oxides, and chalcogenides have been utilized in a wide range of nonvolatile memories and analog devices, which may enable highly efficient in-memory computing and analog computing solutions. At the same time, stringent requirements exist for emerging devices to significantly outperform CMOS in novel computing paradigms, e.g., high density, fast speed, low power, high endurance, long retention, wide analog tunability, asymmetry, etc. [3] Specific requirements vary from application to application. Therefore, device-architecture co-design and co-optimization are important to address these requirements. A holistic approach from basic material exploration to device engineering and further up to architecture co-design has been adopted in more recent research programs, e.g., Energy-Efficient Computing from Devices to Architectures (E2CDA) [4]. This presentation will review the opportunities and challenges of emerging materials and devices for energy-efficient nanoelectronics, and highlight the approaches and perspectives of the E2CDA program. References: K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” IEEE Proc. 98(12), 2169-2184 (2010). C. Pan and A. Naeemi, “Non-Boolean computing benchmarking for beyond-CMOS devices based on cellular neural network,” IEEE J. Explor. Solid-State Comp. Dev. & Circ 2, 36-43 (2016). G.W. Burr, et al, “Neuromorphic computing using non-volatile memory,” Advances in Physics: X, 2(1), 89-124 (2017). A. Chen, “New directions of nanoelectronics research for computing,” 14th IEEE ICSICT (2018).

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22

Stepanov, Valery R., and Dmitry M. Nikulin. "COMPARISON OF THE CALCULATED WORKING RANGE OF THE THIRD GENERATION EOS AND MATRIX FOR NEAR IR RANGE." Interexpo GEO-Siberia 6, no. 2 (July 8, 2020): 88–92. http://dx.doi.org/10.33764/2618-981x-2020-6-2-88-92.

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In the course of work on the master's thesis the analysis of daytime and night-time devices was carried out. The analysis showed that devices based on CCD-matrixes prevail in this segment, but the devices of this type cannot be fully called night devices, because the sensitivity of the matrixes used in their designs does not allow to observe without illumination at natural night illumination of 10-3 lux. It is known that IR illumination is a strong unmasking factor.EOS can provide acceptable image quality in natural nightlight. But their use in day-night devices has limitations. Under prolonged exposure to high light, the photocathode of EOS quickly becomes unusable, so when developing a day-night device must provide EOS protection from daylight. Thus it was decided to use CMOS-matrix as an image receiver in the night channel. This, in turn, solves several problems at once. When using the photoreceiver there is no need for mechanical switching between the channels, as there is no danger of light. Also the spectral range of sensitivity of CMOS-matrixes is much more various than that of CCD and EOS that allows to pick up an optimum range of frequencies and to refuse illumination at normal night illumination. In this article a comparison of the calculated range of detection of the device on the basis of EOS of 3 generation with the device in which as the image receiver CMOS-matrix is used.

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23

Godfrey, M. D. "CMOS device modeling for subthreshold circuits." IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing 39, no. 8 (1992): 532–39. http://dx.doi.org/10.1109/82.168945.

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24

Manku, T. "Microwave CMOS-device physics and design." IEEE Journal of Solid-State Circuits 34, no. 3 (March 1999): 277–85. http://dx.doi.org/10.1109/4.748178.

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25

Kempf, P., R. Hadaway, and J. Kolk. "Complementary metal oxide semiconductor compatible high-voltage transistors." Canadian Journal of Physics 65, no. 8 (August 1, 1987): 1003–8. http://dx.doi.org/10.1139/p87-161.

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The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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26

Pan, James N. "Chromatic and Panchromatic Nonlinear Optoelectronic CMOSFETs for CMOS Image Sensors, Laser Multiplexing, Computing, and Communication." MRS Advances 5, no. 37-38 (2020): 1965–74. http://dx.doi.org/10.1557/adv.2020.273.

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AbstractTraditionally, CMOS transistors are for low power, high speed, and high packing density applications. CMOS is also commonly used as power regulating devices, and light sensors (CCD or CMOS image sensors). In this paper, we would like to introduce Photonic CMOS as a light emitting device for optical computing, ASIC, power transistors, and ultra large scale integration (ULSI). A Photonic CMOS Field Effect Transistor is fabricated with a low-resistance laser or LED in the drain region, and multiple photon sensors in the channel / well regions. The MOSFET, laser, and photon sensors are fabricated as one integral transistor. With embedded nonlinear optical films, the Photonic CMOSFETs have the capability of detecting and generating focused laser beams of various frequencies to perform optical computing, signal modulation, polarization, and multiplexing for digital / analog processing and communication.

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27

NASEH, SASAN, and M. JAMAL DEEN. "RF CMOS RELIABILITY." International Journal of High Speed Electronics and Systems 11, no. 04 (December 2001): 1249–95. http://dx.doi.org/10.1142/s0129156401001088.

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In this chapter the effects of hot carrier on the reliability of NMOS transistors are investigated. First, it is explained why the hot carrier issue can be important in RF CMOS circuits. Important mechanisms of hot carrier generation are reviewed and some of the techniques used in the measurement of hot carrier damages are explained. Next, results of measurement of DC hot carrier stress on the NMOS transistors are presented. The main focus here is the RF performance of the NMOS devices and circuits mode of them, but DC parameters of the device such as its I-V characteristics and threshold voltage are presented, as they directly affect the RF performance. Finally, using the measurements of hot carrier effects on single NMOS transistors, the effects of hot carriers on three parameters of a low noise amplifier, matching, power gain and stability, are predicted using circuit simulation.

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28

Wang, Wei, Hong-An Zeng, Fang Wang, Guanyu Wang, Yingtao Xie та Shijuan Feng. "A speed-optimized, low-noise APD with 0.18 μm CMOS technology for the VLC applications". Modern Physics Letters B 34, № 29 (18 липня 2020): 2050321. http://dx.doi.org/10.1142/s0217984920503212.

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A new avalanche photodiode device applied to a visible light communication (VLC) system is designed using a standard 0.18 [Formula: see text]m complementary metal oxide semiconductor process. Compared to regular CMOS APD devices, the proposed device adds a [Formula: see text]-well layer above the deep [Formula: see text]-well/[Formula: see text]-substrate structure, and an [Formula: see text]/[Formula: see text] layer is deposited upon it. The [Formula: see text]/[Formula: see text] layer acts as an avalanche breakdown layer of the device, and an STI structure is used to prevent the edge break prematurely. The simulation results shows that the avalanche breakdown voltage is as low as 9.9 V, dark current is below [Formula: see text] A under −9.5 V bias voltage, and the 3 dB bandwidth is of 5.9 GHz. It is due to the use of the 0.18 [Formula: see text]m CMOS process-specific STI protection ring and short-circuits the connection of the deep [Formula: see text]-well/[Formula: see text]-substrate, and the dark current is reduced to be lower than two orders of magnitude compared to regular CMOS APD. Gain and noise characteristics are accurately calculated from Hayat dead-space model applied to this CMOS APD. So, this device’s gain and excess noise factor are 20 and 2.5, respectively.

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29

Wagaj, S. C., and S. C. Patil. "Performance Analysis of CMOS Circuits using Shielded Channel Dual Gate Stack Silicon on Nothing Junctionless Transistor." International Journal of Engineering and Advanced Technology 10, no. 6 (August 30, 2021): 1–10. http://dx.doi.org/10.35940/ijeat.e2576.0810621.

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In this paper it has been demonstrated that a shielded channel made by varying the side gate length in silicon-on-nothing junctionless transistor not only improves the short channel effect but also improve the performance of CMOS circuits of this device. The proposed device shielded channel dual gate stack silicon on nothing junctionless transistor (SCDGSSONJLT) drain induced barrier lowering (DIBL), cut-off frequency and subthreshold slope are improved by 20%, 39% and 20% respectively over the single material gate silicon on insulator junctionless transistor (SMG SOI JLT). The proposed device CMOS inverter fall time Tf (pS) and noise margin improves by 50% and 10% compare to shielded channel silicon on insulator junctionless transistor (SCSOIJLT). It has been observed that circuit simulation of CMOS inverter, NAND and NOR of proposed device. The static power dissipation in the case of proposed SCDGSSONJLT device are reduced by 45%, 81% and 83% respectively over the SMGSOIJLT. Thus, significant improvement in DIBL, cut-off frequency, propagation delay and static power dissipation at low power supply voltage shows that the proposed device is more suitable for low power CMOS circuits.

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30

Heyns, M., and W. Tsai. "Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials." MRS Bulletin 34, no. 7 (July 2009): 485–92. http://dx.doi.org/10.1557/mrs2009.136.

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AbstractOver the years, many new materials have been introduced in advanced complementary metal oxide semiconductor (CMOS) processes in order to continue the trend of reducing the gate length and increasing the performance of CMOS devices. This is clearly evidenced in the International Technology Roadmap for Semiconductors (ITRS), which indicates the requirements and technological challenges in the microelectronics industry in various technology nodes. Every new technology node, characterized by the minimal device dimensions that are used, has required innovations in new materials and transistor design. The introduction of deposited high-κ gate dielectrics and metal gates as replacements for the thermally grown SiO2 and poly-Si electrode was a major challenge that has been met in the transition toward the 32 nm technology node since it replaced the heart of the metal oxide semiconductor structure. For the next generation of technology nodes, even bigger hurdles will need to be overcome, since new device structures and high-mobility channel materials such as Ge and III–V compounds might be needed, according to the ITRS roadmap, to meet the power and performance specifications of the 16 nm CMOS node and beyond. The basic properties of these high-mobility channel materials and their impact on the device performance have to be fully understood to allow process integration and full-scale manufacturing. In addition to thermal stability, compatibility with other materials, electronic transport properties, and especially the passivation of electronically active defects at the interface with a high-κ dielectric, are enormous challenges. Many encouraging results have been obtained, but the stringent demands in terms of electrical performance and oxide thickness scaling needed for highly scaled CMOS devices are not yet fully met. Other areas where breakthroughs will be needed are the formation of low-resistivity contacts, especially on III–V materials, and III–V materials suited for pMOS channels. An overview of the major successes and remaining critical issues in the materials research on high-mobility channel materials for advanced CMOS devices is given in this issue of MRS Bulletin.

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31

Dieck-Assad, Graciano, José Manuel Rodríguez-Delgado, and Omar Israel González Peña. "Excel Methods to Design and Validate in Microelectronics (Complementary Metal–Oxide–Semiconductor, CMOS) for Biomedical Instrumentation Application." Sensors 21, no. 22 (November 11, 2021): 7486. http://dx.doi.org/10.3390/s21227486.

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CMOS microelectronics design has evolved tremendously during the last two decades. The evolution of CMOS devices to short channel designs where the feature size is below 1000 nm brings a great deal of uncertainty in the way the microelectronics design cycle is completed. After the conceptual idea, developing a thinking model to understand the operation of the device requires a good “ballpark” evaluation of transistor sizes, decision making, and assumptions to fulfill the specifications. This design process has iterations to meet specifications that exceed in number of the available degrees of freedom to maneuver the design. Once the thinking model is developed, the simulation validation follows to test if the design has a good possibility of delivering a successful prototype. If the simulation provides a good match between specifications and results, then the layout is developed. This paper shows a useful open science strategy, using the Excel software, to develop CMOS microelectronics hand calculations to verify a design, before performing the computer simulation and layout of CMOS analog integrated circuits. The full methodology is described to develop designs of passive components, as well as CMOS amplifiers. The methods are used in teaching CMOS microelectronics to students of electronic engineering with industrial partner participation. This paper describes an exhaustive example of a low-voltage operational transconductance amplifier (OTA) design which is used to design an instrumentation amplifier. Finally, a test is performed using this instrumentation amplifier to implement a front-end signal conditioning device for CMOS-MEMS biomedical applications.

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32

Kurita, Kazunari, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda, and Yoshihiro Koga. "Proximity Gettering Design of Hydrocarbon–Molecular–Ion–Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors." Sensors 19, no. 9 (May 4, 2019): 2073. http://dx.doi.org/10.3390/s19092073.

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We developed silicon epitaxial wafers with high gettering capability by using hydrocarbon–molecular–ion implantation. These wafers also have the effect of hydrogen passivation on process-induced defects and a barrier to out-diffusion of oxygen of the Czochralski silicon (CZ) substrate bulk during Complementary metal-oxide-semiconductor (CMOS) device fabrication processes. We evaluated the electrical device performance of CMOS image sensor fabricated on this type of wafer by using dark current spectroscopy. We found fewer white spot defects compared with those of intrinsic gettering (IG) silicon wafers. We believe that these hydrocarbon–molecular–ion–implanted silicon epitaxial wafers will improve the device performance of CMOS image sensors.

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33

BISDOUNIS, LABROS. "ANALYTICAL MODELING OF OVERSHOOTING EFFECT IN SUB-100 nm CMOS INVERTERS." Journal of Circuits, Systems and Computers 20, no. 07 (November 2011): 1303–21. http://dx.doi.org/10.1142/s0218126611007967.

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Modeling of CMOS inverters and consequently, CMOS gates, is a critical task for improving accuracy and speed of simulation in modern sub-100 nm digital circuits. One of the key factors that determine the operation of a CMOS structure is the influence of the input-to-output coupling capacitance, also called overshooting effect. In this paper, an analytical model for this effect is presented, that computes the time period which is necessary to eliminate the extra output charge transferred through the input-to-output capacitance at the beginning of the switching process in a CMOS inverter. In addition, the maximum or minimum output voltage (depending on the considered edge) is analytically computed. The derived model is based on analytical expressions of the CMOS inverter output voltage waveform, which include the influences of both transistor currents and the input-to-output (gate-to-drain) coupling and load capacitances. An accurate version of the alpha-power law MOSFET model is used to relate the terminal voltages to the drain current in sub-100 nm devices, with an extension for varying transistor widths. The resulting model also accounts for the influences of input voltage transition time, transistors' sizes, as well as device carrier velocity saturation and narrow-width effects. The results produced by the presented model for three sub-100 nm CMOS technologies, several input voltage transition times, capacitive loads and device sizes, show very good agreement with BSIM4 HSPICE simulations.

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34

Tabata, Toshiyuki, Fabien Rozé, Louis Thuries, Sébastien Halty, Pierre-Edouard Raynal, Imen Karmous, and Karim Huet. "Recent Progresses and Perspectives of UV Laser Annealing Technologies for Advanced CMOS Devices." Electronics 11, no. 17 (August 23, 2022): 2636. http://dx.doi.org/10.3390/electronics11172636.

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The state-of-the-art CMOS technology has started to adopt three-dimensional (3D) integration approaches, enabling continuous chip density increment and performance improvement, while alleviating difficulties encountered in traditional planar scaling. This new device architecture, in addition to the efforts required for extracting the best material properties, imposes a challenge of reducing the thermal budget of processes to be applied everywhere in CMOS devices, so that conventional processes must be replaced without any compromise to device performance. Ultra-violet laser annealing (UV-LA) is then of prime importance to address such a requirement. First, the strongly limited absorption of UV light into materials allows surface-localized heat source generation. Second, the process timescale typically ranging from nanoseconds (ns) to microseconds (μs) efficiently restricts the heat diffusion in the vertical direction. In a given 3D stack, these specific features allow the actual process temperature to be elevated in the top-tier layer without introducing any drawback in the bottom-tier one. In addition, short-timescale UV-LA may have some advantages in materials engineering, enabling the nonequilibrium control of certain phenomenon such as crystallization, dopant activation, and diffusion. This paper reviews recent progress reported about the application of short-timescale UV-LA to different stages of CMOS integration, highlighting its potential of being a key enabler for next generation 3D-integrated CMOS devices.

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35

Liu, An-Chen, Po-Tsung Tu, Catherine Langpoklakpam, Yu-Wen Huang, Ya-Ting Chang, An-Jye Tzou, Lung-Hsing Hsu, Chun-Hsiung Lin, Hao-Chung Kuo, and Edward Yi Chang. "The Evolution of Manufacturing Technology for GaN Electronic Devices." Micromachines 12, no. 7 (June 23, 2021): 737. http://dx.doi.org/10.3390/mi12070737.

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GaN has been widely used to develop devices for high-power and high-frequency applications owing to its higher breakdown voltage and high electron saturation velocity. The GaN HEMT radio frequency (RF) power amplifier is the first commercialized product which is fabricated using the conventional Au-based III–V device manufacturing process. In recent years, owing to the increased applications in power electronics, and expanded applications in RF and millimeter-wave (mmW) power amplifiers for 5G mobile communications, the development of high-volume production techniques derived from CMOS technology for GaN electronic devices has become highly demanded. In this article, we will review the history and principles of each unit process for conventional HEMT technology with Au-based metallization schemes, including epitaxy, ohmic contact, and Schottky metal gate technology. The evolution and status of CMOS-compatible Au-less process technology will then be described and discussed. In particular, novel process techniques such as regrown ohmic layers and metal–insulator–semiconductor (MIS) gates are illustrated. New enhancement-mode device technology based on the p-GaN gate is also reviewed. The vertical GaN device is a new direction of development for devices used in high-power applications, and we will also highlight the key features of such kind of device technology.

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36

Kweon, Jun Young, and Yun-Heup Song. "CMOS Based Ovonic Threshold Switching Emulation Circuitry." Journal of Nanoscience and Nanotechnology 20, no. 8 (August 1, 2020): 4977–79. http://dx.doi.org/10.1166/jnn.2020.17807.

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Ovonic Threshold Switch (OTS) device is most popular switching device in PRAM. There are many OTS device research; however, it is hard to make reasonable OTS device which uses a circuit simulation and real device. In this work, we studied the OTS device emulation circuit, which can follow OTS characteristic, especially snapback current using 0.18 μm CMOS technology. This circuitry composes snapback current generator, cut off switch and output driver. Snapback current generator can make the current level up to 300 μA.

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37

Li, Shuo, Nan Pan, Sen Gao, and Lei Li. "Three State Output Module and Digital Switch Circuit Based on Threshold Memristor." Journal of Physics: Conference Series 2395, no. 1 (December 1, 2022): 012021. http://dx.doi.org/10.1088/1742-6596/2395/1/012021.

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Abstract A memristor is a new electronic device with small volumes and small fluctuations. As a two-terminal device, it is mainly characterized by non-volatility and nanoscale characteristic size. Memristors can also calculate and store at the same time, which has a broad application prospect in logic circuits. Traditional integrated circuit technology has been very mature. And CMOS technology has almost reached the limit of physical size. Compared with traditional circuit components, memristor devices are compatible with CMOS circuits with their fast computing speed, low power consumption, and small layout area. A three-state output module based on a threshold memristor is proposed. The structure includes an inverter, a PMOS tube, two NMOS tubes, and two threshold memristors. Compared with the traditional three-state gate which only uses CMOS technology, the circuit area required by the module is smaller and the overall power consumption is lower, which caters to the development trend of portable and low-power electronic devices. Then the digital switch circuit using this module is introduced, which provides a new idea for the data transmission circuit. The circuit and module are simulated and verified by LTspice software.

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38

Mulberry, Geoffrey, Kevin A. White, Matthew A. Crocker, and Brian N. Kim. "A 512-Ch Dual-Mode Microchip for Simultaneous Measurements of Electrophysiological and Neurochemical Activities." Biosensors 13, no. 5 (April 26, 2023): 502. http://dx.doi.org/10.3390/bios13050502.

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In the study of the brain, large and high-density microelectrode arrays have been widely used to study the behavior of neurotransmission. CMOS technology has facilitated these devices by enabling the integration of high-performance amplifiers directly on-chip. Usually, these large arrays measure only the voltage spikes resulting from action potentials traveling along firing neuronal cells. However, at synapses, communication between neurons occurs by the release of neurotransmitters, which cannot be measured on typical CMOS electrophysiology devices. Development of electrochemical amplifiers has resulted in the measurement of neurotransmitter exocytosis down to the level of a single vesicle. To effectively monitor the complete picture of neurotransmission, measurement of both action potentials and neurotransmitter activity is needed. Current efforts have not resulted in a device that is capable of the simultaneous measurement of action potential and neurotransmitter release at the same spatiotemporal resolution needed for a comprehensive study of neurotransmission. In this paper, we present a true dual-mode CMOS device that fully integrates 256-ch electrophysiology amplifiers and 256-ch electrochemical amplifiers, along with an on-chip 512 electrode microelectrode array capable of simultaneous measurement from all 512 channels.

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39

Cheng, Ying, Rui Kang, and Gan Ghua Zhang. "Failure Mechanisms and Lifetime Simulation Method for Nano Scale CMOS Device." Key Engineering Materials 483 (June 2011): 740–44. http://dx.doi.org/10.4028/www.scientific.net/kem.483.740.

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In nano scale, the degradation failure mechanism for CMOS device such as hot-carrier injection, breakdown of thin oxides, electro-migration and NBTI (Negative Bias Temperature Instability) induced damage become a major reliability concern. Physics-of-Failure method is used in lifetime prediction of nano scale CMOS, which integrates loading condition, package, geometry and material with time-to-failure. Common lifetime models for these mechanisms are described and a method to estimate lifetime of nano-scale CMOS device, with simulation based on Physics-of-Failure. Through Failure Mode, Mechanism and Effect Analysis, failure mechanism and lifetime models are clarified and selected, as well as structure, material, processing parameters and environment conditions. Stress analysis, which includes electrical stress by EDA and thermal analysis by FEA (Finite Element Analysis) are carried out to acquire parameters in lifetime model. Damage accumulation algorism and competing theory are utilized to predict lifetime of the device. This method will help CMOS device design engineers better understand the failure mechanisms in nano-scale and take design-for-reliability measures.

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40

Li, Bo, and Guoyong Shi. "A Native SPICE Implementation of Memristor Models for Simulation of Neuromorphic Analog Signal Processing Circuits." ACM Transactions on Design Automation of Electronic Systems 27, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3474364.

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Since the memristor emerged as a programmable analog storage device, it has stimulated research on the design of analog/mixed-signal circuits with the memristor as the enabler of in-memory computation. Due to the difficulty in evaluating the circuit-level nonidealities of both memristors and CMOS devices, SPICE-accuracy simulation tools are necessary for perfecting the art of neuromorphic analog/mixed-signal circuit design. This article is dedicated to a native SPICE implementation of the memristor device models published in the open literature and develops case studies of applying such a circuit simulation with MOSFET models to study how device-level imperfections can make adversarial effects on the analog circuits that implement neuromorphic analog signal processing. Methods on memristor stamping in the framework of modified nodal analysis formulation are presented, and implementation results are reported. Furthermore, functional simulations on neuromorphic signal processing circuits including memristors and CMOS devices are carried out to validate the effectiveness of the native SPICE implementation of memristor models from the perspectives of simulation accuracy, efficiency, and convergence for large-scale simulation tasks.

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41

Gignac, L. M., and K. P. Rodbell. "Metal Microstructures in Advanced CMOS Devices." Proceedings, annual meeting, Electron Microscopy Society of America 54 (August 11, 1996): 358–59. http://dx.doi.org/10.1017/s0424820100164258.

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As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

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42

Li, Yucheng, Shiqi Zhang, and Jianjun Song. "A Germanium Based Quantum Well Complementary Metal-Oxide-Semiconductor Transistor." Journal of Nanoelectronics and Optoelectronics 17, no. 9 (September 1, 2022): 1245–55. http://dx.doi.org/10.1166/jno.2022.3308.

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Germanium is recognized as an important prospective material due to its great carrier mobility. The current design and research of GeSn channel field effect transistors are far from mature. Especially the complementary Ge-based CMOS device is rarely reported. It significantly limits the application and development of Ge-based MOS technology. Based on this, a Si0.2Ge0.66Sn0.14-Ge0.82Sn0.18-Ge double heterojunction quantum well NMOS and PMOS are proposed. Benefiting from the high carrier mobility of Ge and the increased mobility brought by the quantum well, the proposed NMOS and PMOS device achieves mA level output current at 1 V gate bias, and the surface channel is significantly suppressed. Based on quantum well NMOS and PMOS, a new CMOS device compatible with the Si process is constructed. The quantum well CMOS inverter has a faster voltage conversion rate, a 4-fold reduction in propagation delay, a 10% reduction in output overshoot voltage, and a more robust driving capability than the Si-based CMOS inverter.

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43

Milo, Valerio, Gerardo Malavena, Christian Monzio Compagnoni, and Daniele Ielmini. "Memristive and CMOS Devices for Neuromorphic Computing." Materials 13, no. 1 (January 1, 2020): 166. http://dx.doi.org/10.3390/ma13010166.

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Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

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44

Mata-Hernandez, Diana, Daniel Fernández, Saoni Banerji, and Jordi Madrenas. "Resonant MEMS Pressure Sensor in 180 nm CMOS Technology Obtained by BEOL Isotropic Etching." Sensors 20, no. 21 (October 23, 2020): 6037. http://dx.doi.org/10.3390/s20216037.

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This work presents the design and characterization of a resonant CMOS-MEMS pressure sensor manufactured in a standard 180 nm CMOS industry-compatible technology. The device consists of aluminum square plates attached together by means of tungsten vias integrated into the back end of line (BEOL) of the CMOS process. Three prototypes were designed and the structural characteristics were varied, particularly mass and thickness, which are directly related to the resonance frequency, quality factor, and pressure; while the same geometry at the frontal level, as well as the air gap, were maintained to allow structural comparative analysis of the structures. The devices were released through an isotropic wet etching step performed in-house after the CMOS die manufacturing, and characterized in terms of Q-factor vs. pressure, resonant frequency, and drift vs. temperature and biasing voltage.

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45

Maclean, W., M. du Plessis, and J. Schoeman. "Optimisation of CMOS Compatible Microbolometer Device Performance." SAIEE Africa Research Journal 103, no. 1 (March 2012): 3–8. http://dx.doi.org/10.23919/saiee.2012.8531971.

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46

Takagi, Shinichi, Sanjeewa Dissanayake, and Mitsuru Takenaka. "High Mobility Ge-Based CMOS Device Technologies." Key Engineering Materials 470 (February 2011): 1–7. http://dx.doi.org/10.4028/www.scientific.net/kem.470.1.

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In this paper, we report on critical issues and possible solutions for realizing Ge MOSFETs on the Si platform. The main critical objectives in regard to Ge MOSFETs are (1) formation of high quality Ge channel layers on Si substrates (2) MIS gate stacks with much smaller EOT and interface defects (3) superior source/drain junction technology (4) combination of mobility booster technologies such as surface orientation and strain. We demonstrate that GeO2/Ge MOS interfaces can provide superior interface properties, leading to high hole and electron mobility. It is also shown that a gas phase doping technique is promising for forming superior n+/p junctions, which is critical for obtaining Ge nMOSFETs. Also, the importance of surface orientation engineering on the further mobility enhancement of Ge CMOS is addressed.

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47

Tzou, J. J., C. C. Yao, R. Cheung, and H. Chan. "Some CMOS device constraints at low temperatures." IEEE Electron Device Letters 6, no. 1 (January 1985): 33–35. http://dx.doi.org/10.1109/edl.1985.26033.

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48

Chen, J. Y., and D. E. Snyder. "Modeling device isolation in high-density CMOS." IEEE Electron Device Letters 7, no. 2 (February 1986): 64–65. http://dx.doi.org/10.1109/edl.1986.26295.

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49

Dellmann, L., U. Drechsler, T. Morf, H. Rothuizen, R. Stutz, J. Weiss, and M. Despont. "3D opto-electrical device stacking on CMOS." Microelectronic Engineering 87, no. 5-8 (May 2010): 1210–12. http://dx.doi.org/10.1016/j.mee.2009.11.170.

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50

Škereň, Tomáš, Nikola Pascher, Arnaud Garnier, Patrick Reynaud, Emmanuel Rolland, Aurélie Thuaire, Daniel Widmer, Xavier Jehl, and Andreas Fuhrer. "CMOS platform for atomic-scale device fabrication." Nanotechnology 29, no. 43 (August 24, 2018): 435302. http://dx.doi.org/10.1088/1361-6528/aad7ab.

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