Дисертації з теми "CMOS device"
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Rakheja, Shaloo. "Interconnects for post-CMOS devices: physical limits and device and circuit implications." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/45866.
Повний текст джерелаYu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
Повний текст джерелаPh.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
Jain, Ishita. "Modeling and simulation of self-heating effects in sub-14NM CMOS devices." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8137.
Повний текст джерелаWu, Dongping. "Novel concepts for advanced CMOS : Materials, process and device architecture." Doctoral thesis, KTH, Microelectronics and Information Technology, IMIT, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-3805.
Повний текст джерелаThe continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.
High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO2and Al2O3as well as their mixtures are investigated assubstitutes for the traditionally used SiO2in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.
A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.
Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.
Xu, Chen. "Low voltage CMOS digital imaging architecture with device scaling considerations /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20XU.
Повний текст джерелаIncludes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.
Kopalle, Deepika Niu Guofu. "RF linearity analysis in nano scale CMOS using harmonic balance device simulations." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/KOPALLE_DEEPIKA_43.pdf.
Повний текст джерелаOdanaka, Shinji. "A STUDY OF NUMERICAL PROCESS AND DEVICE MODELING CAD FOR SUBMICROMETER CMOS." Kyoto University, 1990. http://hdl.handle.net/2433/86214.
Повний текст джерелаWang, Haihong. "Advanced transport models development for deep submicron low power CMOS device design /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Повний текст джерелаHUSSAIN, IZHAR. "TAMTAMS: A web based performance estimation tool from Device to System level for advanced CMOS processes to beyond CMOS technologies." Doctoral thesis, Politecnico di Torino, 2018. http://hdl.handle.net/11583/2710840.
Повний текст джерелаAbel, Christopher J. "An investigation of nonideal process and device effects in fundamental CMOS analog subcircuits /." The Ohio State University, 1995. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487865929454587.
Повний текст джерелаGreig, Thomas Alexander. "Development of CMOS active pixel sensors." Thesis, Brunel University, 2008. http://bura.brunel.ac.uk/handle/2438/5345.
Повний текст джерелаMoen, Kurt Andrew. "Predictive modeling of device and circuit reliability in highly scaled CMOS and SiGe BiCMOS technology." Diss., Georgia Institute of Technology, 2012. http://hdl.handle.net/1853/44700.
Повний текст джерелаCanals, Gil Joan. "A portable device for time-resolved fluorescence based on an array of CMOS SPADs with integrated microfluidics." Doctoral thesis, Universitat de Barcelona, 2020. http://hdl.handle.net/10803/669582.
Повний текст джерелаTradicionalment, l'anàlisi molecular es realitza en laboratoris equipats amb instruments de sobretaula operats per tècnics especialitzats. Aquest paradigma ha anat canviant en les últimes dècades, a mesura que la tecnologia de biosensor s'ha tornat tan precisa com els instruments de sobretaula, proporcionant resultats en períodes molt més curts de temps i miniaturitzant la instrumentació, permetent així, traslladar gradualment les proves de diagnòstic fora de laboratori central. No obstant això i malgrat els avantatges inherents de l'espectroscòpia de fluorescència resolta en el temps aplicada a la diagnosi molecular, no ha estat fins a l'última dècada que s'han començat a desenvolupar dispositius POC (Point Of Care) basats en la detecció de la fluorescència, degut al desafiament que suposa el desenvolupament de sensors espectroscòpics d'alt rendiment, portàtils i de baix cost. Aquesta tesi presenta el desenvolupament d'un sistema compacte, robust i de baix cost per al diagnòstic molecular basat en l'espectroscòpia de fluorescència resolta en el temps, que serveixi com a plataforma d'ús general per a la detecció òptica d'una varietat de biomarcadors, tancant la bretxa entre el laboratori i el POC dels bioassaigs basats en l'anàlisi de la pèrdua de la fluorescència. En particular, s'han desenvolupat dos sistemes amb diferents nivells d'integració que combinen una matriu unidimensional de píxels SPAD (Single-Photon Avalanch Diode) capaços de detectar un sol fotó, amb un cartutx microfluídic intercanviable emprat per inserir la mostra, així com un díode làser UV premut de baix cost com a font d'excitació. El disseny orientat a la detecció per contacte de l'binomi format pel sensor i la microfluídica, juntament amb l'operació temporitzada dels sensors, permet prescindir de l'ús de lents i filtres. Al seu torn, l'empaquetat a mida de l'xip sensor permet posicionar el cartutx microfluídic directament sobre la matriu de sensors sense cap procediment d'alineament. Tots dos sistemes han estat validats determinant el temps de descomposició de "quantum dots" en 20 nl de solució per a diferents concentracions, emulant així un assaig molecular en un dispositiu POC.
Brotman, Susan Rose. "The Evaluation of Device Model Dependence in the Design of a High-Frequency, Analog, CMOS Transconductance-C Filter." PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4701.
Повний текст джерелаMA, JUN. "STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES." Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3547.
Повний текст джерелаPh.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
LI, HANG. "DESIGN OF A 32 BY 32 BIT READ HEAD DEVICE FOR PAGE-ORIENTED OPTICAL MEMORY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1037304111.
Повний текст джерелаTANG, JIANJING. "DESIGN AND ANALYSIS OF A 32X32-BIT DATABASE FILTER CHIP BASED ON A CMOS COMPATIBLE PHOTONIC VLSI DEVICE TECHNOLOGY." University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1059399964.
Повний текст джерелаLarsen, Frode. "Bipolar device characterization and design in CMOS technologies for the design of high-performance low-cost BiCMOS analog integrated circuits /." The Ohio State University, 1994. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487857546387163.
Повний текст джерелаNikolaidis, Théodoros. "Optimisation des performances ESD de circuits intègres CMOS submicroniques." Grenoble INPG, 1995. http://www.theses.fr/1995INPG0185.
Повний текст джерелаAlzoubi, Khawla Ali. "NANO-ELECTRO-MECHANICAL SWITCH (NEMS) FOR ULTRA-LOW POWER PORTABLE EMBEDDED SYSTEM APPLICATIONS: ANALYSIS, DESIGN, MODELING, AND CIRCUIT SIMULATION." Case Western Reserve University School of Graduate Studies / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1278511770.
Повний текст джерелаSahoo, Amit Kumar. "Electro-thermal Characterizations, Compact Modeling and TCAD based Device Simulations of advanced SiGe : C BiCMOS HBTs and of nanometric CMOS FET." Thesis, Bordeaux 1, 2012. http://www.theses.fr/2012BOR14557/document.
Повний текст джерелаAn extensive evaluation of different techniques for transient and dynamic electro-thermal behavior of microwave SiGe:C BiCMOS hetero-junction bipolar transistors (HBT) and nano-scale metal-oxide-semiconductor field-effect transistors (MOSFETs) have been presented. In particular, new and simple approach to accurately characterize the transient self-heating effect, based on pulse measurements, is demonstrated. The methodology is verified by static measurements at different ambient temperatures, s-parameter measurements at low frequency region and transient thermal simulations. Three dimensional thermal TCAD simulations are performed on different geometries of the submicron SiGe:C BiCMOS HBTs with fT and fmax of 230 GHz and 290 GHz, respectively. A comprehensive evaluation of device self-heating in time and frequency domain has been investigated. A generalized expression for the frequency-domain thermal impedance has been formulated and that is used to extract device thermal impedance below thermal cut-off frequency. The thermal parameters are extracted through transistor compact model simulations connecting electro-thermal network at temperature node. Theoretical works for thermal impedance modeling using different networks, developed until date, have been verified with our experimental results. We report for the first time the experimental verification of the distributed electrothermal model for thermal impedance using a nodal and recursive network. It has been shown that, the conventional single pole thermal network is not sufficient to accurately model the transient thermal spreading behavior and therefore a recursive network needs to be used. Recursive network is verified with device simulations as well as measurements and found to be in excellent agreement. Therefore, finally a scalable electro-thermal model using this recursive network is developed. The scalability has been verified through numerical simulations as well as by low frequency measurements and excellent conformity has been found in for various device geometries
Simionovski, Alexandre. "Sensor de corrente transiente para um sistema de proteção de circuitos integrados contra erros induzidos por radiação ionizante." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2018. http://hdl.handle.net/10183/179523.
Повний текст джерелаA current sensor to detect the occurrence of a single-event transient that is caused by the incidence of ionizing radiation in an integrated circuit is presented. Radiation of interest and their effects on the integrated circuits are discussed. Fundamentals of the Bulk-BICS technique and the circuits proposed in the literature to implement this technique are discussed and evaluated, with emphasis on the dynamic memory cell-based circuit DynBICS, which was developed as a previous work and with fabricated samples available. Experimental results obtained from a series of electrical tests, a TID test, and a laser-stimulated test that were conducted on a number of fabricated and packaged samples are presented. The results confirm that the dynamic memory cell is suitable and robust enough to be used in Bulk-BICS circuits. Next, evolution of the dynamic memory cell into an integrative memory cell is discussed and the circuit of a Bulk-BICS using this new memory cell topology is presented. The electrical operation of this new sensor TRIBICS is evaluated using circuit simulations. By using double-exponential current pulses, both the sensitivity and the response time are determined. The static memory cell operation is analyzed and a comparison of performance between static and integrative cells is performed using a simplified model. The results show that the integrative memory cell is faster and more sensitive than the static cells used in three state-ofthe- art sensors published in literature Then the TRIBICS sensor is simulated connected to a TCAD-modeled device, comprising an inverter, which is used as a target for radiation impact. TCAD models are previously presented and the results obtained when the PMOS and NMOS transistors are separately excited by radiation show the formation of a conductive link between drain and source regions during the occurrence of SET. The simulations also show that the results obtained by using TCAD simulations do not agree with the ones obtained by using circuit simulation regarding the current share among drain, source and bulk during the SET. Mixed-mode simulations using the TCAD models in conjunction of TRIBICS circuits described in SPICE show the relationship between LET and the effective SET-detection with the inter-tap distance as a parameter, and allows to determine the inter-tap distance for 100% of SET detection efficiency. Based on these results, an estimate of how many transistors can be monitored by the Bulk-BICS is obtained. It is proposed to implement the Bulk-BICS as a standard cell, to be positioned in between the standard cell that compose a digital circuit and the area overhead necessary to implant the sensors in a real circuit is estimated. The problem on how to manufacture the Bulk-BICS circuit in the same substrate of the monitored transistors is studied and a solution is proposed. The results show the viability and effectiveness of the Bulk-BICS technique, as a means to detect single-event transients in digital systems.
Chouard, Florian Raoul Verfasser], Doris [Akademischer Betreuer] [Schmitt-Landsiedel, and Sebastian M. [Akademischer Betreuer] Sattler. "Device Aging in Analog Circuits for Nanoelectronic CMOS Technologies / Florian Raoul Chouard. Gutachter: Sebastian M. Sattler ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel." München : Universitätsbibliothek der TU München, 2012. http://d-nb.info/1024355020/34.
Повний текст джерелаOsberger, Laurent. "Etude de magnétomètres haute performance intégrés en technologie silicium." Thesis, Strasbourg, 2017. http://www.theses.fr/2017STRAD012.
Повний текст джерелаThe subject of thesis subject concerns the study of magnetic field sensors integrated in low-voltage standard CMOS process without additional post-processing steps. Co-integrating the magnetic transducer (the sensitive element transforming the magnetic field into an electrical quantity) together with its conditioning electronics onto a same chip allows to implement specific features, which dramatically improve the sensor performances. This work particularly focuses on two types of transducer: the vertical Hall device and a specific magneto-transistor called “CHOPFET”. We developed numerical simulation models in order to predict and optimize the behavior of these transducers. Based on the results, we adapted dedicated signal processing techniques and proposed several innovative magnetic signal conditioning architectures. This led to significant improvement in terms of resolution, offset and power consumption
Ma, Wei. "Linearity Analysis of Single and Double-Gate Silicon-On-Insulator Metal-Oxide-Semiconductor-Field-Effect-Transistor." Ohio University / OhioLINK, 2004. http://www.ohiolink.edu/etd/view.cgi?ohiou1103138153.
Повний текст джерелаJouvet, Nicolas. "Intégration hybride de transistors à un électron sur un noeud technologique CMOS." Phd thesis, INSA de Lyon, 2012. http://tel.archives-ouvertes.fr/tel-00863770.
Повний текст джерелаBari, Mohammad Rezaul. "Fabrication, Characterization, and Modelling of Self-Assembled Silicon Nanostructure Vacuum Field Emission Devices." Thesis, University of Canterbury. Electrical and Computer Engineering, 2011. http://hdl.handle.net/10092/6601.
Повний текст джерелаKerber, Andreas. "Methodology for electrical characterization of MOS devices with alternative gate dielectrics." Phd thesis, [S.l. : s.n.], 2004. http://elib.tu-darmstadt.de/diss/000404.
Повний текст джерелаBouaziz, Jordan. "Mémoires ferroélectriques non-volatiles à base de (Hf,Zr)O2 pour la nanoélectronique basse consommation." Thesis, Lyon, 2020. http://www.theses.fr/2020LYSEI057.
Повний текст джерелаSince 2005, the scaling of memory devices, which used to follow Moore's law, slowed down. This lead researchers to conduct multiple approaches in order to keep improving memory devices. Among these approaches, the pathway on ferroelectric components seems very promising. In 2011, a research team from the NamLab in Dresden, Germany, discovered that Si-doped HfO2 could become ferroelectric with an insulating layer of only 10 nm, which resolves the compatibility issue of perovskite-structured materials with CMOS industry. Since then, other dopants have been investigated. However, new issues are now slowing down the emergence of HfO2-based ferroelectric devices on the market. Understanding the mechanisms behind the ferroelectric properties of these materials has, therefore, become a major industrial issue. In this manuscript, we study (Hf,Zr)O2 (HZO), and we perform an under-utilized technique to elaborate this kind of material: magnetron sputtering. The goal of this thesis is to establish connections between the growth conditions of this material and the electrical properties, to understand the mechanisms behind them, as well as to make the memory devices viable. During the fabrication of the capacitors, we demonstrate that the particular cristallochemical properties are essential to obtain ferroelectricity, and that novel HZO properties are discovered. Afterwards, we seek to cross the state of the art. The results we obtain by sputtering are among the best in the world. The industrial endurance and retention tests are pushed beyond what has been done in the literature so far. Particularly, the influence of electrical stress conditions is thoroughly detailed, and we put to evidence the presence of a relaxation during the different tests that could turn out to become problematic for the emergence of industrial applications. It does not seem that this problem has been identified beforehand
Chang, Meng-Jen, and 張夢仁. "Automatic Measurement for Device/Process Parameters Extraction of Advanced CMOS Device." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/00152933355850759911.
Повний текст джерела國立臺北科技大學
機電整合研究所
89
The MOSFET is the building block of ULSI circuits in microprocessor and dynamics memories. In order to increase the packing density and to improve circuit performance, many researchers have invested their efforts in scaling down the CMOS device size. However, simply reducing device dimension without paying attention to other processing parameters will cause a variety of non-ideal characteristic. In CMOS technology, channel length is a key parameter used for device design and circuit simulation. Though many methods have been proposed for the extraction of effective channel length. Most of them are based on I-V measurement and some others are based on C-V measurement. But they are all failed as the generation goes down to quarter micron or beyond. In this thesis we proposed a new approach for extracting advanced CMOS device parameters by using a modified C-V method, named capacitance-ratio method (C-R method). According to the C-R method, we could determine the effective channel length , metallurgical channel length , process bias , extension overlap bias , source-to-drain series resistance , and the gate to drain capacitance easily. By the algorithm of C-R method, we want to develop an automatic measurement system to help extracting these parameters. With the help of automatic measurement system, one can easily extract parameters and monitor fabrication process. The greatest worth of the system is able to get reasonable and consistent results, besides the cost and time in measurement will be lower in future application. Finally, We show the ease of using our system to extract thin gate oxide parameter.
Cheng, C. B., and 鄭召寶. "CMOS/SOI Device Simulation:Accumulation Mode vs.Enhancement Mode." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/84418223502980781303.
Повний текст джерела國立交通大學
電子研究所
83
Silicon on insulator (SOI) technology is a promising candidate for future ULSI as the quality of SOI material continues to improve. Thin (less than 1000A) SOI film thickness which makes fully depleted SOI MOSFETs is important for minimization of short channel effects, easy isolation, elimination of latch-up, steeper subthreshold slopes, and increased current drive capability which will make low power and high speed devices work well. The purpose of this research is to investigate: A. the dependence of fully depleted SOI as the devices are scaled down to deep submicron area. Three key parameters: (1). The threshold voltage (2). Subthreshold swing (3). Current drive capability B. the scaling rule of CMOS/SOI. Si film thickness, gate oxide thickness , channel length, and channel doping will be the key parameters in this investigation. 2D device simulator is used in device optimization and in gaining insight of physical mechanism.
Huang, Shin-Duen, and 黃信惇. "Gate oxide reliability of advance CMOS device." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/51931041390158072911.
Повний текст джерела國立成功大學
微電子工程研究所碩博士班
91
In this thesis, the sample is an 8inch wafer for 0.15μm technology n-MOSFET’s and p-MOSFET’s and we researched on oxide reliability. As devices scaling down, the device operational voltage and some characteristic still decreases slowly. The area and the thickness of the device oxide layer also decreased that varied the characteristic representation. So the dielectric oxide layer in MOSFET is to pay much attention to people. My experiment focuses on the difference between thin and thick oxide layer and finds the difference of the characteristic between before breakdown and after breakdown. First, I use ramp voltage test and constant voltage test to confer the difference of the I-V changes. Then I use the past breakdown definition to analyze the I-V curve. I want to find what influence on device between thin and thick oxide layer. Besides, I try to generalize it has the more accurate way to define the device breakdown. In these experiments, we used ICS (Interactive Characterization Software) to control HP4155B (Semiconductor Parameter Analyzer) produced by Agilent Technologies and 4200-SCS system produced by Keithley to finish various researches.
Lin, Feng-Wei, and 林峰濰. "Device-partition method and its application to 2-D CMOS device simulation." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/68438742946534956455.
Повний текст джерела國立中央大學
電機工程研究所
91
Abstract In this thesis, we focus on how to effectively save required memory space when simulate a semiconductor device. We develop four different methods to simulate semiconductor devices. First method is coupled method(CM). It requires biggest memory space in all of the methods. Second method is partial decoupled method(PDM). The memory space with PDM is less than CM. Last, we develop device-partition method. It can be divided into two different modes. One is overlapped mode, the other is unoverlapped mode. The advantage of device-partition method is that our program can be compiled without limitation by memory space. We will use these methods to simulate an n-channel MOSFET and compare simulation result. Finally, we will use these methods to simulate a CMOS circuit and compare simulation result also.
Wang, Chun-Sheng, and 王俊升. "Study on substrate effect of RF CMOS device." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/32772666654583251198.
Повний текст джерела國立中興大學
電機工程學系所
98
In this thesis, the substrate resistance of multi-finger MOSFET have been analyzed. Concentrate on the extraction methods and performance analysis of substrate resistance. Using four kinds of guard-ring structure of NMOS transistors to analyze the behavior of Rsub. A small signal model with substrate resistance is proposed to extract the model parameters. In corporate the calculation of substrate resistance using layout configuration, the substrate resistance is characterized comprehensively. We can find that transistor M3(two-sides structure) has biggest Rsub, M1(ring structure) is smallest. To predict the behavior using layout configuration and identify the impact factor in the layout of Rsub. Finaly, two figure-of-merit (FOMs) of MOSFETs, cut off frequency (fT) and maximum oscillation frequency (fmax) were used to characterize these four NMOS FETs in radio-frequency operation. The results show that the fT are the same , while the fmax is proportional to the Rsub. Hence the Rsub affects unilateral power gain U. Measurement demonstrates that the proposed algorithm is consort with the extract approach.
Tsao, Chih-Pin, and 曹志彬. "Hot-Carrier reliability in deep submicron CMOS device." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/16925700898041641574.
Повний текст джерела國立成功大學
微電子工程研究所碩博士班
90
In this study, the effects of hot-carrier induced drain current degradation and gate leakage current induced by ultra-thin gate oxide on 0.18μm and 0.15μm CMOS devices will be investigated. In the first chapter, the background of hot-carrier effects will be discussed. Results show that in deep submicron device, the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than 0.1V which was well known as the worst case condition in long channel device. The worst case of characterized Vd was found to lager at higher temperature and substrate bias. A simplified model was presented to explain this new observation. Results show that the lowering of quasi-fermi level and the effect of the velocity saturation region (DL) contribute to the monotonically decrease ΔID/ID (%) as a function of measured VD. However, Qinv near the drain side also decreases since Vc increases. This mechanism results in the increase in DId/Id. Hence, the value of the worst case of characterized Vd is determined by this two competing mechanisms. In the third chapter, enhanced hot-carrier induced Id degradation under high gate voltage stress was observed in pMOSFETs. Some mechanisms which may contribute to this phenomenon are discussed here。Results show that (I) F-N tunneling-current stress has finite effect on enhanced high gate voltage stress although gate oxide electric field as high as above 15MV/cm was applied. Anode hole injection model was adopted to explain the server F-N tunneling effect on pMOSFET than on nMOSFET. The hole component of the injected F-N tunneling-current was found to the dominant mechanism. (II) Electron tunneling from the gate due to ultra-thin gate oxide and Auger recombination assisted hot hole energy gain process were found to contribute to this phenomenon. Besides, this enhancement in Id degradation is more significant under high temperatures or lower supply voltages. Finally, in the last chapter, future work is discussed.
Bhatnagar, Mayank. "Implementing single electron device in standard CMOS process /." 2008. http://proquest.umi.com/pqdweb?did=1597619851&sid=3&Fmt=2&clientId=10361&RQT=309&VName=PQD.
Повний текст джерелаLIN, JIAN-HUI, and 林建輝. "The CMOS device characteristics under high-frequency operations." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/20335808483286326160.
Повний текст джерелаChang, Kai-Chun, and 張凱鈞. "CMOS LNAs Using Integrated Passive Device Technology and Design of SPDT CMOS Switch Circuit." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/22114588493060895606.
Повний текст джерела國立交通大學
電信工程研究所
104
This thesis is mainly classified into two major parts: First, starting from Chapter 2, we discuss the measured results of MOSFET, especially the performance of noise figure and optimal noise impedance. From measured results, the MOSFET devices possess low noise but fail to perform low noise in the circuits. Thus, it is important to find the main reason of noise figure degradation in the circuits. In Chapter 3, we consider all situations through simulations. Then, we find that the main cause is the input matching inductance. Due to the mismatch and non-ideal effect, they will contribute the most noise in the circuit. As a result, we substitute inductances using integrated passive process for the input match inductors. This design can improve the noise figure of a low noise amplifier (LNA). Using single-band, dual-band and wide-band LNAs, the MOS LNAs with/without IPD are compared by CMOS 0.18 m process. Second, Single-pole Double Throw (SPDT) switches are discussed. A SPDT needs to take into considerations insertion loss (IL), isolation and power handling. A switch in front of a power amplifier must handle large power. Therefore, body floating method and increasing the bias voltage are employed. The asymmetric SPDT switches are designed using CMOS process.
Jamil, Mustafa. "Germanium and epitaxial Ge:C devices for CMOS extension and beyond." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-08-3783.
Повний текст джерелаtext
Mangan, Alain Marc. "Millimetre-wave device characterization for nano-CMOS IC design." 2005. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=370235&T=F.
Повний текст джерелаChen, kuan-hao, and 陳冠豪. "High Frequency Deep-Submicron CMOS device and circuit modeling." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/02579999569987998973.
Повний текст джерела長庚大學
電機工程研究所
88
As the gate lengths of silicon MOSFET’s become smaller and smaller, The conventional device model is not accurate in the GHz range. Because BSIM3v3 has been widely accepted as a standard CMOS model for low and medium frequency applications, we must find a method to solve this problem. Recent research has proposed a high frequency device model by adding a complicated substrate resistance network and modifying the BSIM3v3 source code. So we study the sensitivities of S-parameter to each model parameter at 1GHz and some guide lines are given for parameter extraction. A parameter extraction technique utilizing S-parameter data at the GHz range is finally proposed for a SPICE BSIM3V3 for RF MOSFET. Besides, chip size increases and signal wavelengths approach interconnect wire lengths. Therefore, signal delay due to interconnect become a major concern for high-performance integrated circuits. That is because the capacitance and resistance of wires increase rapidly as chip size grows and the minimum feature size is reduced. The purpose of this project is to establish RF CMOS ring oscillators delay model and to study the sensitivity of delay time to device parameters. The dimensions of the multi-finger type MOSFET is W/L=200μm /0.25μm~W/L=200μm/0.5μm, but we use single finger type NMOS (W/L=5μm/0.35μm) and PMOS (W/L=10μm/0.35μm)devices in ring oscillator. The extracted substrate resistance in high frequency device model for multi-finger type devices cannot be directly applied to the single finger type device in ring oscillators. First, we will establish NMOS (W/L=5μm/0.35μm) model and PMOS (W/L=10μm/0.35μm) BSIM3V3 model. Second, the substrate resistances are extracted by measuring S-parameter of the multi-finger type MOSFET. The substrate resistances for the single finger type device are subsequently calculated according to a proposed method as described in Chapter4.In general, RF modification of BSIM3V3 model significantly improves the accuracy of the high-frequency performance prediction. Furthermore, For high frequency operation, According to the simulation of ring oscillator performance based on RF MOS model, with further consideration of delay time model’s interconnection effect, the accuracy of delay time prediction is much better improved.
Su, Jia-Chern, and 蘇嘉晨. "Modeling of Partially Depleted SOI and Bulk CMOS Device." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/66447000338097748373.
Повний текст джерела國立臺灣大學
電機工程學研究所
87
In this thesis, analytical models for partially-depleted SOI and Bulk CMOS devices are described. In Chapter 2, solving Poisson's equation, the boundary model between PD and FD SOI NMOS device, including uniform doped and nonuniform doped are obtained. In Chapter 3, the threshold voltage model considering short channel effect and drain-source voltage effect of bulk dynamic threshold voltage MOS (B-DTMOS) device is obtained first, then, we derived the drain current model in strong inversion region that consider channel length modulation, effective mobility and pre-pinchoff velocity saturation effect. At the end of Chapter 3, the DC and transient behaviors of B-DTMOS inverter and proposed B-DTMOS inverter are simulated and analyzed.
Tuan, Fu-Yuan, and 段復元. "Discussion on the Leakage Current of Advanced CMOS device." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/36512855547683253188.
Повний текст джерела國立臺北科技大學
製造科技研究所
90
In the coming silicon-nano-device generation, the critical gate oxide thickness is getting much thinner than any process generation else before. We can obviously suppose that the gate leakage current would increase exponentially with decreasing gate oxide thickness. In this thesis, a new model “GCIP (Gate Current Induced Punch-through) model “ is proposed and verified by using our experiment results. We pay much attention to the off-state leakage current of the CMOS device especially the current induced around the Source/Drain extension region. This model describes that a high SDE leakage current causes a large amount E-H(electron-hole) pairs. And at the meanwhile, these E-H pair will enlarge the lateral p-n depletion width. This depletion width modulation effect will make the device become much easier to punch-through. This new GCIP model can also be used to verify the MSJZ Model, which proposed by our lab one year ago.
Kranthi, Nagothu Karmel. "ESD Reliability Physics and Reliability Aware Design of Advanced High Voltage CMOS & Beyond CMOS Devices." Thesis, 2021. https://etd.iisc.ac.in/handle/2005/5474.
Повний текст джерелаYueh-Ping, Yu, and 于岳平. "A Novel CMOS Image Sensing Device with High Dynamic Range." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/01352162170585616572.
Повний текст джерела國立清華大學
電子工程研究所
92
A high dynamic range pixel has been developed for an active-pixel CMOS image sensor, by using a standard 0.25-µm CMOS logic process. The operation method is the same with conventional 3T pixel cell, and applying a control pulse voltage to photo-gate. The experimental results demonstrate that extended dynamic range is obtained when we delay the pulse voltage to apply to photo-gate, and sensing device design also affects dynamic range. So, the high dynamic range can be approached by optimizing pixel design and photo-gate pulse timing. The imaging sensitivity can be improved through optimizing the PG to PD area ratio and the bias pulse high level. The experimental results demonstrate the pixel can achieve both high sensitivity at low illumination and extended dynamic range for high illumination.
Wu, Yang-Zheng, and 吳洋政. "A Differential Capacitive Sensing Circuit for CMOS-MEMS pressure device." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/g66e9x.
Повний текст джерела國立臺北科技大學
機電整合研究所
100
In this thesis, a new type of capacitor sensor composed of pressure and CMOS circuitry is proposed. The capacitor variation can be measured directly by means of the sensing circuit, which is composed of an impedance amplifier or a switched-capacitor amplifier. The goal of this sensor is to detect various blood vessel pressures. It also provides an effective way in applications of bio-sensors. Furthermore, an array-typed MEMS-Pressure sensor can be to detect blood vessel pressures in various pressure ranges, and it is desired to become a wearable or implantable device. The sensing capacitor range of the proposed sensor is about 1~200 fF. By using readout circuits and comparing the I/O waveforms (in sine wave), we can calculate the capacitor variation of MEMS-Pressure sensor. We converted the Pressure-Sensor output capacitance into a voltage by a convert in this study. The sensing signals are then amplified and readout with instrumentation amplifier (IA) circuit. The proposed system is implemented in TSMC 0.35 μm 2P4M technology. The chip area is roughly 2.500*2.482 with power supply of 3.0V. The input signal is 1 MHz sine waves. The proposed structure has a capacitance measuring range from 1 femto-farad to hundreds of femto-farad. This study successfully presents a smart sensor which can detect a very small capacitance variation of MEMS-Pressure sensor.
Chang, Chun-Yuan, and 張峻源. "RF CMOS Device Modeling and Broadband Active Inductor Circuit Design." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/43478743279765619045.
Повний текст джерела逢甲大學
電機工程學系
89
In the thesis, we present RF CMOS active and passive device modeling and broadband active inductor integrated circuit design. The geometry aspect influence of a spiral inductor on inductance and Q-factor was studied. The methodologies to improve Q-factor were also investigated. RF CMOS integrated circuits were designed using extracted device modeling. In addition, we developed a novel cascode cross-couple negative resistance circuit and applied it to active inductor. The Q-factor of the broadband active inductor can easily attain 10000 by tuning bias voltage of negative resistance circuit. The inductance values of the active inductor can be tuned by scaling transistor size. At 2.5-V supply voltage, the active inductor exhibited excellent performance. The active inductor can be applied to the next generation IC process. Finally, we complete a simple, high Q-factor, high-performance, tunable active filter using the active inductor.
Lee, Jeng-Hung, and 李政宏. "CMOS Radio Frequency Device Model and High Frequency Power Performance." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/79489309304787717217.
Повний текст джерела國立中正大學
電機工程所
95
A research of CMOS BSIM4 DC and RF model parameters and power MOS transistor is investigated in this thesis. In the first part, a set of DC test devices which is fabricated by using TSMC 0.35 μm CMOS technology is designed for the BSIM4 CMOS DC model parameters extraction. It employs eight designs in the test set for measurement that all of the devices are implemented based on the design rule of TSMC 0.35 μm CMOS technology to obtain the reasonable BSIM4 DC model parameters. By the aid of extraction software ICCAP-2006A, the DC model parameters of 0.35 μm CMOS technology were extracted. A single-finger and multi-finger high-frequency devices are used to extract the RF model parameters in the second part. The DC model parameters in the first part will be also included to derive the RF model parameters. Some of calibration kits for de-embedded are used to verify the measured S-parameters and small-signal characteristic. Following the two steps, the BSIM4 RF model parameters will be obtained. The last part is a design of CMOS power cell. There are four devices with different sizes being built up of which are measured by a load-pull system for the output power, efficiency , power gain and the optimal impedance for load and source terminals.
Lin, Geng-Cing, and 林耕慶. "Device Threshold Voltage Measurement Circuit of Nano-scale CMOS SRAM." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60550065200696051283.
Повний текст джерела國立交通大學
電子研究所
100
Variation issue is one of the key design factors for robust current VLSI systems, and this kind of issue will affect the device threshold voltage (VTH) value. However, the VTH value is still associated with the device performance, stability and reliability, then when we talk about the variation issue that the VTH is the important indicator to reflect this phenomenon. So we want to create a measurement structure that can measure the device threshold voltage, then we can collect the voltage data to realize how the variation issue will affect this testing chip. We present an all-digital bit transistor characterization scheme for CMOS 6T SRAM array. The scheme employs an on-chip operational amplifier feedback loop to measure the individual threshold voltage (VTH) of 6T SRAM bit cell transistors (holding PMOS, pull-down NMOS, and access NMOS) in SRAM cell array environment. The measured voltage is converted to frequency with dual VCO and counter based digital read-out to facilitate data extraction, processing, and statistical analysis. A 512Kb test chip is implemented in 55nm 1P10M Standard Performance (SP) CMOS technology. Monte Carlo simulations indicate that the accuracy of the VTH measurement scheme is about 2-7mV at TT corner across temperature range from 85oC to -45oC, and post-layout simulations show the resolution of the digital read-out scheme is < 0.2mV per bit.
Hung-YuChiu and 邱宏裕. "Studies of Novel Processing Technologies for Nano CMOS Device Applications." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/79175923032847322963.
Повний текст джерела國立成功大學
微電子工程研究所碩博士班
101
This dissertation presents various skills; including a new STI (shallow trench isolation) etch method, small grain size with low temperature polygen process, post-nitridation annealing (PNA) and the carbon co-implant to promote nano CMOS device performances. First, we use automatically top corner rounding (ATCR) STI etch to improve CMOS narrow width device performances. Compared to the conventional methods, the ATCR could increase 8% of the driving current (Idsat) together in a unit process step, thus getting easy process control and cost down benefits. Additionally, the ATCR has a wider process window. Besides, the technique does not degrade the gate oxide integrity, and junction leakage current. Next, we reduce the grain size of poly Si gate by lowering deposition temperature to achieve low sub-threshold leakage and gate leakage. This is due to the smaller grain size can offer a smoother interface to an ultra-thin gate oxide than a big one. Besides, the driving currents are also respectively increased ~9% and ~7% for n- and p- MOSFETs, as the temperatures are lowered from 715oC to 705oC. The most importance is that the small grain size does not degrade the gate oxide integrity and device junction leakage current. Additionally, used a high temperature post-nitridation annealing (PNA) to improve nano devices with pulsed radio frequency decoupled plasma nitrided ultra-thin (〈 50Å) gate dielectric. Results indicate that for a n-type MOSFET, as the PNA temperature rising from 1000oC to 1050oC, the saturation current and gate leakage are increased and reduced 7.9% and 3.81%, respectively. For a p-type MOSFET, the improvement is more significant i.e., 16.7% and 4.31% in saturation current increase and gate leakage reduction, respectively. The significant improvements are attributed to the higher PNA temperature caused Si/SiON interface improvement and increase of EOT. In final, a new molecular carbon co-implant technique was developed. The introduction of carbon ions induces the tensile strain to enhance the mobility. We optimized the dose and energy ranges for both P and C implants along with some anneal parameters to produce low sheet resistance (Rs) and high tensile strain. Besides, Rs measurement, SIMS, XTEM and HRXRD techniques were employed to characterize the doped layer. The optimized implants effectively improved 55nm n-MOSFET performances with Idsat 4.7% gain and significantly reduced transient enhanced diffusion (TED) due to the formation of SiC complex to sink Si interstitials.