Дисертації з теми "CMOS Device and Integration"

Semiconductor manufacturing is the workhorse for a wide range of industries. It lies at the heart of consumer electronics, telecommunication equipment and medical devices. Most semiconductor electronics are made from Silicon, and are fabricated using CMOS technology. The versatility of semiconductor electronics stems from the ever-reducing cost of integrating more computing and memory functions on chip. The small cost for adding extra functions has been maintained in the past 50 years through transistor scaling. Transistor scaling focuses on shrinking the size of transistors integrated on chip. This reduction in transistor size, while keeping the overall cost of the chip fixed allowed us to reduce the cost per function with scaling, and is what is celebrated as Moore’s law. Scaling has been working gracefully up to the last decade, where the exponential rise in manufacturing cost and diminishing gains of scaling on device performance reduce its economic benefit. To revive the cost reduction trend, different techniques were proposed such as augmenting CMOS manufacturing with new materials (Beyond-CMOS), 3D integration, and integrating more non-transistor elements on-chip (More than Moore). In this work, we focus on the efficient implementation of several circuit functions using an allotropy of carbon known as graphene. Graphene, a single layer of carbon atoms arranged in a hexagonal lattice, has unique electronic properties that has been taken the solid-state electronics community by a storm since its first experimental conception in 2004. Despite its promising electronic properties, namely the very high charge-carrier mobility and reduced scattering by impurities, graphene circuits has been held back by a plethora of nonidealities and technological roadblocks that hamper its use in traditional transistor-based circuits. In this work, we attempt to leverage the unique physical properties of graphene to implement non von-Neumann neuromorphic computing architectures, low-loss diodes and evaluate the behavior of diffusive-transport graphene couplers. We focus on the the design, fabrication and characterization of graphene devices in the presence of the current performance-limiting technological nonidealities in heterogeneous graphene-CMOS systems. We present the design, fabrication and characterization of all-graphene resistive data converters devices and diodes, discussing their performance and application as building elements of all-graphene brain-inspired computing architectures. We evaluate the performance of graphene couplers operating in the diffusive transport regime, which serve as a method to analyze the cross-coupling between adjacent graphene interconnects. We also discuss the current technological limitations hampering the performance of graphene devices, and the roles of different processing non-idealities on the characteristics of graphene devices.

Heteroepitaxial SiGe(C) layers have attracted immense attention as a material for performance boost in state of the art electronic devices during recent years. Alloying silicon with germanium and carbon add exclusive opportunities for strain and bandgap engineering. This work presents details of epitaxial growth using chemical vapor deposition (CVD), material characterization and integration of SiGeC layers in MOS devices. Non-selective and selective epitaxial growth of Si1-x-yGexCy (0≤x≤0.30, 0≤y≤0.02) layers have been performed and optimized aimed for various metal oxide semiconductor field effect transistor (MOSFET) applications. A comprehensive experimental study was performed to investigate the growth of SiGeC layers. The incorporation of C into the SiGe matrix was shown to be strongly sensitive to the growth parameters. As a consequence, a much smaller epitaxial process window compared to SiGe epitaxy was obtained. Incorporation of high boron concentrations (up to 1×1021 atoms/cm3) in SiGe layers aimed for recessed and/or elevated source/drain (S/D) junctions in pMOSFETs was also studied. HCl was used as Si etchant in the CVD reactor to create the recesses which was followed (in a single run) by selective epitaxy of B-doped SiGe. The issue of pattern dependency behavior of selective epitaxial growth was studied in detail. It was shown that a complete removal of pattern dependency in selective SiGe growth using reduced pressure CVD is not likely. However, it was shown that the pattern dependency can be predicted since it is highly dependent on the local Si coverage of the substrate. The pattern dependency was most sensitive for Si coverage in the range 1-10%. In this range drastic changes in growth rate and composition was observed. The pattern dependency was explained by gas depletion inside the low velocity boundary layer. Ni silicide is commonly used to reduce access resistance in S/D and gate areas of MOSFET devices. Therefore, the effect of carbon and germanium on the formation of NiSiGe(C) was studied. An improved thermal stability of Ni silicide was obtained when C is present in the SiGe layer. Integration of SiGe(C) layers in various MOSFET devices was performed. In order to perform a relevant device research the dimensions of the investigated devices have to be in-line with the current technology nodes. A robust spacer gate technology was developed which enabled stable processing of transistors with gate lengths down to 45 nm. SiGe(C) channels in ultra thin body (UTB) silicon on insulator (SOI) MOSFETs, with excellent performance down to 100 nm gate length was demonstrated. The integration of C in the channel of a MOSFET is interesting for future generations of ultra scaled devices where issues such as short channel effects (SCE), temperature budget, dopant diffusion and mobility will be extremely critical. A clear performance enhancement was obtained for both SiGe and SiGeC channels, which point out the potential of SiGe or SiGeC materials for UTB SOI devices. Biaxially strained-Si (sSi) on SiGe virtual substrates (VS) as mobility boosters in nMOSFETs with gate length down to 80 nm was demonstrated. This concept was thoroughly investigated in terms of performance and leakage of the devices. In-situ doping of the relaxed SiGe was shown to be superior over implantation to suppress the junction leakage. A high channel doping could effectively suppress the source to drain leakage.

QC 20100715

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 169-165).
Monolithic integration of III-V compound semiconductors and Si complementary metal-oxide- semiconductor (CMOS) enables the creation of advanced circuits with new functionalities. In order to merge the two technologies, compatible substrate platforms and processing approaches must be developed. The Silicon on Lattice Engineered Silicon (SOLES) substrate allows monolithic integration. It is a Si substrate with embedded III-V template layer, which supports epitaxial IIIV device growth, consistent with present II-V technology. The structure is capped with a silicon-on-insulator (SOI) layer, which enables processing of CMOS devices. The processes required for fabricating and utilizing SOLES wafers which have Ge or InP as the III-V template layers are explored. Allowable thermal budgets are important to consider because the substrate must withstand the thermal budget of all subsequent device processing steps. The maximum processing temperature of Ge SOLES is found to be limited by its melting point. However, Ge diffuses through the buried Si0 2 and must be contained. Solutions include 1) limiting device processing thermal budgets, 2) improving buried silicon dioxide quality and 3) incorporating a silicon nitride diffusion barrier. InP SOLES substrates are created using wafer bonding and layer transfer of silicon, SOI and InP-on-Si wafers, established using a two-step growth method. Two different InP SOLES structures are demonstrated and their allowable thermal budgets are investigated. The thermal budgets appear to be limited by low quality silicon dioxide used for wafer bonding. For ultimate integration, parallel metallization of the III-V and CMOS devices is sought. A method of making ohmic contact to III-V materials through Si encapsulation layers, using Si CMOS technology, is established. The metallurgies and electrical characteristics of nickel silicide structures on Si/III-V films are investigated and the NiSi/Si/III-V structure is found to be optimal. This structure is composed of a standard NiSi/Si interface and novel Si/III-V interface. Specific contact resistivity of the double hetero-interface stack can be tuned by controlling Si/IIIV band alignments at the epitaxial growth interface. P-type Si/GaAs interfaces and n-type Si/InGaAs interfaces create ohmic contacts with the lowest specific contact resistivity and present viable structures for integration. A Si-encapsulated GaAs/AlGaAs laser with NiSi front-side contact is demonstrated and confirms the feasibility of these contact structures.
by Nan Yang Pacella.
Ph.D.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 1999.
Includes bibliographical references (p. 90-91).
GaAs-on-silicon epitaxy techniques as well as wafer bonding GaAs to Si, have been developed to overcome lattice mismatch in order to integrate optoelectronic and Si devices. However, the thermal expansion differences between these materials continues to be a limitation in using either of these approaches. After recognizing that Si devices, such as MOSFETs, are intrinsically thin and relatively strain tolerant, while optoelectronic devices, such as LEDs and lasers, are thick and very strain sensitive, this research was based on developing a better approach which involved bonding thin Si layers to thick GaAs substrates with various dielectric layers as the interface, to produce silicon-on-gallium arsenide (SonG) wafers. Such wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. With the successful development of SonG techniques for monolithic integration, it will be possible to use full-wafer and batch processing techniques for the production of sophisticated economically viable optoelectronic integrated circuits.
by Joanna M. London.
S.M.

Recentment, l'escalat de la tecnologia complementaria metall-òxid-semiconductor (CMOS) està arribant a límits fonamentals, principalment degut a les fuites de corrent no nul·les que el transistor presenta. És per això que s’està investigant una nova branca que va més enllà dels límits de la llei de Moore la qual s’anomena “Més que Moore” i està atraient l’interès per nous dispositius de processat de la informació i memòries, noves tecnologies per integració heterogènia de múltiples funcions, i nous paradigmes d'arquitectures de sistemes. Una d'aquestes tecnologies prometedores per processat de la informació és la tecnologia de relés micro- i nano electromecànica, perquè presenta fuites de corrent pràcticament nul·les i una commutació entre dos estats molt abrupta. Aquesta tesi proposa explorar les possibilitats d'aprofitar les capes disponibles de la tecnologia CMOS comercial AMS 0.35 µm per implementar relés micro i nano electromecànics. En concret, s’exploren dos conceptes diferents: un són relés actuats en el pla i definits usant solament la capa d’interconnexió anomenada via, i l’altre són relés actuats torsionalment i formats amb metalls i vies (sovint anomenat com compost) a la vegada que suportat per vies. Ambdós conceptes es basen en la capa de tungstè VIA3, la qual inclou característiques claus tals com gran duresa, alt punt de fusió, poc estrès, i gran resistència a l’àcid fluorhídric (HF), ja que les estructures mecàniques s'alliberen mitjançant un procés post-CMOS sense màscares basat en una solució d'HF. Gràcies a les característiques excepcionals de la plataforma de VIA3, també s’han fabricat ressonadors MEMS basats en l'esmenada plataforma, el que ha permès contribuir al disseny i la caracterització d'un oscil·lador de doble freqüència que consisteix en ressonadors torsionals de tungstè i en un amplificador de transimpedància ultra-compacte, de baix consum i amb un alt guany. Finalment i paral·lel al principal fil de la tesi, també s’han desenvolupat capacitats commutables en col·laboració amb l’empresa SilTerra Malaysia Sdn. Bhd. Aquests dispositius es caracteritzen per estar totalment integrats en el procés d'una tecnologia comercial CMOS de 180 nm de baix cost (usant la plataforma SilTerra MEMS-on-CMOS).
Recently, several new emerging devices are starting to be explored because the traditional down-scaling approach of the complementary metal-oxide-semiconductor (CMOS) technology (often called “More Moore”) is reaching fundamental limits; mainly due to non-zero transistor off-state leakage. This brand-new domain that goes beyond the boundaries of Moore’s law is commonly named ``More than Moore'' and is driving interest in new devices for information processing and memory, new technologies for heterogeneous integration of multiple functions, and new paradigms for system architecture. One of these new promising technologies for logic and information processing is the micro- and nanoelectromechanical (M/NEM) relay technology, because of its immeasurably low off-state leakage current and super-steep switching behavior. This dissertation proposes to explore the possibilities of leveraging the available layers of the commercial CMOS technology AMS 0.35 µm to implement M/NEM relays. Specifically, two different approaches are explored: in-plane actuated relays defined using solely the via layer, and torsional actuated relays formed with metal and via layers (usually named composite) while supported by vias. Both approaches are supported by the tungsten VIA3 layer, which includes key features such as high hardness, high melting point, low stress and resistance to hydrofluoric (HF) acid, since the mechanical structures are released in a maskless post-CMOS process based on a wet HF enchant. Based on the key structural features that the developed relays showed, MEMS resonators based on the VIA3 platform were also fabricated. In this dissertation, we also present a particular contribution involving the design and characterization of a dual-frequency oscillator that consist of such reliable torsional tungsten resonators and a high gain, low power and ultra-compact transimpedance amplifier (TIA). Finally and parallel to the main thread of this dissertation, RF MEMS switched capacitors are developed as a result of the collaboration with the semiconductor manufacturing enterprise SilTerra Malaysia Sdn. Bhd. These devices have the particularity of being fully integrated into the process flow of a low cost, commercial 180 nm CMOS technology (using the SilTerra MEMS-on-CMOS process platform).

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 97-104).
The electronic-photonic integrated circuit (EPIC) has emerged as a leading technology to surpass the interconnect bottlenecks that threaten to limit the progress of Moore's Law in microprocessors. Compared to conventional metal interconnects, photonic interconnects have the potential to increase bandwidth density while simultaneously reducing power consumption. However, photonic devices are orders of magnitude larger than electronic devices and therefore consume valuable substrate real estate. The ideal solution, in order to take advantage of optical interconnects without decreasing transistor counts, is to monolithically implement dense threedimensional integration of electronics and photonics. This involves moving the photonic devices off the substrate, and into the metal interconnect stack. Moving photonic devices into the interconnect stack imposes two fabrication limitations. First, the available thermal budget allowed for photonic device processing is limited to 450 °C. Second, the metal interconnects are embedded within amorphous dielectrics and therefore there is no crystalline seed to initiate epitaxial growth. This thesis addresses two major barriers for integration of photonics in the back end: (1) how to fabricate high quality Ge for active regions of optoelectronic devices while adhering to back-end processing constraints, and (2) how to couple optical power to these devices. First, an approach was developed to fabricate the active region of Ge-based optoelectronic devices. A new technique, known as two-dimensional geometrically confined lateral growth (2D GCLG), has demonstrated single crystalline Ge on an amorphous substrate. This thesis presents the first application of the 2D GCLG technique to fill a lithographically defined Si0 2 trench with large grain Ge, while adhering to back-end processing constraints. A modified design is then proposed to increases the yield of 2D GCLG structures. This trench filling technique is an integral step towards fabricating Ge-based optoelectronic devices that are capable of being integrated into the back-end of a microprocessor. Once it was established that high quality Ge trenches could be fabricated in the back-end, optical coupling to devices was addressed. For dense three-dimensional integration of photonic devices, vertical coupling between photonic planes is necessary. Therefore, this thesis begins with the design and simulation of vertical couplers. These couplers utilize evanescent coupling between two overlapping inversely tapered waveguides, which ensure efficient coupling due to optical impedance matching. These couplers are designed to exhibit coupling efficiencies in excess of 98.4%, equivalent to a 0.07 dB coupling loss. The technique of evanescent coupling between overlapping inverse tapers is then applied to electro-absorption modulators (EAMs). A design for low-loss evanescent coupling from a waveguide to a Ge EAM is modeled and optimized. The design implements lateral evanescent coupling from overlapping inverse taper structures. Simulation results show that the coupling efficiency into and out of the modulator can be as high as 99%, equivalent to a 0.04 dB coupling loss.
by Brian Pearson.
S.M.

Moore's law has defined the semiconductor industry for the past 50 years. Devices continue to become smaller and increasingly integrated into the world around us. Beginning with personal computers, devices have become integrated into watches, phones, cars, clothing and tablets among other things. These devices have expanded in their functionality as well as their ability to communicate with each other through the internet. Further, devices have increasingly been required to have diverse of functionality. This combination of smaller devices coupled with diversification of device functionality has become known as more than Moore. In this thesis, more than Moore applications of graphene are explored in-depth. Graphene was discovered experimentally in 2004 and since then has fueled tremendous research into its various potential applications. Graphene is a desirable candidate for many applications because of its impressive electronic and mechanical properties. It is stronger than steel, the thinnest known material, and has high electrical conductivity and mobility. In this thesis, the potentials of graphene are examined for pressure sensors, humidity sensors and transistors. Through the course of this work, high sensitivity graphene pressure sensors are developed. These sensors are orders of magnitude more sensitive than competing technologies such as silicon nanowires and carbon nanotubes. Further, these devices are small and can be scaled aggressively. Research into these pressure sensors is then expanded to an exploration of graphene's gas sensing properties -- culminating in a comprehensive investigation of graphene-based humidity sensors. These sensors have rapid response and recovery times over a wide humidity range. Further, these devices can be integrated into CMOS processes back end of the line. In addition to CMOS Integration of these devices, a wafer scale fabrication process flow is established. Both humidity sensors and graphene-based transistors are successfully fabricated on wafer scale in a CMOS compatible process. This is an important step toward both industrialization of graphene as well as heterogeneous integration of graphene devices with diverse functionality. Furthermore, fabrication of graphene transistors on wafer scale provides a framework for the development of statistical analysis software tailored to graphene devices. In summary, graphene-based pressure sensors, humidity sensors, and transistors are developed for potential more than Moore applications. Further, a wafer scale fabrication process flow is established which can incorporate graphene devices into CMOS compatible process flows back end of the line.

QC 20160610

The foundation of vacuum nanoelectronics was laid as early as in 1961 when Kenneth Shoulders proposed the development of vertical field-emission micro-triodes. After years of conspicuous stagnancy in the field much interest has reemerged for the vacuum nanoelectronics in recent years. Electron field emission under high electric field from conventional and exotic nanoemitters, which have now been made possible with the use of modern day technology, has been the driving force behind this renewal of interest in vacuum nanoelectronics. In the research reported in this thesis self-assembled silicon nanostructures were studied as a potential source of field emission for vacuum nanoelectronic device applications. Whiskerlike protruding silicon nanostructures were grown on untreated n- and p-type silicon surfaces using electron-beam annealing under high vacuum. The electrical transport characteristics of the silicon nanostructures were investigated using conductive atomic force microscopy (C-AFM). Higher electrical conductivities for the nanostructured surface compared to that for the surrounding planar silicon substrate region were observed. Non-ideal diode behaviour with high ideality factors were reported for the individual nanostructure-AFM tip Schottky nanocontacts. This demonstration, indicative of the presence of a significant field emission component in the analysed current transport phenomena was also detailed. Field emission from these nanostructures was demonstrated qualitatively in a lift-mode interleave C-AFM study. A technique to fabricate integrated field emission diodes using silicon nanostructures in a CMOS process technology was developed. The process incorporated the nanostructure growth phase at the closing steps in the process flow. Turn-on voltages as low as ~ 0.6 V were reported for these devices, which make them good candidates for incorporation into standard CMOS circuit applications. Reproducible I V characteristics exhibited by these fabricated devices were further studied and field emission parameters were extracted. A new consistent and reliable method to extract field emission parameters such as effective barrier height, field conversion factor, and total emitting area at the onset of the field emission regime was developed and is reported herein. The developed parameter extraction method used a unified electron emission approach in the transition region of the device operation. The existence of an electron-supply limited current saturation region at very high electric field was also confirmed. Both the C-AFM and the device characterization studies were modelled and simulated using the finite element method in COMSOL Multiphysics. The experimental results – the field developed at various operating environments – are explained in relation to these finite element analyses. Field enhancements at the atomically sharp nanostructure apexes as suggested in the experimental studies were confirmed. The nanostructure tip radius effect and sensitivity to small nanostructure height variation were investigated and mathematical relations for the nanostructure regime of our interest were established. A technique to optimize the cathode-opening area was also demonstrated. Suggestions related to further research on field emission from silicon nanostructures, optimization of the field emission device fabrication process, and fabrication of field emission triodes are elaborated in the final chapter of this thesis. The experimental, modelling, and simulation works of this thesis indicate that silicon field emission devices could be integrated into the existing CMOS process technology. This integration would offer goods from both the worlds of vacuum and solid-sate nanoelectronics – fast ballistic electron transport, temperature insensitivity, radiation hardness, high packing density, mature technological backing, and economies of scale among other features.

Dans les prochaines années, en raison des besoins toujours plus grands des applications d'apprentissage machine dans le domaine de l'intelligence artificielle, une augmentation soutenue de la capacité de calcul est nécessaire pour faire face à un véritable "déluge de données". Pour relever ce défi, les architectures de calcul immergé en mémoire (IMC) à haute performance nécessitent le développement de nouvelles technologies adaptées à la fois au calcul local et au stockage. Dans ce contexte, ce travail de thèse présente de nouvelles matrices mémoire 3D 1T1R qui sont dérivées des transistors à nanofeuillés empilés. Cette nouvelle technologie est associée au calcul hyperdimensionnel (HDC), un paradigme inspiré du cerveau qui est à la fois résistant à l’erreur et facilement parallélisable. Tout d’abord, nous montrons que l’IMC peut largement bénéficier des architectures 3D basées sur les mémoires non volatiles (NVM) pour augmenter la densité et les performances de calcul. Toutefois, les difficultés de fabrication et les résistances et capacités parasites inhérentes aux structures 3D limitent parfois considérablement les performances de ces architectures pour l’IMC. Grâce à la technologie 3D 1T1R proposée dans ce travail, qui combine des nanofeuillés empilés comportant des grilles indépendantes avec une RRAM insérée dans le drain des transistors, nous montrons qu’il est possible de s’affranchir, en partie, de ces problèmes. Nous présentons, fabriquons et caractérisons électriquement plusieurs modules technologiques essentiels à la fabrication de structures 1T1R 3D. Nous démontrons également la fonctionnalité de cellules mémoires 1T1R pour lesquelles le point RRAM est intégré dans le drain de différents types de sélecteurs avec une électrode inférieure faite de Si dopé. Enfin, nous proposons d’implémenter l’algorithme HDC en mémoire pour tirer profit de notre structure 3D 1T1R. Différentes implémentations sont explorées et leurs performances sont évaluées à l’aide de simulations SPICE. Nous montrons également à l'aide de simulations logicielles que la classification de langages et la reconnaissance de gestes, basées sur le calcul hyperdimensionnel, peuvent être implémentées à l’aide de notre structure 3D 1T1R de façon réaliste
In the years to come, due to the insatiable need for data-intensive machine learning applications, a drastic expansion of computing power is required to confront a veritable “data deluge”. To meet this challenge, high-performance In-Memory-Computing (IMC) architectures require the development of novel storage devices that are also suited for local computations. In this context, this thesis work presents a novel 3D 1T1R memory array derived from vertically stacked-nanosheet technology, which is used for Hyperdimensional Computing (HDC), an error-resilient and highly parallel brain-inspired computing paradigm. Firstly, the IMC paradigm can greatly benefit from novel 3D non-volatile memory (NVM) architectures which increase the density and the computing performances. However, the fabrication challenges and parasitics can greatly limit the potential benefits of these architectures. With the 3D 1T1R technology, made by coupling new disruptive gate-independent stacked-nanosheets with drain-based RRAM cells, we show that some of these issues can be overcome, thus leading to high-density 3D NVM arrays. We demonstrate various technological modules necessary for the fabrication of 3D 1T1R structures. Devices are fabricated and electrically characterized for both storage and computing applications. In particular, functional MEOL drain-based RRAM cells are demonstrated with a doped-Si bottom electrode for various types of selector technologies. Finally, we propose a full-IMC architecture of HDC to take advantage of the 3D 1T1R structure. Different hardware implementations are proposed and compared with SPICE simulations. We also show with software-based simulations that language and gesture recognition can be realistically performed with our 3D 1T1R implementation

L'activation à basse température est prometteuse pour l'intégration 3D séquentielle où lebudget thermique du transistor supérieur est limité (<650 ºC) pour ne pas dégrader letransistor inférieur, mais aussi dans le cas d'une intégration planaire afin d'atteindre des EOTultra fines et de contrôler le travail de sortie de la grille sans recourir à une intégration de type" gate-last ". Dans ce travail, l'activation par recroissance en phase solide (SPER) a étéétudiée afin de réduire le budget thermique de l'activation des dopants.L'activation à basse température présente plusieurs inconvénients. Les travauxprécédents montrent que les fuites de jonctions sont plus importantes dans ces dispositifs.Ensuite, des fortes désactivations de dopants ont été observées. Troisièmement, la faiblediffusion des dopants rend difficile la connexion des jonctions source et drain avec le canal.Dans ce travail, il est montré que dans un transistor FDSOI, l'augmentation des fuites dejonctions et la désactivation du Bore peuvent être évités grâce à la présence de l'oxyde enterré.De plus les conditions d'implantation ont été optimisées et les transistors activés à650 ºC atteignent les performances des transistors de référence.

La gestion, la manipulation et le stockage de données sont aujourd’hui de réels challenges. Pour supporter cette réalité, le besoin de technologies mémoires plus efficaces, moins énergivores, moins coûteuses à fabriquer et plus denses que les technologies actuelles s’intensifie. Parmi les technologies mémoires émergentes se trouve la technologie mémoire résistive, dans laquelle l’information est stockée sous forme de résistance électrique au sein d’une couche d’oxyde entre deux électrodes conductrices. Le plus gros frein à l’émergence de tels dispositifs mémoires résistives en matrices passives à deux terminaux est l’existence d’importants courants de fuites (ou sneak paths) venant perturber l’adressage individuel de chaque point de la matrice. Les dispositifs complementary resistive switching (CRS), consistant en deux dispositifs OxRRAM agencés dos à dos, constituent une solution performante à ces courants de fuites et sont facilement intégrables dans le back-end-of-line (BEOL) de la technologie CMOS. Cette thèse a permis d’apporter la preuve de concept de la fabrication et de l’intégration de dispositifs CRS de façon 3D monolithique dans le BEOL du CMOS
In our digital era, management, manipulation and data storage are real challenges. To support this reality the need for more efficient, less energy and money consuming memory technologies is drastically increasing. Among those emerging memory technologies we find the oxide resistive memory technology (OxRRAM), where the information is stored as the electrical resistance of a switching oxide in sandwich between two metallic electrodes. Resistive memories are really interested if used inside passive memory matrix. However the main drawback of this architecture remains related to sneak path currents occurring when addressing any point in the passive matrix. To face this problem complementary resistive switching devices (CRS), consisting in two OxRRAM back to back, have been proposed as efficient and costless BEOL CMOS compatible solution. This thesis brought the proof of concept of fabrication and 3D monolithic integration of CRS devices in CMOS BEOL

Spin torque oscillators (STOs) are microwave oscillators with an attractive blend of features, including a more-than-octave tunability, GHz operating frequencies, nanoscale size, nanosecond switching speed and full compatibility with CMOS technology. Over the past decade, STOs' physical phenomena have been explored to a greater extent, their performance has been further improved, and STOs have already shown great potential for a wide range of applications, from microwave sources and detectors to neuromorphic computing. This thesis is devoted to promoting the STO technology towards its applications, by means of implementing the STO's electrical model, dedicated CMOS integrated circuits (ICs), and STO-CMOS IC integration. An electrical model, which can capture magnetic tunnel junction (MTJ) STO's characteristics, while enabling system- and circuit-level designs and performance evaluations, is of great importance for the development of MTJ STO-based applications. A comprehensive and compact analytical model, which is based on macrospin approximations and can fulfill the aforementioned requirements, is proposed. This model is fully implemented in Verilog-A, and can be used for efficient simulations of various MTJ STOs. Moreover, an accurate phase noise generation approach, which ensures a reliable model, is proposed and successfully used in the Verilog-A model implementation. The model is experimentally validated by three different MTJ STOs under different bias conditions. CMOS circuits, which can enhance the limited output power of MTJ STOs to levels that are required in different applications, are proposed, implemented and tested. A novel balun-low noise amplifier (LNA), which can offer sufficient gain, bandwidth and linearity for MTJ STO-based magnetic field sensing applications, is proposed. Additionally, a wideband amplifier, which can be connected to an MTJ STO to form a highly-tunable microwave oscillator in a phase-locked loop (PLL), is also proposed. The measurement results demonstrate that the proposed circuits can be used to develop MTJ STO-based magnetic field sensing and microwave source applications. The investigation of possible STO-CMOS IC integration approaches demonstrates that the wire-bonding-based integration is the most suitable approach. Therefore, a giant magnetoresistance (GMR) STO is integrated with its dedicated CMOS IC, which provides the necessary functions, using the wire-bonding-based approach. The RF characterization of the integrated GMR STO-CMOS IC system under different magnetic fields and DC currents shows that such an integration can eliminate wave reflections. These findings open the possibility of using GMR STOs in magnetic field sensing and microwave source applications.

QC 20151112

The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.
Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Also available online at the MIT Theses Online homepage
Includes bibliographical references (p. 199-211).
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Silicon ULSI compatible, high index contrast waveguides and devices provide high density integration for optical networking and on-chip optical interconnects. Four such waveguide systems were fabricated and analyzed: crystalline silicon-on-insulator (SOI) strip, polycrystalline silicon (polySi) strip, silicon nitride strip and SPARROW waveguides. The loss of 15 dB/cm measured through an SOI waveguide was the smallest ever measured for a silicon strip waveguide and is due to improved side-wall roughness. The TM mode of a single mode polySi strip waveguide with a 1:2.5 aspect ratio exhibited, surprisingly, smaller loss than the TE mode. Further, analysis shows that high index contrast waveguides are more sensitive to polarization dependent loss in the presence of surface roughness. Single mode bends and splits in both silicon and silicon nitride were studied. 0.01 dB/turn loss has been measured for 2 micron radius silicon bends. Polarization dependent loss was also observed; the bending loss of a TM mode was, as expected, much larger than that of a TE mode. The splitting losses for two-degree Y-split was 0.15 dB/split. A 1x16 multi-mode interferometer splitter occupied an area of 480 sq-microns and exhibited loss of 3 dB. ULSI compatible waveguide structures integrated with micro-resonators have been studied. Qs of 10000 and efficiencies close to 100% were achieved in high index contrast ring resonators and Qs of 100 million were achieved in microsphere resonators. A thermal and mechanical tuning mechanism was demonstrated for micro-ring resonators.
(cont.) In addition, >95% coupling efficiency between SPARROW waveguides and microspheres was achieved, the first microspheres to be coupled to integrated optics waveguides. 1x4 wavelength division multiplexing devices have been, for the first time, demonstrated in high index contrast silicon and silicon nitride strip waveguide systems. These systems have a component density of 1-million devices/sq-cm. Higher order filters made from multiple rings exhibited flat top responses and the expected steeper roll-off resonance response. Integrated modulators and switches based on waveguides and rings were also studied. Finally, the integration of the components in systems applications was analyzed. A study of the effect of polarization and loss in silicon microphotonics waveguide systems is presented.
by Desmond Rodney Lim Chin Siong.
Ph.D.

La reducción de los dispositivos MEMS hasta la nano escala (NEMS) ha permitido el acceso a nuevos dominios de la física y promete revolucionar las aplicaciones de sensado. Sin embargo esta miniaturización ha sido conseguida a costa de procesos de fabicración complicados y no reproducibles. Es por ello que esta tesis trata de obtener dichos dispositivos NEMS a partir de una tecnologia CMOS comercial (ST 65nm). Con este objetivo un estudio en detalle de la tecnología ST 65nm es llevado a cabo para posteriormente definir en ella estructuras NEMS en sus diferentes capas (en polysilicio con un grosor y ancho de 60 nm x 100 nm y en metal 1, cobre , con unas dimensiones de 90nm x 100nm). Un nuevo post proceso de liberación es presentado que nos permite liberar las estructuras, demostrando así su correcta fabricación. Sin embargo, fruto de esta miniaturización las señales eléctricas usadas para sensar su movimiento se reducen también. Como alternativa a un sensado capacitivo estudiamos la viabilidad de adaptar a nuestro proceso de fabricación CMOS-MEMS a un método de transducción basado en un transistor cuyo puerta resuena, su movimiento modula las cargas del canal y dicho desplazamiento puede ser leído en la corriente del puerta del transistor. Mediante dicho método de transducción la respuesta en frecuencia de un resonador de polysilicio a 24 MHz fue leída y su funcionamiento como interruptor a bajos voltajes (2.25 V pull-in) fue validado. Además, proponemos el uso de interruptores mecánicos no solo como memorias o en aplicaciones lógicas (gracias a su eficiencia energética) sino como el elemento base para la implementación de un oscilador en anillo, completamente mecánico. Con este oscilador ampliamos el rango de aplicación de los interruptores N/MEMS a nuevos campos como el sensado de masa pero con el valor añadido de tener una señal digital. Para implementar esta nueva configuración presentamos un modelo y desarrollamos interruptores mecánicos en diferentes tecnologías CMOS intentando siempre reducir sus dimensiones. Con estos interruptores mecánicos CMOS hemos conseguido voltajes de operación bajos (5V), respuestas abruptas (4.3 mV/decada) y una buena relación ION/IOFF (1.104).
The reduction of MEMS devices dimensions to the nano scale (NEMS) has allowed them to access a host of new physics and promise to revolutionize sensing applications. However this miniaturization has been obtained at an expense of dedicated, difficult and non reproducible fabrication processes. This thesis deals with the miniaturization of MEMS structures following a CMOS-MEMS approach. In order to it a small pitch CMOS technology (ST 65nm) is studied in depth, NEMS structures are defined using its available layers (width= 60 nm, thickness= 100nm in polysilicon and width= 90nm, thickness= 180nm in metal 1 based on copper) and a post-CMOS releasing process is developed in order to release them. Successful integration of NEMS devices is demostrated with the added value of a robust, reproducible fabrication and an easy integration with additional circuitry. However this aggressive scaling has a main drawback, small output signals. As an alternative to capacitive read-out, the implementation of a resonant gate transduction, based on the idea of modulate the charge of a transistor by the movement of a mechanical structure, is studied and implemented. The frequency response of a polysilicon resonator implemented in AMS 0.35um CMOS technology (24 MHz) has been successfully characterized and its operation as a low voltage switch (2.25 V pull-in) is demonstrated. In addition, we propose the use of mechanical switches not only as memory or logic devices (due to its energy efficiency), but also as the building blocks of a ring oscillator configuration composed exclusively by mechanical switches. This new approach extends their use to other application as mass sensing but with the added value of a digital output signal. In order to implement this new configuration a model to simulate its behavior is developed and mechanical switches are built using different CMOS technologies, trying always to reduce their dimensions. Low operating voltages (5 V, MIM approach), abrupt response (4.3 mV/decade, ST Metal 1) and good ION/IOFF ratio (1.104, MIM approach) are obtained.

The vehicle is a challenging environment in which to interact with computing devices. Therefore, the vehicle environment offers computing a unique challenge, in that a method for safe and secure mobile device integration is required in order to provide a suitable communications channel for interaction with devices without distracting from the primary driving task. Moreover, a security architecture is required for mobile device integration in the vehicle paradigm. This architecture must be scalable, efficient and most importantly built on trusted and mathematically sound algorithms. This thesis examines the relevant literature in the field of automotive telematics, including the notion of mobile device integration. Moreover, issues in the vehicle paradigm are also discussed which include driver distraction, and the legal ramifications of in-vehicle mobile phone use. From a system design view point this thesis will then provide an overview of the design requirements for telematics products, and outline possible security protocols which could be implemented on constrained mobile devices. The ultimate aim of this thesis is to develop a security architecture for mobile device integration for automotive telematics based on the simple network management protocol (SNMPv3) user security model.

Low resolution pharyngeal manometry is an invasive diagnostic method that has recently been used as a biofeedback device for swallowing rehabilitation. The University of Canterbury Rose Centre uses pharyngeal manometry to diagnose and rehabilitate subjects who suffer from pharyngeal mis-sequencing. Pharyngeal mis-sequencing occurs when pressure is applied simultaneously throughout the pharynx rather than sequentially. Rehabilitation can only be performed in clinic due to the need for specialized equipment and trained staff, and the invasiveness of the test limits the time that can be spent training. As an alternative method to measure the pharyngeal pressure sequence, bioimpedance has been investigated by a previous University of Canterbury Master’s student. A prototype was developed that measured bioimpedance in two locations as a proxy for pharyngeal pressure sequence. The prototype device named GULPS (Guided Utility for Latency in Pharyngeal Swallowing), measured a change in impedance during swallowing. However, the features of this waveform were inconsistent and were not present during every swallow. The frequency of the current that passes through tissue affects its path through the tissue, therefore impacting the measured impedance. To improve the consistency of the impedance measurement, the effect of current injection frequency was investigated. A modular-hardware system was created from the original design to allow testing of different injection frequencies. The hardware was further developed by replacing the method of generating the constant amplitude current injection signal. The improvement to the design resulted in a differently-shaped waveform to that of the previous prototype, including a new feature. This feature is a single peak that occurred in both channels and was reproduced in every swallow. Experimentation showed that the features were not obviously frequency dependent. The separation between the peaks of the two impedance channels was compared with the separation between the two pressure peaks recorded during simultaneous pharyngeal manometry but there was no significant correlation between the two measures of peak-peak separations. Two alternative hardware/signal conditioning changes were trialled: electrical isolation of each channel and a subtraction method, which aims to remove the effect of the changing impedance between the two electrode channels. Electrical isolation of the two channels had no effect on the impedance waveforms. However, the subtraction method produced a different output and requires further investigation as the output was inconsistent. Bluetooth communication was integrated into the GULPS hardware, and a corresponding Android Application (App) was written. The developed App was successful in displaying the impedance measurement output and adds greater user flexibility, allowing the user to interface with the bioimpedance measurement hardware from their tablet or phone. With no measured significant correlation between GULPS and pharyngeal manometry, further research needs to be performed to better relate the features measured by GULPS to those seen during pharyngeal manometry. Until this can be achieved, the GULPS device cannot replace pharyngeal manometry for biofeedback-based rehabilitation of pharyngeal mis-sequencing.

The continuous and aggressive dimensional miniaturization ofthe conventional complementary-metal-oxide semiconductor (CMOS)architecture has been the main impetus for the vast growth ofIC industry over the past decades. As the CMOS downscalingapproaches the fundamental limits, unconventional materials andnovel device architectures are required in order to guaranteethe ultimate scaling in device dimensions and maintain theperformance gain expected from the scaling. This thesisinvestigates both unconventional materials for the gate stackand the channel and a novel notched-gate device architecture,with the emphasis on the challenging issues in processintegration.

High-κ gate dielectrics will become indispensable forCMOS technology beyond the 65-nm technology node in order toachieve a small equivalent oxide thickness (EOT) whilemaintaining a low gate leakage current. HfO₂and Al₂O₃as well as their mixtures are investigated assubstitutes for the traditionally used SiO₂in our MOS transistors. These high-κ filmsare deposited by means of atomic layer deposition (ALD) for anexcellent control of film composition, thickness, uniformityand conformality. Surface treatments prior to ALD are found tohave a crucial influence on the growth of the high-κdielectrics and the performance of the resultant transistors.Alternative gate materials such as TiN and poly-SiGe are alsostudied. The challenging issues encountered in processintegration of the TiN or poly-SiGe with the high-k are furtherelaborated. Transistors with TiN or poly-SiGe/high-k gate stackare successfully fabricated and characterized. Furthermore,proof-of-concept strained-SiGe surface-channel pMOSFETs withALD high-κ dielectrics are demonstrated. The pMOSFETs witha strained SiGe channel exhibit a higher hole mobility than theuniversal hole mobility in Si. A new procedure for extractionof carrier mobility in the presence of a high density ofinterface states found in MOSFETs with high-κ dielectricsis developed.

A notched-gate architecture aiming at reducing the parasiticcapacitance of a MOSFET is studied. The notched gate is usuallyreferred to as a local thickness increase of the gatedielectric at the feet of the gate above the source/drainextensions. Two-dimensional simulations are carried out toinvestigate the influence of the notched gate on the static anddynamic characteristics of MOSFETs. MOSFETs with optimizednotch profile exhibit a substantial enhancement in the dynamiccharacteristics with a negligible effect on the staticcharacteristics. Notched-gate MOSFETs are also experimentallyimplemented with the integration of a high-κ gatedielectric and a poly-SiGe/TiN bi-layer gate electrode.

Key words:CMOS technology, MOSFET, high-κ, gatedielectric, ALD, surface pre-treatment, metal gate, poly-SiGe,strained SiGe, surface-channel, buried-channel, notchedgate.

Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2004.
Includes bibliographical references (leaves 131-136). Also available in electronic version. Access restricted to campus users.

La presente tesis ha sido realizada principalmente en el Centro Nacional de Microelectrónica de Barcelona (CNM-IMB) del CSIC, y en parte también en el Instituto de Nanotecnología de Lyon (Francia) del CNRS. El Dr Francesc Pérez-Murano ha codirigido la tesis en el CNM, y el Pr Georges Brémond en el INL. Este trabajo se enmarca en el proyecto europeo NaPa ('Emerging Nanopatterning Methods') cuyo objetivo es desarrollar técnicas emergentes, industrializables a medio plazo, de litografía a nivel nanométrico, y sus posibles aplicaciones. Así pues, los objetivos principales de la tesis han sido los desarrollos simultáneos (i) de sistemas nanoelectromecánicos (NEMS) integrados en CMOS, y (ii) de procesos de fabricación basados en una técnica avanzada de nanolitografía llamada 'nanostencil lithography' para poder fabricar tales sistemas monolíticos.
Como primer paso, dos tipos de resonadores nano/micromecánicos ('cantilevers' y 'quad-beams') se han modelado analíticamente para poder estudiar su respuesta frecuencial mecánica. Con el objetivo de excitarlos y detectarlos eléctricamente, se ha optado por una técnica capacitiva. Para poder prever el comportamiento eléctrico de la estructura mecánica se ha implementado un modelo mixto electromecánico. Luego se han estudiado las ventajas y la viabilidad de una integración monolítica con circuitería CMOS. En efecto, los NEMS/CMOS son sistemas que combinan extraordinarias propiedades de sensado, proporcionadas por la parte móvil mecánica, con la posibilidad de detectar la señal de salida en condiciones mucho más favorables: las capacidades parásitas son reducidas drásticamente al tratar dicha señal a través de una circuitería CMOS 'on-chip'. Por este motivo, se ha diseñado especialmente un circuito CMOS de lectura y de bajo consumo. Funciona como amplificador de transimpedancia para convertir la corriente creada por la resonancia mecánica en un voltaje de salida suficientemente alto. A partir de simulaciones, se ha analizado exhaustivamente (i) el comportamiento intrínseco de este circuito y (ii) cuando está acoplado al resonador mecánico.
Sin embargo, la fabricación de tales nanodispositivos integrados en CMOS constituía un reto ya que la integración a nivel de oblea entera de NEMS sobre CMOS mediante procesos no excesivamente costosos no había sido demostrada aún al inicio de esta tesis. Debido a esto, se puso en marcha una colaboración con el EPFL (École Polytechnique Fédérale de Lausanne, Suiza) para desarrollar la litografía 'nanostencil' con el objetivo de integrar a escala de oblea entera estructuras mesoscópicas (micro y nano) sobre circuitos CMOS pre-fabricados. Después de identificar los principales problemas iniciales, se ha podido desarrollar con éxito una tecnología de post-proceso que permite integrar NEMS en CMOS mediante una única etapa de litografía nanostencil. En paralelo, otro post-proceso basado en una etapa de litografía por haz de electrones ('e-beam lithography') se ha puesto a punto de manera que se pueden fabricar nuevos prototipos de nanodispositivos sobre CMOS en cortos plazos de tiempo.
La caracterización eléctrica de estos NEMS/CMOS se ha llevado a cabo tanto en aire como en vacío y se ha demostrado el correcto funcionamiento del dispositivo NEMS/CMOS fabricado. Han sido analizados los niveles de señal obtenidos experimentalmente y las características principales de los espectros de resonancia.
Finalmente, estos NEMS/CMOS han sido implementados como sensores de masa. Actualmente, esta aplicación de los NEMS es una de las más exploradas ya que los resonadores nano/micromecánicos ofrecen grandes ventajas en términos de sensibilidad e integración de sistemas comparados con las tradicionales microbalanzas de cuarzo. En este contexto, se han llevado a cabo cuatro experimentos diferentes: (i) en colaboración con un grupo de investigación en química física se ha estudiado mediante un resonador nano/micromecánico, utilizado como nano/microbalanza, la evaporación de gotas de volúmenes extremadamente reducidos, del orden del femtolitro (10-15), para profundizar en los conocimientos necesarios para el desarrollo de dispositivos de nano/microfluídica; (ii) una arquitectura nueva de resonador, basada en una palanca doble ('doble cantilever'), se ha diseñado y testeado. Este dispositivo novedoso permite hacer medidas de masa en condiciones ambientales con una auto-referencia proporcionando la incertidumbre de la medida; (iii) se han hecho pruebas de deposición en alto vacío de capas ultra-finas de oro (de espesor equivalente inferior a una mono-capa) sobre resonadores. De esa manera, se ha demostrado la gran sensibilidad en masa distribuida de estos dispositivos, en particular al comparar su respuesta con la de una microbalanza de cuarzo a la que superan por entre dos y tres ordenes de magnitud a nivel de sensibilidad; (iv) basándose en los resultados del experimento previo de deposición de oro, se está diseñando, y sigue en curso, un sistema 'quasi-dinámico' de litografía nanostencil junto con el EPFL. Este sistema consiste en efectuar deposiciones sucesivas de distintos materiales a través de un nanostencil desplazado entre cada deposición: de esa manera se obtienen multi-depósitos estructurados y ultra-puros. De manera muy novedosa, el sensor de masa NEMS/CMOS se utiliza aquí como sensor de alineamiento entre la membrana nanostencil y el substrato a litografiar.
This thesis has been a co-direction between Dr. F. Pérez-Murano from CNM-CSIC, Barcelona (Spain) and Pr. G. Brémond from INSA Lyon/INL-CNRS (France). This work involves two main aspects: one has to see with the modeling, the design and the operation of a nanomechanical device integrated on CMOS, and the other on nanofabrication techniques.
First, the mechanical and electrical behavior of electrostatically actuated nano/microresonators (cantilevers, bridges and quad-beams) embedded in a capacitive detection scheme have been analyzed. In such a scheme, the main issue comes from parasitic stray capacitances that can drastically degrade the performance of the transduction. Additionally, output parasitic capacitances arising from the measurement instrumentation can further reduce the available signal levels. In this sense, the advantages and the feasibility of a monolithic integration with CMOS circuitry have been studied. Indeed NEMS/CMOS are very promising systems which combine outstanding sensing attributes, thanks to the mobile mechanical part, with the possibility to electrically detect the output signal in enhanced conditions. Regarding the electrical response, such integration provides two major advantages: (i) reducing all the parasitic loads at the resonator output, and (ii) amplifying and conditioning 'on-chip' the resonance signal. Hence, a specific low-power CMOS readout circuit, whose function is to read out the capacitive current generated by a resonating nano/micromechanical device, has been designed. It is basically a transimpedance amplifier whose architecture is based on a second generation current conveyor. Its topology and the corresponding layout have been described and the circuit behavior (intrinsic and coupled to the NEMS) has been fully simulated. According to simulation results, the detection of the resonance of nano/microresonators is greatly enhanced through the CMOS integration.
Then, NEMS/CMOS devices have been fabricated combining a standard CMOS technology (CNM one) with emerging nanopatterning techniques, in particular with nanostencil lithography (nSL), of which the resolution and the conditions of applications have been optimized. Our works demonstrate the potential of nSL as a parallel, straightforward and CMOS compatible patterning technique to define at full wafer scale nanodevices on CMOS. These results represent the first time that an emerging nanolithography technique has been used to pattern multiple N-MEMS devices on a whole CMOS wafer in a parallel, potentially low-cost approach. The same strategy could be extended to other examples of nanodevices, such as single electron transistors on CMOS, for which there is at present no affordable technological process that fulfill the requirements of high resolution processing at wafer scale and CMOS compatibility.
After their fabrication, fully integrated nanomechanical resonators (cantilevers and quad-beams) have been extensively characterized electrically. Their mechanical resonance has been successfully sensed by the CMOS circuitry. Cantilevers and quad-beams have exhibited quality factors in vacuum up to 9500 and 7000 respectively. The resonance frequency could be tuned by varying the driving voltage and interesting hysteretic non-linear behaviors have been observed either in air or in vacuum
Finally, these resonators have been implemented as ultra-sensitive mass sensors in four different applications: in this way the extreme versatility and the high performance of such sensors has been demonstrated. Indeed, such ultra-sensitive nanosensors open up new possibilities of exploring new physical or chemical phenomena previously unattainable with any other tools. In the first experiment, wetting mechanisms of sessile droplets have been explored at very small scales (volumes in the femtoliter range) implementing the resonators as nano/microbalances. Such phenomena could not have been analyzed with traditional quartz microbalances whose mass resolution is more limited. In the second experiment, a new architecture of resonator based on a double nano/microcantilever has been designed and tested: this new device allows making reliable measurements under ambient conditions by providing a direct estimation of the measurement uncertainty.
The fact that NEMS-based mass sensors provide an unprecedented mass sensitivity and a very high spatial resolution inherent to their small size makes of them interesting devices for industrial applications as well. With regard to this matter, another experiment has consisted in monitoring in-situ the deposition of ultra-thin gold layers both with NEMS/CMOS and quartz-crystal microbalances. When measuring in real time the mass of these uniform deposits of thicknesses inferior to sub-monolayer, silicon nano/microresonators have exhibited a mass sensitivity better than QCM by between two and three orders of magnitude. This is very promising with regard to the possibility of replacing QCM in the semiconductor industry as a tool to monitor the deposition of thin layers. These outstanding mass sensing attributes have led us to apply such sensors as positioning sensors according to an innovative concept. In fact, CNM and EPFL are presently developing a 'quasi-dynamic' stencil lithography system. This system consists in performing successive depositions of several materials through a nanostencil shadow mask which is displaced in-between each deposition: in this way high-purity and structured multi-deposits can be obtained. In this context, NEMS/CMOS mass sensors are used as positioning sensors for the in-situ alignment between the movable nanostencil and the substrate to be patterned.

Aquesta tesi presenta les investigacions realitzades cap a la integració de transistors verticals d’un sol electró (SET) en tecnologia metall-òxid-semiconductor complementari (CMOS). Dues de les principals motivacions de la indústria de semiconductors són la miniaturització de dispositius i la reducció del consum d’energia. En els nodes més avançats, les arquitectures tridimensionals han guanyat una importància significativa per tal d’augmentar la densitat d’integració, sent els dispositius disposats verticalment els candidats més adequats per a les generacions més recents. D’altra banda, els dispositius d’un sol electró són exemples de circuits de baix consum energètic. En aquest treball, s’aborda la fabricació d’un SET basat en un nanofil vertical i la seva co-integració amb tecnologia CMOS. El punt de partida és un nanopilar de Si/SiO2/Si amb nanopunts de Si a la capa intermèdia de SiO2, que actuen com a punt quàntic del sistema. Els elèctrodes de porta i drenador es situen al voltant de l’òxid intermedi i en contacte amb el cap del pilar, respectivament. La integritat del pilar i el contacte dels seus elèctrodes es validen mitjançant caracterització estructural. Tot i que la integració SET en producció a gran escala és encara un repte, la seva combinació amb tecnologia CMOS es beneficia de la maduresa tecnològica del processament de circuits integrats, superant els inconvenients intrínsecs del SET com el soroll de fons o la inestabilitat del dispositiu. Aquest treball també presenta la fabricació monolítica i compatible amb CMOS d’un transistor planar convencional co-integrat amb un SET vertical. La fabricació del procés s’adapta per complir les restriccions imposades pel SET prefabricat, com ara un pressupost tèrmic reduït, capes de protecció i dopatge modificat. Es demostra la fabricació monolítica de SET vertical i transistors planars convencionals; es preserva la integritat del pilar i els transistors fabricats funcionen en condicions òptimes per a la compatibilitat SET.
Esta tesis presenta las investigaciones realizadas hacia la integración de transistores verticales de un solo electrón (SET) en tecnología metal-óxido-semiconductor complementario (CMOS). Dos de las principales motivaciones de la industria de semiconductores son la miniaturización de dispositivos y la reducción de consumo de energía. En los nodos más avanzados, las arquitecturas tridimensionales han ganado una importancia significativa para aumentar la densidad de integración, siendo los dispositivos dispuestos verticalmente los candidatos más adecuados para las generaciones más recientes. Por otro lado, los dispositivos de un solo electrón son ejemplos de circuitos de bajo consumo energético. En este trabajo, se aborda la fabricación de un SET basado en un nanohilo vertical y su co-integración con tecnología CMOS. El punto de partida es un nanopilar de Si/SiO/Si con nanopuntos de Si en la capa intermedia de SiO2, que actúan como puntos cuánticos del sistema. Los electrodos de puerta y drenador se sitúan alrededor del óxido intermedio y en contacto con la parte superior del pilar, respectivamente. La integridad del pilar y el contacto de sus electrodos se validan mediante caracterización estructural. Aunque la integración SET en producción a gran escala es todavía un reto, su combinación con tecnología CMOS se beneficia de la madurez tecnológica del procesamiento de circuitos integrados, superando al mismo tiempo los inconvenientes intrínsecos del SET como ruido de fondo o la inestabilidad del dispositivo. Este trabajo también presenta la fabricación monolítica y compatible con CMOS de un transistor planar convencional co-integrado con un SET vertical. La fabricación del proceso se adapta para cumplir las restricciones impuestas por el SET prefabricado, como presupuesto térmico reducido, capas de protección o dopaje modificado. Se demuestra la fabricación monolítica de SET vertical y transistores planares convencionales; se preserva la integridad del pilar y los transistores fabricados funcionan en condiciones óptimas para la compatibilidad SET.
This thesis presents the investigations performed towards the integration of Single Electron Transistor (SET) into Complementary Metal-Oxide-Semiconductor (CMOS) technologies. Two of the main drives in semiconductor industry are device miniaturization and power consumption reduction. In the most advanced nodes, three-dimensional architectures have gained significant importance to increase the integration density, being vertically arranged devices the most suitable candidates for the ultimate generations. On the other hand, single electron devices are examples of ultra-low power consumption circuits. In this work, the fabrication of a SET based on a vertical nanowire and its co-integration with CMOS technology is addressed. The starting point is a Si/SiO2/Si nanopillar with Si nanodots in the intermediate SiO2 layer, acting as quantum dot of the system. The subsequent gate and drain electrodes are placed all-around the embedded oxide and on contact with the pillar cap, respectively. Pillar integrity and its electrodes contacting are validated by structural characterization. While SET integration in large-scale production is still challenging, its combination with CMOS technology benefits from the technological maturity of integrated circuits processing, overtaking SET intrinsic drawbacks as background noise or device instability. This work also reports the CMOS compatible and monolithic fabrication of a conventional planar transistor co-integrated with a vertical SET. The process fabrication is adapted to fulfil the restrictions imposed by the pre-fabricated SET, such as reduced thermal budget, protective layers and modified doping. The monolithic fabrication of vertical SET and planar transistors is demonstrated; the pillar integrity is preserved, and the fabricated transistors operate at optimum conditions for SET compatibility.
Universitat Autònoma de Barcelona. Programa de Doctorat en Enginyeria Electrònica i de Telecomunicació

Ces dix dernières années, les technologies de stockage non-volatile Flash ont joué un rôle majeur dans le développement des appareils électroniques mobiles et multimedia (MP3, Smartphone, clés USB, ordinateurs ultraportables…). Afin d’améliorer davantage les performances, augmenter les capacités et diminuer les coûts de fabrication, de nouvelles solutions technologiques sont aujourd’hui étudiées pour pouvoir compléter ou remplacer la technologie Flash. Citées par l’ITRS, les mémoires résistives polymères présentent des caractéristiques très prometteuses : procédés de fabrication à faible coût et possibilité d’intégration haute densité au dessus des niveaux d’interconnexions CMOS ou sur substrat souple. Ce travail de thèse a été consacré au développement et à l'étude des mémoires résistifs organiques à base de polymère de poly-méthyl-méthacrylate (PMMA) et de molécules de fullerènes (C60). Trois axes de recherche ont été menés en parallèle: le développement et la caractérisation physico-chimique de matériaux composites, l’intégration du matériau organique dans des structures de test spécifiques et la caractérisation détaillée du fonctionnement électrique des dispositifs et des performances mémoires
Over the past decade, non-volatile Flash storage technologies have played a major role in the development of mobile electronics and multimedia (MP3, Smartphone, USB, ultraportable computers ...). To further enhance performances, increase the capacity and reduce manufacturing costs, new technological solutions are now studied to provide complementary solutions or replace Flash technology. Cited by ITRS, the polymer resistive memories present very promising characteristics: low cost processing and ability for integration at high densities above CMOS interconnections or on flexible substrate. This PhD specifically focused on the development and study of composite material made of Poly-Methyl-Methacrylate (PMMA) polymer resist doped with C60 fullerene molecules. Studies were carried out on three different axes in parallel: Composite materials development & characterization, integration of the organic material in specific test structure and advanced devices and finally detailed electrical characterization of memory cells and performances analysis

Science and technology is experiencing a period of very rapid change which is euphemistically referred to as the information technology revolution. The main impetus for the latter is born of the ability to fabricate many thousands of devices on a single slice of monolithic crystal, otherwise known as the 'chip'. The ability to do this has meant that the power of the computer touches all facets of society. It is not surprising, therefore, that a great deal of emphasis is placed upon device fabrication. As functional circuits use more and more components, device geometries get progressively smaller, so that the only realistic way of predicting the behaviour of a device is through a computer model, or a device simulation. It is in obtaining improvements in the latter that forms the motivation for this thesis. In the early part of the thesis, the essential groundwork in electronic devices is covered. It serves to introduce both devices and approximate analytic modelling, thus showing the advantages of full numerical simulation. The results obtained serve as qualitative references, giving an idea of the type of solutions to be expected. The calculation of charge integrals is investigated. A fully consistent method contrasts the simpler 'lumping', and results for both formulations are presented. These results have prompted analytic investigations, which, in one dimension, have highlighted serious stability problems in consistent charge integration. In two dimensions, consistent charge integration has also been shown to produce oscillatory results. The origin of these 'wiggles' has been demonstrated as dependent on the mesh topology, showing fully consistent integration to be impractical. This leads to the recommendation of charge 'lumping', which extends to higher dimensions also. An exposition of the 'Multigrid' method is given, with particular emphasis on application to device simulation. All algorithms utilised are described, with detailed definition of problem dependent parameters. An optimal damping factor for damped Jacobi relaxation has been developed in respect of the Pisson equation. The contraction map defined may be extended to allow a fully consistent definition of the map for a general finite element discrete system. 'Multigrid' has been shown to be viable, within the limits of the model presented, for the continuity equations. The final chapter of the thesis serves to unite the material presented. The innovative aspects of the work are highlighted, with particular reference to previously published activity in these areas. This naturally describes the significance of the thesis in device simulation literature.

The objective of this dissertation is to classify the opportunities, advantages, and limits of novel interconnects for post-CMOS logic that can augment or eventually replace the CMOS logic. Post-CMOS devices are envisaged on the idea of using state variables other than the electron charge to store and manipulate information. In the first component of the thesis, a comprehensive analysis of the performance and the energy dissipation of novel logic based on various state variables is conducted, and it is demonstrated that the interconnects will continue to be a major challenge even for post-CMOS logic. The second component of the thesis is focused on the analysis of the interconnection aspects of spin-based logic. This research goal is accomplished through the development of physically-based models of spin-transport parameters for various metallic, semiconducting, and graphene nanoribbon interconnects by incorporating the impact of size effects for narrow cross-sectional dimensions of all-spin logic devices. Due to the generic nature of the models, they can be used in the analysis of spin-based devices to study their functionality and performance more accurately. The compact nature of the models allows them to be easily embedded into the developing CAD tools for spintronic logic. These models then provide the foundation for (i) analyzing the spin injection and transport efficiency in an all-spin logic circuit with various interconnect materials, and (ii) estimating the repeater-insertion requirements in all-spin logic, and (iii) estimating the maximum circuit size for all-spin logic. The research is crucial in pinpointing the implications of the physical limits of novel interconnects at the material, device, circuit, and architecture levels.

We presented here a web-based tool, named TAMTAMS that can accurately calculate the IV characteristics of a transistor based technology and estimate the performance evaluation at system level. We have shown how the modular structure of the tool, makes it possible to estimate an electrical quantity, let’s say A, and evaluate further electrical quantities depending on A in a single run of processing. The tree structure and dependence tree enables a user do analysis from a single nano-scale transistor to a system containing hundreds of thousands of transistors. TAMTAMS Web, as a tool, enables the technologist to observe the effect of changes in process parameters (such as doping Nd)at system level. In other words, the changes in device parameters like Vth, Ion, Ioff etc are reflected in changes in system level performance parameters like Static and Dynamic power consumption. We started the development of the tool from BULK transistor technology by translating the physics based mathematical models as Octave scripts. Moving towards more complex structures like SOI, FinFET, Gate-All-Around, Double/Triple Gate transistors and Post-Silicon technologies like Graphene and Molecular transistors. The technology files (physical parameters)are derived from ITRS roadmap. Transistor models for electrical quantities such as drive current Ion, Off-state current Ioff, Gate leakage current Igate, Threshold voltage Vth etc are integrated inside TAMTAMS. We have shown in our results the tunnelling effect in a transistor i-e how change in Oxide thickness Tox , using parametric analysis, affects gate leakage current Igate . This highlights the intensive nature of the analysis performed with TAMTAMS web. We have shown in our results how static and dynamic power consumption of a Vertex 4 FPGA can be compared for BULK, SOI, DG, GAA and molecular transistor-based technologies. This highlights the extensive nature of the analysis performed with the TAMTAMS Web tool. For interconnection and gate level analysis, NAND and NOR are incorporated inside TAMTAMS as universal gates. Different capacitance models are defined and integrated that acts as bridge between transistors based technologies and system level modules like FPGA, Adders, Multipliers, Memories etc. The tool enables Performance estimation at gate level as well e.g we have shown how reliability models predict the increase in Static/Dynamic power consumption and Delay time for NAND/NOR based circuits. TAMTAMS can be used to analyse different applications under many scenarios. For example, at interconnection level, electromigration models enable the comparison of electromigration effect in copper and Aluminium material based interconnection wires. At system level, different system level modules are written and integrated inside TAMTAMS. For example FPGA module, different types of Adder modules, Multipliers, Content Addressable Memory (CAM), Static RAM (SRAM), Arithmetic and Logic unit (ALU), Finite impulse response filters (FIR) etc. We have shown in the analysis, how a static/dynamic power consumption of an Adder and CAM circuit are affected taking reliability issues into consideration using different technologies. Also in the system level analysis, we have compared performance analysis for Virtex 4 FPGA CLB using current and emerging transistor technologies. Time and space does not allow us to discuss all the technologies and all the integrated modules as it is beyond the scope of this work, but we have analysed few interesting case studies in the analysis part. Regarding the development of the tool TAMTAMS Web, we conclude we have achieved enough and have come a long way considering from where we started, but it is still an on-going work as the technology further evolves. Further we conclude that the tool TAMTAMS Web, as presented in this work, can prove vital for i) technologists in analysis of the process variations ii) for designers to evaluate their circuit design at each of the three levels of abstraction, iii) for transistor model developers to benchmark their proposed models with other industry standard models and iv) for the futurists to know what can be predicted in the years to come regarding transistor based circuit.

Electrospray Ionization (ESI) is a technique that permits the soft ionization of large proteins and biomolecules without fragmenting them, which allows them to be characterized via Mass Spectrometry (MS). It has the potential of permitting the identification of transient intermediate products in biological processes in situ, which would provide great insight to researchers in the growing fields of proteomics and metabolomics. However, this application presents a technical challenge in that most relevant biochemistry occurs in aqueous solutions with high salt content, which makes successful identification of analytes by ESI-MS difficult. This thesis presents the design, fabrication, and characterization of a microfabricated dialysis module that could alleviate this issue by desalting samples inline between sampling and electrospraying interfaces. Its small volume (~10 nL) minimizes sample transit time and, thus, optimizes ESI-MS analysis temporal resolution. A preliminary analytical model of dialysis elucidates the key performance parameters and sets the guidelines for consideration in its design. The device is then microfabricated in a cleanroom environment using techniques that have been well established by the microelectronics industry such as E-beam evaporation and Reactive Ion Etching. The system efficiency is demonstrated experimentally by assessing its salt removal effectiveness as a function of sample residence time. Mass spectrometry analyses of proteins in solutions with high salt content further corroborate its performance.

Gli allotropi bidimensionali (2D) del silicio e del fosforo sono stati i predecessori fra i materiali monoelementali 2D dopo il grafene. I vantaggi scientifici e tecnologici di questi materiali richiedono lo sviluppo di schemi di processo che possano garantire la loro effettiva integrazione in nuovi dispositivi per la nanoelettronica. In questo lavoro di tesi, sono stati investigati alcuni degli ostacoli ancora irrisolti lungo la strada per l’integrazione in dispositivo degli allotropi 2D del fosforo considerando specificatamente il caso delle fasi 2D α-P (corrispondente a un singolo strato di fosforo nero o fosforene) e \ β -P (fosforene-blu). L’integrazione della fase 2D α-P nell’architettura di un dispositivo è stata oggetto di ampie ricerche e si basa su un percorso abbastanza consolidato che ha portato ad applicazioni che spaziano in un’ampia gamma di campi. Uno dei pochi ostacoli rimanenti su questo percorso è la mancanza di un metodo scalabile per produrre 2D α-P su grandi aree e con un accurato controllo dello spessore. In particolare, tale controllo è difficile da raggiungere nell’esfoliazione di cristalli stratificati di fosforo nero (BP). A questo proposito, la spettroscopia micro-Raman è stata usata sia come uno strumento metrologico per determinare lo spessore delle scaglie cristalline esfoliate che come metodo per raggiungere una controllata riduzione del loro spessore sfruttando la tecnica di assottigliamento laser. Tuttavia, i metodi di determinazione dello spessore basati sulla calibrazione delle intensità delle bande Raman sono stati investigati poco nel caso di scaglie cristalline multistrato. In questo lavoro di tesi abbiamo proposto un nuovo approccio basato sulla spettroscopia Raman che ha permesso di discriminare velocemente lo spessore di scaglie cristalline esfoliate di BP tra i 5 nm e i 100 nm. Inoltre, al fine di raggiungere un controllo migliore nel processo di assottigliamento laser, abbiamo anche investigato gli effetti dovuti al substrato sul riscaldamento e ablazione laser in scaglie multistrato di BP. Esperimenti di termometria Raman e calcoli numerici sul problema della diffusione del calore hanno chiarito che effetti ottici, termici e meccanici causati dalla presenza del substrato possono agire differentemente sul riscaldamento e sull’ablazione laser a seconda dello spessore delle scaglie cristalline. Il percorso di integrazione in dispositivo per la fase 2D β -P, invece, è ancora assente a causa delle richieste più stringenti nella sintesi, basata su tecniche epitassiali, e dei problemi di instabilità fuori dall’ambiente di crescita in UHV. Questi ostacoli sono comunemente condivisi con gli altri membri della famiglia degli Xeni 2D e, in questo lavoro, sono stati studiati considerando il caso di β -P cresciuto epitassialmente su substrati di Au(111)/mica. I dettagli della sua struttura atomica e la reattività chimica all’esposizione in-situ ed ex-situ all’ossigeno sono stati analizzati con l’aiuto della microscopia a scansione ad effetto tunnel (STM) e spettroscopia fotoelettronica a raggi X (XPS). I problemi di instabilità in aria sono stati affrontati sviluppando una opportuna strategia di incapsulamento basata sulla crescita in-situ di un film protettivo di Al2O3 che, a sua volta, ha permesso di maneggiare il fosforo epitassiale lungo i primi passi di un processo di integrazione in dispositivo. Da questo punto di vista, sono stati esaminati due nuovi approcci per il trasferimento di un materiale epitassiale da un substrato di crescita verso substrati target. Ambedue questi metodi di trasferimento possono essere adeguatamente generalizzati all’intera classe degli Xeni epitassiali 2D cresciuti su metallo/mica. In particolare, l’universalità di questi approcci è stata impiegata per la fabbricazione di dispositivi FET e MIM sia su membrane di Al2O3/silicene multistrato/Ag(111) che su Al2O3/fosforo epitassiale/Au(111).
Phosphorus and silicon two-dimensional (2D) allotropes have been the forerunners among the post-graphene monoelemental 2D materials. The scientific and technological advantages of these materials require the development of processing methods to guarantee their effective integration in new devices for nanoelectronics. In the present thesis work, some of the unresolved bottlenecks along the device integration path of 2D elemental phosphorus allotropes have been examined considering specifically the case of the α-P (single-layer black phosphorus or phosphorene) and β-P (blue phosphorene) 2D polymorphs. The integration of the 2D α-P phase in devices has been the subject of extensive investigations and nowadays relies on an almost consolidated path that has led to applications spanning a wide range of fields. One of the few remaining obstacles on this path is the lack of a scalable method to produce 2D α-P layers on large areas and with accurate control of the thickness. In particular, such control is difficult to achieve in the exfoliation of layered black phosphorus (BP) crystals. In this respect, micro-Raman spectroscopy has been used both as a metrological tool to determine the thickness of the exfoliated flakes and as method to achieve their controllable thickness reduction employing the laser thinning technique. However, thickness determination methods based on the calibration of the intensity of the Raman bands have been poorly investigated in the case of multilayer BP flakes due to difficulties caused by optical interferences and anisotropy effects. In this thesis work, we have proposed a novel Raman spectroscopy approach that, carefully accounting for these effects, allowed the quick discrimination of the thickness of exfoliated BP flakes between 5 nm and 100 nm. Moreover, in order to achieve a better control of the laser thinning process down to the ultimate 2D limit, we have also investigated the effects of the substrate on the laser heating and ablation of multilayer BP flakes. Raman thermometry experiments and numerical calculations of the heat diffusion problem have elucidated that optical, thermal, and mechanical effects caused by the substrate may act differently on the laser heating and ablation of the flakes depending on their thickness. An effective device integration route for the 2D β-P phase, instead, is still missing due to more stringent requirements in its synthesis, based on epitaxial techniques, and to the instability issue outside the UHV growth environment. These obstacles are commonly shared with other members of the family of 2D epitaxial Xenes and, in this work, have been investigated considering the case of β-P epitaxially grown on Au(111)/mica substrates. The details of its atomic structure and the chemical reactivity to ex-situ and in-situ oxygen exposure have been analyzed with the aid of Scanning Tunneling Microscopy (STM) and X-Ray Photoelectron Spectroscopy (XPS). The air-instability issues have been tackled by developing a suitable encapsulation strategy based on the in-situ growth of an Al2O3 capping layer that, in turn, allowed the handling of epitaxial phosphorus along the preliminary steps of a device integration process. In this respect, two novel approaches for the transfer of the epitaxial membrane from the growth substrate towards target substrates have been surveyed. Both the transfer methods can be suitably generalized to the whole class of 2D epitaxial Xenes grown on metal/mica paving the way for the establishment of methodological standards for their manipulation. In particular, the universality of such approaches has been exploited for the successful fabrication of back-gated FET and MIM devices on Al2O3/multilayer silicene/Ag(111) and Al2O3/epitaxial phosphorus/Au(111) mica-delaminated membranes, respectively. The epitaxial phosphorus MIM devices may open intriguing perspectives in the study of the non-volatile resistive switching in monoelemental epitaxial 2D materials.

The main topic of this thesis is the development of a chemical microsystem based on integration of a silicon-based resonant microsensor and a CMOS ASIC for portable sensing applications. Cantilever and disk-shape microresonators have been used as mass-sensitive sensors. Based on the characteristics of the microresonators, CMOS integrated interface and control electronics have been implemented. The CMOS ASIC utilizes the self-oscillation method, which incorporates the microresonator in an amplifying feedback loop as the frequency determining element. In this manner, the ASIC includes a main feedback loop to sustain oscillation at or close to the fundamental resonance frequency of the microresonator. For stable oscillation, an automatic gain control loop regulates the oscillation amplitude by controlling the gain of the main feedback loop. In addition, an automatic phase control loop has been included to adjust the phase of the main feedback loop to ensure an operating point as close as possible to the resonance frequency, resulting in improved frequency stability. The CMOS chip has been interfaced to cantilever and disk-shape microresonators and short-term frequency stabilities as low as 3.4×10-8 in air have been obtained with a 1 sec gate time. The performance of the implemented microsystem as a chemical sensor has been evaluated experimentally with microresonators coated with chemically sensitive polymer films. With a gas-phase chemical measurement setup constructed in this work, chemical measurements have been performed and different concentrations of VOCs, such as benzene, toluene and m-xylene have been detected with limits of detection of 5.3 ppm, 1.2 ppm and 0.35 ppm, respectively. To improve the long-term stability in monitoring applications with slowly changing analyte signatures, a method to compensate for frequency drift caused by environmental disturbances has been implemented on the CMOS chip. This method uses a controlled stiffness modulation generated by a frequency drift compensation circuit to track the changes in the resonator's Q-factor in response to variations in the environmental conditions. The measured Q-factor is then used to compensate for the frequency drift using an initial calibration step. The feasibility of the proposed method has been verified experimentally by compensating for temperature-induced frequency drift during gas-phase chemical measurements.

The increasing demand for high performance and miniature high frequency electronics has motivated the development of Micro-electro Mechanical Systems (MEMS) resonators, some of which have already become a commercial success for the making of filters, duplexers and oscillators used in radio frequency (RF) front-end systems for portable electronic devices. These MEMS components not only enable size, power and cost reduction with respect to their existing counterparts, but also open exciting opportunities for implementing new functionalities when used in large arrays. Almost all MEMS resonators require interfacing with one or more Complementary Metal Oxide Semiconductor (CMOS) integrated circuit components or modules in processing raw signals from individual MEMS devices. Hence, these devices should be integrated with CMOS circuits in an efficient and robust way in order to facilitate their deployment in large arrays with minimal parasitics, delay and power losses due to signal routing and CMOS-MEMS interconnects. Among the MEMS resonators developed to date, Aluminum Nitride (AlN) MEMS Contour-Mode Resonators (CMRs) offer high electro-mechanical coupling coefficient (𝑘𝑡2) and quality factor (Q), and a center frequency (f0) that can be set lithographically by varying the device in-plane dimensions. Also, AlN MEMS CMRs can be fabricated using state-of-the-art CMOS processes and micromachining techniques. These properties allow the synthesis of multi-frequency band-pass filters (BPFs) on a single chip with a low insertion loss and the capability of direct matching to 50 Ω systems. All these advantages, along with a sufficiently mature fabrication process, make AlN CMRs one of the ideal candidates for pursuing their integration with CMOS technology and implement high performance filters with programming capability. In this work we develop for the first time a three-dimensional (3D) heterogeneously integrated AlN MEMS-CMOS platform that enables the realization of such systems as self- healing filters for RF front-ends and programmable filter arrays for cognitive radios. We collaborated with the A*STAR, Institute of Microelectronics (IME), Singapore in the development of AlN MEMS platform on an 8" silicon (Si) wafer; on the other hand, CMOS chips were fabricated in 65 nm International Business Machines Corporation (IBM) and 28 nm Samsung processes. Solder bumps were placed on CMOS chips by Tag and Label Manufacturers Institute (TLMI) under the supervision of Metal Oxide Semiconductor Implementation Service (MOSIS). We demonstrated 3D integrated chip stacks with primary RF signal routing on MEMS and on CMOS for self-healing filters, and showcased the other system via wire-bonding to off-the-shelf CMOS components on a printed circuit board (PCB) because of the inability to continue to have access to the CMOS wafers and bumping processes over the last two years of the project.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.
Includes bibliographical references (leaves 108-110).
Monolithic OptoPill integration by means of recess mounting is a heterogeneous technique employed to integrate III-V photonic devices on silicon CMOS circuits. The goal is to create an effective fabrication process that enables the volume production of high performance optoelectronic integrated circuits (OEICs). This thesis focuses on the development of post-assembly processes and technologies, in which InGaAs/InP P-i-N photodiodes were integrated as long wavelength photodetectors with an optical clock receiver circuit. Fabrication procedures, challenges experienced, and results accomplished are presented for each process step including the formation of alloyed and non-alloyed ohmic contacts on n-type and p-type InGaAs contact layers, active area definition by dry-etching InGaAs/InP with ECR-enhanced RIE, BCB passivation and planarization, via opening by dry-etching BCB with RIE, and top contact metallization. In conjunction, an InP-based test heterostructure was fabricated into discrete photodiodes. Decoupling the fabrication and benchmarking of III-V photonic device from the Si-CMOS electronic circuit allowed for the independent electrical and optical characterization of the photodetectors. Measurements and analysis of the P-i-N photodiodes will assist the forthcoming analysis of the final OEIC. Preliminary results and discussions of the calibration sample are presented in this thesis.
by Yi-Shu Vivian Lei.
S.M.

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student submitted PDF version of thesis.
Includes bibliographical references (p. 388-407).
As silicon CMOS transistors have scaled, increasing the density and energy efficiency of computation on a single chip, the off-chip communication link to memory has emerged as the major bottleneck within modern processors. Photonic devices promise to break this bottleneck with superior bandwidth-density and energy-efficiency. Initial work by many research groups to adapt photonic device designs to a silicon-based material platform demonstrated suitable independent performance for such links. However, electronic-photonic integration attempts to date have been limited by the high cost and complexity associated with modifying CMOS platforms suitable for modern high-performance computing applications. In this work, we instead utilize existing state-of-the-art electronic CMOS processes to fabricate integrated photonics by: modifying designs to match the existing process; preparing a design-rule compliant layout within industry-standard CAD tools; and locally-removing the handle silicon substrate in the photonic region through post-processing. This effort has resulted in the fabrication of seven test chips from two major foundries in 28, 45, 65 and 90 nm CMOS processes. Of these efforts, a single die fabricated through a widely available 45nm SOI-CMOS mask-share foundry with integrated waveguides with 3.7 dB/cm propagation loss alongside unmodified electronics with less than 5 ps inverter stage delay serves as a proof-of-concept for this approach. Demonstrated photonic devices include high-extinction carrier-injection modulators, 8-channel wavelength division multiplexing filter banks and low-efficiency silicon germanium photodetectors. Simultaneous electronic-photonic functionality is verified by recording a 600 Mb/s eye diagram from a resonant modulator driven by integrated digital circuits. Initial work towards photonic device integration within the peripheral CMOS flow of a memory process that has resulted in polysilicon waveguide propagation losses of 6.4 dB/cm will also be presented.
by Jason S. Orcutt.
Ph.D.

This thesis explores Single-Photon Avalanche Diodes (SPADs), which are solid-state devices for photon timing and counting, and concentrates on SPADs integrated in nano-scale CMOS. The thesis focuses on: the search for new theory regarding Geiger-mode operation; proving the utility of calibrated Technology Computer- Aided Design (TCAD) tools for accurately simulating SPADs for the first time; the investigation of how manufacture influences device operation; and the integration of high performance SPADs into CMOS which rival discrete devices. The accepted theories of SPAD operation are revisited and it is discovered that previously neglected minority carriers have many significant roles such as determining: after-pulsing, Dark Count Rate (DCR), bipolar “SPAD latch-up,” nonequilibrium DCR, and “quenching”. The “quenching” process is revisited and it is concluded that it is the “probability time” of ≈100-200ps, and not the previously thought latching current that is important. SPADs are also found to have transient negative differential resistance. The new theories of SPADs are also supported by steady-state 1D, 2D and 3D TCAD simulations as well as novel transient simulations and videos. It is demonstrated as possible to simulate DCR, Photon Detection Efficiency (PDE), guard ring performance, breakdown voltage, breakdown voltage variation, “quenching,” and transient operation of SPADs with great accuracy. The manufacture of SPADs is studied focusing on the operation and optimisation of guard rings and it is found that ion implantation induced asymmetry from the tilt and rotation/twist is critical. Where symmetric, guard rings fail first along the <100> directions due to enhanced mobility. Process integration rules are outlined for obtaining high performance SPADs in CMOS while maintaining compatibility with transistors. The minimisation of tunnelling with lightly-doped junctions and the reduction of ion implantation induced defects by additional annealing are found essential for achieving low DCR. The thesis demonstrates that it is possible to realise high performance SPADs in CMOS through the innovation of a “Deep SPAD” which achieves record PDE of ≈72% at 560nm with >40% PDE from 410-760nm, combined with 18Hz DCR, <60ps FWHM timing resolution, and <4% after-pulsing which is demonstrated to have potential for significant further improvement. The findings suggest that CMOS SPAD-based micro-systems could outperform existing photon timing and counting solutions in the future.

The emergence of miniaturized electronic sensors for recording neural activity is opening up new opportunities for better health care and understanding brain function. The precise instrumentation for sensing these signals has been developed extensively, but no implantable system available today is capable of providing a high density recording structures that can be scaled to accommodate the large number of electrodes and processing neuroprosthetics need for functional limb replacement. The design of these systems is complicated by micro-volt levels of signal that contain convoluted mixtures of information. This demands highly accurate signal quantization and exhaustive processing that is constrained by the scarce power availability. The resulting difficulty in realizing viable solutions for chronic implants necessitates cutting-edge fabrication technologies and state-of-the-art circuit optimization techniques. This thesis presents the understanding behind optimizing these instrumentation systems in order to maximize the simultaneous sensing capabilities of brain machine interfaces that can be implanted wirelessly into living systems. These analytics enabled this work to outperform state of the art in terms of delivering high precision at 56 dB SINAD with a sub 0.01mm^2 silicon footprint and a 800 nW power budget by employing novel time-domain circuit techniques. This advancement will enable BMIs to be integrated & minimutrized using nanometre CMOS with extensive digital processing capabilities that are capable of decoding neural signals without supervision such that therapy in a fully implanted fashion. Moreover by introducing distributed processing architecture this work is the first to allows scalable fully reconfigurable functionality at the instrumentation interface for complex algorithmic operations while maintaining a power efficiency of 2.7μW per MIPS.

La technologie CMOS à base de Silicium complètement déserté sur isolant (FDSOI) est considérée comme une option privilégiée pour les applications à faible consommation telles que les applications mobiles ou les objets connectés. Elle doit cela à son architecture garantissant un excellent comportement électrostatique des transistors ainsi qu'à l'intégration de canaux contraints améliorant la mobilité des porteurs. Ce travail de thèse explore des solutions innovantes en FDSOI pour nœuds 20nm et en deçà, comprenant l'ingénierie de la contrainte mécanique à travers des études sur les matériaux, les dispositifs, les procédés d'intégration et les dessins des circuits. Des simulations mécaniques, caractérisations physiques (µRaman), et intégrations expérimentales de canaux contraints (sSOI, SiGe) ou de procédés générant de la contrainte (nitrure, fluage de l'oxyde enterré) nous permettent d'apporter des recommandations pour la technologie et le dessin physique des transistors en FDSOI. Dans ce travail de thèse, nous avons étudié le transport dans les dispositifs à canal court, ce qui nous a amené à proposer une méthode originale pour extraire simultanément la mobilité des porteurs et la résistance d'accès. Nous mettons ainsi en évidence la sensibilité de la résistance d'accès à la contrainte que ce soit pour des transistors FDSOI ou nanofils. Nous mettons en évidence et modélisons la relaxation de la contrainte dans le SiGe apparaissant lors de la gravure des motifs et causant des effets géométriques (LLE) dans les technologies FDSOI avancées. Nous proposons des solutions de type dessin ainsi que des solutions technologiques afin d'améliorer la performance des cellules standard digitales et de mémoire vive statique (SRAM). En particulier, nous démontrons l'efficacité d'une isolation duale pour la gestion de la contrainte et l'extension de la capacité de polarisation arrière, qui un atout majeur de la technologie FDSOI. Enfin, la technologie 3D séquentielle rend possible la polarisation arrière en régime dynamique, à travers une co-optimisation dessin/technologie (DTCO)
The Ultra-Thin Body and Buried oxide Fully Depleted Silicon On Insulator (UTBB FDSOI) CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatics in the transistor and the successful integration of strained channel as a carrier mobility booster. This work explores scaling solutions of FDSOI for sub-20nm nodes, including innovative strain engineering, relying on material, device, process integration and circuit design layout studies. Thanks to mechanical simulations, physical characterizations and experimental integration of strained channels (sSOI, SiGe) and local stressors (nitride, oxide creeping, SiGe source/drain) into FDSOI CMOS transistors, we provide guidelines for technology and physical circuit design. In this PhD, we have in-depth studied the carrier transport in short devices, leading us to propose an original method to extract simultaneously the carrier mobility and the access resistance and to clearly evidence and extract the strain sensitivity of the access resistance, not only in FDSOI but also in strained nanowire transistors. Most of all, we evidence and model the patterning-induced SiGe strain relaxation, which is responsible for electrical Local Layout Effects (LLE) in advanced FDSOI transistors. Taking into account these geometrical effects observed at the nano-scale, we propose design and technology solutions to enhance Static Random Access Memory (SRAM) and digital standard cells performance and especially an original dual active isolation integration. Such a solution is not only stress-friendly but can also extend the powerful back-bias capability, which is a key differentiating feature of FDSOI. Eventually the 3D monolithic integration can also leverage planar Fully-Depleted devices by enabling dynamic back-bias owing to a Design/Technology Co-Optimization

This work focuses on device design and process integration of high-performance Ge-based devices for CMOS applications and beyond. Here we addressed several key challenges towards Ge-based devices, such as, poor passivation, underperformance of nMOSFETs, and incompatibility of fragile Ge wafers for mass production. We simultaneously addressed the issues of bulk Ge and passivation for pMOSFETs, by fabricating Si-capped epitaxial Ge:C(C<0.5%) devices. Carbon improves the crystalline quality of the channel, while Si capping prevents GeOx formation, creates a quantum well for holes and thus improves mobility. Temperature-dependent characterization of these devices suggests that Si cap thickness needs to be optimized to ensure highest mobility. We developed a simple approach to grow GeO₂ by rapid thermal oxidation, which provides improved passivation, especially for nMOSFETs. The MOSCAPs with GeO₂ passivation show ~10× lower Dit (~8×10¹¹ cm⁻²eV⁻¹) than that of the HF-last devices. The Ge (111) nMOSFETs with GeO₂ passivation show ~2× enhancement in mobility (~715 cm²V⁻¹s⁻¹ at peak) and ~1.6× enhancement in drive current over control Si (100) devices. For improved n⁺/p junctions, we proposed a simple technique of rapid thermal diffusion from "spin-on-dopants" to avoid implantation damage during junction formation. These junctions show a high ION/IOFF ratio (~10⁵⁻⁶) and an ideality factor of ~1.03, indicating a low defect density, whereas, ion-implanted junctions show higher Ioff (by ~1-2 orders) and a larger ideality factor (~1.45). Diffusion-doped and GeO₂-passivated Ge(100) nMOSFETs show a high ION/IOFF ratio (~10⁴⁻⁵) , a low SS (111 mV/decade), and a high [mu]eff (679 cm²V⁻¹s⁻¹ at peak). Moreover, diffusion-doped Ge (111) nMOSFETs show even higher [mu]eff (970 cm²V⁻¹s⁻¹ at peak) that surpasses the universal Si mobility at low Eeff. For Beyond CMOS devices, we investigated Mn-doped Ge:C-on-Si (100), a novel Si-compatible ferromagnetic semiconductor. The investigation suggests that the magnetic properties of these films depend strongly on crystalline structure and Mn concentration. On a different approach, we developed LaOx/SiOx barrier for Spin-diodes that reduces contact resistance by ~10⁴, compared to Al₂O₃ controls and hence is more conducive for spin injection. These ferromagnetic materials and devices can potentially be useful for novel spintronic devices.
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碩士
國立臺北科技大學
機電整合研究所
96
Nowadays, communication system development toward MMIC and SOC become more and more massive. Due to the reason, using the standard CMOS process for RF communication system design has been regarded as a valuable research. Since CMOS process develops rapidly and its feature sizes reduces gradually, it make the operation speed faster、the power consumption reduced and the operation frequency increased. The increased operation frequency is the most important for RF communication system designs. Therefore, CMOS elements can be applied to RF communication systems widely. The study demonstrates that the Class AB power amplifier based on RF CMOS integrates with MEMS Devices. Because the system is to extend the battery life of sensing points, the power amplifier is necessary to have the characteristic of high efficiency. The power amplifier fabrication is based on TSMC 0.18μm 1P6M CMOS process. Its operation voltage is 1.8 V. The experimental results show: when the frequency is 2.4GHz and the input power is -10dBm, the output power is 14dBm and its PAE is 30%；When the frequency is 1.8GHz and the input power is -10dBm, the output power is 14dBm and its PAE is 24%. We desire to design the high integrated and low power consumption power amplifier. By the circuit simulations, we design the On-chip power amplifier. Avoiding using Lump elements is for the reduction of the area consumption. Moreover, we use 1.8 V low voltage. PAE is up to more 30%.