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Статті в журналах з теми "CMOS applications"

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Автор: Grafiati

Опубліковано: 6 вересня 2023

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1

Banerjee, Sanjay K., Leonard Franklin Register, Emanuel Tutuc, Dipanjan Basu, Seyoung Kim, Dharmendar Reddy, and Allan H. MacDonald. "Graphene for CMOS and Beyond CMOS Applications." Proceedings of the IEEE 98, no. 12 (December 2010): 2032–46. http://dx.doi.org/10.1109/jproc.2010.2064151.

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2

Balaji, G. Naveen, S. Karthikeyan, and M. Merlin Asha. "0.18µm CMOS Comparator for High-Speed Applications." International Journal of Trend in Scientific Research and Development Volume-1, Issue-5 (August 31, 2017): 671–74. http://dx.doi.org/10.31142/ijtsrd2356.

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3

Sukhavasi, Susrutha Babu, Suparshya Babu Sukhavasi, Khaled Elleithy, Shakour Abuzneid, and Abdelrahman Elleithy. "CMOS Image Sensors in Surveillance System Applications." Sensors 21, no. 2 (January 12, 2021): 488. http://dx.doi.org/10.3390/s21020488.

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Recent technology advances in CMOS image sensors (CIS) enable their utilization in the most demanding of surveillance fields, especially visual surveillance and intrusion detection in intelligent surveillance systems, aerial surveillance in war zones, Earth environmental surveillance by satellites in space monitoring, agricultural monitoring using wireless sensor networks and internet of things and driver assistance in automotive fields. This paper presents an overview of CMOS image sensor-based surveillance applications over the last decade by tabulating the design characteristics related to image quality such as resolution, frame rate, dynamic range, signal-to-noise ratio, and also processing technology. Different models of CMOS image sensors used in all applications have been surveyed and tabulated for every year and application.

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4

Faramarzpour, Naser, Munir EL-DESOUKI, M. Deen, Qiyin Fang, Shahramshirani, and L. W. C. Liu. "CMOS imaging for biomedical applications." IEEE Potentials 27, no. 3 (May 2008): 31–36. http://dx.doi.org/10.1109/mpot.2008.916105.

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5

Hosticka, B. J., W. Brockherde, A. Bussmann, T. Heimann, R. Jeremias, A. Kemna, C. Nitta, and O. Schrey. "CMOS imaging for automotive applications." IEEE Transactions on Electron Devices 50, no. 1 (January 2003): 173–83. http://dx.doi.org/10.1109/ted.2002.807258.

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6

Mingam, H. "CMOS technologies for logic applications." Microelectronic Engineering 15, no. 1-4 (October 1991): 243–52. http://dx.doi.org/10.1016/0167-9317(91)90222-y.

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7

Hussain, Inamul, and Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications." Nanoscience & Nanotechnology-Asia 10, no. 3 (June 17, 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Анотація:

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

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8

Bolaños-Pérez, Ricardo, José Miguel Rocha-Pérez, Alejandro Díaz-Sánchez, Jaime Ramirez-Angulo, and Esteban Tlelo-Cuautle. "CMOS Analog AGC for Biomedical Applications." Electronics 9, no. 5 (May 25, 2020): 878. http://dx.doi.org/10.3390/electronics9050878.

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In this paper, we present the design of an analog Automatic Gain Control with a small silicon area and reduced power consumption using a 0.5 μ m process. The design uses a classical approach implementing the AGC system with simple blocks, such as: peak detector, difference amplifier, four-quadrant multiplier, and inversor amplifier. Those blocks were realized by using a modified Miller type OPAMP, which allows indirect compensation, while the peak detector uses a MOS diode. The AGC design is simulated using the Tanner-Eda environment and Berkeley models BSIM49 of the On-Semiconductor C5 process, and it was fabricated through the MOSIS prototyping service. The AGC system has an operation frequency of around 1 kHz, covering the range of biomedical applications, power consumption of 200 μ W, and the design occupies a silicon area of approximately 508.8 μ m × 317.7 μ m. According to the characteristics obtained at the experimental level (attack and release time), this AGC can be applied to hearing aid systems.

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9

OHTA, Jun, Takuma KOBAYASHI, Toshihiko NODA, Kiyotaka SASAGAWA, and Takashi TOKUDA. "CMOS Imaging Devices for Biomedical Applications." IEICE Transactions on Communications E94.B, no. 9 (2011): 2454–60. http://dx.doi.org/10.1587/transcom.e94.b.2454.

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10

Bhuiyan, M. A. S., M. B. I. Reaz, L. F. Rahman, and K. N. Minhad. "Cmos spdt switch for wlan applications." IOP Conference Series: Materials Science and Engineering 78 (April 2, 2015): 012011. http://dx.doi.org/10.1088/1757-899x/78/1/012011.

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11

Laes, E., L. Baldi, C. Dahl, F. R. J. Huisman, and L. Deferm. "CMOS options for single chip applications." IEEE Micro 19, no. 5 (1999): 23–32. http://dx.doi.org/10.1109/40.798106.

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12

Parker, E. H. C., and T. E. Whall. "SiGe heterostructure CMOS circuits and applications." Solid-State Electronics 43, no. 8 (August 1999): 1497–506. http://dx.doi.org/10.1016/s0038-1101(99)00095-7.

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13

Camli, Berk, Baykal Sarioglu, and Arda D. Yalcinkaya. "Photodiodes for Monolithic CMOS Circuit Applications." IEEE Journal of Selected Topics in Quantum Electronics 20, no. 6 (November 2014): 336–43. http://dx.doi.org/10.1109/jstqe.2014.2333236.

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14

NEPPL, F., and H. J. PFLEIDERER. "CMOS-TECHNOLOGY - STATUS, TRENDS AND APPLICATIONS." Le Journal de Physique Colloques 49, no. C4 (September 1988): C4–13—C4–22. http://dx.doi.org/10.1051/jphyscol:1988402.

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15

Ogiers, Werner. "CMOS Imaging Sensors for Space Applications." Sensors Update 4, no. 1 (August 1998): 167–93. http://dx.doi.org/10.1002/1616-8984(199808)4:1<167::aid-seup167>3.0.co;2-m.

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16

SOLIMAN, EMAN A., and SOLIMAN A. MAHMOUD. "THE DIFFERENTIAL DIFFERENCE OPERATIONAL FLOATING AMPLIFIER: NEW CMOS REALIZATIONS AND APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 07 (November 2009): 1287–308. http://dx.doi.org/10.1142/s0218126609005666.

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This paper presents different novel CMOS realizations for the differential difference operational floating amplifier (DDOFA). The DDOFA was first introduced in Ref. 1 and was used to realize different analog circuits like integrators, filters and variable gain amplifiers. New CMOS realizations for the DDOFA are introduced in this literature. Furthermore the DDOFA is modified to realize a fully differential current conveyor (FDCC). Novel CMOS realizations of the FDCC are presented. The FDCC is used to realize second-order band pass–low-pass filter. Performance comparisons between the different realizations of the DDOFA and FDCC are given in this literature. PSPICE simulations of the overall proposed circuits are given using 0.25 μm CMOS Technology from TMSC MOSIS model and dual supply voltages of ±1.5 V.

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17

Kuzmicz, Wieslaw. "A Thermally Stable Quasi-CMOS Bipolar Logic." Electronics 11, no. 1 (December 21, 2021): 6. http://dx.doi.org/10.3390/electronics11010006.

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Logic gates made of pairs of NPN and PNP bipolar transistors, similar to CMOS logic gates, have been proposed and patented long ago but did not find any practical application until now. Other bipolar technologies (TTL, TTL-S, ECL), once the technologies of choice for digital systems, were abandoned and superseded by CMOS. In this paper it is shown that now, when truly complementary pairs of bipolar transistors can be made, properly biased bipolar gates similar to CMOS gates are feasible, can be thermally stable and find practical applications.

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18

Dhar, Subhra, Manisha Pattanaik, and Poolla Rajaram. "Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications." VLSI Design 2011 (May 26, 2011): 1–19. http://dx.doi.org/10.1155/2011/178516.

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In recent years, the demand for power sensitive designs has grown significantly due to the fast growth of battery-operated portable applications. As the technology scaling continues unabated, subthreshold device design has gained a lot of attention due to the low-power and ultra-low-power consumption in various applications. Design of low-power high-performance submicron and deep submicron CMOS devices and circuits is a big challenge. Short-channel effect is a major challenge for scaling the gate length down and below 0.1 μm. Detailed review and potential solutions for prolonging CMOS as the leading information technology proposed by various researchers in the past two decades are presented in this paper. This paper attempts to categorize the challenges and solutions for low-power and low-voltage application and thus provides a roadmap for device designers working in the submicron and deep submicron region of CMOS devices separately.

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19

Vidhyadharan, Abhay Sanjay, and Sanjay Vidhyadharan. "Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications." World Journal of Engineering 18, no. 5 (March 26, 2021): 750–59. http://dx.doi.org/10.1108/wje-08-2020-0367.

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

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20

HASSAN, HASSAN M., and AHMED M. SOLIMAN. "NOVEL CMOS REALIZATIONS OF THE OPERATIONAL FLOATING CONVEYOR AND APPLICATIONS." Journal of Circuits, Systems and Computers 14, no. 06 (December 2005): 1113–43. http://dx.doi.org/10.1142/s0218126605002854.

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This paper presents novel CMOS realizations of the operational floating conveyor (OFC) based on novel block diagrams. It also introduces novel applications based on one of the proposed OFC realizations. The proposed OFC realization provides a wide bandwidth and a large gain bandwidth product. Hence, it exhibits wide bandwidth at higher gains. All the circuits in this paper are designed following a fair comparison criterion. The supply voltages are ±1.5 V . The reference DC current source IB is taken as 50 μA. The CMOS model for all circuits is identical. The transistor model is 0.5 μm CMOS process provided by MOSIS (AGILENT).

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21

C.S, Sajin, and Dr T. A. Shahul Hameed. "Review of CMOS Amplifiers for High Frequency Applications." International Journal of Engineering and Advanced Technology 10, no. 2 (December 30, 2020): 175–80. http://dx.doi.org/10.35940/ijeat.b2101.1210220.

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The headway in electronics technology proffers user-friendly devices. The characteristics such as high integration, low power consumption, good noise immunity are the significant benefits that CMOS offer, paying many challenges simultaneously with it. The short channel effects and presence of parasitic which prevent speed pose questions on the performance parameters. A great sort of works has done by many groups in the design of the CMOS amplifier for high-frequency applications to discuss the parameters such as power consumption, high bandwidth, high speed and linearity trade-off to obtain an optimized output. A lot of amplifier topologies are experimented and discussed in the literature with its design and simulation. In this paper, the various efforts associated with CMOS amplifier circuit for high-frequency applications are studying extensively.

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22

Hasan, A. F., S. A. Z Murad, K. N. Abdul Rani, F. A. Bakar, and T. Z. A. Zulkifli. "Study of CMOS power amplifier design techniques for ka-band applications." Indonesian Journal of Electrical Engineering and Computer Science 13, no. 2 (February 1, 2019): 808. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp808-817.

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<span>This paper reviews of high efficiency CMOS power amplifiers (PAs) in millimeter (mm) wave Ka - Band applications. The study is focused on the challenges in designing PA especially in GHz frequencies inclusive of high gain, good input and output matching, efficiency, linearity, low group delay and low power consumption. Several works on CMOS PA from year 2009 to 2018 are discussed in this paper. Recent developments of CMOS PAs are examined and a comparison of the performance criteria of various techniques is presented.</span>

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23

Chakraverty, Mayank, and V. N. Ramakrishnan. "Principles of Logic Design with Nanoscale Thin Film Memristive Systems for High Performance Digital Circuit Applications." Advanced Materials Research 1176 (April 28, 2023): 19–31. http://dx.doi.org/10.4028/p-90x9b8.

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The characteristic pinched hysteresis behavior of memristors has been reported by stacks of a variety of materials. This paper aims to examine the principles of logic design using such two terminal memristive systems for high performance digital circuit applications. As against logic design with standard CMOS, the benefits of logic design with memristors have been stated. The realization and operation of memristor based AND and OR hybrid logic gates obtained by integrating memristors with standard CMOS logic have been discussed. The IMPLY and MAGIC logic families have been demonstrated by covering MAGIC NOR and NAND logic gate implementation with MAGIC NOR in detail. A qualitative comparison has been drawn towards the end of the paper to conclude on the suitability and application space for each of the logic families studied in this paper. This work also describes the hybrid CMOS-memristive logic family known as MRL (Memristor Ratioed Logic). With the addition of CMOS inverters, this logic family's OR and AND logic gates, which are based on memristive components, are given a full logic structure and signal restoration. The MRL family, in contrast to earlier memristor-based logic families, is compatible with conventional CMOS logic.

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24

Mahmoud, Soliman A. "Wide Dynamic Range CMOS Pseudo-differential Current Conveyors: CMOS Realizations and Applications." Circuits, Systems, and Signal Processing 32, no. 2 (August 29, 2012): 477–97. http://dx.doi.org/10.1007/s00034-012-9478-y.

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25

LIN, HUNG-YI, and YEN-TAI LAI. "DESIGN OF LOW POWER TWO-PHASE CMOS BUFFER FOR LARGE CAPACITIVE LOADING APPLICATIONS." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250092. http://dx.doi.org/10.1142/s0218126612500922.

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In this paper, a low power two-phase CMOS buffer with short-circuit power elimination and charge reuse for non-speed-critical large capacitive loading applications is proposed. The short-circuit power eliminating circuit is designed to remove the short-circuit current at the buffer's output, which accounts for the largest portion of the short-circuit power dissipation of the CMOS buffer. The charge reuse circuit is used to reduce the output dynamic power dissipation of the two-phase buffer. Moreover, the overall power dissipation of the proposed buffer is further decreased by optimizing the number of tapered stages and the values of tapered factors in the tapered chains of the short-circuit power eliminating circuit. In order to validate the efficiency of the proposed design, theoretical analysis and simulations with various capacitive loads are conducted using TSMC 0.18-μm 1P6M and UMC advanced 90-nm 1P9M CMOS technologies. The results show that the power dissipation of the proposed two-phase CMOS buffer is 8.6% lower than that of the conventional two-phase CMOS tapered buffer. The power-delay product of the proposed buffer is 2.7% smaller than that of the conventional tapered buffer.

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26

Li, Ming, Rony E. Amaya, Robert G. Harrison, and N. Garry Tarr. "Investigation of CMOS Varactors for High-GHz-Range Applications." Research Letters in Electronics 2009 (2009): 1–4. http://dx.doi.org/10.1155/2009/535809.

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This paper explores a variety of different CMOS varactor structures for RF and MMICs. A typical 0.18 μm CMOS foundry process was used as the study platform. The varactors' capacitance-voltage characteristics and cutoff frequencies have been examined up to 55 GHz. The primary aim of this work is to design varactors that can improve nonlinear-transmission-line (NLTL) pulse-compression circuits. The results should also be valuable for other applications up to millimeter wavelengths.

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27

Zhang, Zhang, Zheng Xi Cheng, and Yi Wei Zhuang. "CMOS Amplifier for Neural Signal Recording Applications." Key Engineering Materials 645-646 (May 2015): 1279–84. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.1279.

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A low power low noise CMOS amplifier with integrated filter for neural signal recording is designed and fabricated with CSMC 0.5 μm CMOS process. DC offsets introduced by electrode-tissue interface are rejected through a feedback low-pass filter. The bandwidth of the amplifier is in 3.5Hz-5.5KHz range, and the gain is about 48dB in the midband. AC input differential mode voltage range is 10mV, and DC input differential mode voltage range is 180mV. The amplifier can accommodate 180mV DC offsets drift and 10mV neural spikes. The neural probe array is integrated directly on the surface of the amplifier array chip, and is tested in saline solution, and also is implanted in rats in vivo , the results of the experiments show that the amplifier is suitable for neural signal recording. The power dissipation is about 14μW while consuming 0.16 mm2 of chip area, which satisfies implantable devices requirements.

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28

Karthikeyan, A., and P. S. Mallick. "Body-Biased Subthreshold Bootstrapped CMOS Driver." Journal of Circuits, Systems and Computers 28, no. 03 (February 24, 2019): 1950051. http://dx.doi.org/10.1142/s0218126619500518.

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This paper proposes a body-biased bootstrapped CMOS driver for subthreshold applications. The proposed driver has been implemented with the same number of transistors as conventional bootstrapped CMOS driver. The performance of the subthreshold bootstrapped CMOS driver has been compared with the conventional bootstrapped CMOS driver. Our results show that the proposed body-biased subthreshold bootstrapped CMOS driver has 37% reduction in delay and 39% reduction in power dissipation compared to conventional bootstrapped CMOS driver. The proposed driver is more suitable to drive large loads compared to the conventional driver and operates better at subthreshold region.

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29

Campos, Fernando de Souza, Bruno Albuquerque de Castro, and Jacobus W. Swart. "A Tunable CMOS Image Sensor with High Fill-Factor for High Dynamic Range Applications." Engineering Proceedings 2, no. 1 (November 14, 2020): 79. http://dx.doi.org/10.3390/ecsa-7-08235.

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Several CMOS imager sensors were proposed to obtain high dynamic range imager (>100 dB). However, as drawback these imagers implement a large number of transistors per pixel resulting in a low fill factor, high power consumption and high complexity CMOS image sensors. In this work, a new operation mode for 3 T CMOS image sensors is presented for high dynamic range (HDR) applications. The operation mode consists of biasing the conventional reset transistor as active load to photodiode generating a reference current. The output voltage achieves a steady state when the photocurrent becomes equal to the reference current, similar to the inverter operation in the transition region. At a specific bias voltage, the output swings from o to Vdd in a small light intensity range; however, high dynamic range is achieve using multiple readout at different bias voltage. For high dynamic range operation different values of bias voltage can be applied from each one, and the signal can be captured to compose a high dynamic range image. Compared to other high dynamic range architectures this proposed CMOS image pixel show as advantage high fill-factor (3 T) and lower complexity. Moreover, as the CMOS pixel does not operate in integration mode, de readout can be performed at higher speed. A prototype was fabricated at 3.3 V 0.35 µm CMOS technology. Experimental results are shown by applying five different control voltage from 0.65 to 1.2 V is possible to obtain a dynamic range of about 100 dB.

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30

El-Desouki, Munir, M. Jamal Deen, Qiyin Fang, Louis Liu, Frances Tse, and David Armstrong. "CMOS Image Sensors for High Speed Applications." Sensors 9, no. 1 (January 13, 2009): 430–44. http://dx.doi.org/10.3390/s90100430.

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31

Wäny, Martin, Pedro Santos, Elena G. Reis, Alice Andrade, Ricardo M. Sousa, and L. Natércia Sousa. "Octagonal CMOS Image Sensor for Endoscopic Applications." Electronic Imaging 2017, no. 11 (January 29, 2017): 46–51. http://dx.doi.org/10.2352/issn.2470-1173.2017.11.imse-185.

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32

Lee, Hong-Tak, Yu-Mi Lee, Chang-Kun Park, and Song-Cheol Hong. "Class-E CMOS PAs for GSM Applications." Journal of electromagnetic engineering and science 9, no. 1 (March 31, 2009): 32–37. http://dx.doi.org/10.5515/jkiees.2009.9.1.032.

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33

Herzel, F., H. Erzgräber, and P. Weger. "Integrated CMOS wideband oscillator for RF applications." Electronics Letters 37, no. 6 (2001): 330. http://dx.doi.org/10.1049/el:20010245.

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34

Weihsing Liu, Shen-Iuan Liu, and Shui-Ken Wei. "CMOS current-mode divider and its applications." IEEE Transactions on Circuits and Systems II: Express Briefs 52, no. 3 (March 2005): 145–48. http://dx.doi.org/10.1109/tcsii.2004.842041.

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35

Machida, K., T. Konishi, D. Yamane, H. Toshiyoshi, and K. Masu. "Integrated CMOS-MEMS Technology and Its Applications." ECS Transactions 61, no. 6 (March 19, 2014): 21–39. http://dx.doi.org/10.1149/06106.0021ecst.

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36

Song, B. "CMOS RF circuits for data communications applications." IEEE Journal of Solid-State Circuits 21, no. 2 (April 1986): 310–17. http://dx.doi.org/10.1109/jssc.1986.1052521.

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