Дисертації з теми "Circuit reliability simulation"

Thesis (Ph. D.) -- University of Maryland, College Park, 2005.
Thesis research directed by: Mechanical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

O efeito das variações intrínsecas afetando parâmetros elétricos de circuitos fabricados com tecnologia CMOS de escala nanométrica apresenta novos desafios para o yield de circuitos integrados. Este trabalho apresenta modelos para representar variações físicas que afetam transistores projetados em escala sub-micrônica e metodologias computacionalmente eficientes para simular estes dispositivos utilizando ferramentas de Electronic Design Automation (EDA). O trabalho apresenta uma investigação sobre o estado-da-arte de modelos para variabilidade em nível de simulação de transistor. Modelos de variações no processo de fabricação (RDF, LER, etc) e confiabilidade (NBTI, RTS, etc) são investigados e um novo modelo estatístico para a simulação de Random Telegraph Signal (RTS) e Bias Temperature Instability (BTI) para circuitos digitais é proposta. A partir desses modelos de dispositivo, o trabalho propõe modelos eficientes para analisar a propagação desses fenômenos para o nível de circuito através de simulação. As simulações focam no impacto de variabilidade em três diferentes aspectos do projeto de circuitos integrados digitais: caracterização de biblioteca de células, análise de violações de tempo de hold e células SRAM. Monte Carlo é a técnica mais conhecida e mais simples para simular o impacto da variabilidade para o nível elétrico do circuito. Este trabalho emprega Monte Carlo para a análise do skew em redes de distribuição do sinal de relógio e em caracterização de células SRAM considerando RTS. Contudo, simulações Monte Carlo exigem tempo de execução elevado. A fim de acelerar a análise do impacto de variabilidade em biblioteca de células este trabalho apresenta duas alternativas aMonte Carlo: 1) propagação de erros usando aproximação linear de primeira ordem e 2)Metodologia de Superfície de Resposta (RSM). As técnicas são validados usando circuitos de nível comercial, como a rede de clock de um chip comercial utilizando a tecnologia de 90nm e uma biblioteca de células usando um nó tecnológico de 32nm.
In nanometer scale complementary metal-oxide-semiconductor (CMOS) parameter variations pose a challenge for the design of high yield integrated circuits. This work presents models that were developed to represent physical variations affecting Deep- Submicron (DSM) transistors and computationally efficient methodologies for simulating these devices using Electronic Design Automation (EDA) tools. An investigation on the state-of-the-art of computer models and methodologies for simulating transistor variability is performed. Modeling of process variability and aging are investigated and a new statistical model for simulation of Random Telegraph Signal (RTS) in digital circuits is proposed. The work then focuses on methodologies for simulating these models at circuit level. The simulations focus on the impact of variability to three relevant aspects of digital integrated circuits design: library characterization, analysis of hold time violations and Static Random Access Memory (SRAM) cells. Monte Carlo is regarded as the "golden reference" technique to simulate the impact of process variability at the circuit level. This work employs Monte Carlo for the analysis of hold time and SRAM characterization. However Monte Carlo can be extremely time consuming. In order to speed-up variability analysis this work presents linear sensitivity analysis and Response Surface Methodology (RSM) for substitutingMonte Carlo simulations for library characterization. The techniques are validated using production level circuits, such as the clock network of a commercial chip using 90nm technology node and a cell library using a state-of-theart 32nm technology node.

Long-term hot-carrier induced degradation of MOS devices has become more severe as the device size continues to scale down to submicron range. In our work, a simple yet effective method has been developed to provide the degradation laws with a better predictability. The method can be easily augmented into any of the existing degradation laws without requiring additional algorithm. With more accurate extrapolation method, we present a direct and accurate approach to modeling empirically the 0.18-ìm MOS reliability, which can predict the MOS lifetime as a function of drain voltage and channel length. With the further study on physical mechanism of MOS device degradation, experimental results indicated that the widely used power-law model for lifetime estimation is inaccurate for deep submicron devices. A better lifetime prediction method is proposed for the deep-submicron devices. We also develop a Spice-like reliability model for advanced radio frequency RF MOS devices and implement our reliability model into SpectreRF circuit simulator via Verilog-A HDL (Hardware Description Language). This RF reliability model can be conveniently used to simulate RF circuit performance degradation
Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering

The fundamental requirement of the research reported within this thesis is the provision of physical models to enable model based simulation of mainstream printed circuit assembly (PCA) process discrete events for use within to-be-developed (or under development) software tools which codify cause & effects knowledge for use in product and process design optimisation. To support a national competitive advantage in high reliability electronics UK based producers of aircraft electronic subsystems require advanced simulation tools which offer model based guidance. In turn, maximization of manufacturability and minimization of uncontrolled rework must therefore enhance inservice sustainability for 'power-by-the-hour' commercial aircraft operation business models.

Au cours des dernières décennies, la demande de fonctionnalités complexes et d'intégration haute densité pour les Circuits Intégrés (CI) a mené à une réduction de la taille des dispositifs métal-oxyde-silicium (MOS). Dans ce scénario, les problèmes de fiabilité sont les préoccupations considérables par suite de la miniaturisation de l'appareil, telles que Hot Carrier Injection (HCI) et Bias Temperature Instability (BTI) qui ont un impact sérieux sur les performances de l'appareil. Dans certains domaines d'application où le coût des pannes est extrêmement élevé, comme l'espace, les champs pétrolifères ou les soins de santé, l'appareil doit pouvoir fonctionner de manière stable et fiable, en particulier dans une plage de températures étendue. Bien que les mécanismes de défaillance des dispositifs aient été intensivement étudiés dans le passé, les investigations de ces mécanismes à hautes températures sont rarement étudiées.L'objectif de cette thèse est de développer les lois de vieillissement de la technologie CMOS 0.18µm afin d'optimiser la conception des circuits pour une durée de vie ciblée sous des températures extrêmes. Nous avons mené une campagne intensive de tests de vieillissement pour nMOS et pMOS avec plusieurs longueurs de grille. Les mécanismes HCI et BTI intrinsèques ont été caractérisés et modélisés sous des tensions de polarisation de fonctionnement typique pour éviter le risque de sur-accélération d'autres mécanismes d'usure qui ne sont pas censés être expérimentés dans l'application pratique. Notre expérimentation est un test à longue durée avec un temps de stress allant jusqu'à 2,000 heures. Cette thèse présente des résultats de mesure jusqu'à 230°C qui n'ont jamais été étudiés auparavant dans la littérature pour cette technologie.Les lois de vieillissement sont finalement intégrées dans un environnement de conception assistée par ordinateur (EDA) pour prédire l'évolution des paramètres électriques dégradés du transistor/circuit et l'estimation de la durée de vie en conséquence des effets du vieillissement. De plus, le test de fiabilité au niveau du circuit a été réalisé pour valider et vérifier les modèles de vieillissement proposés. Cette approche offre la possibilité d'évaluer et de simuler la dérive de spécification du CI due à l'effet du vieillissement dans la phase de conception précoce
In the past decades, the demand for complicated functionality and high-density integration for Integrated Circuits (ICs) has resulted in metal-oxide-silicon (MOS) devices' scaling down. In this scenario, the reliability problems are the considerable concerns due to the device miniaturization, such as Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) that seriously impact the device performance. In some application fields where the cost of failure is extremely high such as space, oilfield, or healthcare, the device must be able to stably and reliably work, especially at an extensive temperature range. Although device failure mechanisms have been intensively investigated in the past, the investigations of these mechanisms at high temperatures are seldom studied.This thesis aims to develop the aging laws for 0.18µm CMOS technology to optimize circuit design for a targeted lifetime under extreme temperatures. We conducted an intensive aging test campaign for both nMOS and pMOS featuring several gate lengths. The intrinsic HCI and BTI mechanisms were characterized and modeled under typical operating voltage biases to avoid the risk of overaccelerating other wear-out mechanisms that are not supposed to be experienced in practical application. Our experiment is a long-term test with a stress time of up to 2,000 hours. This thesis presents measurement results up to 230°C that have never been studied before in the literature for this technology.The aging laws are finally integrated into an electronic design automation (EDA) environment to predict the evolution of the degraded transistor/circuit electrical parameters and the lifetime estimation due to the aging effects. In addition, the reliability test at the circuit level has been performed to validate and verify the proposed aging models. This approach offers the possibility to assess and simulate the IC specification drift due to the aging effect in the early design phase and optimize the circuit design over lifetime

Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citées
This Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.
Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.

Thesis (Ph. D.) -- University of Maryland, College Park, 2007.
Thesis research directed by: Reliability Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

Les travaux de cette thèse portent sur la simulation de la dégradation des paramètres électriques des transistors MOS et bipolaires sous stress statiques et dynamiques. Cette étude a été menée à l’aide d’un outil de simulation de fiabilité développé en interne. Selon la technologie MOS ou bipolaire, les mécanismes étudiés ont été successivement : Hot Carrier Injection, Bias Temperature instability, Mixed Mode et Reverse base emitter bias. L’investigation a été aussi étendue au niveau circuit. Nous nous sommes ainsi intéressés à l’effet de la dégradation des transistors sur la fréquence d’un oscillateur en anneau et les performances RF d’un amplificateur faible bruit. Les circuits ont été soumis à des contraintes DC , AC et RF. La prédictibilité, établie de ces dégradations, a été validée par des essais de vieillissement expérimentaux sur des démonstrateurs encapsulés et montés sur PCB. Les résultats de ces études ont permis de valider la précision du simulateur et la méthode de calcul quasi-statique utilisée pour calculer les dégradations sous stress dynamiques. Ces travaux de recherche ont pour but d’inscrire cette approche prédictive dans un flot de conception de circuits afin d’assurer leur fiabilité
The work of this thesis focuses on the simulation of the electrical parameters degradation of MOS and bipolar transistors under static and dynamic stresses. This study was conducted using an in-house reliability simulation tool. According to the MOS or bipolar technology, the studied mechanisms were successively: Hot Carrier Injection, Bias Temperature instability, Mixed Mode and Reverse base emitter bias. The investigation was then extended to circuit-level. The effect of transistors degradation on a ring oscillator frequency and the RF performances of a low noise amplifier were investigated. The circuits were subjected to DC, AC and RF constraints. Predictability of these degradations has been validated by experimental aging tests on encapsulated and PCB-mounted demonstrators. The results of these studies proved the accuracy of the simulator and validated the quasi-static calculation method used to predict the degradation under dynamic stress. The goal of this research is to embed this predictive approach into a circuit design flow to ensure its reliability

Three-dimensional integrated circuits (3D ICs) have been designed with the purpose of achieving higher communication speed by reducing the interconnect length between integrated circuits, and integrating heterogeneous functions into one single package, among other advantages. As a growing, new technology, researchers are still studying the different parameters that impact the overall lifetime of such packages in order to ensure the customer receives reliable end products. This study focused on the effect of four design parameters on the lifetime of the interconnects and, in particular, solder balls and through-silicon vias (TSVs). These parameters included TSV pitch, TSV diameter, underfill stiffness and underfill thickness. A three-dimensional finite element model of a 3D IC package was built in ANSYS to analyze the effect of these parameters under thermo-mechanical cyclic loading. The stresses and damage in the interconnects of the IC were evaluated using Coffin-Manson and the energy partitioning fatigue damage models. A three-level Taguchi design of experiment method was utilized to evaluate the effect of each parameter. Minitab software was used to assess the main effects of the selected design parameters. Locations of maximum stresses and possible damage initiation were discussed, and recommendations were made to the manufacturer for package optimization. Due to the very small scale of the interconnects, conducting mechanical tests and measuring strains in small microscopic scale material is very complicated and challenging; therefore, it is very difficult to validate finite element and analytical analysis of stress and strain in microelectronic devices. At the next step of this work, a new device and method were proposed to facilitate testing and strain measurements of material at microscopic scale. This new micro-electromechanical system (MEMS) consisted of two piezoelectric members that were constrained by a rigid frame and that sandwiched the test material. These two piezoelectric members act as load cell and strain measurement sensors. As the voltage is applied to the first member, it induces a force to the specimen and deforms it, which in turn deforms the second piezoelectric member. The second piezoelectric member induces an output voltage that is proportional to its deformation. Therefore, the strain and stresses in the test material can be determined by knowing the mechanical characteristics of the piezoelectric members. Advantages of the proposed system include ease of use, particularly at microscopic scale, adaptability to measure the strain of different materials, and flexibility to measure the modulus of elasticity for an unknown material. An analytical analysis of the device and method was presented, and the finite element simulation of the device was accomplished. The results were compared and discussed. An inelastic specimen was also analyzed and sensitivity of the device to detecting nonlinear behavior was evaluated. A characteristic curve was developed for the specific geometry and piezoelectric material.

Cette thèse, qui s’intègre dans le cadre du projet européen EMCOMIT, a pour objectif de contribuer à l’étude des circuits imprimés haute densité d’intégration comportant un nombre de couches important et des composants enterrés. La qualification de cette technologie est effectuée en conduisant des simulations et des mesures électriques sur des véhicules de tests spécifiques. L’analyse des résultats électriques permet d’évaluer l’aptitude de ces matériaux à répondre aux exigences des applications de télécommunication et de technologie de l’information rapide. La fiabilité d’un assemblage de BGA de grande taille sur un circuit imprimé a été évaluée. Des simulations thermomécaniques ont été effectuées afin de calculer les contraintes résiduelles accumulées pendant le procédé d’assemblage puis l’énergie dépensée dans les parties critiques des joints au cours d’un cycle thermique. Simultanément, des BGA reportés sur des circuits imprimés ont été placés dans une chambre climatique et ont subi des variations de températures
This thesis, which is part of the European EMCOMIT project, aims at contributing to the study of high density printed circuit board including a great number of internal layers and embedded components. The qualification of this technology is done by the way of simulations and electrical measurements on specific test vehicles. The electrical results allow estimating the performance of materials for telecommunication applications and speed data transfer. The reliability of the assembly of the large BGA on a printed circuit board has been evaluated. Thermomechanical simulations have been done in order to compute residual stresses stored during the assembly process and the deformation energy density in the solder joints during one thermal cycle. Simultaneously BGA soldered on printed circuits have been positioned in climatic chamber and have been subjected to temperature variations

Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.; The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (Vsubscript T) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (Vsubscript T]) shift and 25% to electron mobility (mu subscript n]) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation.
ID: 029809399; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 90-105).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science

Atualmente, a simulação de falhas é um estágio importante em qualquer desenvolvimento de Circuitos Integrados. A predição de falhas comportamentais em qualquer estagio do processo é essencial para garantir que o chip desenvolvido seja bem implementado. Vários problemas podem ser conferidos e solucionados enquanto se executa a simulação. As falhas transientes mais conhecidas são os Single-Event-Upset (SEU), as quais acontecem nos circuitos de memória, e as Single-Event Transient (SET), que acontecem em circuitos de lógica combinacional. A análise do comportamento do circuito sob falhas é fundamental para a escolha de técnicas de proteção e medição da susceptibilidade aos diferentes tipos de falhas. Neste trabalho, apresenta-se uma ferramenta para simular os efeitos que acontecem quando uma fonte de falha é inserida num circuito digital, especialmente falhas SEU. Além disso, é desenvolvido o método TMR que pode verificar a existência de uma falha e inibir que esta se propague pelo circuito todo. Foram desenvolvidos módulos para simulação de circuitos analógicos como o Oscilador Controlado por Voltagem (VCO) permitindo a visualização dos efeitos de falhas nestes circuitos. A ferramenta LabVIEWr da National Instruments é usada para criar o conjunto de Instrumentos Virtuais (VIs) para simular os SEUs. Esta é também usada pela simulação de SETs. Foram feitos várias simulações com as ferramentas desenvolvidas para validar sua funcionalidade os quais mostram resultados semelhantes aos descritos na literatura. As ferramentas desenvolvidas para simulação de falhas transientes em portas lógicas inserem falhas SET de forma automática sem análise prévia do sinal de saída. Usando as ferramentas de Lógica Booleana é possível obter resultados para fazer estudos estatísticos dos erros acontecidos e determinar tendências no comportamento das técnicas de Redundância Modular Triplo (TMR) e TMR com redundância no tempo. O modelo desenvolvido para a análise de falhas do VCO apresenta uma melhor semelhança com o resultado real que com o simulado com ferramentas comerciais.
Nowadays, the fault simulation is an important step in any IC design. Predicting the behavioral faults of any process step is essential to ensure that the design is well implemented. During the simulation various problems can be detected and corrected. The transient faults are the most well known Single-Event-Upset (SEU), which affect memory circuits, and Single-Event Transient (SET), which affect combinational logic circuits. The analyses of the circuit under faults is crucial to the choice of protection techniques and measurement of susceptibility to different types of failures. In this work a tool to simulate the effects that occur when a source of fault is inserted in a digital circuit, especially SEU faults is presented. In addition to modeling a fault, it is developed a Triple Modular Redundancy (TMR) method capable of verifying the existence of a fault preventing it from spreading through the whole circuit. It is also developed a Voltage Controled Oscillator (VCO) to view fault effects in analog circuit. LabVIEWr is used to create a set of virtual instruments to simulate SEUs. It is efficient in modeling the characteristics of SETs. It is possible with this toolkit to replicate the effects of SEUs and SETs described in the literature. The tools developed for simulation of transient faults in logic gates insert SET failures automatically without output signal prior analysis. Using the tools of Boolean Logic is possible to obtain results to make statistical studies of the errors that occurred and determine trends in the behavior of TMR with and without redundancy in time. The model developed for failature analysis of the VCO is similar to the real result with that simulated with commercial tools.

La motivation de cette thèse est deux des principaux problèmes soulevés par la mise à l'échelle des appareils de la nouvelle ère dans la conception MOSFET contemporaine: le développement d'un modèle de courant de drain analytique et compact, valable dans toutes les régions d'opération, décrivant précisément les caractéristiques Id-Vg et Id-Vd des dispositifs FDSOI à canaux courts et l'étude des problèmes de fiabilité et de variabilité de ces transistors évolués à l'échelle nanométrique. Le chapitre II fournit une base théorique et technique pour une meilleure compréhension de cette thèse, en mettant l'accent sur les paramètres électriques MOSFET critiques et les techniques d'extraction. Il démontre les méthodologies de Y-Function et de Split-CV pour la caractérisation électrique dans divers types de semiconducteurs. L'influence du niveau de l'oscillateur du signal AC sur la mesure de la mobilité efficace par la technique Split-CV dans MOSFET est également analysée. Une nouvelle méthodologie basée sur la fonction Lambert W qui permet d'extraire les paramètres MOSFET sur la gamme de tension de grille complète, permettant de décrire la transition entre les regions en dessous et au dessus du seuil, malgré la réduction de la tension d'alimentation. Enfin, certains éléments de base concernant le bruit à basse fréquence (LFN) sur la caractérisation MOSFET sont décrits. Le chapitre III présente la modélisation analytique et compacte du courant de drain dans les MOSFET FDSOI à l'échelle nanométrique. Des modèles analytiques simples pour les tensions de seuil de la grille avant et arrière et les facteurs d'idéalité ont été développés en termes de paramètres de géométrie du dispositif et de tensions de polarisation appliquées avec contrôle de la grille arrière. Un modèle analytique et compact de courant de drain a été développé pour les MOSFET FDSOI UTBB légèrement dopés avec contrôle de la grille arrière, prenant en compte la géométrie réduite et d'autres effets importants dans ces technologies et implémenté en Verilog-A pour la simulation des circuits dans Cadence Spectre. Le chapitre IV traite des problèmes de fiabilité dans les transistors FDSOI. La dégradation par des porteurs chauds des nMOSFET UTBB FDSOI decananométrique a été étudiée dans différentes conditions de stress de drain et de grille. Les mécanismes de dégradation ont été identifiés grâce à des mesures LFN à température ambiante dans les domaines de la fréquence et du temps. Un modèle de vieillissement HC est proposé permettant de prédire la dégradation du dispositif stressé dans différentes conditions de polarisation, en utilisant de paramètres uniques déterminés pour chaque technologie extraits par des mesures. Enfin, les caractéristiques de stress NBTI et le comportement de relaxation après stress sous la polarisation positive des pMOSFET UTBB FDSOI de grille HfSiON ont été étudiés. Un modèle pour le NBTI a été développé en considérant les mécanismes de piégeage/dépiégeage des trous, en fonction de la température et de la tension de polarisation. Le chapitre V présente des études sur les problèmes de variabilité dans les dispositifs décananométriques. Les principales sources de courant de drain et de grille de la variabilité locale ont été étudiées. Dans cet aspect, un modèle de courant de drain de la variabilité locale, valable pour toute condition de polarisation de grille et de drain, a été développé. Les principaux paramètres MOSFET de variabilité locale et globale ont été extraits par ce modèle pour différentes technologies CMOS (Bulk 28nm, FDSOI 14nm, Si bulk FinFET 14nm, nanofils Si/SiGe sous 15nm). L’impact de la variabilité du courant de drain sur les circuits de Cadence Spectre est présenté. Un résumé de cette thèse est présenté au chapitre VI, qui souligne les principales contributions à la recherche et les orientations de recherche futures sont suggérées
Τhe motivation for this dissertation is two of the main issues brought up by the scaling of new-era devices in contemporary MOSFET design: the development of an analytical and compact drain current model, valid in all regions of operation describing accurately the transfer and output characteristics of short-channel FDSOI devices and the investigation of reliability and variability issues of such advanced nanoscale transistors. Chapter II provides a theoretical and technical background for the better understanding of this dissertation, focusing on the critical MOSFET electrical parameters and the techniques for their extraction. It demonstrates the so-called Y-Function and Split-CV methodologies for electrical characterization in diverse types of semiconductors. The influence of AC signal oscillator level on effective mobility measurement by split C-V technique in MOSFETs is also analyzed. A new methodology based on the Lambert W function which allows the extraction of MOSFET parameters over the full gate voltage range, enabling to fully capture the transition between subthreshold and above threshold region, despite the reduction of supply voltage Vdd is presented. Finally, some basic elements concerning the low frequency noise (LFN) on MOSFETs characterization are described. Chapter III presents the analytical drain current compact modeling in nanoscale FDSOI MOSFETs. Simple analytical models for the front and back gate threshold voltages and ideality factors have been derived in terms of the device geometry parameters and the applied bias voltages with back gate control. An analytical compact drain current model has been developed for lightly doped UTBB FDSOI MOSFETs with back gate control, accounting for small geometry and other significant in such technologies effects and implemented via Verilog-A code for simulation of circuits in Cadence Spectre. Chapter IV is dealing with reliability issues in FDSOI transistors. The hot-carrier degradation of nanoscale UTBB FDSOI nMOSFETs has been investigated under different drain and gate bias stress conditions. The degradation mechanisms have been identified by combined LFN measurements at room temperature in the frequency and time domains. Based on our analytical compact model of Chapter III, an HC aging model is proposed enabling to predict the device degradation stressed under different bias conditions, using a unique set of few model parameters determined for each technology through measurements. Finally, the NBTI stress characteristics and the recovery behavior under positive bias temperature stress of HfSiON gate dielectric UTBB FDSOI pMOSFETs have been investigated. A model for the NBTI has been developed by considering hole-trapping/detrapping mechanisms, capturing the temperature and bias voltage dependence. In Chapter V studies of variability issues in advanced nano-scale devices are presented. The main sources of drain and gate current local variability have been thoroughly studied. In this aspect, a fully functional drain current mismatch model, valid for any gate and drain bias condition has been developed. The main local and global variability MOSFET parameters have been extracted owing to this generalized analytical mismatch model. Furthermore, the impact of the source-drain series resistance mismatch on the drain current variability has been investigated for 28nm Bulk MOSFETs. A detailed statistical characterization of the drain current local and global variability in sub 15nm Si/SiGe Trigate nanowire pMOSFETs and 14nm Si bulk FinFETs has been conducted. Finally, a complete investigation of the gate and drain current mismatch in advanced FDSOI devices has been performed. Finally, the impact of drain current variability on circuits in Cadence Spectre is presented. An overall summary of this dissertation is presented in Chapter VI, which highlights the key research contributions and future research directions are suggested

La mise à l'échelle de la technologie CMOS classique augmente les performances des circuits numériques grâce à la possibilité d'incorporation de composants de circuit supplémentaires dans la même zone de silicium. La technologie FDSOI 28nm de ST Microélectroniques est une stratégie d'échelle innovante qui maintient une structure de transistor planaire et donc une meilleure performance sans augmentation des coûts de fabrication de puces pour les applications basse tension. Il est important de s'assurer que l'augmentation des fonctionnalités et des performances ne se fasse pas au détriment de la fiabilité réduite, ce qui est assuré en répondant aux exigences des normes internationales ISO26262 pour les applications critiques dans les environnements automobile et industriel. Les entreprises de semi-conducteurs, pour se conformer à ces normes, doivent donc présenter des capacités d'estimation de la fiabilité au stade de la conception du circuit, qui est pour l'instant évaluer qu'après la fabrication d'un circuit numérique. Ce travail se concentre sur le vieillissement des standard cell et des circuits numériques avec le temps sous l'influence du mécanisme de dégradation du NBTI pour une large gamme de variations de processus, de tension et de température (PVT) et la compensation de vieillissement avec l'application de la tension à la face arrière (Body-Bias). L'un des principaux objectifs de cette thèse est la mise en place d'une infrastructure d'analyse de fiabilité composée d'outils logiciels et d'un modèle de vieillissement dans un cadre industriel d'estimation du taux de défaillance des circuits numériques au stade de la conception des circuits développés en technologie ST 28nm FDSOI
Scaling of classical CMOS technology provides an increase in performance of digital circuits owing to the possibility of incorporation of additional circuit components within the same silicon area. 28nm FDSOI technology from ST Microelectronics is an innovative scaling strategy maintaining a planar transistor structure and thus provide better performance with no increase in silicon chip fabrication costs for low power applications. It is important to ensure that the increased functionality and performance is not at the expense of decreased reliability, which can be ensured by meeting the requirements of international standards like ISO26262 for critical applications in the automotive and industrial settings. Semiconductor companies, to conform to these standards, are thus required to exhibit the capabilities for reliability estimation at the design conception stage most of which, currently, is done only after a digital circuit has been taped out. This work concentrates on Aging of standard cells and digital circuits with time under the influence of NBTI degradation mechanism for a wide range of Process, Voltage and Temperature (PVT) variations and aging compensation using backbiasing. One of the principal aims of this thesis is the establishment of a reliability analysis infrastructure consisting of software tools and gate level aging model in an industrial framework for failure rate estimation of digital circuits at the design conception stage for circuits developed using ST 28nm FDSOI technology

HBT-based MMIC performance is very sensitive to the variation of core device characteristics and the reliability issues put the limit on its radio frequency (RF) behaviors. While many researchers have reported the observed stress-induced degradations of GaAs HBT characteristics, there has been little published data on the full understanding of stress impact on the GaAs HBT-based MMICs. If care is not taken to understand this issue, stress-induced degradation paths can lead to built-in circuit failure during regular operations. However, detection of this failure may be difficult due to the circuit complexity and lead to erroneous data or output conditions. Thus, a practical and analytical methodology has been developed to predict the stress impacts on HBT-based MMICs. It provides a quick way and guidance for the RF design engineer to evaluate the circuit performance with reliability considerations. Using the present existing EDA tools (Cadance SpectreRF and Agilent ADS) with the extracted pre- and post-stress transistor models, the electrothermal stress effects on InGaP/GaAs HBT-based RF building blocks including power amplifier (PA), low-noise amplifier (LNA) and oscillator have been systematically evaluated. This provides a potential way for the RF/microwave industry to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of advanced GaAs HBT MMIC technology and researchers have been exploring here for years. The reliability of GaAs HBT technology is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation provide methods and guidance for the RF designers to achieve more reliable RF circuits with advanced GaAs HBT technology in the future.; Recent years have shown real advances of microwave monolithic integrated circuits (MMICs) for millimeter-wave frequency systems, such as wireless communication, advanced imaging, remote sensing and automotive radar systems, as MMICs can provide the size, weight and performance required for these systems. Traditionally, GaAs pseudomorphic high electron mobility transistor (pHEMT) or InP based MMIC technology has dominated in millimeter-wave frequency applications because of their high fsubscript T] and fsubscript max] as well as their superior noise performance. But these technologies are very expensive. Thus, for low cost and high performance applications, InGaP/GaAs heterojunction bipolar transistors (HBTs) are quickly becoming the preferred technology to be used due to their inherently excellent characteristics. These features, together with the need for only one power supply to bias the device, make InGaP/GaAs HBTs very attractive for the design of high performance fully integrated MMICs. With the smaller dimensions for improving speed and functionality of InGaP/GaAs HBTs, which dissipate large amount of power and result in heat flux accumulated in the device junction, technology reliability issues are the first concern for the commercialization. As the thermally triggered instabilities often seen in InGaP/GaAs HBTs, a carefully derived technique to define the stress conditions of accelerated life test has been employed in our study to acquire post-stress device characteristics for the projection of long-term device performance degradation pattern. To identify the possible origins of the post-stress device behaviors observed experimentally, a two dimensional (2-D) TCAD numerical device simulation has been carried out. Using this approach, it is suggested that the acceptor-type trapping states located in the emitter bulk are responsible for the commonly seen post-stress base current instability over the moderate base-emitter voltage region.
ID: 030423028; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 82-88).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science

Les circuits logiques programmables (FPGA) bénéficient des technologies les plus avancés de noeuds CMOS, afin de répondre aux demandes croissantes de haute performance et de faible puissance des circuits intégrés numériques. Cela les rend sensibles aux différents mécanismes de dégradations à l'échelle nanométrique. Dans cette thèse, nous nous concentrons sur le vieillissements des tables de correspondances (LUT) sur FPGA. L'utilisation de la dernière technologie d'échelle réduite et la flexibilité de l'architecture du FPGA, permettent de développer un nouveau banc de test à faible coût pour évaluer la fiabilité en fonction de conditions d'utilisations. Ce banc de test peut-être implanté sur plusieurs véhicules du tests et suivis en temps réel par un logiciel de surveillance développé pendant cette thèse. Nous avons caractérisé la dégradation de temps de propagation de la LUT en fonction du rapport cyclique et la fréquence des vecteurs de stress. Nous avons identifié également que le rapport cyclique affecte fortement le temps en descente et modérément le temps en montée de LUT en raison du mécanisme de vieillissement NBTI, tandis que HCI affecte à la fois les deux temps de propagation. En outre, deux modèles semi-empiriques de la dégradation du temps de propagation de la LUT en raison de NBTI et HCI sont proposés dans ce travail. D'autre part, nous avons analysé l'influence de la tension de seuil et la mobilité du transistor sur la dégradation de temps de propagation de la LUT en utilisant le modèle de simulation du transistor. Enfin, un modèle de dégradation de la LUT prenant en compte l'architecture supposée de la LUT est proposé. Ce travail est idéal pour modéliser la dégradation des FPGA au niveau des portes
Field-Programmable Gate Arrays (FPGAs) benefit from the most advanced CMOS technology nodes, in order to meet the increasing demands of high performance and low power digital integrated cricuits. This makes tem sensible to various aging mechanisms at nanao-scale. In this thesis we focus on aging degradation of the Look-Up Table (LUT) on FPGAs. Benefits from the latest downscaling technology and the flexibility of the FPGAs architecture, allow to develop a new low cost test bench to assess reliabilty depending on the operation condition. This test bench can be implemented on up to 32 FPGAs ans monitored in real time by a supervisory software we developed in this work. We have characterized the delay degradation of LUT depending on the duty cycle and the frequency of stress vectors. We have identified also that the duty cycle affects strongly the fall and moderately the rise delay of LUT due to the NBTI aging mechanisme, while HCI affects both delays. Furthermore, two semiempirical models of the degradation of LUT timing due to NBTI and HCI are proposed in this work. Moreover, we analyzed the influence of threshokd voltage and the mobility of transistor on the timing degradation of LUT using the simulation model of transistor. Finally a model of degradationof LUT taking into account the supposed LUT architecture has been proposed. This work is edeal to model the degradation of FPGA at gate level

La progressivité du claquage des oxydes de grille d'épaisseurs inférieures à 20 nm permet d'envisager une prolongation de la durée de vie des circuits. Cet enjeu majeur de la fiabilité contemporaine requiert des modèles adaptés afin de contrôler la variabilité des paramètres induites par le claquage. Après avoir étudié l'impact d'une fuite de courant sur une couche chargée, nous avons mis au point un modèle bas niveau de simulation par éléments finis, capable de reproduire la dérive des paramètres mesurée sur des dispositifs du nœud 45 nm. Des lois empiriques de ces dérives ont été injectées dans un modèle compact du transistor dégradé, simplifié par nos observations originales de la dépolarisation du canal et de la répartition des courants. Finalement nous avons simulé l'impact du claquage sur le fonctionnement de circuits simples et estimés la dérive de leurs paramètres tels que l'augmentation de la consommation due au claquage.

La conception en vue de la fiabilité (DFR, Design for Reliability) consiste à simuler le vieillissement électrique des composants élémentaires pour évaluer la dégradation d'un circuit complet. C'est dans ce contexte de fiabilité et de simulation de cette dernière, qu'une stratégie de conception en vue de la fiabilité a été développée au cours de ses travaux. Cette stratégie, intégrant une approche « système » de la simulation, s'appuie sur l'ajout de deux étapes intermédiaires dans la phase de conception. La première étape est une étape de construction de modèles comportementaux compacts à l'aide d'une méthodologie basée sur une approche de modélisation multi niveaux (du niveau transistor au niveau circuit) des dégradations d'un circuit. La seconde étape consiste alors l'analyse descendante de la fiabilité de ce circuit, à l'aide de simulations électriques utilisant ses modèles comportementaux dits « dégradables », afin de déterminer les blocs fonctionnels et/ou les composants élémentaires critiques de l'architecture de ce dernier, vis-à-vis d'un mécanisme de défaillance et un profil de mission donnés. Cette analyse descendante permet aussi d'évaluer l'instant de défaillance de ce circuit. Les dispersions statiques, lies au procédé de fabrication utilisé, sur les performances d'un lot de CIs ont aussi été prises en compte afin d'évaluer leur impact sur la dispersion des instants de défaillance des circuits intégrés. Ces méthodes ont été appliquées à deux mécanismes de dégradation : les porteurs chauds et les radiations
Design for reliability (DFR) consists in assessing the impact of electrical ageing of each elementary component, using electrical simulations, on performance degradations of a full device. According to DFR concept and reliability simulation, theses works present a new DFR strategy. This strategy based on the integration of two intermediate phases in the ICs and SoC design flow. The first phase is a bottom-up ageing behavioural modelling phase of a circuit (from transistor level to circuit level). The second phase is a « top-down reliability analyses » phase of this circuit, performing electrical simulations using its ageing behavioural models, in order to determine critical functional blocks and / or elementary components of its architecture according to a failure mechanism and a given mission profile. Theses analyses also allow determining the failure time of this circuit. Statistical dispersions on ICs performances, due to the used manufacturing process, have been taking into account in order to assess their impact on failure time dispersions of a ICs lot. The method has been applied on two degradation mechanisms: hot carriers and radiations

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

Ce travail se place dans le contexte de la conception, la modélisation et la simulation de systèmes hétérogènes contenant a la fois des capteurs, des composants analogiques, des composants numériques et des circuits RF.La seule manière de simuler un système avec une telle complexité avec un temps de simulation raisonnable est de faire une modélisation haut niveau.Cependant, pour que ce modèle haut niveau soit fiable, les modèles des blocs analogiques et RF doivent contenir une description précise des leurs imperfections.Dans ce travail nous proposons une méthode systématique pour la caractérisation et le raffinement des modèles des blocs analogiques et RF.Cette méthode est réalisée dans un environnement C++ base sur: - l'outil de simulation haut niveau SystemC-AMS- l'outil de résolution d'expression symbolique GiNaC- l'outil de synthèse de circuits intégrés analogique CAIRO+/CHAMSPour illustrer la validité de la méthode proposée, nous présenterons le modèle d'un nœud d'un réseau de capteurs sans fil avec une caractérisation automatique de certains blocs analogiques et RF.Les points suivant résument les contributions apportées pour ce travail.- La première implémentation d'un modèle analogique numérique mixte complexe avec le langage SystemC AMS: un nœud de réseau de capteurs sans fil.- L'introduction du raffinement pour une approche générique des modèles au niveau système.- Un outil d'évaluation précise des performances linéaires et non-linéaires des circuit analogiques pour le raffinement des modèles niveau système et l'optimisation de la conception niveau circuit.- Une méthodologie de conception niveau circuit basée sur des outils de dimensionnement et d'évaluation des performances avec précision.- Un environnement de conception multi-niveaux unifiée appliqué aux systèmes mixtes avec une très forte interaction entre la simulation niveau système et la conception optimisée niveau circuit.

L'augmentation de la densité des transistors dans les circuits électroniques conduit à une augmentation de la consommation d'énergie induisant des phénomènes thermiques plus complexes à maitriser. Dans le cas de systèmes embarqués en environnement où la température ambiante varie dans des proportions importantes (automobile par exemple), ces phénomènes peuvent conduire à des problèmes de fiabilité. Parmi les mécanismes de défaillance observés, on peut citer les cycles thermiques (CT) qui induisent des déformations dans les couches métalliques de la puce pouvant conduire à des fissurations. L'objectif de la thèse est de proposer pour des architectures de type multiprocesseur sur puce une technique de réduction des CT subis par les processeurs, et ce en respectant les contraintes temps réel des applications. L'exemple du circuit MPC5517 de Freescale a été considéré. Dans un premier temps un modèle thermique de ce circuit a été élaboré à partir de mesures par une caméra thermique sur ce circuit décapsulé. Un environnement de simulation a été mis en oeuvre pour permettre d'effectuer simultanément des analyses thermiques et d'ordonnancement de tâches et mettre en évidence l'influence de la température sur la puissance dissipée. Une heuristique globale pour réduire à la fois les CT et la température maximale des processeurs a été étudiée. Elle tient compte des variations de la température ambiante et se base sur les techniques DVFS et DPM. Les résultats de simulation avec les algorithmes d'ordonnancement globaux RM, EDF et EDZL et avec différentes charges processeur (sur un circuit type MPC5517 et un UltraSparc T1) illustrent l'efficacité de la technique proposée.

Cette étude constitue une contribution dans un grand projet européen dénommé : 3DICE (3D Integration of Chips using Embedding technologies). La fiabilité mécanique et thermomécanique des composants 3D a été étudiée par des essais normalisés et des simulations numériques. L’essai de chute et le cyclage thermique ont été sélectionnés pour la présente étude. Des analyses de défaillance sont menées pour compléter les approches expérimentales. Les propriétés mécaniques des éléments constituant les composants ont fait l’objet d’une compagne de caractérisation complétée par des recherches bibliographiques. Les simulations numériques, dynamiques transitoires pour l’essai de chute et thermomécanique pour l’essai de cyclage thermique, ont été réalisées pour une estimation numérique de la tenue mécanique des composants. Les modèles numériques sont utilisés pour optimiser le design des composants et prédire les durées de vie en utilisant un modèle de fatigue
This work establishes a contribution in an important European project mentioned 3DICE (3D Integration of Chips using Embedding technologies). The mechanical and thermomechanical reliability of 3D microelectronic components are studied by employing standardized tests and numerical modeling. The board level drop test and thermal cycling reliability tests are selected for this study. Failures analysis has been used to complete the experimental study. The mechanical properties of elements constituting the microelectronic components were characterized using DMA, tensile test and nanoindentation. Bibliographical researches have been done in order to complete the materials properties data. Numerical simulations using submodeling technique were carried out using a transient dynamic model to simulate the drop test and a thermomechanical model for the thermal cycling test. Numerical results were employing in the design optimization of 3D components and the life prediction using a fatigue model

abstract: Negative bias temperature instability (NBTI) is a leading aging mechanism in modern digital and analog circuits. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and Dynamic Voltage Scaling (DVS) in real circuit operation. To overcome these barriers, the modeling effort in this work (1) practically explains the aging statistics due to randomness in number of traps with log(t) model, accurately predicting the mean and variance shift; (2) proposes cycle-to-cycle model (from the first-principle of trapping) to handle aging under multiple supply voltages, predicting the non-monotonic behavior under DVS (3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles, and (4) comprehensively validates the new set of aging models with 65nm statistical silicon data. Compared to previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard-banding during the design stage. With CMOS technology scaling, design for reliability has become an important step in the design cycle, and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI induced delay shifts in logic paths are asymmetric in nature, as opposed to averaging effect due to recovery assumed in traditional aging analysis. Timing violations due to aging, in particular, are very sensitive to the standby operation regime of a digital circuit. In this report, by identifying the critical moments in circuit operation and considering the asymmetric aging effects, timing violations under NBTI effect are correctly predicted. The unique contributions of the simulation flow include: (1) accurate modeling of aging induced delay shift due to threshold voltage (Vth) shift using only the delay dependence on supply voltage from cell library; (2) simulation flow for asymmetric aging analysis is proposed and conducted at critical points in circuit operation; (3) setup and hold timing violations due to NBTI aging in logic and clock buffer are investigated in sequential circuits and (4) proposed framework is tested in VLSI applications such DDR memory circuits. This methodology is comprehensively demonstrated with ISCAS89 benchmark circuits using a 45nm Nangate standard cell library characterized using predictive technology models. Our proposed design margin assessment provides design insights and enables resilient techniques for mitigating digital circuit aging.
Dissertation/Thesis
Ph.D. Electrical Engineering 2012

Indiana University-Purdue University Indianapolis (IUPUI)
Lithium ion (Li-ion) batteries have become integral parts of our lives; they are widely used in applications like handheld consumer products, automotive systems, and power tools among others. To extract maximum output from a Li-ion battery under optimal conditions it is imperative to have access to the state of the battery under every operating condition. Faults occurring in the battery when left unchecked can lead to irreversible, and under extreme conditions, catastrophic damage. In this thesis, an adaptive fault diagnosis technique is developed for Li-ion batteries. For the purpose of fault diagnosis the battery is modeled by using lumped electrical elements under the equivalent circuit paradigm. The model takes into account much of the electro-chemical phenomenon while keeping the computational effort at the minimum. The diagnosis process consists of multiple models representing the various conditions of the battery. A bank of observers is used to estimate the output of each model; the estimated output is compared with the measurement for generating residual signals. These residuals are then used in the multiple model adaptive estimation (MMAE) technique for generating probabilities and for detecting the signature faults. The effectiveness of the fault detection and identification process is also dependent on the model uncertainties caused by the battery modeling process. The diagnosis performance is compared for both the linear and nonlinear battery models. The non-linear battery model better captures the actual system dynamics and results in considerable improvement and hence robust battery fault diagnosis in real time. Furthermore, it is shown that the non-linear battery model enables precise battery condition monitoring in different degrees of over-discharge.

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

Technology has become increasingly more prevalent in all aspects of society since the age of the computer. The United States Military has successfully integrated the powerful processing capabilities of computers to increase the proficiency and lethality of its Soldiers, Sailors, Marines, and Airmen. However, this increased lethality comes at risk due to the inherent vulnerabilities of computer systems to spyware, malware, and counterfeit components. Inspired by the ability of canines to seek out and find electronic devices, this research sought methods to characterize components by their “scent” using precise analytical tools. Using these tools, this thesis sought to develop and utilize non-invasive methods to show proof-of-concept for electronic device classification by volatile compounds unique to different types of components. The findings of this research proved that electronic components that vary by age, origin, type, or manufacturer emit different volatile compounds available for detection using modern two-dimensional gas chromatography and solid-phase microextraction technologies. If developed further, the methods used in this research have the potential for application in the United States Department of Defense to ensure that all electronic components installed in their systems are authentic, come from a trusted source, and can be relied upon in even the most stressful operating conditions.