Дисертації з теми "Circuit Intégrés"
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Archambeau, Éric. "Test fonctionnel des circuits intégrés digitaux." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316164.
Palmier, Luc. "Conception fonctionnelle de circuits intégrés de traitement d'image." Paris 11, 1985. http://www.theses.fr/1985PA112246.
This work is concerned with a functional approach to image processing integrated circuit design. Aiming to adjust dynamically some processing features to enable various enough types of operators and to adapt them to the given data, the chips are supposed to be easily associated using predetermined criteria for slicing and cascading. This, different possibilities of integration and several examples of specialized circuits are analysed. The definition, the effective integration and the test of three elementary image processing functions are described. An attempt of generalization towards the “functional” conception of chips and its future prospects are presented as a conclusion
Chotin, Eric. "Placement automatique de circuits intégrés." Phd thesis, Grenoble INPG, 1992. http://tel.archives-ouvertes.fr/tel-00341773.
Deyine, Amjad. "Contribution au développement de techniques de stimulation laser dynamique pour la localisation de défauts dans les circuits VLSI." Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14252/document.
The principal objective of the project is to investigate laser based techniques for failure analysis of VLSI integrated circuits. The investigations will be performed on the DCGSystems’ Meridian laser scanning microscope coupled with the Credence’s Diamond D10 tester available at CNES. This study was interested more specifically in the improvement of dynamic laser stimulation techniques said DLS like Dynamic Laser Stimulation. DLS techniques consists in modifying the operation of a dynamically failing integrated circuit by photoelectric effect or photothermal effect using a continuous laser beam sweeping the surface of the circuit. A laser beam modulated in the nanosecond range synchronously with the electrical test through a TTL signal can also be advantageously used. Analysis of the electrical parameters response to the laser disturbance leads to an identification of the dynamic failure origin. The optimization of current DLS techniques will increase the failure analyses success rate and bring information hardly accessible by other means, which allows determining the failure root cause. The work performed was the improvement of the DLS process flow by closely integrating the test to monitor any relevant electrical parameters upon DLS. The « Pass-Fail Mapping » technique and the parametric techniques were implemented on the test tools combining the D10 and the Meridian. The synchronization of the test with the laser scan allows establishing methodologies and techniques in order to add timing information to the defect localisation. Indeed, by modulating the laser beam depending on the test pattern sequences, we show our capability to identify precisely which are the vectors responsible for the IC defective behaviour. We are able now to correlate the defective IC functions with the IC structures involved. This technique is known as F-DLS for Full Dynamic Laser Stimulation.In some cases, we know when the failure occurs in the test pattern but we ignore which IC structures are involved. So, we also developed a dynamic current measurement under laser stimulation technique. This technique proved to be efficient to obtain information about the internal IC behaviour. As an example, for the latched component which signals are synchronised just before the outputs, it is hard to measure shift in the signal propagation. Nevertheless, the IC internal activities can be characterized by monitoring on a scope the current variations under laser stimulation when the IC is activated. The information about the shift in the signal propagation could be extracted then by observing of the IC internal activities.Finally, these DLS techniques proved their efficiency for device qualification for reliability issues. Their accuracy allows early detection of operational parameter tiny variations. This is used to highlight electrical parameter margin evolutions during accelerated aging process. DLS techniques demonstrate their potential to deal with the IC robustness evolution facing external perturbation for reliability purposes.The techniques and methodologies developed during this work have been successfully integrated in the IC analysis and characterisation process in the laboratory. We exposed these techniques but the main case studies remain confidential
Morin, Vincent. "Sybilin : un logiciel de conception symbolique pour circuits intégrés micro-ondes." Brest, 1988. http://www.theses.fr/1988BRES2025.
Aboudou, Abderraouf. "Application de la photodétection dans les circuits intégrés III-V pour le contrôle optique d'un circuit logique." Lille 1, 1991. http://www.theses.fr/1991LIL10053.
Cette étude préliminaire nous a permis de réaliser un deuxième diviseur où cette fois-ci l'emplacement et la structure géométrique du photoconducteur ont été optimisés, de sorte que la division par deux a pu être effectuée jusqu'à 1. 2GHz avec une puissance optique modulée minimale de l'ordre de 500 nW seulement. Dans le quatrième chapitre, nous remplaçons dans le circuit intégré, le photoconducteur par un MSM GaAlAs/GaAs/GaAs de structure géométrique semblable. Ici aussi la division par deux est effectuée jusqu'à 1. 2 GHz avec le même seuil de puissance optique. L'un des enseignements que l'on peut tirer de cette étude est le comportement quasi-identique des deux photodétecteurs en hautes fréquences. Dans le cinquième chapitre, nous démontrons expérimentalement, après l'avoir valider théoriquement, la faisabilité d'un MSM GaAs intégré monolithiquement à un guide optique diélectrique Si3N4/SiO2. Les résultats obtenus sont très encourageants et laissent envisager la possibilité de réaliser un circuit numérique commandé optiquement et dont la distribution du signal optique s'effectue à l'aide de guides diélectriques
Angui, Ettiboua. "Conception d'un circuit intégré VLSI turbo-décodeur." Brest, 1994. http://www.theses.fr/1994BRES2005.
Tran, Duc Anh. "Architecture hybride tolérante aux fautes pour l'amélioration de la robustesse des circuits et systèmes intégrés numériques." Thesis, Montpellier 2, 2012. http://www.theses.fr/2012MON20132/document.
Evolution of CMOS technology consists in continuous downscaling of transistor features sizes, which allows the production of smaller and cheaper integrated circuits with higher performance and lower power consumption. However, each new CMOS technology node is facing reliability problems due to increasing rate of faults and errors. Consequently, fault-tolerance techniques, which employ redundant resources to guarantee correct operations of digital circuits and systems despite the presence of faults, have become essential in digital design. This thesis studies a novel hybrid fault-tolerant architecture for robustness improvement of digital circuits and systems. It targets all kinds of error in combinational part of logic circuits, i.e. hard, SETs and timing errors. Combining information redundancy for error detection, timing redundancy for transient error correction and hardware redundancy for permanent error corrections, the proposed architecture allows significant power consumption saving, while having similar silicon area compared to existing solutions. Furthermore, it can also be used in other applications, such as dealing with aging phenomenon, tolerating faults in pipeline architecture, and being combined with advanced SEUs protection scheme for sequential parts of logic circuits
Delorme, Nicolas. "Influence des interconnexions sur les performances des circuits intégrés silicium en technologie largement submicronique." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0173.
Fontaine, Jonathan. "Optimisation de l’insertion de contre-mesures pour la sécurité des circuits intégrés." Electronic Thesis or Diss., Sorbonne université, 2024. http://www.theses.fr/2024SORUS058.
Over the last 75 years, the electronics industry has experienced a spectacular evolution, moving from manual design to an automated industry. This industrialization has led to increased complexity in circuits, requiring specialization in tasks during the design of electronic circuits. Various companies around the world have emerged to perform these tasks, with varying levels of trust assigned. From a designer's perspective, these actors pose several threats, such as the insertion of malicious functionalities, intellectual property theft, or circuit counterfeiting. These threats impact the economy of the semiconductor industry, amounting to billions of dollars in losses annually.One way to combat these threats is to lock the circuit with a key, preventing it from functioning correctly if the right key is not present. Logic locking is a method that involves logically locking a circuit using key gates and the corresponding digital key. Several implementations of logic locking have been developed. In these works, we focus on Strong Logic Locking. It locks the circuit by connecting XOR/XNOR gates to the digital key, inserted in circuit signals. Each insertion position has a different impact on security, which is the possibility of recovering the digital key. However, adding logic gates in a circuit increases power consumption, the circuit's area, and decreases performance. Strong logic locking aims to maximize the security of the lock by identifying positions that enhance security, regardless of the resulting impact.In this thesis, we seek to optimize security while considering the impact on circuit performance. We propose a new approach to solving strong logic locking. We start by formulating our security problem based on mathematical models that include security for optimally inserting key gates in the circuit. This formulation calculates the cliques of a subgraph representing the insertion positions. We establish a branch and bound solving algorithm for our problem and evaluate it. We then present a second mathematical models representing the impact on the delay from inserting key gates in the circuit. Finaly, we propose strategies to optimize security while limiting the impact on circuit performance. Our tools are integrated into the design flow, allowing us to validate them with numerical results obtained on circuits used by the electronic community
Vuillod, Patrick. "Optimisation et décomposition technologique de circuits intégrés à faible consommation." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0096.
Bouchaala, Afef. "Méthode de modélisation prédictive de boîtiers des circuits intégrés en vue d’anticiper avant design l’immunité au bruit du circuit." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S128.
Modern electronic systems require a high-level of integrations. As a result, some phenomena which are known as ElectroMagnetic Compatibility (EMC) issues are arising, and they are the major causes of system redesign. This main objective of this work is to develop a predictive methodology for systems immunity. To do so, different fields have been investigated: first, we have developed a predictive method for package parasites called “MCTL Matrix Method” which is based on a virtual package prototyping and Multiconductor transmission lines. Then we have proposed a new methodology for system immunity at the earliest design stages
Larguech, Syhem. "Test indirect des circuits analogiques et RF : implémentation sûre et efficace." Thesis, Montpellier, 2015. http://www.theses.fr/2015MONTS185/document.
Being able to check whether an IC is functional or not after the manufacturing process is very difficult. Particularly for analog and Radio Frequency (RF) circuits, test equipment and procedures required have a major impact on the circuits cost. An interesting approach to reduce the impact of the test cost is to measure parameters requiring low cost test resources and correlate these measurements, called indirect measurements, with the targeted specifications. This is known as indirect test technique because there is no direct measurement for these specifications, which requires so expensive test equipment and an important testing time, but these specifications are estimated w.r.t "low-cost measurements". While this approach seems attractive, it is only viable if we are able to establish a sufficient accuracy for the performance estimation and if this estimation remains stable and independent from the circuits sets under test.The main goal of this thesis is to implement a robust and effective indirect test strategy for a given application and to improve test decisions based on data analysis.To be able to build this strategy, we have brought various contributions. Initially, we have defined new metric developed in this thesis to assess the reliability of the estimated performances. Secondly, we have analyzed and defined a strategy for the construction of an optimal model. This latter includes a data preprocessing followed by a comparative analysis of different methods of indirect measurement selection. Then, we have proposed a strategy for a confidant exploration of the indirect measurement space in order to build several best models that can be used later to solve trust and optimization issues. Comparative studies were performed on 2 experimental data sets by using both of the conventional and the developed metrics to evaluate the robustness of each solution in an objective way.Finally, we have developed a comprehensive strategy based on an efficient implementation of the redundancy techniques w.r.t to the build models. This strategy has greatly improved the robustness and the effectiveness of the decision plan based on the obtained measurements. This strategy is adaptable to any context in terms of compromise between the test cost, the confidence level and the expected precision
Kervella, Gaël. "Circuits intégrés photoniques sur InP pour la génération de signaux hyperfréquences." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S008/document.
This thesis deals with the microwave photonics context. We have implemented various opto- electronic solutions in order to realize a monolithically integrated microwave synthesizer which has a low noise and a wide tunability until millimeter-wave frequencies. The synthesizer is based on the integration of two InP DFB lasers, an optical coupler and a fast photodiode. In addition, an electro-optic modulator is also implemented on the chip in order to transmit data on the generated carrier. The performances obtained in terms of tunability and wireless data transmission proved consistent with the objectives. Thus, a tuning range of 0-110 GHz and a short distance wireless data transmission rate of 1 Gbit /s have been demonstrated, establishing our system to the state of the art for this type of fully integrated component. Phase noise and linewidth performances have however been disappointing. To solve this problem affecting the data rate we have investigated two ways of stabilizing the carrier frequency. The first, based on an electronic feedback loop (OPLL) has yet proved unsuccessful but allowed us to further explore the related issues. However, the second solution, based on a new system of optical cross injection and stabilization to an external electronic oscillator has filled our wishes. Indeed, the stabilization of the carrier frequency by this technique has demonstrated linewidth less than 30 Hz and a reduced phase noise to -90 dBc / Hz at 10 kHz for a given carrier at 90 GHz. Next to the first generation components, a second generation was developed to improve the intrinsic performances of the chip by remedying the limitations previously observed. Thus, a new cavity configuration was designed including longer lasers and high reflectivity integrated mirrors made by materials deep etching. Moreover, optimization of the photodiode structure was carried out to further improve the bandwidth. Such a source allows to consider the generation and modulation of low phase noise and widely tunable microwave signals on monolithically integrated components matching the compactness, reproducibility and high speed performances required by the telecom, defense and space industries
Rivière, Antoine. "Protection des circuits intégrés CMOS profondément submicroniques contre les décharges électrostatiques." Montpellier 2, 2008. http://www.theses.fr/2008MON20242.
The first part of this thesis recalls the involvement of electrostatic discharge within submicron CMOS circuits, ways of assessing the protection of a circuit and the different protection strategies commonly used to protect a circuit against ESD events and also presents the results obtained silicon structures test using the parasitic bipolar as a protective element (ggNMOS, LVTpnp). Since then, our work has focused on design and development of protections central conduction using MOS devices to evacuate ESD current. We bring a significant improvement in particular with untimely triggers caused by the phenomena of noise encountered on power supplies. A robust design of the circuit and a trigger approach to overcome the adverse effects encountered with very slow supply ramp-up. Thereafter we propose a method for the design of a central dynamic protection associated with the submission of a comprehensive flood automated characterization in the context of the use of a comprehensive strategy for the protection of a circuit. The last part of this work proposes two new approaches regarding detection function which could make ramps power up very fast without causing the outbreak of protection that can lead to a static critical current consumption
Cioranesco, Jean-Michel. "Nouvelles Contre-Mesures pour la Protection de Circuits Intégrés." Thesis, Paris 1, 2014. http://www.theses.fr/2014PA010022/document.
Embedded security applications are diverse and at the center of all personal embedded applications. They introduced an obvious need for data confidentiality and security in general. Invasive attacks on hardware have always been part of the industrial scene. The aim of this thesis is to propose new solutions in order to protect embedded circuits against some physical attacks described above. ln a first part of the manuscript, we detail the techniques used to achieve side-channel, invasive attacks and reverse engineering. I could implement several of these attacks during my thesis research, they will be detailed extensively. ln the second part we propose different hardware countermeasures against side-channel attacks. The third part is dedicated to protection strategies against invasive attacks using active shielding and we conclude this work by proposing an innovative cryptographic shield which is faulty and dpa resistant
Koompai, Natnicha. "Mid-IR SiGe photonics circuit for sensing application." Electronic Thesis or Diss., université Paris-Saclay, 2024. http://www.theses.fr/2024UPAST027.
There is currently a growing interest in the developement of mid-infrared photonics integrated circuits driven by their unique features and potential to identify chemical and biological substances. Commercially available mid-infrared systems currently rely on bulky and expensive equipment. Substantial efforts are devoted to downsizing mid-infrared systems to chip-scale dimensions. The use of silicon photonics for the demonstration of mid-IR integrated circuits offers great advantages in terms of compactness, high-performance, and cost-effective sensing systems. A key point for development of real application is to be able to couple the mid-infrared light source with the photonics circuits in a compact way. In this context, the main objective of this thesis has been focused on two different challenges: (i) progress towards the integration of QCL with SiGe photonics circuits in the mid-IR range (ii) contribution to the development of SiGe photonics devices by the development of high-quality factor resonators operating around 8 µm wavelength. This work has opened the route for future development of on-chip integrated photonics circuit in the mid-IR
Krischer, Stefan. "Méthodes de vérification de circuits digitaux." Vandoeuvre-les-Nancy, INPL, 1994. http://www.theses.fr/1994INPL043N.
Fkih, Yassine. "Conception en vue du Test des Circuits Intégrés 3D à base de TSVs." Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20063/document.
For several years, the complexity of integrated circuits continues to increase, from SOC (System On Chip) to SIP (System In Package) , and more recently 3D SICs (Stacked Integrated Circuits) based on TSVs (Through Silicon Vias ) that vertically interconnect stacked circuits in a 3D system. 3D SICs have many advantages in terms of small form factor, high performances and low power consumption but have many challenges regarding their test which is a necessary step before the commissioning of these complex systems. In this thesis we focus on defining the test infrastructure that will detect any occurring defects during the manufacturing process of TSVs or the different sacked chips in the system. We propose a BIST (Built In Self Test) solution for TSVs testing before stacking, this solution is based on the use of ring oscillators which their oscillation frequencies depend on the electrical characteristics of the TSVs. The proposed test solution not only allows the detection of faulty TSVs but also gives information about the number of defective TSVs and their location. On the other hand, we propose a 3D DFT (Design For Test) architecture based on the new proposed test standard IEEE P1687. The proposed test architecture provides test access to the components of the 3D system before and after stacking. Also it allows the re-use of recycled test data developed and applied before stacking to each die in the mid-bond and post-bond test levels. This work lead to the opening of a new problem related to the test scheduling under constraints such as: power consumption, temperature.Keywords: test, 3D circuits, TSV, BIST, ring oscillators, 3D DFT architecture, IEEE P1687, pre-bond test, post-bond test
Benhaddou, Mohamed. "Définition d'une méthodologie de conception de circuits intégrés numériques indépendante de la technologie : application à la conception d'un processeur flou." Vandoeuvre-les-Nancy, INPL, 1995. http://www.theses.fr/1995INPL067N.
Kara-Terki, Chafik. "Une méthode de mise au point des circuits intégrés." Paris 6, 1986. http://www.theses.fr/1986PA066113.
Tang, Qingshan. "Méthodologie de génération de plateforme de prototypage à base de multi-fpga." Electronic Thesis or Diss., Paris 6, 2015. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2015PA066016.pdf.
Multi-FPGA based prototyping is no longer optional for hardware/software integration. We can classify multi-FPGA prototyping platforms in three categories: off-the-shelf, custom and cabling. The cabling platform is semi off-the-shelf and semi custom. Nevertheless, crafting a custom and a cabling platform is today a manual process, which is time-consuming. The performance and the cost of the platform lie on the FPGA expertise and SoC DUT knowledge of the engineers. Compared to OTS platforms, the added value, in terms of performance, of cabling or custom platforms can be heavily impaired by an inefficient board design. Moreover, FPGA I/Os are becoming a scarce resource, worsening the inter-FPGA bandwidth generation after generation. Therefore, it becomes more and more difficult to prototype an SoC/ASIC design at proper performance. The contributions of the manuscript are: (1). An automatic implementation flow for an OTS platform is proposed. (2). An automatic design flow for creating a custom platform is proposed, thus increasing the productivity, enabling the board exploration, and optimizing cost and performance. (3). The cabling platform is proposed where one board is composed of one FPGA and several connectors, with an algorithm to automatically find a solution for the cable distribution. (4). Thanks to the developed automatic tools, the three different multi-FPGA platforms are compared. The custom platform always achieves better performance and lower deployment cost, but still with 3-5 months in time of availability. If the performance or the deployment cost are not rigorous constraints, the cabling platform offers an attractive alternative compared to others
Kenmei, Nganguem II Louis Bertrand. "Mise en oeuvre d'une méthode d'éléments finis à éléments d'arêtes en deux et trois dimensions : applications aux lignes de topologies complexes pour circuits intégrés monolithiques micro-ondes et aux interconnexions sur circuit silicium." Lille 1, 1999. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/1999/50376-1999-215.pdf.
Christoforou, Georges. "Conception de préamplificateurs intégrés pour fonctionnement à basse température et sous rayonnement intense." Université Joseph Fourier (Grenoble), 1998. http://www.theses.fr/1998GRE10031.
Tintori, Olivier. "Modélisation et simulation des transistors Double-Grille : du dispositif au circuit intégré." Aix-Marseille 1, 2006. http://www.theses.fr/2006AIX11051.
Schoellkopf, Jean-Pierre. "Siliciel : contributions à l'architecture des circuits intégrés et à la compilation du silicium." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00315393.
Tobich, Karim. "Évaluation de l’efficacité des techniques d’injection de fautes, au sein de microcontrôleurs, par agression électromagnétique." Thesis, Montpellier 2, 2013. http://www.theses.fr/2013MON20017.
Nowadays, LASER remains the tool the most effective and most used to inject faults within the modern secure microcontrollers. Among its main advantages we can quote its strong spatial and temporal resolutions. These advantages are however accessible only to the price of consequent investments in time and money with a cost oscillating between two and four hundreds of thousand euro according to the quality of the LASER. Besides these financial aspects, the publication by scientists, as well as the integration by the manufacturers of smart cards, effective countermeasures, as light detectors, incited to the development of alternative faults injection techniques with moderate costs. Among these alternative techniques, we find the electromagnetic fault injection techniques which allow perturbing the behavior of circuits. It is in this context that this thesis presents the main effects of this kind of fault injection by proceeding to a first decomposition in front side and back side, then in one second bound to the shape of the disturbing signal (harmonic or pulsed) used. So, we highlight coupling effects with metals lines but also a Forward effect on the target circuit
Pan, Fanny. "Design of a pacemaker for animal biomedical research on pulmonary arterial hypertension." Electronic Thesis or Diss., université Paris-Saclay, 2024. http://www.theses.fr/2024UPAST029.
Pulmonary arterial hypertension (PAH) is a rare, progressive cardiovascular disease that affects an average of 15 to 50 individuals per 1 million worldwide. It is characterized by an abnormal rise in pressure in the pulmonary arteries, which can lead to severe right heart failure, and Biomedical research on cardiovascular diseases heavily relies on the use of animal models, particularly rats, which allow for the study of a pathology over their entire lifespan, with a large sample population. Heart rate is strongly implicated in the onset and progression of many pathologies, making it a very interesting therapeutic target. In the pursuit of exploring its impact on the progression of PAH, the objective of this work is to develop a programmable pacemaker that can be implanted in small animals.Pacemakers are implanted medical devices delivering electrical impulses (stimulation) to the heart to trigger its contraction. In this thesis, we focused on the design of the fundamental part of a pacemaker: pacing. Existing literature on pacemakers tends to be limited and safeguarded, particularly regarding stimulation circuits. Hence, our work had two main objectives: to test and validate in vivo a suitable pacing waveform, and to design a circuit for generating it that is potentially implantable, i.e. in an integrated technology and with a very low power consumption.In vivo experiments conducted using an FPGA prototype on rats at the Marie Lannelongue Hospital validated not only the shape of the stimulating waveform but also the electrical and temporal orders of magnitude required for efficient and safe animal stimulation. These results allowed us to set the specifications for designing an integrated pulse generator circuit, employing a methodology centered around the design of ultra-low power elements. The circuit and simulations were implemented using XFAB XH018 0.18 µm technology.The proposed architecture is based on an H-bridge structure and, with the appropriate control set, can generate a biphasic stimulation at a programmable frequency. It also comprises two voltage multipliers controlled by an oscillator in the kHz range and a relaxation oscillator in the ten Hz range. In order to minimize the total power consumption of the circuit, this second oscillator was designed following a state-of-the-art study of ultra-low power techniques (e.g., Stacking, Reverse Body Biasing, Dynamic Leakage Suppression Logic - DLS), which led to the ad hoc design of DLS logic gates. This novel technique, reserved for low frequency operations (<100 Hz), consists of adding, to a standard CMOS gate, a header NMOS connected to Vdd and a footer PMOS connected to ground, with their gate looped on the output node, driving the transistors in a 'super-cut-off' state, thus drastically reducing current leakage. The entire stimulation circuit consumes 112 µW, of which 100 µW is consumed directly by the H-bridge for the stimulation of the heart, which requires two pulses of at least 30 µA per wave period, as established by the in vivo tests. The oscillator in the kHz range with its reshaping and one of the multipliers consumes 9.9 µW. Finally, thanks to the ultra-low power approach adopted in this design, the relaxation oscillator and control synthesis assembly consume only 1.8 µW, i.e. 1.6 % of the stimulation circuit's total consumption.Therefore, the proposed circuit generates a biphasic impulse at frequencies ranging between 6.8 and 10.1 Hz, translating to 400 and 600 bpm, meeting the specifications for small animal stimulation within the scope of studying PAH
Vayssade, Thibault. "Une approche digitale pour le test faible coût de circuits intégrés RF : application à un transceiver ZigBee." Thesis, Montpellier, 2020. http://www.theses.fr/2020MONTS065.
This thesis focuses on the reduction of testing costs for RF integrated circuits. The original approach that is investigated relies on the use of a standard digital ATE to perform an under-sampled acquisition of the RF signal to be analyzed. The basic idea is to use the comparator present in a digital tester channel to convert the RF signal into a binary sequence. During this conversion, the information carried by the RF signal (amplitude, frequency, phase ...) is transformed into a timing information contained in the binary vector captured by the ATE. The objective is then to develop dedicated processing algorithms able to retrieve the essential RF signal characteristics from the analysis of the binary vector. The major benefit of this solution is that it eliminates the need of expensive RF test resources traditionally required. In addition, since digital channels are generally available in large numbers on a standard ATE, this approach also provides the ability to implement multi-site tests to further reduce testing costs. In this thesis, the proposed approach is implemented for ZigBee Transceiver from NXP Semiconductors operating at 2.4 GHz and intended for the growing market of Internet of Things (IoT). The under-sampling conditions allowing to preserve the information contained in the RF signal while respecting the test equipment constraints are defined and dedicated algorithms are developed to implement the various tests specified by IEEE Std 802.15.4 ™ (power test, spectral mask test, EVM measurements). The proposed solution is first evaluated in simulation within the Matlab environment. A laboratory test bench is then developed to carry out an initial validation. Finally, measurements performed with an ATE on several hundreds of circuits in an industrial environment fully validate the proposed solution
Choudens, Philippe de. "Test intégré de processeur facilement testable." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00319265.
Sanseau, Pierre. "Etude de polymères thermostables pour l'isolation des interconnexions dans les circuits intégrés." Grenoble 1, 1988. http://www.theses.fr/1988GRE10021.
Josse, Stève. "Transportabilité de fonctions analogiques en technologies CMOS submicroniques : application : contrôle du retard des fronts d'horloges d'un imageur CCD." Toulouse, INPT, 2003. http://www.theses.fr/2003INPT029H.
Santos, Filipe Vinci dos. "Techniques de conception pour le durcissement des circuits intégrés face aux rayonnements." Grenoble 1, 1998. http://www.theses.fr/1998GRE10208.
Geffroy, Vincent Rémy. "Conception de circuits intégrés radiofréquences sur technologie CMOS pour des applications sans fil grand public : application aux mélangeurs pour DECT." Paris, ENST, 2002. http://www.theses.fr/2002ENST0028.
Baschiera, Daniel. "Modélisation de pannes et méthodes de test de circuits intégrés CMOS." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320020.
Aparicio, Marina. "Modélisation et Simulation du phénomène d'IR-Drop dans les circuits intégrés." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2013. http://tel.archives-ouvertes.fr/tel-00943295.
Rivière, Antoine. "Protection des Circuits Intégrés CMOS Profondément Submicroniques contre les Décharges Electrostatiques." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2008. http://tel.archives-ouvertes.fr/tel-00341887.
Desèvedavy, Jennifer. "Conception de circuits intégrés radiofréquences reconfigurables en technologie FD-SOI pour application IoT." Thesis, Bordeaux, 2018. http://www.theses.fr/2018BORD0177/document.
Communicating objects are inviting themselves into daily life leading to digitization of the physical world. This explosion of multimedia wireless applications for consumer electronics makes the power consumption a key metric in the design of multi-mode wireless portable devices. Conventional transceivers have fixed performances and are designed to meet high performances in all wireless link conditions. However, most of the time, the channel of communication is not at worst case and these transceivers are therefore over specified. Being aware of the channel link conditions would allow such devices to adapt themselves and to reduce significantly their power consumption. Therefore, the challenge is to propose a QoS (Quality of Service) in terms of communication range, response time as instance, equivalent to industrial modules with a reduced overall power consumption.To address this purpose, this thesis proposes a design strategy for the implementation of adaptive radio-frequency receiver (Rx) modules. Hence the Rx front end achieves the correct QoS for various scenarii of communications with a minimum of power consumption.As a proof of concept, the adaptive approach is demonstrated with the design of a tunable LNA (Low Noise Amplifier). As the first element of the receiver chain, the LNA limits the receiver in terms of sensitivity and is therefore a good candidate to perform reconfiguration. The body biasing of the FD-SOI (Fully Depleted Silicon-On-Insulator) technology is first exploited to reduce the power consumption of a circuit and then as an opportunity to perform circuit tunability
Le, Pallec Michel. "Technologie de photorécepteurs intégrés sur InP." Grenoble INPG, 1997. http://www.theses.fr/1997INPG0144.
Pagano, Philippe. "Conception d'un circuit intégré spécifique pour la résolution de l'équation de poisson à 3 dimensions." Ecully, Ecole centrale de Lyon, 1990. http://www.theses.fr/1990ECDL0024.
Diaz, Nava Mario. "Proposition d'une méthodologie de conception de circuits intégrés de communication : réalisation d'un communicateur pour le réseau local FIP." Phd thesis, Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320454.
Gonnard, Olivier. "Efficacité d'isolation dans les circuits intégrés de puissance isolés par jonction." Phd thesis, Université Paul Sabatier - Toulouse III, 2001. http://tel.archives-ouvertes.fr/tel-00515821.
Moignard, Renaud. "Les composants à cristal liquide ferroélectrique sur circuit intégré : application à la commutation optique en espace libre." Brest, 1997. http://www.theses.fr/1997BRES2010.
Delamotte, Pascal. "Conception et réalisation d'un circuit integré de filtrage." Paris 11, 1985. http://www.theses.fr/1985PA112297.
Meysenc, Luc. "Étude des micro-échangeurs intégrés pour le refroidissement des semi-conducteurs de puissance." Grenoble INPG, 1998. http://www.theses.fr/1998INPG0022.
The aim of this work is to study the cooling of power semiconductors by the use of integrated micro heat exchangers. The heatsink is not placed under the component case but is directly integrated under the silicon chip. Thus, in a first time, electrical, thermal and technological characteristics of power components are renûnded. Two cooling principles hâve been retained : single phase forced convection and two-phase forced convection. Single phase forced convection is studied in the second chapter. The most adéquate corrélations for the calculation of the heat transfer coefficient are extracted from a bibliography review. Then, a conception methodology is established to optimise the heatsink sizes in order to minimise its thermal résistance and the pumping energy. Finally, the validity of the study is checked with measurements realised on single chip prototypes. A similar way is employed to study two-phase forced convection. Two-phase heat transfer, pressure drop and critical heat flux are obtained from a bibliographical review. From thèse instructions, a conception methodology is established, methodology which is also checked by measurements realised on prototypes
Emzivat, Delphine. "Etude et conception d'un circuit à optiques et traitements intégrés pour la vision en contrôle qualité." Lorient, 2000. http://www.theses.fr/2000LORIS008.
Libéros, Véronique. "Etablissement automatique de schémas équivalents pour des dispositifs de puissance intégrés." Toulouse, INSA, 1989. http://www.theses.fr/1989ISAT0035.
Malinge, Pierre. "Etude et modélisation d'un point mémoire eDRAM sans capacité, et conception de circuit mémoire haute densité." Lyon, INSA, 2005. http://theses.insa-lyon.fr/publication/2005ISAL0099/these.pdf.
Today, Systems on Chip are always a fast growing market. They embed more and more complex functions that require increasing memory capacity. The standard eDRAM memory cell, composed of one access transistor and a storage capacitor, is the mostly used solution for SoC that need both high performance logic, and large memory capacity. But manufacturers face a tremendous challenge to shrink its area below 90nm technology node. New dielectrics are necessary for capacitor and access transistor leakage becomes problematic. Then a new cell concept, using capacitor-less DRAM memory cell, was proposed to replace standard eDRAM. The analysis and the integration of this memory point in high-density memory circuit are the topics of this thesis. The new memory effect principle is to store an electrical charge in the floating body of a transistor. This new concept presents a process low cost and does not seem having scale reduction limitations. Electrical analysis of this memory cell enabled the use of new operating conditions that allow integration in matrix organization of the memory point. New circuits architectures have been proposed, they enable denser circuits than traditionale DRAM. The concept presented here could become the eDRAM memory solution for next technologies
Cozzi, Maxime. "Infrared Imaging for Integrated Circuit Trust and Hardware Security." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS046.
The generalization of integrated circuits and more generally electronics to everyday life systems (military, finance, health, etc) rises the question about their security. Today, the integrity of such circuits relies on a large panel of known attacks for which countermeasures have been developed. Hence, the search of new vulnerabilities represents one of the largest contribution to hardware security. The always rising complexity of dies leads to larger silicon surfaces.Circuit imaging is therefore a popular step among the hardware security community in order to identify regions of interest within the die. In this objective, the work presented here proposes new methodologies for infrared circuit imaging. In particular, it is demonstrated that statistical measurement analysis can be performed for automated localization of active areas in an integrated circuit.Also, a new methodology allowing efficient statistical infrared image comparison is proposed. Finally, all results are acquired using a cost efficient infrared measurement platform that allows the investigation of weak electrical source, detecting power consumption as low as 200 µW
Boyer, Jean-Marc. "Prévision du comportement à long terme des circuits intégrés CMOS irradiés." Toulouse, ENSAE, 1996. http://www.theses.fr/1996ESAE0013.