Статті в журналах: "Buffering Architecture"

1

Mulder, H., and M. J. Flynn. "Processor architecture and data buffering." IEEE Transactions on Computers 41, no. 10 (1992): 1211–22. http://dx.doi.org/10.1109/12.166600.

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2

Taleb, Tarik, Nei Kato, and Yoshiaki Nemoto. "Neighbors-buffering-based video-on-demand architecture." Signal Processing: Image Communication 18, no. 7 (August 2003): 515–26. http://dx.doi.org/10.1016/s0923-5965(03)00039-0.

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3

Mauceri, Daniela, Anna M. Hagenston, Kathrin Schramm, Ursula Weiss, and Hilmar Bading. "Nuclear Calcium Buffering Capacity Shapes Neuronal Architecture." Journal of Biological Chemistry 290, no. 38 (July 31, 2015): 23039–49. http://dx.doi.org/10.1074/jbc.m115.654962.

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4

Guild, K. M., and M. J. O'Mahony. "Routing and buffering architecture in all-optical switching node." Electronics Letters 35, no. 2 (1999): 161. http://dx.doi.org/10.1049/el:19990129.

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5

Wang, Ru-yan, Jie Zhang, Fang Guo, and Ke-ping Long. "An effective buffering architecture for optical packet switching networks." Photonic Network Communications 16, no. 3 (June 27, 2008): 239–43. http://dx.doi.org/10.1007/s11107-008-0135-0.

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6

Tan, Xu, Xiao-Wei Shen, Xiao-Chun Ye, Da Wang, Dong-Rui Fan, Lunkai Zhang, Wen-Ming Li, Zhi-Min Zhang, and Zhi-Min Tang. "A Non-Stop Double Buffering Mechanism for Dataflow Architecture." Journal of Computer Science and Technology 33, no. 1 (January 2018): 145–57. http://dx.doi.org/10.1007/s11390-017-1747-6.

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7

Kim, Joongheon, and Aziz Mohaisen. "Distributed and reliable decision-making for cloud-enabled mobile service platforms." International Journal of Distributed Sensor Networks 13, no. 8 (August 2017): 155014771772650. http://dx.doi.org/10.1177/1550147717726509.

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This article proposes distributed decision-making algorithms for reliable operation in cloud-assisted social network architectures. The considered architecture consists of three types of units: a cloud platform, access units, and mobile units (MUs). For reliable operations in such architectures, two distributed decision-making algorithms are proposed: (1) decision-making for fair connection at MUs and (2) decision-making for dynamic buffering at access units. For the decision-making in fair connection at MUs, the deployed MUs find their new access units to be associated with them when currently associated access units are out of order. The proposed algorithm works considering buffer backlog in access units, achievable rates with access units, and the number of associated MUs in access units. For the decision-making in dynamic buffering at access units, the buffers in access units are dynamically controlled for time-average expected power consumption minimization (i.e. energy-efficiency maximization) subjected to buffer stability.

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8

Leff, A., J. L. Wolf, and P. S. Yu. "Efficient LRU-based buffering in a LAN remote caching architecture." IEEE Transactions on Parallel and Distributed Systems 7, no. 2 (1996): 191–206. http://dx.doi.org/10.1109/71.485508.

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9

Brustoloni, José Carlos, and Peter Steenkiste. "Effects of buffering semantics on I/O performance." ACM SIGOPS Operating Systems Review 30, SI (October 28, 1996): 277–91. http://dx.doi.org/10.1145/248155.238787.

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10

Maniotis, P., D. Fitsios, G. T. Kanellos, and N. Pleros. "Optical Buffering for Chip Multiprocessors: A 16GHz Optical Cache Memory Architecture." Journal of Lightwave Technology 31, no. 24 (December 2013): 4175–91. http://dx.doi.org/10.1109/jlt.2013.2290741.

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11

De Rossi, Giacomo, and Riccardo Muradore. "A Bilateral Teleoperation Architecture using Smith Predictor and Adaptive Network Buffering." IFAC-PapersOnLine 50, no. 1 (July 2017): 11421–26. http://dx.doi.org/10.1016/j.ifacol.2017.08.1806.

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12

Chen, Kai-Sheng, and Wien Hong. "Multi-Level Buffering Services Based on Optical Packet Encoding of Composite Maximal-Length Sequences in a GMPLS Network." Applied Sciences 10, no. 3 (January 21, 2020): 730. http://dx.doi.org/10.3390/app10030730.

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Generalized multi-protocol label-switching (GMPLS) provides packet-switching with multiple speeds and quality-of-services (QoSs). Packet buffering in GMPLS reduces packet loss by resolving the conflicts between packets requesting for a common channel. Presently, due to the diversity of multimedia applications, enabling multiple services in networks has become necessary. In this paper, a family of codes known as composite maximal-length sequence (CMLS) codes is introduced into an optical buffering scheme based on code-switching. A given number of available CMLS codes is divided into several code subsets. The buffer selects an unused CMLS code from a code subset and assigns it to the incoming packet. When all codes in a specific subset have been distributed to the queued packets, a free CMLS code in another subset is chosen for the new arrival. To achieve multi-level buffering services, the partition scenario with a lower subset number but with a higher number of codes in an individual subset is used as a code-assigning method for buffering high-QoS users. A two-level buffering system is demonstrated by examining the QoS of each class in terms of packet-dropping probability (PDP). The results show that different levels of PDPs can be effectively supported by a common buffer architecture.

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13

Yang, Shuna, and Norvald Stol. "A novel delay line buffering architecture for asynchronous optical packet switched networks." International Journal of Information, Communication Technology and Applications 1, no. 1 (March 9, 2015): 69–82. http://dx.doi.org/10.17972/ajicta20151112.

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Optical buffering is one major challenge in realizing all-optical packet switching. In this paper we focus on a delay-line buffer architecture, named a Multiple-Input Single-Output (MISO) optical buffer, which is realized by cascaded fiber delay lines (FDLs). This architecture reduces the physical size of a buffer by up to an order of magnitude or more by allowing reuse of its delay line elements. We consider the MISO buffers in a network scenario where the incoming packets are asynchronous and of fixed length. A novel Markov model is developed to analyze the performance of our buffering scheme, in terms of packet loss ratio, average packet delay and the output link utilization. Both simulation and analytical results show that the length value of basic FDL element will significantly affect the performance of this buffer. This paper gives clear guidelines for designing optimal basic FDL lengths under different network scenarios. It is noticeable that this optimal length value is independent of the buffer sizes for specific traffic load and pattern.

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14

Li, Lin, Jitender S. Deogun, and Stephen D. Scott. "Performance analysis of optical packet switches with a hybrid buffering architecture [Invited]." Journal of Optical Networking 3, no. 6 (2004): 433. http://dx.doi.org/10.1364/jon.3.000433.

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15

Reza, Ahmed Galib, and Hyotaek Lim. "Hybrid buffering architecture for packet contention resolution of an optical packet switch." Optik 122, no. 7 (April 2011): 591–93. http://dx.doi.org/10.1016/j.ijleo.2010.04.017.

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16

Kong, B. Y. "Multi‐touch detector architecture based on efficient buffering of intensities and labels." Electronics Letters 56, no. 14 (July 2020): 699–701. http://dx.doi.org/10.1049/el.2020.0884.

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17

George, Binto, and Jayant R. Haritsa. "Secure buffering in firm real-time database systems." VLDB Journal The International Journal on Very Large Data Bases 8, no. 3-4 (February 1, 2000): 178–98. http://dx.doi.org/10.1007/s007780050003.

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18

Desnoyers, Mathieu, and Michel R. Dagenais. "Lockless multi-core high-throughput buffering scheme for kernel tracing." ACM SIGOPS Operating Systems Review 46, no. 3 (December 18, 2012): 65–81. http://dx.doi.org/10.1145/2421648.2421659.

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19

Ortiz, Jorge, and David Andrews. "A Streaming High-Throughput Linear Sorter System with Contention Buffering." International Journal of Reconfigurable Computing 2011 (2011): 1–12. http://dx.doi.org/10.1155/2011/963539.

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Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks, systolic sorters, and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel to increase overall throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Contention for available linear sorters in the system is solved through the use of buffers that accumulate conflicting requests, dispatching them in bulk to reduce latency penalties. Implementation of this system into a field programmable gate array (FPGA) results in a speedup of 68 compared to a MicroBlaze processor running quicksort.

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20

Wang, Jia, Lin Liu, Yuchen Zhou, and Shiyan Hu. "Buffering Carbon Nanotube Interconnects Considering Inductive Effects." Journal of Circuits, Systems and Computers 25, no. 08 (May 17, 2016): 1650093. http://dx.doi.org/10.1142/s0218126616500936.

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While copper interconnect scaling is approaching its fundamental physical limit, increasing wire resistivity and delay have greatly limited the circuit miniaturization. The emerging carbon nanotube (CNT) interconnects, especially single-walled CNTs (SWCNTs) bundle interconnects, have become a promising replacement material. Nevertheless, physical design optimization techniques are still needed to allow them achieving the desired performances. While the preliminary conference version of this work [L. Liu, Y. Zhou and S. Hu, Proc. IEEE Computer Society Annual Symp. on VLSI (ISVLSI), 2014] designs the first timing driven buffer insertion technique for SWCNT interconnects, it only considers resistive and capacitive effects but not inductive effects. Although inductance could be negligible for prevailing CNT-based circuit designs, it becomes important when designing ultra-high performance chips in the future. Thus, this paper considers buffering inductive bundled SWCNTs interconnects through developing a dynamic programming algorithm for buffer insertion using the RLC tree delay model. Our experiments demonstrate that bundled SWCNTs interconnect-based buffering can effectively reduce the delay by over [Formula: see text] when inductive effects are considered. With the same timing constraint, bundled SWCNTs interconnect-based buffering can save over 20% buffer area compared to copper interconnect based buffering, while still running about [Formula: see text] faster.

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21

BYNA, SURENDRA, KIRK W. CAMERON, and XIAN-HE SUN. "ISOLATING COSTS IN SHARED MEMORY COMMUNICATION BUFFERING." Parallel Processing Letters 15, no. 04 (December 2005): 357–65. http://dx.doi.org/10.1142/s0129626405002271.

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Communication in parallel applications is a combination of data transfers internally at a source or destination and across the network. Previous research focused on quantifying network transfer costs has indirectly resulted in reduced overall communication cost. Optimized data transfer from source memory to the network interface has received less attention. In shared memory systems, such memory-to-memory transfers dominate communication cost. In distributed memory systems, memory-to-network interface transfers grow in significance as processor and network speeds increase at faster rates than memory latency speeds. Our objective is to minimize the cost of internal data transfers. The following examples illustrating the impact of memory transfers on communication, we present a methodology for classifying the effects of data size and data distribution on hardware, middleware, and application software performance. This cost is quantified using hardware counter event measurements on the SGI Origin 2000. For the SGI O2K, we empirically identify the cost caused by just copying data from one buffer to another and the middleware overhead. We use MPICH in our experiments, but our techniques are generally applicable to any communication implementation.

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22

White, Marcus, and Stephen Glackin. "Broadband‐acre City: ‘No Traffic Problem, No Buffering’." Architectural Design 93, no. 1 (January 2023): 30–37. http://dx.doi.org/10.1002/ad.2891.

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23

Zhang, Tianpei, and Sachin S. Sapatnekar. "Buffering global interconnects in structured ASIC design." Integration 41, no. 2 (February 2008): 171–82. http://dx.doi.org/10.1016/j.vlsi.2007.04.002.

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24

Nenninger, Philipp, Oliver Rooks, and Uwe Kiencke. "IMPROVED SYSTEM ARCHITECTURE FOR SAFETY-RELEVANT SYSTEMS USING DYNAMIC DISTRIBUTION AND STATE BUFFERING." IFAC Proceedings Volumes 38, no. 1 (2005): 176–81. http://dx.doi.org/10.3182/20050703-6-cz-1902.01917.

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25

Sundan, Bose, and Kannan Arputharaj. "ADAPTIVE MULTIPATH MULTIMEDIA STREAMING ARCHITECTURE FOR MOBILE NETWORKS WITH PROACTIVE BUFFERING USING MOBILE PROXIES." Journal of Computing and Information Technology 15, no. 3 (2007): 215. http://dx.doi.org/10.2498/cit.1000884.

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26

Huang, Sheng-Min, and Li-Pin Chang. "Exploiting Page Correlations for Write Buffering in Page-Mapping Multichannel SSDs." ACM Transactions on Embedded Computing Systems 15, no. 1 (February 20, 2016): 1–25. http://dx.doi.org/10.1145/2815622.

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27

Geldenhuys, R., Y. Liu, M. T. Hill, G. D. Khoe, F. W. Leuschner, and H. J. S. Dorren. "Architectures and Buffering for All-Optical Packet-Switched Cross-Connects." Photonic Network Communications 11, no. 1 (January 2006): 65–75. http://dx.doi.org/10.1007/s11107-006-5324-0.

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28

Qadri, Muhammad Yasir, Nadia N. Qadri, Martin Fleury, and Klaus D. McDonald-Maier. "Software-Controlled Instruction Prefetch Buffering for Low-End Processors." Journal of Circuits, Systems and Computers 24, no. 10 (October 25, 2015): 1550161. http://dx.doi.org/10.1142/s0218126615501613.

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This paper proposes a method of buffering instructions by software-based prefetching. The method allows low-end processors to improve their instruction throughput with a minimum of additional logic and power consumption. Low-end embedded processors do not employ caches for mainly two reasons. The first reason is that the overhead of cache implementation in terms of energy and area is considerable. The second reason is that, because a cache's performance primarily depends on the number of hits, an increasing number of misses could cause a processor to remain in stall mode for a longer duration. As a result, a cache may become more of a liability than an advantage. In contrast, the benchmarked results for the proposed software-based prefetch buffering without a cache show a 5–10% improvement in execution time. They also show a 4% or more reduction in the energy-delay-square-product (ED2P) with a maximum reduction of 40%. The results additionally demonstrate that the performance and efficiency of the proposed architecture scales with the number of multicycle instructions. The benchmarked routines tested to arrive at these results are widely deployed components of embedded applications.

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29

Fang, J. P., Y. S. Tong, and S. J. Chen. "Simultaneous routing and buffering in SOC floorplan design." IEE Proceedings - Computers and Digital Techniques 151, no. 1 (2004): 17. http://dx.doi.org/10.1049/ip-cdt:20040072.

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30

Lee, J. H., C. Weems, and S. D. Kim. "Selective block buffering TLB system for embedded processors." IEE Proceedings - Computers and Digital Techniques 152, no. 4 (2005): 507. http://dx.doi.org/10.1049/ip-cdt:20045025.

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31

Chi Ta Wu, Ang-Chih Hsieh, and Ting Ting Hwang. "Instruction buffering for nested loops in low-power design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14, no. 7 (July 2006): 780–84. http://dx.doi.org/10.1109/tvlsi.2006.878348.

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32

Min, P. S., M. V. Hegde, A. Chandra, and A. Maunder. "Analysis of banyan-based copy networks with internal buffering." Journal of High Speed Networks 5, no. 3 (1996): 259–75. http://dx.doi.org/10.3233/jhs-1996-5303.

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33

Gou, Xiantai. "An Adaptive Jitter Buffering Algorithm for Voice over IP Networks." Journal of Computer Research and Development 42, no. 12 (2005): 2149. http://dx.doi.org/10.1360/crad20051218.

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34

Ho, Dennis. "Climatic responsive atrium design in Europe." Architectural Research Quarterly 1, no. 3 (1996): 64–75. http://dx.doi.org/10.1017/s135913550000292x.

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This paper considers the relationship between atrium design and different climatic conditions in Europe. The analyses may be used to inform design proposals for buildings which seek to optimise the thermal buffering characteristics of atria. Particular attention is given to certain parameters witl a potential to form climatic responsive and energy efficient atrium buildings.

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35

Bregni, Stefano, Angelo Caruso, and Achille Pattavina. "Buffering-deflection tradeoffs in optical burst switching." Photonic Network Communications 20, no. 2 (August 4, 2010): 193–200. http://dx.doi.org/10.1007/s11107-010-0259-x.

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36

Yiannopoulos, K., S. Sygletos, M. Spyropoulou, E. Varvarigos, and I. Tomkos. "Optical buffering up to 160 Gb/s employing a quantum dot semiconductor optical amplifier-based architecture." IET Optoelectronics 5, no. 1 (February 1, 2011): 50–56. http://dx.doi.org/10.1049/iet-opt.2009.0057.

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37

Wang, Diane R., Rongkui Han, Edward J. Wolfrum, and Susan R. McCouch. "The buffering capacity of stems: genetic architecture of nonstructural carbohydrates in cultivated Asian rice,Oryza sativa." New Phytologist 215, no. 2 (May 30, 2017): 658–71. http://dx.doi.org/10.1111/nph.14614.

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38

Sarper, Hasan, and Isik Aybay. "Improving VoD Performance with LAN Client Back-End Buffering." IEEE Multimedia 14, no. 1 (2007): 48–60. http://dx.doi.org/10.1109/mmul.2007.13.

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39

Lee, J., F. Peper, S. Adachi, and K. Morita. "Universal delay-insensitive circuits with bidirectional and buffering lines." IEEE Transactions on Computers 53, no. 8 (August 2004): 1034–46. http://dx.doi.org/10.1109/tc.2004.51.

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40

Myllymaki, Jussi, and Miron Livny. "Efficient buffering for concurrent disk and tape I/O." Performance Evaluation 27-28 (October 1996): 453–71. http://dx.doi.org/10.1016/s0166-5316(96)90040-1.

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41

Garzarán, María Jesús, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, and Josep Torrellas. "Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors." ACM Transactions on Architecture and Code Optimization 2, no. 3 (September 2005): 247–79. http://dx.doi.org/10.1145/1089008.1089010.

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42

Yoon, Hanbin, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, and Onur Mutlu. "Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories." ACM Transactions on Architecture and Code Optimization 11, no. 4 (January 9, 2015): 1–25. http://dx.doi.org/10.1145/2669365.

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43

PETRELLIS, N., G. ADAM, and D. VENTZAS. "MONOTONIC ERROR ELIMINATION IN SUBRANGE A/D CONVERTERS." Journal of Circuits, Systems and Computers 22, no. 01 (January 2013): 1250073. http://dx.doi.org/10.1142/s0218126612500739.

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Monotonic errors cause severe errors and are inherent in several A/D Converter (ADC) architectures. Moreover, several error correcting and ADC output processing methods require a monotonic behavior for a successful operation. Based on the features of asynchronous ADCs, an architecture for the elimination of monotonic errors is presented. This monotonic error correcting module is connected at the output of an ADC and does not require any modification in its internal circuits. It controls an output buffering stage that discards output codes with monotonic errors and this correcting procedure is triggered by changes in specific output bits of the ADC. Simulation results show an improvement by 8 dB or 25% maximum, in the signal-to-noise and distortion ratio (SNDR) of an 8-bit ADC if this monotonic error elimination method is used alone and a further improvement by 1–5 dB if it is combined with a post processing method developed by the authors. Similar improvement can also be achieved in several other architectures like Subrange or Folding ADCs that operate in relatively high oversampling ratio and suffer from monotonic errors with specific features.

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44

DOROSHENKO, A. E. "ON ASYNCHRONOUS AVOIDANCE OF DEADLOCKS IN PARALLEL PROGRAMS." Parallel Processing Letters 02, no. 02n03 (September 1992): 291–97. http://dx.doi.org/10.1142/s012962649200043x.

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A number of approaches to asynchronous communication in parallel programs based on both data dependence analysis and buffering techniques are briefly described. A criterion for automatically resolving some classes of deadlocks by means of asynchronous data exchanges is established and examples showing the comparative power of the approaches for deadlock avoidance are presented.

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45

Wodnicki, Robert, Haochen Kang, Di Li, Douglas N. Stephens, Hayong Jung, Yizhe Sun, Ruimin Chen, et al. "Highly Integrated Multiplexing and Buffering Electronics for Large Aperture Ultrasonic Arrays." BME Frontiers 2022 (June 30, 2022): 1–22. http://dx.doi.org/10.34133/2022/9870386.

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Large aperture ultrasonic arrays can be implemented by tiling together multiple pretested modules of high-density acoustic arrays with closely integrated multiplexing and buffering electronics to form a larger aperture with high yield. These modular arrays can be used to implement large 1.75D array apertures capable of focusing in elevation for uniform slice thickness along the axial direction which can improve image contrast. An important goal for large array tiling is obtaining high yield and sensitivity while reducing extraneous image artifacts. We have been developing tileable acoustic-electric modules for the implementation of large array apertures utilizing Application Specific Integrated Circuits (ASICs) implemented using 0.35 μm high voltage (50 V) CMOS. Multiple generations of ASICs have been designed and tested. The ASICs were integrated with high-density transducer arrays for acoustic testing and imaging. The modules were further interfaced to a Verasonics Vantage imaging system and were used to image industry standard ultrasound phantoms. The first-generation modules comprise ASICs with both multiplexing and buffering electronics on-chip and have demonstrated a switching artifact which was visible in the images. A second-generation ASIC design incorporates low switching injection circuits which effectively mitigate the artifacts observed with the first-generation devices. Here, we present the architecture of the two ASIC designs and module types as well imaging results that demonstrate reduction in switching artifacts for the second-generation devices.

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46

Loghi, M., P. Azzoni, and M. Poncino. "Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 5 (May 2009): 728–32. http://dx.doi.org/10.1109/tvlsi.2009.2016720.

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47

TOMITA, Ryuta, Katsuo INOUE, and Syuta KAWAMATA. "HEAD IMPACT BUFFERING EFFECT OF DIRECT PASTED WOODEN FLOORINGS BY HUMAN FALLING IN THE HOUSE." AIJ Journal of Technology and Design 13, no. 26 (2007): 591–96. http://dx.doi.org/10.3130/aijt.13.591.

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48

Davaasambuu, Battulga. "Handover with Buffering for Distributed Mobility Management in Software Defined Mobile Networks." Australian Journal of Telecommunications and the Digital Economy 6, no. 1 (March 30, 2018): 26–40. http://dx.doi.org/10.18080/ajtde.v6n1.137.

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The rapidly-growing number of mobile subscribers has led to the creation of a large number of signalling messages. This makes it difficult to efficiently handle the mobility of subscribers in mobile cellular networks. The long-term evolution (LTE) architecture provides software-defined networking (SDN) to meet the requirements of 5G networks and to forward massive mobile data traffic. The SDN solution proposes separation of the control and data planes of a network. Centralized mobility management (CMM) is widely used in current mobile network technologies, such as 4G networks. One of the problems related to CMM is a single point of failure. To solve the problems of CMM and in order to provide for efficient mobility management, IETF has developed a solution called distributed mobility management (DMM), in which mobility is handled via the nearest mobility anchor. In this paper, we propose a DMM solution with handover operations for SDN-enabled mobile networks. The advantage of the proposed solution is that intra and inter handover procedures are defined with the data buffering and forwarding processes between base stations and mobility anchors. We adopt a simulation model to evaluate and compare the proposed solution with the existing solution in terms of handover latency, packet loss and handover failures.

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Davaasambuu, Battulga. "Handover with Buffering for Distributed Mobility Management in Software Defined Mobile Networks." Journal of Telecommunications and the Digital Economy 6, no. 1 (March 30, 2018): 26–40. http://dx.doi.org/10.18080/jtde.v6n1.137.

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The rapidly-growing number of mobile subscribers has led to the creation of a large number of signalling messages. This makes it difficult to efficiently handle the mobility of subscribers in mobile cellular networks. The long-term evolution (LTE) architecture provides software-defined networking (SDN) to meet the requirements of 5G networks and to forward massive mobile data traffic. The SDN solution proposes separation of the control and data planes of a network. Centralized mobility management (CMM) is widely used in current mobile network technologies, such as 4G networks. One of the problems related to CMM is a single point of failure. To solve the problems of CMM and in order to provide for efficient mobility management, IETF has developed a solution called distributed mobility management (DMM), in which mobility is handled via the nearest mobility anchor. In this paper, we propose a DMM solution with handover operations for SDN-enabled mobile networks. The advantage of the proposed solution is that intra and inter handover procedures are defined with the data buffering and forwarding processes between base stations and mobility anchors. We adopt a simulation model to evaluate and compare the proposed solution with the existing solution in terms of handover latency, packet loss and handover failures.

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50

Ma, X., J. Lee, and M. Winslett. "High-level buffering for hiding periodic output cost in scientific simulations." IEEE Transactions on Parallel and Distributed Systems 17, no. 3 (March 2006): 193–204. http://dx.doi.org/10.1109/tpds.2006.36.

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