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1
Pisár, Peter. "Metody návrhu aktivních kmitočtových filtrů na základě pasivního RLC prototypu." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218107.
Повний текст джерелаАнотація:
The aim of this diploma thesis is to design active frequency filters based on passive RLC prototype. Three methods of the design of active filters and active functional blocks of electronic circuits working in current or mixed mode are used to this purpose. These blocks allow to process electrical signals with frequencies up to low tens of megahertz. In addition they feature for instance with high slew rate and low supply voltage power. Active high-pass and low-pass 2nd order filters are designed using simulation of inductor by active subcircuit method. Grounded and subsequently floating synthetic inductor is made with the current conveyors in the first case and with the current operational amplifiers with single input and differential output in the second case. This method advantage is relatively simple design and disadvantage is great quantity of active functional blocks. Active filters based on passive frequency ladder 3rd order filter while only one floating inductor is connected, are designed with circuit equation method. In the first design differential input / output current followers are used and in the second case current-differencing buffered amplifiers are used. This method benefits by smaller active blocks number and disadvantage is more complex design of the active filter. Active filter based on passive prototype of low-pass 3rd order filter with two floating inductors is designed with Bruton transformation method. Final active filter uses current operational amplifiers with single input and differential output which together with other passive elements replace frequency depending negative resistor, which arise after previous Bruton transform. This method usage is advantageous if the design consists of larger quantity of inductors and less number of capacitors. High-pass 2nd order filter is simulated by tolerance and parametrical analyses. Physical realisation utilising current feedback operational amplifier which substitute commercially hardly accessible current conveyors is subsequently made. Measurements of constructed active filter show that additional modifications, which allow better amplitude frequency characteristics conformity, are necessary.
2
Foxcroft, Michael. "Design and analysis of a 3.3V, unity-gain, CMOS buffer amplifier." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0003/MQ42617.pdf.
Повний текст джерела
3
Naini, Srikar Reddy. "PING-PONG AUTO-ZERO AMPLIFIER WITH RAIL-TO-RAIL OUTPUT BUFFER." University of Akron / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=akron1537224512595497.
Повний текст джерела
4
Johanssson, Stefan. "Precision Amplifier for Applications in Electrical Metrology." Thesis, Linköping University, Linköping University, Electronics System, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16896.
Повний текст джерелаАнотація:
This master's thesis addresses two main problems. The first is how to suppress a common mode voltage that appears for current shunts, and the second how to let a voltage divider work under an unloaded condition to prevent loading errors and thereby a decreased measurement accuracy. Both these problems occurs during calibration of power meters, and verification of current shunts and voltage dividers. To the first problem three alternative solutions are presented; prototype a proposed instrumentation amplifier circuit, evaluate the commercial available instrumentation amplifier Analog Devices AD8130 or let the voltage measuring device suppress the common mode voltage. It is up to the researchers at SP to choose a solution. To address the second problem, a prototype buffer amplifier is built and verified. Measurements of the buffer amplifier show that it performs very well. At 100 kHz, the amplitude error is less than 20 μV/V, the phase error is less than 20 μrad, and the input Rp is over 10 MΩ. This is performance in line with the required to make accurate measurements possible at 100 kHz and over that.
5
Dinc, Huseyin. "A high-speed two-step analog-to-digital converter with an open-loop residue amplifier." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39572.
Повний текст джерелаАнотація:
It is well known that feedback is a very valuable tool for analog designers to improve linearity, and desensitize various parameters affected by process, temperature and supply variations. However, using strong global feedback limits the operation speed of analog circuits due to stability requirements. The circuits and techniques explored in this research avoid the usage of strong-global-feedback circuits to achieve high conversion rates in a two-stage analog-to-digital converter (ADC). A two-step, 9-bit, complementary-metal-oxide-semiconductor (CMOS) ADC utilizing an open-loop residue-amplifier is demonstrated. A background-calibration technique was proposed to generate the reference voltage to be used in the second stage of the ADC. This technique alleviates the gain variation in the residue amplifier, and allows an open-loop residue amplifier topology. Even though the proposed calibration idea can be extended to multistage topologies, this design was limited to two stages. Further, the ADC exploits a high-performance double-switching frontend sample-and-hold amplifier (SHA). The proposed double-switching SHA architecture results in exceptional hold-mode isolation. Therefore, the SHA maintains the desired linearity performance over the entire Nyquist bandwidth.
6
Johansson, Jimmy. "Power-Efficient Settling Time Reduction Techniques for a Folded-Cascode Amplifier in 1.8 V, 0.18 um CMOS." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-138446.
Повний текст джерелаАнотація:
Testability is crucial in today’s complex industrial system on chips (SoCs), where sensitive on-chip analog voltages need to be measured. In such cases, an operational amplifier (opamp) is required to sufficiently buffer the signals before they can drive the chip pad and probe parasitics. A single-stage opamp offers an attractive choice since it is power efficient and eliminates the need for frequency compensation. However, it has to satisfy demanding specifications on its stability, input common mode range, output swing, settling time, closed-loop gain and offset voltage. In this work, the settling time performance of a conventional folded-cascode (FC) opamp is substantially improved. Settling time of an opamp consists of two major components, namely the slewing period and the linear settling period. In order to reduce the settling time significantly without incurring excessive area and power penalty, a prudent circuit implementation that minimizes both these constituents is essential. In this work, three different slew rate enhancement (SRE) circuits have been evaluated through extensive simulations. The SRE candidate providing robust slew rate improvement was combined with a current recycling folded cascode structure, resulting in lower slewing and linear settling time periods. Exhaustive simulations on a FC cascode amplifier with complementary inputs illustrate the effectiveness of these techniques in settling time reduction over all envisaged operating conditions.
7
Rashid, S. M. Shahriar. "Design and Heterogeneous Integration of Single and Dual Band Pulse Modulated Class E RF Power Amplifiers." The Ohio State University, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=osu1543505207173487.
Повний текст джерела
8
Thomas, Dylan Buxton. "Silicon-germanium devices and circuits for high temperature applications." Thesis, Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/33949.
Повний текст джерелаАнотація:
Using bandgap engineering, silicon-germanium (SiGe) BiCMOS technology effectively combines III-V transistor performance with the cost and integration advantages associated with CMOS manufacturing. The suitability of SiGe technology for cryogenic and radiation-intense environments is well known, yet SiGe has been generally overlooked for applications involving extreme high temperature operation. This work is an investigation into the potential capabilities of SiGe technology for operation up to 300°C, including the development of packaging and testing procedures to enable the necessary measurements. At the device level, SiGe heterojunction bipolar transistors (HBTs), field-effect transistors (FETs), and resistors are verified to maintain acceptable functionality across the temperature range, laying the foundation for high temperature circuit design. This work also includes the characterization of existing bandgap references circuits, redesign for high temperature operation, validation, and further optimization recommendations. In addition, the performance of temperature sensor, operational amplifier, and output buffer circuits under extreme high temperature conditions is presented. To the author's knowledge, this work represents the first demonstration of functional circuits from a SiGe technology platform in ambient temperatures up to 300°C; furthermore, the optimized bandgap reference presented in this work is believed to show the best performance recorded across a 500°C range in a bulk-silicon technology platform.
9
KAUR, ARSHDEEP. "CURRENT DIFFERENCING DIFFERENTIAL OUTPUT BUFFERED AMPLIFIER (CDDOBA) AND ITS APPLICCTIONS IN SIGNAL PROCESSING." Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/15508.
Повний текст джерелаАнотація:
In the present dissertation implementation of new active building block Current differencing differential output buffer amplifier (CDDOBA) using IC AD844 has been presented. CDDOBA is a new active building block with two input p and n terminal and two output, +w and -w terminal. CDDOBA can be well thought-out as a collection of inverting and non inverting current mode and inverting and non inverting voltage mode unity-gain cells. Recent advancements in current mode signal processing and advantages of current mode signal processing over voltage mode are briefly described in the second chapter. In this dissertation detailed description of the architecture of CDDOBA and PSPICE simulation of CDDOBA realized with IC AD844 is presented. General first order filters, voltage mode amplifier and differentiator and integrator circuits have been presented as application examples in order to demonstrate the performance of the CDDOBA. The PSPICE simulation results for frequency response are incorporated to verify the theory. A new Biquad filter, employing one CDDOBA as active element and four resistors and four capacitors is proposed.
10
Yu, Jingjing. "Electromagnetic Interference (EMI) Resisting Analog Integrated Circuit Design Tutorial." Thesis, 2012. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11687.
Повний текст джерелаАнотація:
This work introduces fundamental knowledge of EMI, and presents three basic features correlated to EMI susceptibility: nonlinear distortion, asymmetric slew rate (SR) and parasitic capacitance. Different existing EMI-resisting techniques are analyzed and compared to each other in terms of EMI-Induced input offset voltage and other important specifications such as current consumption.
In this work, EMI-robust analog circuits are proposed, of which the architecture is based on source-buffered differential pair in the previous publications. The EMI performance of the proposed topologies has been verified within a test IC which was fabricated in NCSU 0.5um CMOS technology. Experimental results are presented when an EMI disturbance signal of 400mV and 800mV amplitude was injected at the input terminals, and compared with a conventional and an existing topology. The tested maximal EMI-induced input offset voltage corresponds to -222mV for the new structure, which is compared to -712mV for the conventional one and -368mV for the one using existing source-buffered technique in literature. Furthermore the overall performances of the circuits such as current consumption or input referred noise are also provided with the corresponding simulation results.
11
Tung-Hsuan, Hsu. "Low-Offset Buffer Amplifier for AMLCD Applications." 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0005-0208200613152700.
Повний текст джерела
12
Hsu, Tung-Hsuan, and 徐同璇. "Low-Offset Buffer Amplifier for AMLCD Applications." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/29646527442999726882.
Повний текст джерелаАнотація:
碩士國立中興大學
電機工程學系所
94
The driving circuits of thin-film transistor-liquid crystal displays (TFT-LCDs) for LCD-TV and large-size LCD applications were studied. In the first part, a high slew rate and low offset voltage buffer for TFT-LCD source driver was proposed. For LCD-TV and multimedia applications, TFT-LCD panels become larger and usually have heavy loads in scan/data lines on the array. In order to enhance driving capability of the buffer, two comparators which sense the rising and falling edges of the input waveform were used to turn on the auxiliary driving transistors to enhance charging/discharging of the output load. When the buffer is at steady-state, it consumes no extra power. On the other hand, it needs a low offset voltage to reach the high color depth. The replica-gain circuit could reduce the offset voltage and minimize affection of the mismatch transistors. The offset voltage of the novel buffer amplifier I was reduced to 4.99 mV. In the second part, based on the buffer amplifier I, the buffer amplifier II with the improved offset voltage and output swing were proposed. The active load was adds in the replica-gain stage which could effectively reduce the offset voltage. In this part, two type buffers were designed and simulated. Type A is with the pure offset cancellation in the circuit. Type B is with the offset cancellation and slew rate enhancement functions. The output swing of the buffer amplifier II is from 0.0 to 4.9 V. The offset voltage of the type A and type B can be reduced and controlled within 0.07 mV and 0.19 mV, respectively. Therefore, the proposed high slew rate and low offset voltage buffer has a potential to be applied to the source driver for LCD-TVs and large-size TFT-LCD monitors with high color depth and high resolution.
13
Liu, Cheng-Chieh, and 劉政杰. "Low-Offset Buffer Amplifier for FPD Applications." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/51592442790739998472.
Повний текст джерела
14
Hsieh, Chia-Yu, and 謝家瑜. "Design of 60-GHz Buffer Amplifier and Low Phase Variation Variable Gain Amplifier." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/76843822133276427501.
Повний текст джерелаАнотація:
碩士臺灣大學
電信工程學研究所
98
According to the progress of communication techniques and process technologies, wireless communication and high data-rate transmissions become the trend of developments. Recently, 60 GHz becomes a more important developed frequency band, since it is an unlicensed band for application of WPAN, which can provide the secure and efficient short-distant transmission. On the other hand, in process technologies, because of the advantages of high integration potential, low cost and low power in CMOS, it gradually replaces other process to become a major process to realize analog circuits. In this thesis, two amplifiers, which are buffer amplifier and variable gain amplifier (VGA), are applied in 60 GHz and realized by CMOS technology The 60 GHz buffer amplifier, which can amplify signal from prior stage to input of front-end power amplifier and guarantee the maximum output power can be delivered without saturation at prior stages, is discussed in first part. This amplifier is implemented by 65-nm CMOS process, and matched by TFMS lines. With reasonable power consumption, the amplifier achieves high gain and high output power with broadband characteristics of both small-signal and large-signal due to broadband matching technique. This buffer amplifier can achieve maximum linear-gain of 23.7 dB with 3-dB bandwidth of 14 GHz with maximum saturated output power of 10.3 dBm and maximum peak PAE of 16%. Therefore, it also can be applied as a medium power amplifier. In the second part, the 60 GHz VGA, which can be applied in receiver phase array systems, is designed and fabricated. With current-steering topology to realize variable gain, this VGA is implemented by 90-nm CMOS process, and matched TFMS lines. In addition to the characteristics of high linear-gain with good flatness and large gain variation range, the technique to compensate insertion phase is implemented in this VGA. As a result, the insertion phase variation is lower than 6.6° versus gain tuning. Low phase variation VGA can be applied in phase array systems to reduce the complexity of control systems while can enhance the quality of modulated signals in vector sum modulators.
15
Liao, Chun-Yu, and 廖駿宇. "A Buffer Amplifier for Active Probes of Oscilloscope." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/31653560859042267252.
Повний текст джерелаАнотація:
碩士國立臺灣大學
電子工程學研究所
104
As the extremely rapid development of electronic industry, the demand for measurement equipment and it’s related commercial value obviously increase year by year. However, most measurement equipment in the market is made by foreign manufacturers, such as Agilent and Tektronix Technology. In order to enhance the competitiveness of domestic measurement instruments industries, we must develop our own technologies and system in this field. Above all, the two crucial specifications which impact the price and margin of digital oscilloscope are bandwidth and sampling rate. In this thesis, the advantages and disadvantages are analyzed between different probes. Also, a prototype of 10X active probe is proposed. There are two parts in the prototype of active probe, attenuation circuit and buffer amplifier. Using the architecture of super source follower and complementary source follower, the buffer amplifier is demonstrated to achieve wideband and high input voltage range. In the second work, an offset voltage calibration circuit is used to reduce the offset voltage in output at the same time. All of chip designed in this thesis are implemented in 0.18 m 1P6M CMOS process.The measured -3dB bandwidth can achieve 2.7 GHz and the input voltage range from -1 V to 6 V in the first work. The chip size is 261 um x 279 um. In the second work, the measurement results show that the active probe system bandwidth achieve 1.7 GHz, and the input voltage range from 0.5 V to 5 V. The chip size is 570 um x 370 um.
16
Huang, Sheng-Hong, and 黃聖紘. "High Performance Buffer Amplifiers for AMLCD Applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/30760732876102042991.
Повний текст джерелаАнотація:
碩士國立中興大學
電機工程學系
92
This thesis focuses on the design of the output buffer for the TFT-LCD source driver circuit that is applied to the large-size panel. The design goals are high-speed, high driving capability, high precise and low-power consumption. Therefore, an improved output buffer used in the type of UXGA is designed. In the circuit, the operation of the pixel on TFT is simulated by using a loading capacitance at the output and the model of the TSMC 0.35um 2P4M CMOS technology. The driver circuit is simulated by the HSPICE program to get the electric characteristics. The operation frequency of the circuit is 100KHz and the full swing on the output voltage is achieved. In addition, to reduce the difference between the practical and ideal values due to the mismatch effects of the circuit and devices, nulling-input part is included in this circuit. Thus, the error voltage is less than 1mV by using this circuit. Finally, owing to the increase of the size and the resolution of the TFT, it would increase the parasitic resistance and capacitance on the data line and shorten the one-row-line time. Therefore, we need to compensate the problem of the RC delay effect and shorten the settling time by adding a pre-emphasis voltage on the voltage of the video signal line.
17
Shiau, Jyh-Woei, and 蕭志偉. "The Design and Realization of CMOS Buffer Amplifier Circuits." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/46463125266036918503.
Повний текст джерелаАнотація:
碩士國立臺灣大學
電機工程學系
85
The main function of the CMOS buffer amplifier is to drive a load made up of either a small resistor or a large capacitor or both, and it can still maintain the perfect performance of an amplifier in such situations. In this thesis, two kinds of output stage structure of the buffer amplifier, which contain source follower and common source push-pull type circuit will be discussed. The buffer amplifier which utilizes common source push-pull type circuit as its output stage has been finished IC verifying and testing.
18
Rangan, Giri N. K. "High speed buffers for op-amp characterization." Thesis, 1993. http://hdl.handle.net/1957/35884.
Повний текст джерелаАнотація:
The feasibility of developing test circuits to perform in-circuit testing of analog
circuits is investigated in this thesis. A modular approach to analog testing has been
adopted. Accordingly, the testing of an operational amplifier, which is a basic building
block in analog circuits, is addressed. One convenient technique for measuring the frequency
response of an op-amp requires a unity gain buffer to be inserted into its feedback
loop. This buffer has to be simple in construction, small and accurate. Two buffer circuits
that satisfy these requirements are described in this thesis. Enhanced slewing techniques
are devised to achieve increased levels of performance. The buffers were integrated with
an op-amp into a test chip. Digital logic is used to provide controllability and accessibility
to each of the buffers and the op-amp so that they can characterized separately.
The performance of the enhanced slewing buffers was verified with measurements
performed on the test chip. The performance of the buffers conformed well with the simulated
values. The buffers exhibited excellent settling times even while driving large capacitive
loads. Their output swing and distortion performance were good for inputs as large as
2 V peak-to-peak values.Graduation date: 1994
19
Chen, Hsing-Yu, and 陳星羽. "V-band Subharmonic IQ Mixer Using Transformer Coupling and Buffer Amplifier." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/19169221908164212934.
Повний текст джерелаАнотація:
碩士國立臺灣大學
電子工程學研究所
104
In this thesis, a buffer amplifier and two subharmonic down-conversion mixers for V-band communication receiver system are designed and fabricated. This thesis starts from introducing buffer amplifier design principles. Then, this thesis introduces different mixer topologies and features, including active, passive, single balanced and double balanced mixers. Finally, this thesis introduces different sub-harmonic mixer topologies and features. Among all the sub-harmonic mixer topology, the sub-harmonic Gilbert cell mixer is the most widely used. This thesis proposes a two stage cascade amplifier using cascode amplifier with common-source amplifier, and successfully implement a low-power, high linearity and low noise buffer amplifier. Then, we propose an improved single balanced harmonic mixer. This mixer uses frequency multiplier to double local oscillation frequency, active load of cross-coupled to enhance conversion gain, and transformer to improve linearity. Finally, this thesis proposes an improved sub-harmonic Gilbert cell mixer, also using transformer to improve linearity, and adding transimpedance amplifier at output stage to reduce sensitivity to next stage’s impedance, and avoid circuit oscillation. In this thesis, buffer amplifier is developed in TSMC 40 nm CMOS technology. The measured 2dB bandwidth is 51.9GHz to 52GHz, and small signal gain is 9.9dB. The minimum noise figure is 4.8dB at 59GHz, input P1dB is -13dBm, IIP3 is -0.5 dBm, and DC power consumption is 11.23mW. The measured results comparing with simulated results have some deviation, due to in-accurate transistor model at high frequency. The sub-harmonic IQ mixer is developed in TSMC 90 nm CMOS technology. The measured conversion gain is -20.5dB, the input P1dB is 1dBm, and the DC power consumption is 13.92mW. The measured results comparing with simulated results have some deviation, and the reason is explained in Chapter 6. Finally, the sub-harmonic IQ mixer using transformer is developed in TSMC 40 nm CMOS technology. This chip is still under fabrication. The simulated conversion gain is -13 dB, input P1dB is -13dB, IIP3 is 4dBm, and DC power consumption is 26.62mW.
20
Yao, Tuo-yu, and 姚拓宇. "Differential-to-Single Voltage Buffer Amplifier for DDFS and Wireless Duplex Modulation Circuit Using A Single Coil." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/79v565.
Повний текст джерелаАнотація:
碩士國立中山大學
電機工程學系研究所
97
The thesis is composed of two topics: the differential to single voltage buffer amplifier used in DDFS designs and a wireless duplex modulation circuit with a single coil for bio-implants. A voltage buffer implemented in 2P4M 0.35 μm CMOS process, which is addressed in first part of this thesis, can amplify the small sinusoid outputs from DDFS (direct digital frequency synthesizer, DDFS), while convert the differential output into a single-end output. Not only can it amplify signal by a pre-defined multiple, but also reduce the common mode noise coupled from DDFS. A wireless duplex modulation circuit using a single coil for biomedical implantable systems is disclosed in the second part of this thesis. It enables full duplex communication between the external controller and the implants at same time by a wireless a RF transmission interface. Since the proposed duplex design employs a single coil, the volume of the implanted device is drastically reduced.
21
Lu, Yu-Cheng, and 盧昱程. "The Circuit Design of A Power Efficient Variable Gain Buffer Amplifier And Reconfigurable Dual Channel Analog Front-End for Biomedical Applications." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/yhqfd4.
Повний текст джерелаАнотація:
碩士國立臺灣科技大學
電機工程系
106
This thesis presents the design of power-efficient dual channel analog front-end (AFE) circuits for biomedical applications based on floating-gate programming technologies. The circuits in each channel of the analog front-end include a low noise amplifier (LNA), a variable gain amplifier (VGA), two reconfigurable biquadratic filter sections, and a buffer amplifier (BA). Floating-gate transistors are employed to implement programmable current sources, common-mode feedback, and programmable linear pseudo resistors, achieving low noise and high linearity with low power consumption. Since the bias current level is programmable, the bandwidth of the circuits can be easily tuned to fit into a variety of physiological signal sensing applications, such as the electrocardiogram (ECG), electroencephalogram (EEG), and electromyogram (EMG) from human bodies. The proposed AFE was fabricated in a 0.35μm CMOS process, and its area is 6.88mm2. To prevent that the filter impacts the sensitivity of the low frequency signal, the designed sensing channel includes the LNA and the VGA, achieving 116Hz of the high frequency cutoff point and 0.8Hz of the low frequency cutoff point under 205nA of current consumption. The midband gain is designed from 55.35dB to 81.58dB. The measured input referred noise voltage is 2.43Vrms integrated from 0.5Hz to 100kHz. The noise efficiency factor (NEF) is 3.94. The total harmonic distortion (THD) is -58.34dB with 1.136V of the output peak-to-peak voltage in the low gain set. Since the variable gain amplifier employs T-network to implement the small feedback capacitance, the feedback pseudo resistance should be several times larger than that in LNA to achieve a low frequency cutoff point. To improve this drawback, the variable gain amplifier is redesigned by employing the original structure of the buffer amplifier. Compared with conventional operational amplifier, the linearity is improved because of the floating-gate based class-AB input stage with enhanced slew rate. The bandwidth and the closed-loop gain are both reconfigurable through programming the floating-gate current source and switching different amount of feedback capacitors. The improved buffer amplifier was designed and fabricated in a 0.35μm CMOS process occupying a silicon area of 0.084mm2. The current consumptions under 100kHz, 500kHz, and 1MHz conditions are 5.9μA, 38μA, and 124.8μA, respectively. The measured IIP3 is above 28.7dBV, and the THD is below -82.6dB in the low gain set.