Статті в журналах: "Approximate Circuit"

1

Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits." Computers 11, no. 1 (January 8, 2022): 11. http://dx.doi.org/10.3390/computers11010011.

Повний текст джерела

Анотація:

Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.

Стилі APA, Harvard, Vancouver, ISO та ін.

2

Visweswariah, C., and R. A. Rohrer. "Piecewise approximate circuit simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 7 (July 1991): 861–70. http://dx.doi.org/10.1109/43.87597.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

3

Koseoglu, Murat, Furkan Nur Deniz, Baris Baykant Alagoz, Ali Yuce, and Nusret Tan. "An experimental analog circuit realization of Matsuda’s approximate fractional-order integral operators for industrial electronics." Engineering Research Express 3, no. 4 (December 1, 2021): 045041. http://dx.doi.org/10.1088/2631-8695/ac3e11.

Повний текст джерела

Анотація:

Abstract Analog circuit realization of fractional order (FO) elements is a significant step for the industrialization of FO control systems because of enabling a low-cost, electric circuit realization by means of standard industrial electronics components. This study demonstrates an effective operational amplifier-based analog circuit realization of approximate FO integral elements for industrial electronics. To this end, approximate transfer function models of FO integral elements, which are calculated by using Matsuda’s approximation method, are decomposed into the sum of low-pass filter forms according to the partial fraction expansion. Each partial fraction term is implemented by using low-pass filters and amplifier circuits, and these circuits are combined with a summing amplifier to compose the approximate FO integral circuits. Widely used low-cost industrial electronics components, which are LF347N opamps, resistor and capacitor components, are used to achieve a discrete, easy-to-build analog realization of the approximate FO integral elements. The performance of designed circuit is compared with performance of Krishna’s FO circuit design and performance improvements are shown. The study presents design, performance validation and experimental verification of this straightforward approximate FO integral realization method.

Стилі APA, Harvard, Vancouver, ISO та ін.

4

Yang, Zhixi, Xianbin Li, and Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction." Journal of Circuits, Systems and Computers 29, no. 15 (June 30, 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.

Повний текст джерела

Анотація:

Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.

Стилі APA, Harvard, Vancouver, ISO та ін.

5

Ykuntam, Yamini Devi, Bujjibabu Penumutchi, Bala Srinivas Peteti, and Satyanarayana Vella. "Performance Evaluation of Approximate Adders: Case Study." International Journal of Engineering and Advanced Technology 12, no. 1 (October 30, 2022): 68–75. http://dx.doi.org/10.35940/ijeat.a3836.1012122.

Повний текст джерела

Анотація:

A computing device designed to carry out a variety of arithmetic computations. The adder circuit, whose operation must be quick with a small area of occupancy, performs the addition, which is a necessary operation in many other mathematical operations including subtraction, multiplication, and division. There is a mandate for an adder circuit with minimal power consumption, minimal delay, and minimal size in various real-time applications such as processing of signals, pictures & video, VLSI data pathways, processors, neural networks, and many more. There is a new class of adders called approximation adders that operate inaccurately but with favorable area, speed, and power consumption. Since their output is inaccurate, the other names for approximate adders are imprecise adders. This set of adders operates at a high speed thanks to a circuit critical path design that uses fewer components. Additionally, compared to precise adders, the approximate adder circuit has a relatively low component count, resulting in a small footprint and circuits that use less energy. There are different ways to create approximate adders. The area can be predicted by counting the number of circuit components that are present. By examining a number of the critical path’s components, delay can be predicted. Several errors that appear in the output of the particular circuit can be used to calculate the accuracy percentage. This review compares approximate adders from four different categories across the board in terms of design constraints and makes note of the differences between each adder.

Стилі APA, Harvard, Vancouver, ISO та ін.

6

Osta, Mario, Ali Ibrahim, and Maurizio Valle. "Approximate Computing Circuits for Embedded Tactile Data Processing." Electronics 11, no. 2 (January 8, 2022): 190. http://dx.doi.org/10.3390/electronics11020190.

Повний текст джерела

Анотація:

In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.

Стилі APA, Harvard, Vancouver, ISO та ін.

7

Joshi, Viraj, Pravin Mane, and Bits Pilani. "Approximate Arithmetic Circuit Design for Error Resilient Applications." International Journal of VLSI Design & Communication Systems 13, no. 1/2/3/4/5/6 (December 30, 2022): 01–16. http://dx.doi.org/10.5121/vlsic.2022.13601.

Повний текст джерела

Анотація:

When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on performance are rapidly getting replaced by approximate arithmetic circuits which are the need of the hour, and so on about their design.

Стилі APA, Harvard, Vancouver, ISO та ін.

8

Barnes, Christopher L., Daniel Bonnéry, and Albert Cardona. "Synaptic counts approximate synaptic contact area in Drosophila." PLOS ONE 17, no. 4 (April 4, 2022): e0266064. http://dx.doi.org/10.1371/journal.pone.0266064.

Повний текст джерела

Анотація:

The pattern of synaptic connections among neurons defines the circuit structure, which constrains the computations that a circuit can perform. The strength of synaptic connections is costly to measure yet important for accurate circuit modeling. Synaptic surface area has been shown to correlate with synaptic strength, yet in the emerging field of connectomics, most studies rely instead on the counts of synaptic contacts between two neurons. Here we quantified the relationship between synaptic count and synaptic area as measured from volume electron microscopy of the larval Drosophila central nervous system. We found that the total synaptic surface area, summed across all synaptic contacts from one presynaptic neuron to a postsynaptic one, can be accurately predicted solely from the number of synaptic contacts, for a variety of neurotransmitters. Our findings support the use of synaptic counts for approximating synaptic strength when modeling neural circuits.

Стилі APA, Harvard, Vancouver, ISO та ін.

9

Bhargav, Avireni, and Phat Huynh. "Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs." Sensors 21, no. 24 (December 8, 2021): 8203. http://dx.doi.org/10.3390/s21248203.

Повний текст джерела

Анотація:

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.

Стилі APA, Harvard, Vancouver, ISO та ін.

10

Goyal, Candy, Jagpal Singh Ubhi, and Balwinder Raj. "A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise." Mathematical Problems in Engineering 2018 (December 16, 2018): 1–16. http://dx.doi.org/10.1155/2018/3501041.

Повний текст джерела

Анотація:

In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.

Стилі APA, Harvard, Vancouver, ISO та ін.

11

Berndt, Augusto André Souza, Brunno Abreu, Isac S. Campos, Bryan Lima, Mateus Grellert, Jonata T. Carvalho, and Cristina Meinhardt. "CGP-based Logic Flow: Optimizing Accuracy and Size of Approximate Circuits." Journal of Integrated Circuits and Systems 17, no. 1 (April 30, 2022): 1–12. http://dx.doi.org/10.29292/jics.v17i1.546.

Повний текст джерела

Анотація:

Logic synthesis tools face tough challenges when providing algorithms for synthesizing circuits with increased inputs and complexity. Machine learning techniques show high performance in solving specific problems, being an attractive option to improve electronic design tools. We explore Cartesian Genetic Programming (CGP) for logic optimization of exact or approximate Boolean functions in our work. The proposed CGP-based flow receives the expected circuit behavior as a truth-table and either performs the synthesis starting from random circuits or optimizes a circuit description provided in the format of an AND-Inverter Graph. The optimization flow improves solutions found by other techniques, using them for bootstrapping the evolutionary process. We use two metrics to evaluate our CGP-based flow: (i) the number of AIG nodes or (ii) the circuit accuracy. The results obtained showed that the CGP-based flow provided at least 22.6% superior results when considering the trade-off between accuracy and size compared with two other methods that brought the best accuracy and size outcomes, respectively.

Стилі APA, Harvard, Vancouver, ISO та ін.

12

Kim, Kibeom, Seokha Hwang, Youngjoo Lee, and Sunggu Lee. "Approximate Radix-4 Booth Multiplication Circuit." JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 19, no. 5 (October 31, 2019): 435–45. http://dx.doi.org/10.5573/jsts.2019.19.5.435.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

13

Jena, Saumya Ranjan, and Damayanti Nayak. "Approximate instantneous current in RLC circuit." Bulletin of Electrical Engineering and Informatics 9, no. 2 (April 1, 2020): 801–7. http://dx.doi.org/10.11591/eei.v9i2.1641.

Повний текст джерела

Анотація:

In this study, a mixed rule of degree of precision nine has been developed and implemented in the field of electrical sciences to obtain the instantaneous current in the RLC- circuit for particular value .The linearity has been performed with the Volterra’s integral equation of second kind with particular kernel . Then the definite integral has been evaluated through the mixed quadrature to obtain the numerical result which is very effective. A polynomial has been used to evaluate Volterra’s integral equation in the place of unknown functions. The accuracy of the proposed method has been tested taking different electromotive force in the circuit and absolute error has been estimated.

Стилі APA, Harvard, Vancouver, ISO та ін.

14

Sussman-Fort, Stephen E. "Approximate direct-search minimax circuit optimization." International Journal for Numerical Methods in Engineering 28, no. 2 (February 1989): 359–68. http://dx.doi.org/10.1002/nme.1620280208.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

15

Shafiabadi, Mohammad Ali, and Fazel Sharifi. "Approximate 5-2 Compressor Cell Using Spin-Based Majority Gates." SPIN 10, no. 02 (June 2020): 2040004. http://dx.doi.org/10.1142/s2010324720400044.

Повний текст джерела

Анотація:

One of the most interesting solutions for decreasing the static power of computational circuits is to use approximate computing. Approximate computing has been extensively considered to trade-off limited accuracy for improvements in other circuit metrics such as area, power and performance. On the other hand, the increasing leakage power and limited scalability have become serious obstacles that prevent the continuous miniaturization of conventional CMOS-based logic circuits. Spintronic devices are being considered as a promising alternative technology for silicon-based FET to implement digital circuits. In this paper, an approximate 5-2 compressor cell is presented using spin-based devices. The proposed circuit is designed by majority gates which can be implemented very easily and efficiently by spintronic threshold device (STD). The proposed design has been simulated comprehensively for both quantitative and qualitative metrics. The results show that the spin-based compressor decreases the power consumption about 7X compared to the best state-of-the-art design. Also, the application simulations using the multiplier implemented by the proposed compressor indicate the acceptable results.

Стилі APA, Harvard, Vancouver, ISO та ін.

16

G, Navabharath Reddy, Sruti Setlam, V. Prakasam, and D. Kiran Kumar. "Approximate arithmetic circuits." International Journal of Reconfigurable and Embedded Systems (IJRES) 9, no. 3 (November 1, 2020): 183. http://dx.doi.org/10.11591/ijres.v9.i3.pp183-200.

Повний текст джерела

Анотація:

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

Стилі APA, Harvard, Vancouver, ISO та ін.

17

Ammes, Gabriel, Paulo Francisco Butzen, André Inácio Reis, and Renato Ribas. "Two-Level and Multilevel Approximate Logic Synthesis." Journal of Integrated Circuits and Systems 17, no. 3 (January 25, 2023): 1–14. http://dx.doi.org/10.29292/jics.v17i3.661.

Повний текст джерела

Анотація:

Approximate computing represents a modern design paradigm that allows systems to have imprecise or inexact execution, aiming to optimize circuit area, performance, and power dissipation. The automatic construction of approximate integrated circuits (IC) is performed through computer-aided design (CAD) tools available in electronic design automation (EDA) frameworks. Approximate logic synthesis (ALS), in particular, treats two-level and multilevel topologies of combinational blocks in the development of digital IC design. This work provides a survey of ALS methods presented in the literature, from the pioneers until the state-of-the-art approaches.

Стилі APA, Harvard, Vancouver, ISO та ін.

18

Feldmann, P., T. V. Nguyen, S. W. Director, and R. A. Rohrer. "Sensitivity computation in piecewise approximate circuit simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 2 (1991): 171–83. http://dx.doi.org/10.1109/43.68404.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

19

Taha, Mohammad M. A., and Christof Teuscher. "Approximate Memristive In-Memory Hamming Distance Circuit." ACM Journal on Emerging Technologies in Computing Systems 16, no. 2 (April 30, 2020): 1–14. http://dx.doi.org/10.1145/3371391.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

20

Mrazek, Vojtech, Zdenek Vasicek, and Radek Hrbacek. "Role of circuit representation in evolutionary design of energy‐efficient approximate circuits." IET Computers & Digital Techniques 12, no. 4 (June 6, 2018): 139–49. http://dx.doi.org/10.1049/iet-cdt.2017.0188.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

21

Madden, Liam, and Andrea Simonetto. "Best Approximate Quantum Compiling Problems." ACM Transactions on Quantum Computing 3, no. 2 (June 30, 2022): 1–29. http://dx.doi.org/10.1145/3505181.

Повний текст джерела

Анотація:

We study the problem of finding the best approximate circuit that is the closest (in some pertinent metric) to a target circuit, and which satisfies a number of hardware constraints, like gate alphabet and connectivity. We look at the problem in the CNOT+rotation gate set from a mathematical programming standpoint, offering contributions both in terms of understanding the mathematics of the problem and its efficient solution. Among the results that we present, we are able to derive a 14-CNOT 4-qubit Toffoli decomposition from scratch, and show that the Quantum Shannon Decomposition can be compressed by a factor of two without practical loss of fidelity.

Стилі APA, Harvard, Vancouver, ISO та ін.

22

Dharmaraj, Celia, Vinita Vasudevan, and Nitin Chandrachoodan. "Optimization of Signal Processing Applications Using Parameterized Error Models for Approximate Adders." ACM Transactions on Embedded Computing Systems 20, no. 2 (March 2021): 1–25. http://dx.doi.org/10.1145/3430509.

Повний текст джерела

Анотація:

Approximate circuit design has gained significance in recent years targeting error-tolerant applications. In the literature, there have been several attempts at optimizing the number of approximate bits of each approximate adder in a system for a given accuracy constraint. For computational efficiency, the error models used in these routines are simple expressions obtained using regression or by assuming inputs or the error is uniformly distributed. In this article, we first demonstrate that for many approximate adders, these assumptions lead to an inaccurate prediction of error statistics for multi-level circuits. We show that mean error and mean square error can be computed accurately if static probabilities of adders at all stages are taken into account. Therefore, in a system with a certain type of approximate adder, any optimization framework needs to take into account not just the functionality of the adder but also its position in the circuit, functionality of its parents, and the number of approximate bits in the parent blocks. We propose a method to derive parameterized error models for various types of approximate adders. We incorporate these models within an optimization framework and demonstrate that the noise power is computed accurately.

Стилі APA, Harvard, Vancouver, ISO та ін.

23

Yuan, Wei Jun, An Ping He, and Jin Zhao Wu. "Error Analysis of Approximate Ripple Borrow Subtractors." Applied Mechanics and Materials 291-294 (February 2013): 2941–47. http://dx.doi.org/10.4028/www.scientific.net/amm.291-294.2941.

Повний текст джерела

Анотація:

In this article, we study the output error in terms of the delay of the arithmetic subtractor circuit. By the formal analysis the borrow in arithmetic subtractor, especially the borrow chain, we model the discrete signals in the continuously, then construct the output error model and energy consumption model of the ripple borrow subtractor circuit. With these models, we do the trustable analysis formally.

Стилі APA, Harvard, Vancouver, ISO та ін.

24

Caravelli, Francesco. "Asymptotic Behavior of Memristive Circuits." Entropy 21, no. 8 (August 13, 2019): 789. http://dx.doi.org/10.3390/e21080789.

Повний текст джерела

Анотація:

The interest in memristors has risen due to their possible application both as memory units and as computational devices in combination with CMOS. This is in part due to their nonlinear dynamics, and a strong dependence on the circuit topology. We provide evidence that also purely memristive circuits can be employed for computational purposes. In the present paper we show that a polynomial Lyapunov function in the memory parameters exists for the case of DC controlled memristors. Such a Lyapunov function can be asymptotically approximated with binary variables, and mapped to quadratic combinatorial optimization problems. This also shows a direct parallel between memristive circuits and the Hopfield-Little model. In the case of Erdos-Renyi random circuits, we show numerically that the distribution of the matrix elements of the projectors can be roughly approximated with a Gaussian distribution, and that it scales with the inverse square root of the number of elements. This provides an approximated but direct connection with the physics of disordered system and, in particular, of mean field spin glasses. Using this and the fact that the interaction is controlled by a projector operator on the loop space of the circuit. We estimate the number of stationary points of the approximate Lyapunov function and provide a scaling formula as an upper bound in terms of the circuit topology only.

Стилі APA, Harvard, Vancouver, ISO та ін.

25

Freeborn, Todd, Brent Maundy, and Ahmed S. Elwakil. "Approximated Fractional Order Chebyshev Lowpass Filters." Mathematical Problems in Engineering 2015 (2015): 1–7. http://dx.doi.org/10.1155/2015/832468.

Повний текст джерела

Анотація:

We propose the use of nonlinear least squares optimization to approximate the passband ripple characteristics of traditional Chebyshev lowpass filters with fractional order steps in the stopband. MATLAB simulations of(1+α),(2+α), and(3+α)order lowpass filters with fractional steps fromα = 0.1 toα = 0.9 are given as examples. SPICE simulations of 1.2, 1.5, and 1.8 order lowpass filters using approximated fractional order capacitors in a Tow-Thomas biquad circuit validate the implementation of these filter circuits.

Стилі APA, Harvard, Vancouver, ISO та ін.

26

Bogle, A. G. "Addendum: Rectifier circuit performance: some new approximate formulas." IEE Proceedings G (Electronic Circuits and Systems) 133, no. 3 (1986): 128. http://dx.doi.org/10.1049/ip-g-1.1986.0020.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

27

Quan, Yu Sheng, Zong Cheng Zhang, Guang Chen, and Dai Juan Wang. "Study on Method Detecting Turn-to-Turn Short Circuit of Transformer Based on Kalman Filter." Applied Mechanics and Materials 521 (February 2014): 371–74. http://dx.doi.org/10.4028/www.scientific.net/amm.521.371.

Повний текст джерела

Анотація:

Distribution transformer is an important device in the power system, once its failure can cause power outages. According to statistics, 70% -80% of the transformer accident was caused by a short circuit between the transformer turns. In this paper, the ground current of transformer core as the signal source, using Kalman filter techniques to approximate the measured signal, obtained state transition parameters of the prediction signal that most approximate the signal measured , Generated the inter-turn short circuit fault diagnostic parameters, based on the range of parameters to achieve the transformer inter-turn short circuits fault diagnosis. To verify this method, this paper design experiment, the results prove the validity and feasibility of the methods for fault diagnosis.

Стилі APA, Harvard, Vancouver, ISO та ін.

28

Safaei Mehrabani, Yavar, Mehdi Bagherizadeh, Mohammad Hossein Shafiabadi, and Abolghasem Ghasempour. "A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology." Circuit World 45, no. 3 (August 5, 2019): 156–68. http://dx.doi.org/10.1108/cw-01-2019-0009.

Повний текст джерела

Анотація:

Purpose This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs). Design/methodology/approach To design this cell, the capacitive threshold logic (CTL) has been used. Findings To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others. Originality/value This cell significantly reduces the number of transistors and only consists of NOT gates.

Стилі APA, Harvard, Vancouver, ISO та ін.

29

Qiao, Yaqiong, Zhiguo Liang, Jianjie Yu, Wu Duan, and Shuai Bai. "Verification and Analysis of Lumped-Circuit Approximate Models of Twisted-Stranded Cables for High-Speed Railway Signaling Systems." Journal of Nanoelectronics and Optoelectronics 17, no. 2 (February 1, 2022): 324–34. http://dx.doi.org/10.1166/jno.2022.3202.

Повний текст джерела

Анотація:

To evaluate the transmission characteristics, anti-electromagnetic interference performance, and cable channel fault detection of multi-core twisted-stranded cables used in high-speed railway signaling systems, this study established a model for accurate twisted cable physical simulations. With the LEU-BSYYP cable, the finite element method (FME) software constructed a one twisted cycle length model and calculated the per-unit-length (pul) distribution parameters of the cable under high-frequency pulses. The purpose is to simulate long-distance twisted cables physically and analyze the factors affecting the transmission quality and transmission distance of high-frequency signals quantitatively by constructing a lumped equivalent circuit comprising cascaded T-type circuits. Additionally, by analyzing the relationship between the working frequency and the characteristic impedance error, where the characteristic impedance error is the difference in characteristic impedance between a lumped equivalent circuit and a lossy uniform transmission line, the number of T-type cascaded circuits that fulfill the accuracy requirements of the physical simulation is determined. Finally, the model output is compared with the measured waveforms using a 500 m LEU-BSYYP twisted pair cable as an example to verify the correctness of the equivalent modeling of the lumped circuit in the paper.

Стилі APA, Harvard, Vancouver, ISO та ін.

30

Song, Soonbum, and Youngmin Kim. "Novel In-Memory Computing Adder Using 8+T SRAM." Electronics 11, no. 6 (March 16, 2022): 929. http://dx.doi.org/10.3390/electronics11060929.

Повний текст джерела

Анотація:

Von Neumann architecture-based computing systems are facing a von Neumann bottleneck owing to data transfer between separated memory and processor units. In-memory computing (IMC), on the other hand, reduces energy consumption and improves computing performance. This study explains an 8+T SRAM IMC circuit based on 8+T differential SRAM (8+T SRAM) and proposes 8+T SRAM-based IMC full adder (FA) and 8+T SRAM-based IMC approximate adder, which are based on the 8+T SRAM IMC circuit. The 8+T SRAM IMC circuit performs SRAM read and bitwise operations simultaneously and performs each logic operation parallelly. The proposed IMC FA and the proposed IMC approximate adder can be applied to a multi-bit adder. The two adders are based on the 8+T SRAM IMC circuit and thus read and compute simultaneously. In this study, the 8+T SRAM IMC circuit was applied to the adder, leveraging its ability to perform read and logic operations simultaneously. According to the performance in this study, the 8+T SRAM IMC circuit, proposed FA, proposed RCA, and proposed approximated adder are good candidates for IMC, which aims to reduce energy consumption and improve overall performance.

Стилі APA, Harvard, Vancouver, ISO та ін.

31

Chowdhury, Prattay, and Benjamin Carrion Schafer. "Leveraging Automatic High-Level Synthesis Resource Sharing to Maximize Dynamical Voltage Overscaling with Error Control." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (March 31, 2022): 1–18. http://dx.doi.org/10.1145/3473909.

Повний текст джерела

Анотація:

Approximate Computing has emerged as an alternative way to further reduce the power consumption of integrated circuits (ICs) by trading off errors at the output with simpler, more efficient logic. So far the main approaches in approximate computing have been to simplify the hardware circuit by pruning the circuit until the maximum error threshold is met. One of the critical issues, though, is the training data used to prune the circuit. The output error can significantly exceed the maximum error if the final workload does not match the training data. Thus, most previous work typically assumes that training data matches with the workload data distribution. In this work, we present a method that dynamically overscales the supply voltage based on different workload distribution at runtime. This allows to adaptively select the supply voltage that leads to the largest power savings while ensuring that the error will never exceed the maximum error threshold. This approach also allows restoring of the original error-free circuit if no matching workload distribution is found. The proposed method also leverages the ability of High-Level Synthesis (HLS) to automatically generate circuits with different properties by setting different synthesis constraints to maximize the available timing slack and, hence, maximize the power savings. Experimental results show that our proposed method works very well, saving on average 47.08% of power as compared to the exact output circuit and 20.25% more than a traditional approximation method.

Стилі APA, Harvard, Vancouver, ISO та ін.

32

Kosuri, Lakshmi Thirumala, M. Deepika Krishna, Adilakshmi i. Karapat, B. S. B. Ayyappa Swamy, and Dinesh Nayak S. "A Low Power High Speed Accuracy Controllable Approximate Multiplier Design." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (April 30, 2022): 1625–30. http://dx.doi.org/10.22214/ijraset.2022.41617.

Повний текст джерела

Анотація:

Abstract: For energy effective and high performance design, the low power VLSI circuit is used. Multiplier is an essential part of low power VLSI design, since the effectiveness of the digital signal processor depends upon the multiplier. In multiplier circuit, utmost of the power is dissipated across in full adder circuits. Multiplication is one of the important process in microprocessor and there will be a lot of delay because of array multiplier, which can be compressed with the help of the column compressor approach. It uses a selection of half adders, full adders and compressors to sum the partial products in stages until two numbers are left. An 8 * 8 and 16 * 16 bit multiplier design is executed by assigning the adder and compressor. Partial product totality is the speed limiting operation in multiplication due to the propagation detention in adder networks. In order to reduce the propagation detention, compressors are introduced. Compressors calculate the sum and carry at each position concurrently. The attendant carry is added with a advanced significant sum bit in the coming stage. This is continued until the final product is generated. The partial product tree of the multiplier is estimated by the proposed tree compressor ( High Speed Compressor, Dual Stage Compressor, Exact Compressor). Keywords: Partial Products, Half Adder, Full Adder, High Speed Compressor, Dual Stage Compressor, Exact Compressor.

Стилі APA, Harvard, Vancouver, ISO та ін.

33

ANTREICH, KURT J., HELMUT E. GRAEB, and CLAUDIA U. WIESER. "PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS." International Journal of High Speed Electronics and Systems 04, no. 03 (September 1993): 261–82. http://dx.doi.org/10.1142/s0129156493000121.

Повний текст джерела

Анотація:

Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

Стилі APA, Harvard, Vancouver, ISO та ін.

34

Arifeen, Tooba, Abdus Hassan, and Jeong-A. Lee. "A Fault Tolerant Voter for Approximate Triple Modular Redundancy." Electronics 8, no. 3 (March 18, 2019): 332. http://dx.doi.org/10.3390/electronics8030332.

Повний текст джерела

Анотація:

Approximate Triple Modular Redundancy has been proposed in the literature to overcome the area overhead issue of Triple Modular Redundancy (TMR). The outcome of TMR/Approximate TMR modules serves as the voter input to produce the final output of a system. Because the working principle of Approximate TMR conditionally allows one of the approximate modules to differ from the original circuit, it is critical for Approximate TMR that a voter not only be tolerant toward its internal faults but also toward faults that occur at the voter inputs. Herein, we present a novel compact voter for Approximate TMR using pass transistors and quadded transistor level redundancy to achieve a higher fault masking. The design also targets a better Quality of Circuit (QoC), a new metric which we have proposed for highlighting the ability of a circuit to fully mask all possible internal faults for an input vector. Comparing the fault masking features with those of existing works, the proposed voter delivered upto 45.1%, 62.5%, 26.6% improvement in Fault Masking Ratio (FMR), QoC, and reliability, respectively. With respect to the electrical characteristics, our proposed voter can achieve an improvement of up to 50% and 56% in terms of the transistor count and power delay product, respectively.

Стилі APA, Harvard, Vancouver, ISO та ін.

35

Feldman, A., G. Provan, and A. Van Gemund. "Approximate Model-Based Diagnosis Using Greedy Stochastic Search." Journal of Artificial Intelligence Research 38 (July 27, 2010): 371–413. http://dx.doi.org/10.1613/jair.3025.

Повний текст джерела

Анотація:

We propose a StochAstic Fault diagnosis AlgoRIthm, called SAFARI, which trades off guarantees of computing minimal diagnoses for computational efficiency. We empirically demonstrate, using the 74XXX and ISCAS-85 suites of benchmark combinatorial circuits, that SAFARI achieves several orders-of-magnitude speedup over two well-known deterministic algorithms, CDA* and HA*, for multiple-fault diagnoses; further, SAFARI can compute a range of multiple-fault diagnoses that CDA* and HA* cannot. We also prove that SAFARI is optimal for a range of propositional fault models, such as the widely-used weak-fault models (models with ignorance of abnormal behavior). We discuss the optimality of SAFARI in a class of strong-fault circuit models with stuck-at failure modes. By modeling the algorithm itself as a Markov chain, we provide exact bounds on the minimality of the diagnosis computed. SAFARI also displays strong anytime behavior, and will return a diagnosis after any non-trivial inference time.

Стилі APA, Harvard, Vancouver, ISO та ін.

36

Gupta, Rohit, Rahul Gupta, and Dinesh Verma. "Response of RLC network circuit with steady source via rohit transform." International Journal of Engineering, Science and Technology 14, no. 1 (August 8, 2022): 21–27. http://dx.doi.org/10.4314/ijest.v14i1.3.

Повний текст джерела

Анотація:

The electric network circuits are designed by using the elements like resistor R, inductor L, and capacitor Ϲ. There are a number of techniques: exact, approximate, and purely numerical available for analyzing the R L Ϲ network circuits. Since the application of numerical method becomes more complex, computationally intensive, or needs complicated symbolic computations, there is a need to seek the help of integral transform methods for analyzing the RLϹ network circuits. Integral transform methods provide effective ways for solving a variety of problems arising in basic sciences and engineering. In thispaper, a new integral transform Rohit transform is discussed for obtaining the response of a series RLϹ electric network circuit connected to a steady voltage source, and a parallel R L Ϲ electric network circuit connected to a steady current source. The response of a series R L Ϲ network circuit connected to a steady voltage source via the application of Rohit transform will provide an expression for the electric current, and that of a parallel R L Ϲ network circuit connected to a steady current source will provide an expression for the voltage across the parallel RLϹ electric network circuit. The nature of the response of such series (or parallel) network circuits is determined by the values of R, L, and Ϲ of the electric network circuit. The Rohit transform will come out to be a powerful technique for analyzing such series or parallel electric network circuits with steady voltage or current sources.

Стилі APA, Harvard, Vancouver, ISO та ін.

37

Sun, Qiu Dong, Zheng Guo Liu, Wen Xin Ma, and Jiang Wei Huang. "The Equivalent Proving of Two Typical Vector Composing PM Circuits and their Characteristic Analysis." Advanced Materials Research 298 (July 2011): 193–96. http://dx.doi.org/10.4028/www.scientific.net/amr.298.193.

Повний текст джерела

Анотація:

PM, Vector Composing, Armstrong PM, QAM-based PM, Equivalent Analysis Abstract. Both the Armstrong phase modulation (PM) and QAM-based PM are typical vector composing circuits in the course “Radio Frequency Circuits”. Due to having innate defects of nonlinear phase distortion and parasitical AM, the characteristics of Armstrong PM are not good unless the modulation exponent is small enough. Therefore, the Armstrong PM is an approximate circuit. The QAM- based PM is a quite different circuit from the Armstrong PM, and its defects are not given in general teaching material. The equivalence of two circuits is proved in this paper by mathematical method. So, the QAM-based PM has same pros and cons with Armstrong PM and can be replaced with the latter completely.

Стилі APA, Harvard, Vancouver, ISO та ін.

38

Zhao, Xi-Ning, and Xiao-Dong Yang. "Elastic Wave Properties of an Adaptive Electromechanical Metamaterial Beam." Shock and Vibration 2020 (October 20, 2020): 1–14. http://dx.doi.org/10.1155/2020/8834856.

Повний текст джерела

Анотація:

An adaptive metamaterial beam with a couple of electromechanical resonators in each unit cell is proposed in this study to open Bragg bandgap or locally resonant bandgap for flexural wave attenuation in Euler–Bernoulli beams. The electromechanical resonator is composed of a piezoelectric layer with segmented electrodes and shunt circuits, which affect the dynamic equivalent stiffness. It is illustrated that there is only a Bragg bandgap when the circuits of the two adjacent resonators are approximate to a short circuit or open circuit, and the locally resonant bandgap will be generated in the pure inductance circuits when the resonant frequencies are different in general. The locally resonant bandgap can be broadened by adding more resonators into the unit cell with the resonant frequencies of the shunting circuits satisfying a proper ratio.

Стилі APA, Harvard, Vancouver, ISO та ін.

39

Abuelma'atti, Muhammad Taher. "An Approximate Analysis and Its Application to The Non-Linear Performance of Three Mosfet Transconductance Amplifiers." Active and Passive Electronic Components 17, no. 3 (1994): 135–49. http://dx.doi.org/10.1155/1994/30565.

Повний текст джерела

Анотація:

A simple procedure for approximating the input-output characteristic of non-linear electronic circuits is presented. Using this procedure, closed-form analytical expressions, in terms of the ordinary Bessel functions, are obtained for the output spectra of a non-linear electronic circuit resulting from a multisinusoidal input. Using these expressions, the non-linear performance of three basic MOSFET transconductance amplifiers is considered in an attempt to determine the transistor parameters for best linearity.

Стилі APA, Harvard, Vancouver, ISO та ін.

40

Engel, P. A., and J. T. Vogelmann. "Approximate Structural Analysis of Circuit Card Systems Subjected to Torsion." Journal of Electronic Packaging 114, no. 2 (June 1, 1992): 203–10. http://dx.doi.org/10.1115/1.2906419.

Повний текст джерела

Анотація:

Engineering analysis of module-populated printed circuit cards subjected to torsion is pursued by approximate engineering analysis, numerical (finite element), and experimental means. The engineering theory utilizes a simplified method of evaluating the torsional stiffness and maximum lead force, the latter found at the module corners. Finite element methods are used to check these values for circuit cards with a wide variety of module configurations, starting from a single-module to sixteen PLCC modules, having 44, 68, and 84 J-leads. An experimental torsion apparatus is used to obtain data for further comparison with the former approaches, and for getting data from the geometrically nonlinear (large deflection) range.

Стилі APA, Harvard, Vancouver, ISO та ін.

41

Khan, Yasir, and Naeem Faraz. "Simple use of the Maclaurin series method for linear and non-linear differential equations arising in circuit analysis." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 40, no. 3 (August 7, 2021): 593–601. http://dx.doi.org/10.1108/compel-08-2020-0286.

Повний текст джерела

Анотація:

Purpose The purpose of this paper is to investigate the circuit analysis differential equations, which play an important role in the field of electrical and electronic engineering, and it was necessary to propose a very simple and direct method to obtain approximate solutions for the linear or non-linear differential equations, which should be simple for engineers to understand. Design/methodology/approach This paper introduces a simple novel Maclaurin series method (MSM) to propose an approximate novel solution in the area of circuit analysis for linear and non-linear differential equations. These equations describe the alternating current circuit of the resistor–capacitor, which evaluates the effect of non-linear current resistance. Linear and non-linear differential equations are evaluated as a computational analysis to assist the research, which reveals that the MSM is incredibly simple and effective. Findings Simulation findings indicate that the achieved proposed solution using the novel suggested approach is identical to the exact solutions mentioned in the literature. As the Maclaurin series is available to all non-mathematicians, this paper reflects mostly on theoretical implementations of the numerous circuit problems that occur in the field of electrical engineering. Originality/value A very simple and efficient method has been proposed in this paper, which is very easy to understand for even non-mathematicians such as engineers. The paper introduced a method of the Maclaurin series to solve non-linear differential equations resulting from the study of the circuits. The MSM mentioned here will be a useful tool in areas of physical and engineering anywhere the problem of the circuits is studied.

Стилі APA, Harvard, Vancouver, ISO та ін.

42

Funcke, Lena, Tobias Hartung, Karl Jansen, Stefan Kühn, and Paolo Stornati. "Dimensional Expressivity Analysis of Parametric Quantum Circuits." Quantum 5 (March 29, 2021): 422. http://dx.doi.org/10.22331/q-2021-03-29-422.

Повний текст джерела

Анотація:

Parametric quantum circuits play a crucial role in the performance of many variational quantum algorithms. To successfully implement such algorithms, one must design efficient quantum circuits that sufficiently approximate the solution space while maintaining a low parameter count and circuit depth. In this paper, develop a method to analyze the dimensional expressivity of parametric quantum circuits. Our technique allows for identifying superfluous parameters in the circuit layout and for obtaining a maximally expressive ansatz with a minimum number of parameters. Using a hybrid quantum-classical approach, we show how to efficiently implement the expressivity analysis using quantum hardware, and we provide a proof of principle demonstration of this procedure on IBM's quantum hardware. We also discuss the effect of symmetries and demonstrate how to incorporate or remove symmetries from the parametrized ansatz.

Стилі APA, Harvard, Vancouver, ISO та ін.

43

Davidovitz, Marat. "An approximate equivalent-circuit of a truncated nonradiative dielectric waveguide." Microwave and Optical Technology Letters 15, no. 4 (July 1997): 224–27. http://dx.doi.org/10.1002/(sici)1098-2760(199707)15:4<224::aid-mop10>3.0.co;2-7.

Повний текст джерела

Стилі APA, Harvard, Vancouver, ISO та ін.

44

Cies, Jeffrey J., Wayne S. Moore, Nadji Giliam, Tracy Low, Daniel Marino, Jillian Deacon, Adela Enache, and Arun Chopra. "Oxygenator impact on voriconazole in extracorporeal membrane oxygenation circuits." Perfusion 35, no. 6 (July 6, 2020): 529–33. http://dx.doi.org/10.1177/0267659120937906.

Повний текст джерела

Анотація:

Introduction: To determine the oxygenator impact on alterations of voriconazole in a contemporary neonatal/pediatric (1/4 inch) and adolescent/adult (3/8 inch) extracorporeal membrane oxygenation circuit including the Quadrox-i® oxygenator. Methods: Simulated closed-loop extracorporeal membrane oxygenation circuits (1/4 and 3/8 inch) were prepared with a Quadrox-i pediatric and Quadrox-i adult oxygenator and blood primed. In addition, 1/4- and 3/8-inch circuits were also prepared without an oxygenator in series. A one-time dose of voriconazole was administered into the circuits, and serial pre- and post-oxygenator concentrations were obtained at 5 minutes, 1, 2, 3, 4, 5, 6, and 24 hour time points. Voriconazole was also maintained in a glass vial and samples were taken from the vial at the same time periods for control purposes to assess for spontaneous drug degradation Results: For the 1/4-inch circuit, there was an approximate mean of 64-67% voriconazole loss with the oxygenator in series and mean of 15-20% voriconazole loss without an oxygenator in series at 24 hours. For the 3/8-inch circuit, there was an approximate mean of 44-51% voriconazole loss with the oxygenator in series and a mean of 8-12% voriconazole loss without an oxygenator in series at 24 hours. The reference voriconazole concentrations remained relatively constant during the entire study period demonstrating that the drug loss in each size of the extracorporeal membrane oxygenation circuit with or without an oxygenator was not a result of spontaneous drug degradation. Conclusion: This ex vivo investigation demonstrated substantial voriconazole loss within an extracorporeal membrane oxygenation circuit with an oxygenator in series with both sizes of the Quadrox-i oxygenator at 24 hours and no significant voriconazole loss in the absence of an oxygenator. Further evaluations with multiple dose in vitro and in vivo investigations are needed before specific voriconazole dosing recommendations can be made for clinical application with extracorporeal membrane oxygenation.

Стилі APA, Harvard, Vancouver, ISO та ін.

45

Zhao, Zuoqin, Yufei Nai, Zhiguo Yu, Xin Xu, Xiaoyang Cao, and Xiaofeng Gu. "Design of Low-Power ECG Sampling and Compression Circuit." Applied Sciences 13, no. 5 (March 6, 2023): 3350. http://dx.doi.org/10.3390/app13053350.

Повний текст джерела

Анотація:

Compressed Sensing (CS) has been applied to electrocardiogram monitoring in wireless sensor networks, but existing sampling and compression circuits consume too much hardware. This paper proposes a low-power and small-area sampling and compression circuit with an Analog-to-Digital Converter (ADC) and a CS module. The ADC adopts split capacitors to reduce hardware consumption and uses a calibration technique to decrease offset voltage. The CS module uses an approximate addition calculation for compression and stores the compressed data in pulsed latches. The proposed addition completes the accurate calculation of the high part and the approximate calculation of the low part. In a 55 nm CMOS process, the ADC has an area of 0.011 mm2 and a power consumption of 0.214 μW at 10 kHz. Compared with traditional design, the area and power consumption of the proposed CS module are reduced by 19.5% and 31.7%, respectively. The sampling and compression circuit area is 0.325 mm2, and the power consumption is 2.951 μW at 1.2 V and 100 kHz. The compressed data are reconstructed with a percentage root mean square difference of less than 2%. The results indicate that the proposed circuit has performance advantages of hardware consumption and reconstruction quality.

Стилі APA, Harvard, Vancouver, ISO та ін.

46

Rizzo, Roberto Giorgio, and Andrea Calimera. "Implementing Adaptive Voltage Over-Scaling: Algorithmic Noise Tolerance vs. Approximate Error Detection." Journal of Low Power Electronics and Applications 9, no. 2 (April 21, 2019): 17. http://dx.doi.org/10.3390/jlpea9020017.

Повний текст джерела

Анотація:

Adaptive Voltage Over-Scaling can be applied at run-time to reach the best tradeoff between quality of results and energy consumption. This strategy encompasses the concept of timing speculation through some level of approximation. How and on which part of the circuit to implement such approximation is an open issue. This work introduces a quantitative comparison between two complementary strategies: Algorithmic Noise Tolerance and Approximate Error Detection. The first implements a timing speculation by means approximate computing, while the latter exploits a more sophisticated approach that is based on the approximation of the error detection mechanism. The aim of this study was to provide both a qualitative and quantitative analysis on two real-life digital circuits mapped onto a state-of-the-art 28-nm CMOS technology.

Стилі APA, Harvard, Vancouver, ISO та ін.

47

Kalajdzievski, Timjan, and Nicolás Quesada. "Exact and approximate continuous-variable gate decompositions." Quantum 5 (February 8, 2021): 394. http://dx.doi.org/10.22331/q-2021-02-08-394.

Повний текст джерела

Анотація:

We gather and examine in detail gate decomposition techniques for continuous-variable quantum computers and also introduce some new techniques which expand on these methods. Both exact and approximate decomposition methods are studied and gate counts are compared for some common operations. While each having distinct advantages, we find that exact decompositions have lower gate counts whereas approximate techniques can cover decompositions for all continuous-variable operations but require significant circuit depth for a modest precision.

Стилі APA, Harvard, Vancouver, ISO та ін.

48

Brandao, Fernando G. S. L., and Michal Horodecki. "Exponential quantum speed-ups are generic." Quantum Information and Computation 13, no. 11&12 (November 2013): 901–24. http://dx.doi.org/10.26421/qic13.11-12-1.

Повний текст джерела

Анотація:

A central problem in quantum computation is to understand which quantum circuits are useful for exponential speed-ups over classical computation. We address this question in the setting of query complexity and show that for almost any sufficiently long quantum circuit one can construct a black-box problem which is solved by the circuit with a constant number of quantum queries, but which requires exponentially many classical queries, even if the classical machine has the ability to postselect. We prove the result in two steps. In the first, we show that almost any element of an approximate unitary 3-design is useful to solve a certain black-box problem efficiently. The problem is based on a recent oracle construction of Aaronson and gives an exponential separation between quantum and classical post-selected bounded-error query complexities. In the second step, which may be of independent interest, we prove that linear-sized random quantum circuits give an approximate unitary 3-design. The key ingredient in the proof is a technique from quantum many-body theory to lower bound the spectral gap of local quantum Hamiltonians.

Стилі APA, Harvard, Vancouver, ISO та ін.

49

FORBES, PEADAR, SARAH BOYLE, KEITH O'DONOGHUE, and MICHAEL PETER KENNEDY. "ON THE APPROXIMATE ONE-D MAP IN CHUA'S OSCILLATOR." International Journal of Bifurcation and Chaos 15, no. 08 (August 2005): 2545–50. http://dx.doi.org/10.1142/s0218127405013472.

Повний текст джерела

Анотація:

Due to strong contraction in the outer regions of Chua's circuit with piecewise-linear dynamics, the system can be described by an approximate one-dimensional map. We confirm by simulation and experiment that the initial slope of this map is defined by [Formula: see text].

Стилі APA, Harvard, Vancouver, ISO та ін.

50

Rabinovich, Daniil, Richik Sengupta, Ernesto Campos, Vishwanathan Akshay, and Jacob Biamonte. "Progress towards Analytically Optimal Angles in Quantum Approximate Optimisation." Mathematics 10, no. 15 (July 26, 2022): 2601. http://dx.doi.org/10.3390/math10152601.

Повний текст джерела

Анотація:

The quantum approximate optimisation algorithm is a p layer, time variable split operator method executed on a quantum processor and driven to convergence by classical outer-loop optimisation. The classical co-processor varies individual application times of a problem/driver propagator sequence to prepare a state which approximately minimises the problem’s generator. Analytical solutions to choose optimal application times (called parameters or angles) have proven difficult to find, whereas outer-loop optimisation is resource intensive. Here we prove that the optimal quantum approximate optimisation algorithm parameters for p=1 layer reduce to one free variable and in the thermodynamic limit, we recover optimal angles. We moreover demonstrate that conditions for vanishing gradients of the overlap function share a similar form which leads to a linear relation between circuit parameters, independent of the number of qubits. Finally, we present a list of numerical effects, observed for particular system size and circuit depth, which are yet to be explained analytically.

Стилі APA, Harvard, Vancouver, ISO та ін.

Статті в журналах з теми "Approximate Circuit"

Оформте джерело за APA, MLA, Chicago, Harvard та іншими стилями