Дисертації з теми "Approximate Circuit"

We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-optimal results, and finally a simulated annealing method that provides near optimal solutions with runtimes that meet our performance goals. The simulated annealing approach when applied on a ten benchmarks chosen from IWLS 93 benchmark suite, provides watermarking results with edge overhead of less than 6% on average with runtimes not exceeding five minutes.

Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas.
The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.

This thesis is concerned with the utilization of formal verification techniques in the design of the functional approximations of combinational circuits. We thoroughly study the existing formal approaches for the approximate equivalence checking and their utilization in the approximate circuit development. We present a new method that integrates the formal techniques into the Cartesian Genetic Programming. The key idea of our approach is to employ a new search strategy that drives the evolution towards promptly verifiable candidate solutions. The proposed method was implemented within ABC synthesis tool. Various parameters of the search strategy were examined and the algorithm's performance was evaluated on the functional approximations of multipliers and adders with operand widths up to 32 and 128 bits respectively. Achieved results show an unprecedented scalability of our approach.

In recent years, there has been a strong need for the design of integrated  circuits showing low power consumption. It is possible to create intentionally approximate circuits which don't fully implement the specified logic behaviour, but exhibit improvements in term of area, delay and power consumption. These circuits can be used in many error resilient applications, especially in signal and image processing, computer graphics, computer vision and machine learning. This work describes an evolutionary approach to approximate design of arithmetic circuits and other more complex systems. This text presents a parallel calculation of a fitness function. The proposed method accelerated evaluation of 8-bit approximate multiplier 170 times in comparison with the common version. Evolved approximate circuits were used in different types of edge detectors.

Au cours des dernières décennies, la demande d’efficacité informatique n’a cessé de croître. L’affirmation d’applications de nouvelle génération consommatrices d’énergie d’un côté, et d’appareils portables basse consommation de l’autre, exige un nouveau paradigme informatique capable de faire face aux exigences concurrentes des défis technologiques actuels. Ces dernières années, plusieurs études sur les applications dites de "Recognition, Mining and Synthesis (RMS)" ont été menées. Une particularité très intéressante a été identifiée : la résilience intrinsèque de ces applications. Une telle propriété permet aux applications RMS d’être très tolérantes aux erreurs. Ceci est dû à différents facteurs, tels que les données bruyantes traitées par ces applications, les algorithmes non déterministes utilisés et les réponses non uniques possibles. Ces propriétés ont été exploitées par un nouveau paradigme informatique de plus en plus établi : le calcul approximé (AxC). L’AxC profite intelligemment de la résilience intrinsèque des applications RMS pour réaliser des gains en termes de consommation électrique, de temps de fonctionnement et/ou de surface de puce. En effet, en introduisant des assouplissants sélectifs des spécifications non critiques, certaines parties du système informatique cible peuvent être simplifiées, pour finalement atteindre l’objectif de l’AxC. De plus, l’AxC est capable de cibler différentes couches des systèmes informatiques, du matériel au logiciel. Dans cette thèse, nous nous concentrons sur les circuits intégrés approximés (AxICs) qui sont le résultat de l’application AxC au niveau matériel. En particulier, nous nous concentrons sur l’approximation fonctionnelle des circuits intégrés, utilisée au cours des dernières années afin de concevoir efficacement les AxICs. En raison de la pertinence croissante des AxICs, il devient important de relever les nouveaux défis pour tester de tels circuits. À cet égard, certains travaux ont attiré l’attention sur les défis que représente l’approximation fonctionnelle pour les procédures de test. En même temps, l’approximation fonctionnelle des circuits intégrés offre également des possibilités. Plus en détails - d’une part - le concept de circuit acceptable change : alors qu’un circuit est conventionnellement bon si ses réponses ne sont jamais différentes de celles attendues, dans le contexte AxIC certaines réponses inattendues peuvent encore être acceptables. Pour la même raison - d’autre part - certaines fautes acceptables peuvent ne pas être détectées, ce qui mène à un gain de rendement de production (c.-à-d., augmentation du pourcentage de circuits acceptables, parmi tous les circuits fabriqués). Pour mesurer l’erreur produite par un AxIC, plusieurs métriques d’erreur ont été proposées dans la littérature. Dans cette thèse, nous présentons un ensemble de techniques de test pour les circuits approximés. En particulier, nous nous concentrons sur trois phases fondamentales du déroulement du test. Premièrement, la classification des fautes AxIC en non-redundant et ax-redundant (c.-à-d. catastrophique et acceptable, respectivement) en fonction d’un seuil d’erreur (c.-à-d. la quantité maximale tolérable d’erreur). Cette classification permet d’obtenir deux listes de fautes (c.-à-d. nonredundant et ax-redundant). Ensuite, nous proposons une génération automatique de séquences de test qui soit “consciente de l’approximation”. Les tests obtenus préviennent les défaillances catastrophiques en détectant les fautes non-redundant. En même temps, ils minimisent la détection sur les ax-redundant. Enfin – puisque dans certains cas le gain de rendement obtenu ne correspond toujours pas à celui attendu, à cause de la structure propre des AxICs – nous proposons une technique pour classer correctement les AxICs dans les catégories “catastrophiquement défectueux” et “acceptablement défectueux”, après l’application du test
Despite great improvements of the semiconductor industry in terms of energy efficiency, the computer systems’ energy consumption is constantly growing. Many largely used applications – usually referred to as Recognition, Mining and Synthesis (RMS) applications – are more and more deployed as mobile applications and on Internet of Things (IoT) structures. Therefore, it is mandatory to improve the future silicon devices and architectures on which these applications will run. Inherent resiliency property of RMS applications has been thoroughly investigated over the last few years. This interesting property leads applications to be tolerant to errors, as long as their results remain close enough to the expected ones. Approximate Computing (AxC) , is an emerging computing paradigm which takes advantages of this property. AxC has gained increasing interest in the scientific community in last years. It is based on the intuitive observation that introducing selective relaxation of non-critical specifications may lead to efficiency gains in terms of power consumption, run time, and/or chip area. So far, AxC has been applied on the whole digital system stack, from hardware to application level. This work focuses on approximate integrated circuits (AxICs), which are the result of AxC application at hardware-level. Functional approximation has been successfully applied to integrated circuits (ICs) in order to efficiently design AxICs. Specifically, we focus on testing aspects of functionally approximate ICs. In fact – since approximation changes the functional behavior of ICs – techniques to test them have to be revisited. In fact, some previous works – have shown that circuit approximation brings along some challenges for testing procedures, but also some opportunities. In particular, approximation procedures intrinsically lead the circuit to produce errors, which have to be taken into account in test procedures. Error can be measured according to different error metrics. On the one hand, the occurrence of a defect in the circuit can lead it to produce unexpected catastrophic errors. On the other hand, some defects can be tolerated, when they do not induce errors over a certain threshold. This phenomenon could lead to a yield increase, if properly investigated and managed. To deal with such aspects, conventional test flow should be revisited. Therefore, we introduce Approximation-Aware testing (AxA testing). We identify three main AxA testing phases: (i) AxA fault classification, (ii) AxA test pattern generation and (iii) AxA test set application. Briefly, the first phase has to classify faults into catastrophic and acceptable; the test pattern generation has to produce test vectors able to cover all the catastrophic faults and, at the same time, to leave acceptable faults undetected; finally, the test set application needs to correctly classify AxICs under test into catastrophically faulty, acceptably faulty, fault-free. Only AxICs falling into the first group will be rejected. In this thesis, we thoroughly discuss the three phases of AxA testing, and we present a set of AxA test techniques for approximate circuits. Firstly, we work on the classification of AxIC faults into catastrophic and acceptable according to an error threshold (i.e. the maximum tolerable amount of error). This classification provides two lists of faults (i.e. catastrophic and acceptable). Then, we propose an approximation-aware (ax-aware) Automatic Test Pattern Generation. Obtained test patterns prevent catastrophic failures by detecting catastrophic defects. At the same time, they minimize the detection of acceptable ones. Finally – since the AxIC structure often leads to a yield gain lower than expected – we propose a technique to correctly classify AxICs into “catastrophically faulty”, “acceptably faulty”, “and fault-free”, after the test application. To evaluate the proposed techniques, we perform extensive experiments on state-ofthe-art AxICs

La triple redundancia modular (TMR) es una técnica bien conocida de mitigación de fallos que proporciona una alta protección frente a fallos únicos pero con un gran coste en términos de área y consumo de potencia. Por esta razón, la redundancia parcial se suele aplicar para aligerar estos sobrecostes. En este contexto, la TMR aproximada (ATMR), que consisten en la implementación de la redundancia triple con versiones aproximadas del circuito a proteger, ha surgido en los últimos años como una alternativa a la replicación parcial, con la ventaja de obtener mejores soluciones de compromiso entre la cobertura a fallos y los sobrecostes. En la literatura ya han sido propuestas varias técnicas para la generación de circuitos aproximados, cada una con sus pros y sus contras. Este trabajo realiza un estudio de la técnica ATMR, evaluando el coste-beneficio entre el incremento de recursos (área) y la cobertura frente a fallos. La primera contribución es una nueva aproximación ATMR donde todos los módulos redundantes son versiones aproximadas del diseño original, permitiendo la generación de circuitos ATMR con un sobrecoste de área muy reducido, esta técnica se denomina Full-ATMR (ATMR completo o FATMR). El trabajo también presenta una segunda aproximación para implementar la ATMR de forma automática combinando una biblioteca de puertas aproximadas (ApxLib) y un algoritmo genético multi-objetivo (MOOGA). El algoritmo realiza una búsqueda ciega sobre el inmenso espacio de soluciones, optimizando conjuntamente la cobertura frente a fallos y el sobrecoste de área. Los experimentos comparando nuestra aproximación con las técnicas del estado del arte muestran una mejora de los trade-offs para diferentes circuitos de prueba (benchmark).

L'objet de ce travail est la modélisation des lignes de transmission multifilaires dans le domaine temporel. Nous rappelons dans un premier temps les différentes méthodes permettant le calcul des courants et des tensions distribuées sur la ligne de transmission uniforme comportant N conducteurs. Ces méthodes sont souvent limitées pour des lignes à pertes constantes ou faibles, et pour des charges linéaires. D'autre part, elles ont toutefois pour inconvénient majeur d'accroître la durée des calculs d'un facteur directement proportionnel au rapport liant la dimension des lignes à la longueur d'onde. Contrairement à la méthode en cellules cascades, la méthode proposée, basé sur l'approximants de Padé, permet de réduire le nombre de cellules, et par conséquent la durée du calcul. Par ailleurs, elle permet de tenir compte des pertes dépendantes de la fréquence. Cette méthode est représentée par un modèle circuit, facile à implémenter dans les simulateurs circuits, comme Esacap, Spice et Saber. Afin de s'assurer de la stabilité des résultats donnés par ce modèle, une étude a été effectuée à partir de la matrice admittance en utilisant le critère de passivité. Ce modèle est ensuite étendu aux lignes blindées en tenant compte de l'impédance de transfert du blindage. Des exemples d'applications, de simulations issues de la littérature ont été présentés pour valider ce modèle
A transmission line model is presented in this thesis. Various methods allowing calculation of the currents and the tensions distributed on the uniform transmission line. The most of these methods are limited to lines with constants or low losses, and only for linear loads. Using Padé approximant, this proposed model use most variable than the conventional lumped discretization model. The model is suitable for inclusion in general circuit simulator, such as Esacap, Spice and Saber. This method offers an efficient means to discretize transmission lines on real and complexes cells compared to the conventional lumped discretization. In addition, the model can handle frequency-dependent line parameters directly in the time domain. However, the model is extended of shielded cable for coaxial cable and general shielded cable as bundle cable. Numerical examples are presented to demonstrate the validity of the proposed model and to illustrate its application to a variety of cable category

La jonction tunnel magnétique (JTM) commutée par la couple de transfert de spin (STT) a été considérée comme un candidat prometteur pour la prochaine génération de mémoires non-volatiles et de circuits logiques, car elle fournit une solution pour surmonter le goulet d'étranglement de l'augmentation de puissance statique causée par la mise à l'échelle de la technologie CMOS. Cependant, sa commercialisation est limitée par la fiabilité faible, qui se détériore gravement avec la réduction de la taille du dispositif. Cette thèse porte sur l'étude de la fiabilité des circuits basés sur JTM. Tout d'abord, un modèle compact de JTM incluant les problèmes principaux de fiabilité est proposé et validé par la comparaison avec des données expérimentales. Sur la base de ce modèle précis, la fiabilité des circuits typiques est analysée et une méthodologie d'optimisation de la fiabilité est proposée. Enfin, le comportement de commutation stochastique est utilisé dans certaines nouvelles conceptions d'applications classiques
Spin transfer torque magnetic tunnel junction (STT-MTJ) has been considered as a promising candidate for next generation of non-volatile memories and logic circuits, because it provides a perfect solution to overcome the bottleneck of increasing static power caused by CMOS technology scaling. However, its commercialization is limited by the poor reliability, which deteriorates severely with device scaling down. This thesis focuses on the reliability investigation of MTJ based non-volatile circuits. Firstly, a compact model of MTJ including main reliability issues is proposed and validated by the comparison with experimental data. Based on this accurate model, the reliability of typical circuits is analyzed and reliability optimization methodology is proposed. Finally, the stochastic switching behavior is utilized in some new designs of conventional applications

Spotřeba a energetická efektivita se stává jedním z nejdůležitějších parametrů při návrhu počítačových systémů, zejména kvůli omezené kapacitě napájení u zařízení napájených bateriemi a velmi vysoké spotřebě energie rostoucích datacenter a cloudové infrastruktury. Současně jsou uživatelé ochotni do určité míry tolerovat nepřesné nebo chybné výpočty v roustoucím počtu aplikací díky nedokonalostem lidských smyslů, statistické povaze výpočtů, šumu ve vstupních datech apod. Přibližné počítání, nová oblast výzkumu v počítačovém inženýrství, využívá rozvolnění požadavků na funkčnost za účelem zvýšení efektivity počítačových systémů, pokud jde o spotřebu energie, výpočetní výkon či složitost. Aplikace tolerující chyby mohou být implementovány efektivněji a stále sloužit svému účelu se stejnou nebo mírně sníženou kvalitou. Ačkoli se objevují nové metody pro návrh přibližně počítajících výpočetních systémů, je stále nedostatek automatických návrhových metod, které by nabízely velké množství kompromisních řešení dané úlohy. Konvenční metody navíc často produkují řešení, která jsou daleko od optima. Evoluční algoritmy sice přinášejí inovativní řešení složitých optimalizačních a návrhových problémů, nicméně trpí několika nedostatky, např. nízkou škálovatelností či vysokým počtem generací nutných k dosažení konkurenceschopných výsledků. Pro přibližné počítání je vhodný zejména multikriteriální návrh, což existující metody většinou nepodporují. V této práci je představen nový automatický multikriteriální paralelní evoluční algoritmus pro návrh a aproximaci digitálních obvodů. Metoda je založena na kartézském genetickém programování, pro zvýšení škálovatelnosti byla navržena nová vysoce paralelizovaná implementace. Multikriteriální návrh byl založen na principech algoritmu NSGA-II. Výkonnost implementace byla vyhodnocena na několika různých úlohách, konkrétně při návrhu (přibližně počítajících) aritmetických obvodů, Booleovských funkcích s vysokou nelinearitou či přibližných logických obvodů pro tří-modulovou redundanci. V těchto úlohách bylo dosaženo význammých zlepšení ve srovnání se současnými metodami.

Táto práca sa zaoberá využitím aproximovaných obvodov v neurónových sieťach so zámerom prínosu energetických úspor. K tejto téme už existujú štúdie, avšak väčšina z nich bola príliš špecifická k aplikácii alebo bola demonštrovaná v malom rozsahu. Pre dodatočné preskúmanie možností sme preto skrz netriviálne modifikácie open-source frameworku TensorFlow vytvorili platformu umožňujúcu simulovať používanie approximovaných obvodov na populárnych a robustných neurónových sieťach ako Inception alebo MobileNet. Bodom záujmu bolo nahradenie väčšiny výpočtovo náročných častí konvolučných neurónových sietí, ktorými sú konkrétne operácie násobenia v konvolučnách vrstvách. Experimentálne sme ukázali a porovnávali rozličné varianty a aj napriek tomu, že sme postupovali bez preučenia siete sa nám podarilo získať zaujímavé výsledky. Napríklad pri architektúre Inception v4 sme získali takmer 8% úspor, pričom nedošlo k žiadnemu poklesu presnosti. Táto úspora vie rozhodne nájsť uplatnenie v mobilných zariadeniach alebo pri veľkých neurónových sieťach s enormnými výpočtovými nárokmi.

Rozšiřování moderních vestavěných a mobilních systémů napájených bateriemi zvyšuje požadavky na návrh těchto systémů s ohledem na příkon. Přestože moderní návrhové techniky optimalizují příkon, elektrická spotřeba těchto obvodů stále roste díky jejich složitosti. Nicméně existuje celá řada aplikací, kde nepotřebujeme získat úplně přesný výstup. Díky tomu se objevuje technika zvaná aproximativní (přibližné) počítání, která umožňuje za cenu zanesení malé chyby do výpočtu významně redukovat příkon obvodů. V práci se zaměřujeme na použití evolučních algoritmů v této oblasti. Ačkoliv již tyto algoritmy byly úspěšně použity v syntéze přesných i aproximativních obvodů, objevují se problémy škálovatelnosti - schopnosti aproximovat složité obvody. Cílem této disertační práce je ukázat, že aproximační logická syntéza založená na genetickém programování umožňuje dosáhnout vynikajícího kompromisu mezi spotřebou a chybou. Byla provedena analýza čtyř různých aplikacích na třech úrovních popisu. Pomocí kartézského genetického programování s modifikovanou reprezentací jsme snížili spotřebu malých obvodů popsaných na úrovni tranzistorů použitelných například v technologické knihovně. Dále jsme zavedli novou metodu pro aproximaci aritmetických obvodů, jako jsou sčítačky a násobičky, popsaných na úrovni hradel. S využitím metod formální verifikace navíc celý návrhový proces umožňuje garantovat stanovenou chybu aproximace. Tyto obvody byly využity pro významné snížení příkonu v neuronových sítích pro rozpoznávání obrázků a v diskrétní kosinově transformaci v HEVC kodéru. Pomocí nové chybové metriky nezávislé na rozložení vstupních dat jsme navrhli komplexní aproximativní mediánové filtry vhodné pro zpracování signálů. Disertační práce reprezentuje ucelenou metodiku pro návrh aproximativních obvodů na různých úrovních popisu, která navíc garantuje nepřekročení zadané chyby aproximace.

Práce se zabývá metodami pro testování lineárních analogových obvodů v kmitočtové oblasti. Cílem je navrhnout efektivní metody pro automatické generování testovacího plánu. Snížením počtu měření a výpočetní náročnosti lze výrazně snížit náklady za testování. Práce se zabývá multifrekveční parametrickou poruchovou analýzou, která byla plně implementována do programu Matlab. Vhodnou volbou testovacích kmitočtů lze potlačit chyby měření a chyby způsobené výrobními tolerancemi obvodových prvků. Navržené metody pro optimální volbu kmitočtů byly statisticky ověřeny metodou MonteCarlo. Pro zvýšení přesnosti a snížení výpočetní náročnosti poruchové analýzy byly vyvinuty postupy založené na metodě nejmenších čtverců a přibližné symbolické analýze.

Approximate Computing has recently emerged as a promising solution to enhance circuits performance by relaxing the requisite on exact calculations. Multimedia and Machine Learning constitute a typical example of error resilient, albeit compute-intensive, applications. In this dissertation, the design and optimization of approximate fundamental VLSI digital blocks is investigated. In chapter one the theoretical motivations of Approximate Computing, from the VLSI perspective, are discussed. In chapter two my research activity about approximate adders is reported. In this chapter approximate adders for both traditional non-error tolerant applications and error resilient applications are discussed. In chapter three precision-scalable units are investigated. Real-time precision scalability allows adapting the precision level of the unit with the precision requirements of the applications. In this context my research activities regarding approximate Multiply-and-Accumulate and memory units are described. In chapter four a precision-scalable approximate convolver for computer vision applications is discussed. This is composed of both the approximate Multiply-and-Accumulate and memory units, presented in the chapter three.

CMOS technology scaling, the process of shrinking transistor dimensions based on Moore's law, has been the thrust behind increasingly powerful integrated circuits for over half a century. As dimensions are scaled to few tens of nanometers, process and environmental variations can significantly alter transistor characteristics, thus degrading reliability and reducing performance gains in CMOS designs with technology scaling. Although design solutions proposed in recent years to improve reliability of CMOS designs are power-efficient, the performance penalty associated with these solutions further reduces performance gains with technology scaling, and hence these solutions are not well-suited for high-performance designs. This thesis proposes approximate logic circuits as a new logic synthesis paradigm for reliable, high-performance computing systems. Given a specification, an approximate logic circuit is functionally equivalent to the given specification for a "significant" portion of the input space, but has a smaller delay and power as compared to a circuit implementation of the original specification. This contributions of this thesis include (i) a general theory of approximation and efficient algorithms for automated synthesis of approximations for unrestricted random logic circuits, (ii) logic design solutions based on approximate circuits to improve reliability of designs with negligible performance penalty, and (iii) efficient decomposition algorithms based on approxiiii mate circuits to improve performance of designs during logic synthesis. This thesis concludes with other potential applications of approximate circuits and identifies. open problems in logic decomposition and approximate circuit synthesis.

Energy minimization has become an ever more important concern in the design of very large scale integrated circuits (VLSI). In recent years, approximate computing, which is based on the idea of trading off computational accuracy for improved energy efficiency, has attracted significant attention. Applications that are both compute-intensive and error-tolerant are most suitable to adopt approximation strategies. This includes digital signal processing, data mining, machine learning or search algorithms. Such approximations can be achieved at several design levels, ranging from software, algorithm and architecture, down to logic or transistor levels. This dissertation investigates two research threads for the derivation of approximate digital circuits at the logic level: 1) modeling and synthesis of fundamental arithmetic building blocks; 2) automated techniques for synthesizing arbitrary approximate logic circuits under general error specifications. The first thread investigates elementary arithmetic blocks, such as adders and multipliers, which are at the core of all data processing and often consume most of the energy in a circuit. An optimal strategy is developed to reduce energy consumption in timing-starved adders under voltage over-scaling. This allows a formal demonstration that, under quadratic error measures prevalent in signal processing applications, an adder design strategy that separates the most significant bits (MSBs) from the least significant bits (LSBs) is optimal. An optimal conditional bounding (CB) logic is further proposed for the LSBs, which selectively compensates for the occurrence of errors in the MSB part. There is a rich design space of optimal adders defined by different CB solutions. The other thread considers the problem of approximate logic synthesis (ALS) in two-level form. ALS is concerned with formally synthesizing a minimum-cost approximate Boolean function, whose behavior deviates from a specified exact Boolean function in a well-constrained manner. It is established that the ALS problem un-constrained by the frequency of errors is isomorphic to a Boolean relation (BR) minimization problem, and hence can be efficiently solved by existing BR minimizers. An efficient heuristic is further developed which iteratively refines the magnitude-constrained solution to arrive at a two-level representation also satisfying error frequency constraints. To extend the two-level solution into an approach for multi-level approximate logic synthesis (MALS), Boolean network simplifications allowed by external don't cares (EXDCs) are used. The key contribution is in finding non-trivial EXDCs that can maximally approach the external BR and, when applied to the Boolean network, solve the MALS problem constrained by magnitude only. The algorithm then ensures compliance to error frequency constraints by recovering the correct outputs on the sought number of error-producing inputs while aiming to minimize the network cost increase. Experiments have demonstrated the effectiveness of the proposed techniques in deriving approximate circuits. The approximate adders can save up to 60% energy compared to exact adders for a reasonable accuracy. When used in larger systems implementing image-processing algorithms, energy savings of 40% are possible. The logic synthesis approaches generally can produce approximate Boolean functions or networks with complexity reductions ranging from 30% to 50% under small error constraints.
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This work presents different global and local optimization techniques for designing "approximate" circuits which decrease energy consumption, one of the most important criteria in present day circuit design. The concept of "approximate" circuits which trades off energy consumption to output quality, thus creating a new dimension to the design space, is radically different from the conventional design principle in which all circuits operate correctly all the time. But efficient and intelligent designs have to be realized to tap its full potential. These techniques, which have not been explored till date, are based on a rigorous mathematical model and target to improve the output quality of a given circuit keeping the energy consumption to a minimum. They use the value of information and the architecture of the circuit to maximize efficiency. They have been applied to digital signal processing circuits to realize energy savings up to 2X the conventional value.

There is an increasing demand for power converters with small size, light weight, high conversion efficiency and higher power density. Also, in many applications, there is a need for dc-to-dc converters to accept dc input voltage and provide regulated and/or isolated dc output voltage at a desired voltage level including telecommunications equipment, process control systems, and in industry applications. This thesis presents the analysis, design, simulation and experimental results of three-phase high-frequency transformer isolated resonant converters. The first converter presented is a three-phase LCC-type dc-dc resonant converter with capacitor output filter including the effect of the magnetizing inductance of the three-phase HF transformer. The equivalent ac load resistance is derived and the converter is analyzed by using approximation analysis approach. Base on this analysis, design curves have been obtained and a design example is given. Intusoft simulation results for the designed converter are given for various input voltage and for different load conditions. The experimental verification of the designed converter performance was established by building a 300 W rated power converter and the experimental results have been given. It is shown that the converter works in zero-voltage switching (ZVS) at various input voltage and different load conditions. A three-phase (LC)(L)-type dc-dc series-resonant converter with capacitive output filter has been proposed. Operation of the converter has been presented using the operating waveforms and equivalent circuit diagrams during different intervals. An approximate analysis approach is used to analyze the converter operation, and design procedure is presented with a design example. Intusoft simulation results for the designed converter are given for input voltage and load variations. Experimental results obtained in a 300 W converter are presented. Major advantages of this converter are the leakage and magnetizing inductances of the high-frequency transformer are used as part of resonant circuit and the output rectifier voltage is clamped to the output voltage. The converter operates in soft-switching for the inverter switches for the wide variations in supply voltage and load and it requires narrow switching frequency variation (compared to LCC-type) to regulate the output voltage. A three-phase high-frequency transformer isolated interleaved (LC)(L)-type dc-dc series-resonant converter with capacitive output filter using fixed frequency control is proposed. The converter operation for different modes is presented using the operating waveforms and equivalent circuit diagrams during different intervals. This converter is modeled and then analyzed using the approximate complex ac circuit analysis approach. Based on the analysis, design curves were obtained and the design procedure is presented with a design example. The designed converter is simulated using PSIM software to predict the performance of the converter for variations in supply voltage and load conditions. The converter operates in ZVS for the inverter switches with minimum input voltage and loses ZVS for two switches in each bridge for higher input voltages.
Graduate

碩士
逢甲大學
資訊電機工程碩士在職專班
94
This thesis is designing a piece of circuit to generating approximate step waveforms of current mainly. Apply to test the response time of the detecting device of current. Because the biggest current of step waveforms current is up to several dozen amperes. The circuit adopts MOSFET power electronic element to be done for the switch component of the current. The size current of flowing through MOSFET is urged the voltage to control. Drive voltage of step can is it generating approximate step waveforms of current. But rise time of step current must meet the requirement of grade microsecond. It is unable to reach this request that traditional MOSFET circuit designs. This thesis puts forward an improved generating approximate current waveforms circuit design method of the step. And probe into the factor influencing rise time of current in the circuit with the experiment and simulation.

碩士
國立清華大學
資訊工程學系所
105
Recently, threshold logic attracts a lot of attention due to the advances of its physical implementation and the strong binding to neural networks.On the other hand, approximate computing is a new design paradigm that focuses on error-tolerant applications, e.g., machine learning or pattern recognition.In this thesis, we integrate threshold logic with approximate computing and propose a synthesis algorithm to obtain cost-efficient approximate threshold logic circuits with an error rate guarantee.We conduct experiments on a set of IWLS 2005 benchmarks.The experimental results show that the proposed algorithm can efficiently explore the approximability of each benchmark.For a 5\% error rate constraint, the circuit cost can be reduced by 22.8\% on average.

This work investigates energy-efficient approximate computation for solving differential equations. It extends the analog computing techniques to a new paradigm: continuous-time hybrid computation, where both analog and digital circuits operate in continuous time. In this approach, the time intervals in the digital signals contain important information. Unlike conventional synchronous digital circuits, continuous-time digital signals offer the benefits of adaptive power dissipation and no quantization noise. Two prototype chips have been fabricated in 65 nm CMOS technology and tested successfully. The first chip is capable of solving nonlinear differential equations up to 4th order, and the second chip scales up to 16th order based on the first chip. Nonlinear functions are generated by a programmable, clockless, continuous-time 8-bit hybrid architecture (ADC+SRAM+DAC). Digitally-assisted calibration is used in all analog/mixed-signal blocks. Compared to the prior art, our chips makes possible arbitrary nonlinearities and achieves 16 times lower power dissipation, thanks to technology scaling and extensive use of class-AB analog blocks. Typically, the unit achieves a computational accuracy of about 0.5% to 5% RMS, solution times from a fraction of 1 micro second to several hundred micro seconds, and total computational energy from a fraction of 1 nJ to hundreds of nJ, depending on equation details. Very significant advantages are observed in computational speed and energy (over two orders of magnitude and over one order of magnitude, respectively) compared to those obtained with a modern MSP430 microcontroller for the same RMS error.

Lead is a highly toxic metal that has been used by humans for over 2000 years. Over this time it has become increasingly apparent that despite its usefulness, lead is one of the most highly toxic substances known to man. Current research into lead exposure of humans focuses on low-level chronic exposure and its effects on learning and behaviour. However, investigations into lead exposure of wildlife are still focussed on mortalities, particularly of waterfowl and raptors, with little known about low-level exposures or the effects on other species. This study examines the exposure of free-ranging kea (Nestor notabilis) from the Aoraki/ Mt Cook village and national park, takahe (Porphyrio hochstetteri) from Tiritiri Matangi, Kapiti and Mana Islands, and the lead associated syndrome of clenched-claw paralysis and leg paresis in harriers (Circus approximans) in New Zealand. Thirty-eight kea had detectable blood lead with concentrations ranging from 0.028 mg/L to 3.43 mg/L (mean = 0.428 mg/L ± 0.581). Analysis of tissue samples found that seven of 15 birds died with elevated tissue lead. Lead exposure may be an important contributing factor in kea mortality. As a result of these findings, lead abatement in areas frequented by kea is being considered. Eighteen of 45 takahe had detectable blood lead concentrations ranging from 0.015 mg/L to 0.148 mg/L (mean = 0.028 mg/L ± 0.042). Analysis of tissue samples from offshore island and Murchison Mountains birds found that all had detectable lead. Despite levels of lead exposure in the population being low and unlikely to result in overt clinical signs, it is widespread and there may be significant exposure of birds living around old buildings. An investigation into the clinical signs, pathology and response to treatment of clenched-claw paralysis and leg paresis in wild harriers was carried out. Harriers with clenched feet had significantly higher blood lead concentrations than those without. In conclusion, lead is a major factor in the expression of this clinical syndrome but other factors not yet identified are playing a role. This study demonstrates that lead is widespread in the New Zealand environment exposing a diverse range of avifauna, and has made some progress towards exploring some of its effects on health and survival.