Готові списки джерел за темами / Approximate Circuit

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Опубліковано: 14 березня 2023

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Статті в журналах з теми "Approximate Circuit"

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Balasubramanian, Padmanabhan, Raunaq Nayar, Okkar Min, and Douglas L. Maskell. "Approximator: A Software Tool for Automatic Generation of Approximate Arithmetic Circuits." Computers 11, no. 1 (January 8, 2022): 11. http://dx.doi.org/10.3390/computers11010011.

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Анотація:
Approximate arithmetic circuits are an attractive alternative to accurate arithmetic circuits because they have significantly reduced delay, area, and power, albeit at the cost of some loss in accuracy. By keeping errors due to approximate computation within acceptable limits, approximate arithmetic circuits can be used for various practical applications such as digital signal processing, digital filtering, low power graphics processing, neuromorphic computing, hardware realization of neural networks for artificial intelligence and machine learning etc. The degree of approximation that can be incorporated into an approximate arithmetic circuit tends to vary depending on the error resiliency of the target application. Given this, the manual coding of approximate arithmetic circuits corresponding to different degrees of approximation in a hardware description language (HDL) may be a cumbersome and a time-consuming process—more so when the circuit is big. Therefore, a software tool that can automatically generate approximate arithmetic circuits of any size corresponding to a desired accuracy would not only aid the design flow but also help to improve a designer’s productivity by speeding up the circuit/system development. In this context, this paper presents ‘Approximator’, which is a software tool developed to automatically generate approximate arithmetic circuits based on a user’s specification. Approximator can automatically generate Verilog HDL codes of approximate adders and multipliers of any size based on the novel approximate arithmetic circuit architectures proposed by us. The Verilog HDL codes output by Approximator can be used for synthesis in an FPGA or ASIC (standard cell based) design environment. Additionally, the tool can perform error and accuracy analyses of approximate arithmetic circuits. The salient features of the tool are illustrated through some example screenshots captured during different stages of the tool use. Approximator has been made open-access on GitHub for the benefit of the research community, and the tool documentation is provided for the user’s reference.
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2

Visweswariah, C., and R. A. Rohrer. "Piecewise approximate circuit simulation." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, no. 7 (July 1991): 861–70. http://dx.doi.org/10.1109/43.87597.

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Koseoglu, Murat, Furkan Nur Deniz, Baris Baykant Alagoz, Ali Yuce, and Nusret Tan. "An experimental analog circuit realization of Matsuda’s approximate fractional-order integral operators for industrial electronics." Engineering Research Express 3, no. 4 (December 1, 2021): 045041. http://dx.doi.org/10.1088/2631-8695/ac3e11.

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Abstract Analog circuit realization of fractional order (FO) elements is a significant step for the industrialization of FO control systems because of enabling a low-cost, electric circuit realization by means of standard industrial electronics components. This study demonstrates an effective operational amplifier-based analog circuit realization of approximate FO integral elements for industrial electronics. To this end, approximate transfer function models of FO integral elements, which are calculated by using Matsuda’s approximation method, are decomposed into the sum of low-pass filter forms according to the partial fraction expansion. Each partial fraction term is implemented by using low-pass filters and amplifier circuits, and these circuits are combined with a summing amplifier to compose the approximate FO integral circuits. Widely used low-cost industrial electronics components, which are LF347N opamps, resistor and capacitor components, are used to achieve a discrete, easy-to-build analog realization of the approximate FO integral elements. The performance of designed circuit is compared with performance of Krishna’s FO circuit design and performance improvements are shown. The study presents design, performance validation and experimental verification of this straightforward approximate FO integral realization method.
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4

Yang, Zhixi, Xianbin Li, and Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction." Journal of Circuits, Systems and Computers 29, no. 15 (June 30, 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.

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Анотація:
Approximate arithmetic circuits have been considered as an innovative circuit paradigm with improved performance for error-resilient applications which could tolerant certain loss of accuracy. In this paper, a novel approximate multiplier with a different scheme of partial product reduction is proposed. An analysis of accuracy (measured by error distance, pass rate and accuracy of amplitude) as well as circuit-based design metrics (power, delay and area, etc.) is utilized to assess the performance of the proposed approximate multiplier. Extensive simulation results show that the proposed design achieves a higher accuracy than the other approximate multipliers from the previous works. Moreover, the proposed design has a better performance under comprehensive comparisons taking both accuracy and circuit-related metrics into considerations. In addition, an error detection and correction (EDC) circuit is used to correct the approximate results to accurate results. Compared with the exact Wallace tree multiplier, the proposed approximate multiplier design with the error detection and correction circuit still has up to 15% and 10% saving for power and delay, respectively.
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Ykuntam, Yamini Devi, Bujjibabu Penumutchi, Bala Srinivas Peteti, and Satyanarayana Vella. "Performance Evaluation of Approximate Adders: Case Study." International Journal of Engineering and Advanced Technology 12, no. 1 (October 30, 2022): 68–75. http://dx.doi.org/10.35940/ijeat.a3836.1012122.

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Анотація:
A computing device designed to carry out a variety of arithmetic computations. The adder circuit, whose operation must be quick with a small area of occupancy, performs the addition, which is a necessary operation in many other mathematical operations including subtraction, multiplication, and division. There is a mandate for an adder circuit with minimal power consumption, minimal delay, and minimal size in various real-time applications such as processing of signals, pictures & video, VLSI data pathways, processors, neural networks, and many more. There is a new class of adders called approximation adders that operate inaccurately but with favorable area, speed, and power consumption. Since their output is inaccurate, the other names for approximate adders are imprecise adders. This set of adders operates at a high speed thanks to a circuit critical path design that uses fewer components. Additionally, compared to precise adders, the approximate adder circuit has a relatively low component count, resulting in a small footprint and circuits that use less energy. There are different ways to create approximate adders. The area can be predicted by counting the number of circuit components that are present. By examining a number of the critical path’s components, delay can be predicted. Several errors that appear in the output of the particular circuit can be used to calculate the accuracy percentage. This review compares approximate adders from four different categories across the board in terms of design constraints and makes note of the differences between each adder.
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Osta, Mario, Ali Ibrahim, and Maurizio Valle. "Approximate Computing Circuits for Embedded Tactile Data Processing." Electronics 11, no. 2 (January 8, 2022): 190. http://dx.doi.org/10.3390/electronics11020190.

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Анотація:
In this paper, we demonstrate the feasibility and efficiency of approximate computing techniques (ACTs) in the embedded Support Vector Machine (SVM) tensorial kernel circuit implementation in tactile sensing systems. Improving the performance of the embedded SVM in terms of power, area, and delay can be achieved by implementing approximate multipliers in the SVD. Singular Value Decomposition (SVD) is the main computational bottleneck of the tensorial kernel approach; since digital multipliers are extensively used in SVD implementation, we aim to optimize the implementation of the multiplier circuit. We present the implementation of the approximate SVD circuit based on the Approximate Baugh-Wooley (Approx-BW) multiplier. The approximate SVD achieves an energy consumption reduction of up to 16% at the cost of a Mean Relative Error decrease (MRE) of less than 5%. We assess the impact of the approximate SVD on the accuracy of the classification; showing that approximate SVD increases the Error rate (Err) within a range of one to eight percent. Besides, we propose a hybrid evaluation test approach that consists of implementing three different approximate SVD circuits having different numbers of approximated Least Significant Bits (LSBs). The results show that energy consumption is reduced by more than five percent with the same accuracy loss.
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7

Joshi, Viraj, Pravin Mane, and Bits Pilani. "Approximate Arithmetic Circuit Design for Error Resilient Applications." International Journal of VLSI Design & Communication Systems 13, no. 1/2/3/4/5/6 (December 30, 2022): 01–16. http://dx.doi.org/10.5121/vlsic.2022.13601.

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Анотація:
When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on performance are rapidly getting replaced by approximate arithmetic circuits which are the need of the hour, and so on about their design.
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Barnes, Christopher L., Daniel Bonnéry, and Albert Cardona. "Synaptic counts approximate synaptic contact area in Drosophila." PLOS ONE 17, no. 4 (April 4, 2022): e0266064. http://dx.doi.org/10.1371/journal.pone.0266064.

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Анотація:
The pattern of synaptic connections among neurons defines the circuit structure, which constrains the computations that a circuit can perform. The strength of synaptic connections is costly to measure yet important for accurate circuit modeling. Synaptic surface area has been shown to correlate with synaptic strength, yet in the emerging field of connectomics, most studies rely instead on the counts of synaptic contacts between two neurons. Here we quantified the relationship between synaptic count and synaptic area as measured from volume electron microscopy of the larval Drosophila central nervous system. We found that the total synaptic surface area, summed across all synaptic contacts from one presynaptic neuron to a postsynaptic one, can be accurately predicted solely from the number of synaptic contacts, for a variety of neurotransmitters. Our findings support the use of synaptic counts for approximating synaptic strength when modeling neural circuits.
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Bhargav, Avireni, and Phat Huynh. "Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs." Sensors 21, no. 24 (December 8, 2021): 8203. http://dx.doi.org/10.3390/s21248203.

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Анотація:
Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.
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Goyal, Candy, Jagpal Singh Ubhi, and Balwinder Raj. "A Reliable Leakage Reduction Technique for Approximate Full Adder with Reduced Ground Bounce Noise." Mathematical Problems in Engineering 2018 (December 16, 2018): 1–16. http://dx.doi.org/10.1155/2018/3501041.

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Анотація:
In this paper, an effective and reliable sleep circuit is proposed, which not only reduces leakage power but also shows significant reduction in ground bounce noise (GBN) in approximate full adder (FA) circuits. Four 1-bit approximate FA circuits are modified using proposed sleep circuit which uses one NMOS and one PMOS transistor. The design metrics such as average power, delay, power delay product (PDP), leakage power, and GBN are compared with nine other 1-bit FA circuits reported till date. All the comparisons are done using post-layout netlist at 45nm technology. The modified designs achieve reduction in leakage power and GBN up to 60% and 80%, respectively, as compared to the best reported approximate FA circuits. The modified approximate FA also achieves 83% reduction in leakage power as compared to conventional FA. Finally, application level metrics such as peak signal to noise ratio (PSNR) are considered to measure the performance of all the proposed approximate FAs.
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Більше джерел

Дисертації з теми "Approximate Circuit"

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Meana, Richard William Piper. "Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware." Scholar Commons, 2013. http://scholarcommons.usf.edu/etd/4728.

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Анотація:
We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-optimal results, and finally a simulated annealing method that provides near optimal solutions with runtimes that meet our performance goals. The simulated annealing approach when applied on a ten benchmarks chosen from IWLS 93 benchmark suite, provides watermarking results with edge overhead of less than 6% on average with runtimes not exceeding five minutes.
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2

Martins, Mayler Gama Alvarenga. "Applications of functional composition for CMOS and emerging technologies." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2015. http://hdl.handle.net/10183/164452.

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Os avanços da indústria de semicondutores nas últimas décadas foram baseados fortemente na contínua redução de tamanho dos dispositivos CMOS fabricados. Os usos de dispositivos CMOS dependem profundamente da lógica de portas E/OU/INV. À medida que os dispositivos CMOS estão atingindo oslimites fisicos, pesquisadores aumento esforço para prolongar a vida útil da tecnologia CMOS. Também é necessário investigar dispositivos alternativos, que em muitos casos implicam no uso de operações lógicas básicas diferentes. Como as ferramentas comerciais de síntese não são capazes de manipular eficientemente estas tecnologias Esta tese de doutorado foca em produzir algoritmos eficientes para projeto de circuitos tanto em CMOS quanto em novas tecnologias, integrando estes algorithmos em fluxos de projeto. Para esta tarefa, aplicamos a técnica da composição functional, para sintetizar eficiente tanto em CMOS quanto em tecnologias emergentes. A composição funcional é uma abordagem de síntese de baixo para cima, provendo flexibilidade para implementar algoritmos com resultados ótimos ou sub-ótimos para diferentes tecnologias. A fim de investigar como a composição funcional se compara às abordagens de síntese estado-da-arte, propomos aplicar esse paradigma de síntese em seis cenários diferentes. Dois deles se concentram em circuitos baseados em CMOS e outros quatro em circuitos baseados em tecnologias emergentes. Em relação a circuitos baseados em CMOS, investigamos a composição funcional para fatoração de funções multi-saídas, aplicadas em um fluxo de resíntese. Também manipulamos funções aproximadas, a fim de sintetizar módulos de redundância tripla aproximada. No que diz respeito as tecnologias emergentes, exploramos a composição funcional através de diodos spintrônicos e outras abordagens promissoras com base em diferentes implementações de lógica: a lógica de limiar, lógica majoritária e lógica de implicação. Resultados apresentam uma melhoria considerável em relação aos métodos estadoda- arte tanto para aplicações CMOS quanto aplicações de tecnologias emergentes, demonstrando a capacidade de lidar com diferentes tecnologias e mostrando a possibilidade de melhorar tecnologias ainda não exploradas.
The advances in semiconductor industry over the last decades have been strongly based on continuous scaling down of dimensions in manufactured CMOS devices. The use of CMOS devices profoundly relies on AND/OR/Inverter logic. As the CMOS scaling is reaching its physical limits, researchers increase the effort to prolong the CMOS life. Also, it is necessary to investigate alternative devices, which in many cases implies the use of different basic logic operations. As the commercial synthesis tools are not able to handle these technologies efficiently, there is an opportunity to research alternative logic implementations better suited for these new devices. This thesis focuses on presenting efficient algorithms to design circuits in both CMOS and new technologies while integrating these algorithms into regular design flows. For this task, we apply the functional composition technique, to efficiently synthesize both CMOS and emerging technologies. The functional composition is a bottom-up synthesis approach, providing flexibility to implement algorithms with optimal or suboptimal results for different technologies. To investigate how the functional composition compares to the state-of-the-art synthesis methods, we propose to apply this synthesis paradigm into six different scenarios. Two of them focus on CMOS-based circuits, and other four are based on emerging technologies. Regarding CMOSbased circuits, we investigate functional composition to investigate multi-output factorization in a circuit resynthesis flow. Also, we manipulate approximate functions to synthesize approximate triple modular redundancy (ATMR) modules. Concerning emerging technologies, we explore functional composition over spin-diode circuits and other promising approaches based on different logic implementations: threshold logic, majority logic, and implication logic. Results present a considerable improvement over the state-of-the-art methods for both CMOS and emerging technologies applications, demonstrating the ability to handle different technologies and showing the possibility to improve technologies not explored yet.
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3

Matyáš, Jiří. "Využití přibližné ekvivalence při návrhu přibližných obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363841.

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Анотація:
This thesis is concerned with the utilization of formal verification techniques in the design of the functional approximations of combinational circuits. We thoroughly study the existing formal approaches for the approximate equivalence checking and their utilization in the approximate circuit development. We present a new method that integrates the formal techniques into the Cartesian Genetic Programming. The key idea of our approach is to employ a new search strategy that drives the evolution towards promptly verifiable candidate solutions. The proposed method was implemented within ABC synthesis tool. Various parameters of the search strategy were examined and the algorithm's performance was evaluated on the functional approximations of multipliers and adders with operand widths up to 32 and 128 bits respectively. Achieved results show an unprecedented scalability of our approach.
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4

RIZZO, ROBERTO GIORGIO. "Energy-Accuracy Scaling in Digital ICs: Static and Adaptive Design Methods and Tools." Doctoral thesis, Politecnico di Torino, 2019. http://hdl.handle.net/11583/2743228.

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5

Dvořáček, Petr. "Evoluční návrh pro aproximaci obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2015. http://www.nusl.cz/ntk/nusl-234958.

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Анотація:
In recent years, there has been a strong need for the design of integrated  circuits showing low power consumption. It is possible to create intentionally approximate circuits which don't fully implement the specified logic behaviour, but exhibit improvements in term of area, delay and power consumption. These circuits can be used in many error resilient applications, especially in signal and image processing, computer graphics, computer vision and machine learning. This work describes an evolutionary approach to approximate design of arithmetic circuits and other more complex systems. This text presents a parallel calculation of a fitness function. The proposed method accelerated evaluation of 8-bit approximate multiplier 170 times in comparison with the common version. Evolved approximate circuits were used in different types of edge detectors.
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6

Traiola, Marcello. "TEST TECHNIQUES FOR APPROXIMATE DIGITAL CIRCUITS." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS060.

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Анотація:
Au cours des dernières décennies, la demande d’efficacité informatique n’a cessé de croître. L’affirmation d’applications de nouvelle génération consommatrices d’énergie d’un côté, et d’appareils portables basse consommation de l’autre, exige un nouveau paradigme informatique capable de faire face aux exigences concurrentes des défis technologiques actuels. Ces dernières années, plusieurs études sur les applications dites de "Recognition, Mining and Synthesis (RMS)" ont été menées. Une particularité très intéressante a été identifiée : la résilience intrinsèque de ces applications. Une telle propriété permet aux applications RMS d’être très tolérantes aux erreurs. Ceci est dû à différents facteurs, tels que les données bruyantes traitées par ces applications, les algorithmes non déterministes utilisés et les réponses non uniques possibles. Ces propriétés ont été exploitées par un nouveau paradigme informatique de plus en plus établi : le calcul approximé (AxC). L’AxC profite intelligemment de la résilience intrinsèque des applications RMS pour réaliser des gains en termes de consommation électrique, de temps de fonctionnement et/ou de surface de puce. En effet, en introduisant des assouplissants sélectifs des spécifications non critiques, certaines parties du système informatique cible peuvent être simplifiées, pour finalement atteindre l’objectif de l’AxC. De plus, l’AxC est capable de cibler différentes couches des systèmes informatiques, du matériel au logiciel. Dans cette thèse, nous nous concentrons sur les circuits intégrés approximés (AxICs) qui sont le résultat de l’application AxC au niveau matériel. En particulier, nous nous concentrons sur l’approximation fonctionnelle des circuits intégrés, utilisée au cours des dernières années afin de concevoir efficacement les AxICs. En raison de la pertinence croissante des AxICs, il devient important de relever les nouveaux défis pour tester de tels circuits. À cet égard, certains travaux ont attiré l’attention sur les défis que représente l’approximation fonctionnelle pour les procédures de test. En même temps, l’approximation fonctionnelle des circuits intégrés offre également des possibilités. Plus en détails - d’une part - le concept de circuit acceptable change : alors qu’un circuit est conventionnellement bon si ses réponses ne sont jamais différentes de celles attendues, dans le contexte AxIC certaines réponses inattendues peuvent encore être acceptables. Pour la même raison - d’autre part - certaines fautes acceptables peuvent ne pas être détectées, ce qui mène à un gain de rendement de production (c.-à-d., augmentation du pourcentage de circuits acceptables, parmi tous les circuits fabriqués). Pour mesurer l’erreur produite par un AxIC, plusieurs métriques d’erreur ont été proposées dans la littérature. Dans cette thèse, nous présentons un ensemble de techniques de test pour les circuits approximés. En particulier, nous nous concentrons sur trois phases fondamentales du déroulement du test. Premièrement, la classification des fautes AxIC en non-redundant et ax-redundant (c.-à-d. catastrophique et acceptable, respectivement) en fonction d’un seuil d’erreur (c.-à-d. la quantité maximale tolérable d’erreur). Cette classification permet d’obtenir deux listes de fautes (c.-à-d. nonredundant et ax-redundant). Ensuite, nous proposons une génération automatique de séquences de test qui soit “consciente de l’approximation”. Les tests obtenus préviennent les défaillances catastrophiques en détectant les fautes non-redundant. En même temps, ils minimisent la détection sur les ax-redundant. Enfin – puisque dans certains cas le gain de rendement obtenu ne correspond toujours pas à celui attendu, à cause de la structure propre des AxICs – nous proposons une technique pour classer correctement les AxICs dans les catégories “catastrophiquement défectueux” et “acceptablement défectueux”, après l’application du test
Despite great improvements of the semiconductor industry in terms of energy efficiency, the computer systems’ energy consumption is constantly growing. Many largely used applications – usually referred to as Recognition, Mining and Synthesis (RMS) applications – are more and more deployed as mobile applications and on Internet of Things (IoT) structures. Therefore, it is mandatory to improve the future silicon devices and architectures on which these applications will run. Inherent resiliency property of RMS applications has been thoroughly investigated over the last few years. This interesting property leads applications to be tolerant to errors, as long as their results remain close enough to the expected ones. Approximate Computing (AxC) , is an emerging computing paradigm which takes advantages of this property. AxC has gained increasing interest in the scientific community in last years. It is based on the intuitive observation that introducing selective relaxation of non-critical specifications may lead to efficiency gains in terms of power consumption, run time, and/or chip area. So far, AxC has been applied on the whole digital system stack, from hardware to application level. This work focuses on approximate integrated circuits (AxICs), which are the result of AxC application at hardware-level. Functional approximation has been successfully applied to integrated circuits (ICs) in order to efficiently design AxICs. Specifically, we focus on testing aspects of functionally approximate ICs. In fact – since approximation changes the functional behavior of ICs – techniques to test them have to be revisited. In fact, some previous works – have shown that circuit approximation brings along some challenges for testing procedures, but also some opportunities. In particular, approximation procedures intrinsically lead the circuit to produce errors, which have to be taken into account in test procedures. Error can be measured according to different error metrics. On the one hand, the occurrence of a defect in the circuit can lead it to produce unexpected catastrophic errors. On the other hand, some defects can be tolerated, when they do not induce errors over a certain threshold. This phenomenon could lead to a yield increase, if properly investigated and managed. To deal with such aspects, conventional test flow should be revisited. Therefore, we introduce Approximation-Aware testing (AxA testing). We identify three main AxA testing phases: (i) AxA fault classification, (ii) AxA test pattern generation and (iii) AxA test set application. Briefly, the first phase has to classify faults into catastrophic and acceptable; the test pattern generation has to produce test vectors able to cover all the catastrophic faults and, at the same time, to leave acceptable faults undetected; finally, the test set application needs to correctly classify AxICs under test into catastrophically faulty, acceptably faulty, fault-free. Only AxICs falling into the first group will be rejected. In this thesis, we thoroughly discuss the three phases of AxA testing, and we present a set of AxA test techniques for approximate circuits. Firstly, we work on the classification of AxIC faults into catastrophic and acceptable according to an error threshold (i.e. the maximum tolerable amount of error). This classification provides two lists of faults (i.e. catastrophic and acceptable). Then, we propose an approximation-aware (ax-aware) Automatic Test Pattern Generation. Obtained test patterns prevent catastrophic failures by detecting catastrophic defects. At the same time, they minimize the detection of acceptable ones. Finally – since the AxIC structure often leads to a yield gain lower than expected – we propose a technique to correctly classify AxICs into “catastrophically faulty”, “acceptably faulty”, “and fault-free”, after the test application. To evaluate the proposed techniques, we perform extensive experiments on state-ofthe-art AxICs
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7

Albandes, Iuri. "Use of Approximate Triple Modular Redundancy for Fault Tolerance in Digital Circuits." Doctoral thesis, Universidad de Alicante, 2018. http://hdl.handle.net/10045/88248.

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La triple redundancia modular (TMR) es una técnica bien conocida de mitigación de fallos que proporciona una alta protección frente a fallos únicos pero con un gran coste en términos de área y consumo de potencia. Por esta razón, la redundancia parcial se suele aplicar para aligerar estos sobrecostes. En este contexto, la TMR aproximada (ATMR), que consisten en la implementación de la redundancia triple con versiones aproximadas del circuito a proteger, ha surgido en los últimos años como una alternativa a la replicación parcial, con la ventaja de obtener mejores soluciones de compromiso entre la cobertura a fallos y los sobrecostes. En la literatura ya han sido propuestas varias técnicas para la generación de circuitos aproximados, cada una con sus pros y sus contras. Este trabajo realiza un estudio de la técnica ATMR, evaluando el coste-beneficio entre el incremento de recursos (área) y la cobertura frente a fallos. La primera contribución es una nueva aproximación ATMR donde todos los módulos redundantes son versiones aproximadas del diseño original, permitiendo la generación de circuitos ATMR con un sobrecoste de área muy reducido, esta técnica se denomina Full-ATMR (ATMR completo o FATMR). El trabajo también presenta una segunda aproximación para implementar la ATMR de forma automática combinando una biblioteca de puertas aproximadas (ApxLib) y un algoritmo genético multi-objetivo (MOOGA). El algoritmo realiza una búsqueda ciega sobre el inmenso espacio de soluciones, optimizando conjuntamente la cobertura frente a fallos y el sobrecoste de área. Los experimentos comparando nuestra aproximación con las técnicas del estado del arte muestran una mejora de los trade-offs para diferentes circuitos de prueba (benchmark).
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Rouijaa, Hicham. "Modelisation des lignes de transmission multiconducteurs par la méthode des approximants de Padé : approche circuit." Aix-Marseille 3, 2004. http://www.theses.fr/2004AIX30011.

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L'objet de ce travail est la modélisation des lignes de transmission multifilaires dans le domaine temporel. Nous rappelons dans un premier temps les différentes méthodes permettant le calcul des courants et des tensions distribuées sur la ligne de transmission uniforme comportant N conducteurs. Ces méthodes sont souvent limitées pour des lignes à pertes constantes ou faibles, et pour des charges linéaires. D'autre part, elles ont toutefois pour inconvénient majeur d'accroître la durée des calculs d'un facteur directement proportionnel au rapport liant la dimension des lignes à la longueur d'onde. Contrairement à la méthode en cellules cascades, la méthode proposée, basé sur l'approximants de Padé, permet de réduire le nombre de cellules, et par conséquent la durée du calcul. Par ailleurs, elle permet de tenir compte des pertes dépendantes de la fréquence. Cette méthode est représentée par un modèle circuit, facile à implémenter dans les simulateurs circuits, comme Esacap, Spice et Saber. Afin de s'assurer de la stabilité des résultats donnés par ce modèle, une étude a été effectuée à partir de la matrice admittance en utilisant le critère de passivité. Ce modèle est ensuite étendu aux lignes blindées en tenant compte de l'impédance de transfert du blindage. Des exemples d'applications, de simulations issues de la littérature ont été présentés pour valider ce modèle
A transmission line model is presented in this thesis. Various methods allowing calculation of the currents and the tensions distributed on the uniform transmission line. The most of these methods are limited to lines with constants or low losses, and only for linear loads. Using Padé approximant, this proposed model use most variable than the conventional lumped discretization model. The model is suitable for inclusion in general circuit simulator, such as Esacap, Spice and Saber. This method offers an efficient means to discretize transmission lines on real and complexes cells compared to the conventional lumped discretization. In addition, the model can handle frequency-dependent line parameters directly in the time domain. However, the model is extended of shielded cable for coaxial cable and general shielded cable as bundle cable. Numerical examples are presented to demonstrate the validity of the proposed model and to illustrate its application to a variety of cable category
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Wang, You. "Analyse de fiabilité de circuits logiques et de mémoire basés sur dispositif spintronique." Thesis, Paris, ENST, 2017. http://www.theses.fr/2017ENST0005/document.

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La jonction tunnel magnétique (JTM) commutée par la couple de transfert de spin (STT) a été considérée comme un candidat prometteur pour la prochaine génération de mémoires non-volatiles et de circuits logiques, car elle fournit une solution pour surmonter le goulet d'étranglement de l'augmentation de puissance statique causée par la mise à l'échelle de la technologie CMOS. Cependant, sa commercialisation est limitée par la fiabilité faible, qui se détériore gravement avec la réduction de la taille du dispositif. Cette thèse porte sur l'étude de la fiabilité des circuits basés sur JTM. Tout d'abord, un modèle compact de JTM incluant les problèmes principaux de fiabilité est proposé et validé par la comparaison avec des données expérimentales. Sur la base de ce modèle précis, la fiabilité des circuits typiques est analysée et une méthodologie d'optimisation de la fiabilité est proposée. Enfin, le comportement de commutation stochastique est utilisé dans certaines nouvelles conceptions d'applications classiques
Spin transfer torque magnetic tunnel junction (STT-MTJ) has been considered as a promising candidate for next generation of non-volatile memories and logic circuits, because it provides a perfect solution to overcome the bottleneck of increasing static power caused by CMOS technology scaling. However, its commercialization is limited by the poor reliability, which deteriorates severely with device scaling down. This thesis focuses on the reliability investigation of MTJ based non-volatile circuits. Firstly, a compact model of MTJ including main reliability issues is proposed and validated by the comparison with experimental data. Based on this accurate model, the reliability of typical circuits is analyzed and reliability optimization methodology is proposed. Finally, the stochastic switching behavior is utilized in some new designs of conventional applications
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Hrbáček, Radek. "Automatický multikriteriální paralelní evoluční návrh a aproximace obvodů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412591.

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Spotřeba a energetická efektivita se stává jedním z nejdůležitějších parametrů při návrhu počítačových systémů, zejména kvůli omezené kapacitě napájení u zařízení napájených bateriemi a velmi vysoké spotřebě energie rostoucích datacenter a cloudové infrastruktury. Současně jsou uživatelé ochotni do určité míry tolerovat nepřesné nebo chybné výpočty v roustoucím počtu aplikací díky nedokonalostem lidských smyslů, statistické povaze výpočtů, šumu ve vstupních datech apod. Přibližné počítání, nová oblast výzkumu v počítačovém inženýrství, využívá rozvolnění požadavků na funkčnost za účelem zvýšení efektivity počítačových systémů, pokud jde o spotřebu energie, výpočetní výkon či složitost. Aplikace tolerující chyby mohou být implementovány efektivněji a stále sloužit svému účelu se stejnou nebo mírně sníženou kvalitou. Ačkoli se objevují nové metody pro návrh přibližně počítajících výpočetních systémů, je stále nedostatek automatických návrhových metod, které by nabízely velké množství kompromisních řešení dané úlohy. Konvenční metody navíc často produkují řešení, která jsou daleko od optima. Evoluční algoritmy sice přinášejí inovativní řešení složitých optimalizačních a návrhových problémů, nicméně trpí několika nedostatky, např. nízkou škálovatelností či vysokým počtem generací nutných k dosažení konkurenceschopných výsledků. Pro přibližné počítání je vhodný zejména multikriteriální návrh, což existující metody většinou nepodporují. V této práci je představen nový automatický multikriteriální paralelní evoluční algoritmus pro návrh a aproximaci digitálních obvodů. Metoda je založena na kartézském genetickém programování, pro zvýšení škálovatelnosti byla navržena nová vysoce paralelizovaná implementace. Multikriteriální návrh byl založen na principech algoritmu NSGA-II. Výkonnost implementace byla vyhodnocena na několika různých úlohách, konkrétně při návrhu (přibližně počítajících) aritmetických obvodů, Booleovských funkcích s vysokou nelinearitou či přibližných logických obvodů pro tří-modulovou redundanci. V těchto úlohách bylo dosaženo význammých zlepšení ve srovnání se současnými metodami.
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Книги з теми "Approximate Circuit"

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Ullah, Salim, and Akash Kumar. Approximate Arithmetic Circuit Architectures for FPGA-based Systems. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-21294-9.

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Reda, Sherief, and Muhammad Shafique, eds. Approximate Circuits. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-99322-5.

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Ullah, Salim, and Akash Kumar. Approximate Arithmetic Circuit Architectures for FPGA-Based Systems. Springer International Publishing AG, 2023.

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Approximate Circuits: Methodologies and CAD. Springer, 2018.

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5

Benini, Luca, Rajesh K. Gupta, and Abbas Rahimi. From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators. Springer, 2018.

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Benini, Luca, Rajesh K. Gupta, and Abbas Rahimi. From Variability Tolerance to Approximate Computing in Parallel Integrated Architectures and Accelerators. Springer, 2017.

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7

Wilson Kimber, Marian. Womanly Women and Moral Uplift. University of Illinois Press, 2017. http://dx.doi.org/10.5406/illinois/9780252040719.003.0007.

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Imagery surrounding the female readers on the Chautauqua tent circuit reflected appropriately domestic ideals. Chautauqua, which lasted from approximately 1904 to 1930, was a commercial venture with “talent” supplied by regional entertainment bureaus. The brochures compiled by the Redpath Bureau document ensembles known as concert companies, which regularly featured women “readers.” Due to Chautauqua’s conservative audiences, spoken word performers worked to distinguish themselves from actresses, through women were sometimes marketed to audiences based on their attractiveness. Readers accompanied themselves in pianologues, such as those by Clay Smith, or recited to others’ accompaniments in musical readings. In spite of the tensions between its highbrow ideals and the necessity of presenting more popular middlebrow entertainment, Chautauqua had a wide cultural impact in rural America.
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Feusner, Jamie D., and Danyale McCurdy-McKinnon. Body Dysmorphic Disorder. Edited by Christopher Pittenger. Oxford University Press, 2017. http://dx.doi.org/10.1093/med/9780190228163.003.0050.

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This chapter covers the latest studies addressing neurobiological and genetic/heritable factors that may contribute to body dysmorphic disorder (BDD). BDD affects approximately 2% of the population and involves perceived defects of appearance along with obsessive preoccupation and repetitive, compulsive-like behaviors. Studies of visual processing suggest that disturbances in visual perception and visuospatial information processing, characterized by heightened attention to detail and impairment in holistic and global assessment, contribute to the condition. Also reviewed are studies of brain circuitry in BDD, which implicate white matter and structural connectivity abnormalities as playing possible roles in the pathophysiology of BDD. Finally, this chapter reviews the evidence that the susceptibility for BDD may be partly heritable and that there may be shared genetic factors among the obsessive-compulsive and related disorders (of which BDD is a member) as a group.
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Ferreira, Maria Helena Alves, Alice de Mello, and Elayne Oliveira Silva. Passeios a pé em Belo Horizonte: Um ciclo formativo aos guias de turismo. Brazil Publishing, 2021. http://dx.doi.org/10.31012/978-65-5861-340-4.

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A city that arose already modern, welcoming, and rich in experiences, affectionately called "Belô" or "Beagá" by some of its most intimate citizens. Every tourist easily feels welcomed in Belo Horizonte, a city that was planned to be the capital of Minas Gerais – with tree-lined streets and alleys that breathe art, stories, and charm. Despite being a Metropolis and home to approximately 2,600,000 (two million six hundred thousand) inhabitants, it still keeps secrets as a country town valuing its origins, which means not refusing a delicious coffee with "pão de queijo" (Brazilian cheese bread), and some chitchat in its squares and gardens. The best way to get to know and experience a city as a whole is to walk through it and experience its daily life, thus, connecting with the city and people. Walking around the city makes you notice details that you may have never noticed before. In this work, we present “UAI a PÉ” tours through Belo Horizonte, so that you can be familiar with and experience each one of them. Itineraries that will make you even more enchanted by our beautiful capital. Walk freely through the “Belo Horizonte Cultural: Circuito Liberdade” amid gardens and many stories and tales. Walk around the streets of the downtown, enjoying our “Belo Horizonte Urbana: Visual Arts,” which is an opportunity to experience our Urban Art that is a worldwide reference. Have a conversation at “Praça da Estação Circuito Cultural”, the gateway to our city since its foundation – many stories are kept in museums and mansions there. “Cultura e Política Mineira”, which is an itinerary from Praça da Assembeia (Assembly Square) to Praça da Estação (Station Square), to understand our history and culture. Fresh breeze and sunset in the beautiful “Pampulha: Patrimônio da Humanidade” (cultural heritage of humanity) where modernism is present in every detail of this picturesque place.
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Bloch, Michael H. Comorbidity in Pediatric OCD. Edited by Christopher Pittenger. Oxford University Press, 2017. http://dx.doi.org/10.1093/med/9780190228163.003.0053.

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Tic disorders, including Tourette syndrome (TS), are not formally part of the category of “OCD-related disorders” in the DSM; but the association with OCD is sufficiently strong, and clinically important, that the OCD diagnosis now carries an optional “tic-related” specifier. Comorbidity is the norm in TS; in addition to OCD, attention deficit symptoms are particularly common. The presence of these comorbidities can affect both behavioral and pharmacological treatments, which are reviewed in this chapter. Tics commonly begin in childhood (part of the definition of TS), often improving in late adolescence. Approximately 30% of children with TS will develop OCD; the onset of OCD symptoms is usually later than that of tics, and they are more likely to persist into adulthood. Tic-associated OCD has a male preponderance and is more likely to be characterized by symmetry-related obsessions and compulsions. Like OCD, tic disorders are characterized by abnormalities in the cortico-striatal circuitry.
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Частини книг з теми "Approximate Circuit"

1

Wu, Ying, Chuangtao Chen, Chenyi Wen, Weikang Qian, Xunzhao Yin, and Cheng Zhuo. "Approximate Multiplier Design for Energy Efficiency: From Circuit to Algorithm." In Approximate Computing, 51–76. Cham: Springer International Publishing, 2012. http://dx.doi.org/10.1007/978-3-030-98347-5_3.

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Ullah, Salim, and Akash Kumar. "Approximate Multipliers." In Approximate Arithmetic Circuit Architectures for FPGA-based Systems, 73–112. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-21294-9_4.

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Moons, Bert, Daniel Bankman, and Marian Verhelst. "Circuit Techniques for Approximate Computing." In Embedded Deep Learning, 89–113. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-99223-5_4.

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Ullah, Salim, and Akash Kumar. "Designing Application-Specific Approximate Operators." In Approximate Arithmetic Circuit Architectures for FPGA-based Systems, 113–47. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-21294-9_5.

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Thakur, Garima, Shruti Jain, and Harsh Sohal. "Approximate Arithmetic Circuit for Error-Resilient Application." In Mobile Radio Communications and 5G Networks, 647–56. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-7982-8_54.

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Badrieh, Fuad. "Approximate and Numerical Techniques in Fourier Transform." In Spectral, Convolution and Numerical Techniques in Circuit Theory, 231–49. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-71437-0_12.

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Ullah, Salim, and Akash Kumar. "Preliminaries." In Approximate Arithmetic Circuit Architectures for FPGA-based Systems, 27–40. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-21294-9_2.

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Ullah, Salim, and Akash Kumar. "Accurate Multipliers." In Approximate Arithmetic Circuit Architectures for FPGA-based Systems, 41–72. Cham: Springer International Publishing, 2023. http://dx.doi.org/10.1007/978-3-031-21294-9_3.

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Ullah, Salim, and Akash Kumar. "A Framework for Cross-Layer Approximations." In Approximate Arithmetic Circuit Architectures for FPGA-based Systems, 149–70. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-21294-9_6.

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Ullah, Salim, and Akash Kumar. "Conclusions and Future Work." In Approximate Arithmetic Circuit Architectures for FPGA-based Systems, 171–74. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-21294-9_7.

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Тези доповідей конференцій з теми "Approximate Circuit"

1

Chen, Daniel, Betis Baheri, Vipin Chaudhary, Qiang Guan, Ning Xie, and Shuai Xu. "Approximate Quantum Circuit Reconstruction." In 2022 IEEE International Conference on Quantum Computing and Engineering (QCE). IEEE, 2022. http://dx.doi.org/10.1109/qce53715.2022.00073.

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2

Catelan, Daniela, Ricardo Santos, and Liana Duenha. "Accuracy and Physical Characterization of Approximate Arithmetic Circuits." In XXI Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2020. http://dx.doi.org/10.5753/wscad.2020.14065.

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With the end of Dennard's scale, designers have been looking for new alternatives and approximate computing (AC) has managed to attract the attention of researchers, by offering techniques ranging from the application level to the circuit level. When applying approximate circuit techniques in hardware design, the program user may speed up the application while a designer may save area and power dissipation at the cost of less accuracy on the operations results. This paper discusses the compromise between accuracy versus physical efficiency by presenting a set of experiments and results of tailor-made approximate arithmetic circuits on Field-Programmable Gate Array (FPGA) platforms. Our results reveal that an approximate circuit with accuracy control could not be useful if the goal is to save circuit area or even power dissipation. Even for circuits that seem to have power efficiency, we should care about the size and prototyping platform where the hardware will be used.
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Zhang, Yuwei, Zuodong Zhang, Zhe Zhang, Jiayang Zhang, Runsheng Wang, Zhiting Ling, and Ru Huang. "Circuit Reliability Evaluation of Approximate Computing." In 2020 China Semiconductor Technology International Conference (CSTIC). IEEE, 2020. http://dx.doi.org/10.1109/cstic49141.2020.9282447.

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Qiu, Ling, Ziji Zhang, Jon Calhoun, and Yingjie Lao. "Towards Data-Driven Approximate Circuit Design." In 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). IEEE, 2019. http://dx.doi.org/10.1109/isvlsi.2019.00078.

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Venturelli, Davide, Minh Do, Eleanor Rieffel, and Jeremy Frank. "Temporal Planning for Compilation of Quantum Approximate Optimization Circuits." In Twenty-Sixth International Joint Conference on Artificial Intelligence. California: International Joint Conferences on Artificial Intelligence Organization, 2017. http://dx.doi.org/10.24963/ijcai.2017/620.

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We investigate the application of temporal planners to the problem of compiling quantum circuits to emerging quantum hardware. While our approach is general, we focus our initial experiments on Quantum Approximate Optimization Algorithm (QAOA) circuits that have few ordering constraints and thus allow highly parallel plans. We report on experiments using several temporal planners to compile circuits of various sizes to a realistic hardware architecture. This early empirical evaluation suggests that temporal planning is a viable approach to quantum circuit compilation.
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Sekanina, Lukas, and Zdenek Vasicek. "Approximate circuit design by means of evolvable hardware." In 2013 IEEE International Conference on Evolvable Systems (ICES). IEEE, 2013. http://dx.doi.org/10.1109/ices.2013.6613278.

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Oliveri, A., M. Lodi, and M. Storace. "Design and circuit implementation of approximate switched MPC." In 2013 European Conference on Circuit Theory and Design (ECCTD). IEEE, 2013. http://dx.doi.org/10.1109/ecctd.2013.6662329.

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Alam, Mahabubul, Abdullah Ash-Saki, and Swaroop Ghosh. "Circuit Compilation Methodologies for Quantum Approximate Optimization Algorithm." In 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2020. http://dx.doi.org/10.1109/micro50266.2020.00029.

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Soltani, Mohammad, Cesar Vargas, Niraj Kumar, Rahul Kulkarni, and Abhyudai Singh. "Approximate statistical dynamics of a genetic feedback circuit." In 2015 American Control Conference (ACC). IEEE, 2015. http://dx.doi.org/10.1109/acc.2015.7172025.

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Bohdanowicz, Thomas C., Elizabeth Crosson, Chinmay Nirkhe, and Henry Yuen. "Good approximate quantum LDPC codes from spacetime circuit Hamiltonians." In STOC '19: 51st Annual ACM SIGACT Symposium on the Theory of Computing. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3313276.3316384.

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