Статті в журналах з теми "Application specific instruction-set processor (ASIP)"
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Imai, Masaharu, Yoshinori Takeuchi, Keishi Sakanushi, and Nagisa Ishiura. "Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)." IPSJ Transactions on System LSI Design Methodology 3 (2010): 161–78. http://dx.doi.org/10.2197/ipsjtsldm.3.161.
Повний текст джерелаSharma, Poonam, Ashwani Kumar Dubey, and Ayush Goyal. "Efficient Computing in Image Processing and DSPs with ASIP Based Multiplier." Recent Patents on Engineering 13, no. 2 (May 27, 2019): 174–80. http://dx.doi.org/10.2174/1872212112666180810150357.
Повний текст джерелаXin, Yao, Will X. Y. Li, Zhaorui Zhang, Ray C. C. Cheung, Dong Song, and Theodore W. Berger. "An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics." IEEE/ACM Transactions on Computational Biology and Bioinformatics 12, no. 5 (September 1, 2015): 1034–47. http://dx.doi.org/10.1109/tcbb.2015.2440248.
Повний текст джерелаSafaei Mehrabani, Yavar. "Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm." International Journal of Electronics Letters 7, no. 2 (May 25, 2018): 154–65. http://dx.doi.org/10.1080/21681724.2018.1477182.
Повний текст джерелаZhang, Diandian, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd Ascheid, Rainer Leupers, and Bart Vanthournout. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs." International Journal of Embedded and Real-Time Communication Systems 4, no. 1 (January 2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.
Повний текст джерелаIwaizumi, Hiroki, Shingo Yoshizawa, and Yoshikazu Miyanaga. "A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems." VLSI Design 2013 (March 18, 2013): 1–10. http://dx.doi.org/10.1155/2013/625019.
Повний текст джерелаQiao, Wan, and Dake Liu. "A scalable ASIP for BP Polar decoding with multiple code lengths." MATEC Web of Conferences 232 (2018): 01046. http://dx.doi.org/10.1051/matecconf/201823201046.
Повний текст джерелаWong, Tingh Wee, Bryan Ng, and Chee Onn Wong. "Encoding Custom Instruction Generation as Satisfiability Problem." Advanced Materials Research 403-408 (November 2011): 502–10. http://dx.doi.org/10.4028/www.scientific.net/amr.403-408.502.
Повний текст джерелаFischer, Dirk, Jürgen Teich, Ralph Weper, and Michael Thies. "BUILDABONG: A Framework for Architecture/Compiler Co-Exploration for ASIPs." Journal of Circuits, Systems and Computers 12, no. 03 (June 2003): 353–75. http://dx.doi.org/10.1142/s0218126603000799.
Повний текст джерелаAhmed, O., S. Areibi, and G. Grewal. "Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm." International Journal of Reconfigurable Computing 2013 (2013): 1–33. http://dx.doi.org/10.1155/2013/681894.
Повний текст джерелаSalmela, Perttu, Adrian Burian, Tuomas Järvinen, Aki Happonen, and Jarmo Henrik Takala. "Low-Complexity Inverse Square Root Approximation for Baseband Matrix Operations." ISRN Signal Processing 2011 (February 16, 2011): 1–8. http://dx.doi.org/10.5402/2011/615934.
Повний текст джерелаCATANIA, VINCENZO, MAURIZIO PALESI, and DAVIDE PATTI. "ANALYSIS AND TOOLS FOR THE DESIGN OF VLIW EMBEDDED SYSTEMS IN A MULTI-OBJECTIVE SCENARIO." Journal of Circuits, Systems and Computers 16, no. 05 (October 2007): 819–46. http://dx.doi.org/10.1142/s0218126607003915.
Повний текст джерелаUrban, Roberto, Heinrich T. Vierhaus, Mario Schölzel, Enrico Altmann, and Horst Seelig. "Non-Cyclic Design Space Exploration for ASIPs — Compiler-Centered Microprocessor Design (CoMet)." Journal of Circuits, Systems and Computers 25, no. 03 (December 28, 2015): 1640012. http://dx.doi.org/10.1142/s0218126616400120.
Повний текст джерелаMeloni, Paolo, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, and Menno Lindwer. "Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper." VLSI Design 2012 (March 29, 2012): 1–16. http://dx.doi.org/10.1155/2012/580584.
Повний текст джерелаKammler, David, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, and Heinrich Meyr. "Automatic Generation of Memory Interfaces for ASIPs." International Journal of Embedded and Real-Time Communication Systems 1, no. 3 (July 2010): 1–23. http://dx.doi.org/10.4018/jertcs.2010070101.
Повний текст джерелаYoshitomi, Hiroyuki. "OrientalHydrocyphon(Coleoptera: Scirtidae: Scirtinae): Seven New Species from Indonesia, Thailand, Malaysia, and India." Psyche: A Journal of Entomology 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/603875.
Повний текст джерелаRadhakrishnan, S., H. Guo, S. Parameswaran, and A. Ignjatovic. "HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors." IET Computers & Digital Techniques 3, no. 1 (2009): 94. http://dx.doi.org/10.1049/iet-cdt:20080005.
Повний текст джерелаShen, Zheng, Hu He, Yanjun Zhang, and Yihe Sun. "A Video Specific Instruction Set Architecture for ASIP design." VLSI Design 2007 (November 15, 2007): 1–7. http://dx.doi.org/10.1155/2007/58431.
Повний текст джерелаAntikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector." EURASIP Journal on Embedded Systems 2007 (2007): 1–14. http://dx.doi.org/10.1155/2007/54173.
Повний текст джерелаAntikainen, Juho, Perttu Salmela, Olli Silvén, Markku Juntti, Jarmo Takala, and Markus Myllylä. "Application-Specific Instruction Set Processor Implementation of List Sphere Detector." EURASIP Journal on Embedded Systems 2007, no. 1 (2007): 054173. http://dx.doi.org/10.1186/1687-3963-2007-054173.
Повний текст джерелаSisto, A., L. Pilato, R. Serventi, S. Saponara, and L. Fanucci. "Application specific instruction set processor for sensor conditioning in automotive applications." Microprocessors and Microsystems 47 (November 2016): 375–84. http://dx.doi.org/10.1016/j.micpro.2016.10.001.
Повний текст джерелаSaponara, Sergio, Luca Fanucci, Stefano Marsi, Giovanni Ramponi, David Kammler, and Ernst Martin Witte. "Application-Specific Instruction-Set Processor for Retinex-Like Image and Video Processing." IEEE Transactions on Circuits and Systems II: Express Briefs 54, no. 7 (July 2007): 596–600. http://dx.doi.org/10.1109/tcsii.2007.896778.
Повний текст джерелаPeters, H., R. Sethuraman, A. Beric, P. Meuwissen, S. Balakrishnan, C. A. A. Pinto, W. Kruijtzer, et al. "Application specific instruction-set processor template for motion estimation in video applications." IEEE Transactions on Circuits and Systems for Video Technology 15, no. 4 (April 2005): 508–27. http://dx.doi.org/10.1109/tcsvt.2005.844462.
Повний текст джерелаHoffmann, A., T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr. "A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20, no. 11 (2001): 1338–54. http://dx.doi.org/10.1109/43.959863.
Повний текст джерелаChoi, Seung-Hyun, Tae-Moon Roh, Yong Ho Song, and Seong-Won Lee. "Design of an application specific instruction set processor for a universal bitstream codec." IEICE Electronics Express 11, no. 24 (2014): 20141047. http://dx.doi.org/10.1587/elex.11.20141047.
Повний текст джерелаZhaohui Liu, K. Dickson, and J. V. McCanny. "Application-specific instruction set processor for SoC implementation of modern signal processing algorithms." IEEE Transactions on Circuits and Systems I: Regular Papers 52, no. 4 (April 2005): 755–65. http://dx.doi.org/10.1109/tcsi.2005.844109.
Повний текст джерелаMbaye, Mame Maria, Normand Bélanger, Yvon Savaria, and Samuel Pierre. "A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration." Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology 47, no. 3 (March 27, 2007): 297–315. http://dx.doi.org/10.1007/s11265-007-0050-0.
Повний текст джерелаBytyn, Andreas, Rainer Leupers, and Gerd Ascheid. "ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs." IEEE Open Journal of Circuits and Systems 2 (2021): 3–15. http://dx.doi.org/10.1109/ojcas.2020.3037758.
Повний текст джерелаMooney, James, Abdulhussain E. Mahdi, and Mark Halton. "Application-Specific Instruction-Set Processor for Control of Multi-Rail DC-DC Converter Systems." IEEE Transactions on Circuits and Systems I: Regular Papers 60, no. 1 (January 2013): 243–54. http://dx.doi.org/10.1109/tcsi.2012.2215783.
Повний текст джерелаHeo, Ingoo, Minsu Kim, Yongje Lee, Changho Choi, Jinyong Lee, Brent Byunghoon Kang, and Yunheung Paek. "Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines." ACM Transactions on Design Automation of Electronic Systems 20, no. 4 (September 28, 2015): 1–32. http://dx.doi.org/10.1145/2746238.
Повний текст джерелаZHANG, Yuli, Jun HAN, Xinqian WENG, Zhongzhu HE, and Xiaoyang ZENG. "Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm." IEICE Transactions on Electronics E95.C, no. 8 (2012): 1415–26. http://dx.doi.org/10.1587/transele.e95.c.1415.
Повний текст джерелаTamagnone, M., M. Martina, and G. Masera. "An application specific instruction set processor based implementation for signal detection in multiple antenna systems." Microprocessors and Microsystems 36, no. 3 (May 2012): 245–56. http://dx.doi.org/10.1016/j.micpro.2011.11.003.
Повний текст джерелаXIAO, Shanlin, Tsuyoshi ISSHIKI, Dongju LI, and Hiroaki KUNIEDA. "Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E100.A, no. 7 (2017): 1384–95. http://dx.doi.org/10.1587/transfun.e100.a.1384.
Повний текст джерелаGuan, Xuan, Yunsi Fei, and Hai Lin. "Hierarchical Design of an Application-Specific Instruction Set Processor for High-Throughput and Scalable FFT Processing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20, no. 3 (March 2012): 551–63. http://dx.doi.org/10.1109/tvlsi.2011.2105512.
Повний текст джерелаLin, Hai, and Yunsi Fei. "Resource Sharing of Pipelined Custom Hardware Extension for Energy-Efficient Application-Specific Instruction Set Processor Design." ACM Transactions on Design Automation of Electronic Systems 17, no. 4 (October 2012): 1–20. http://dx.doi.org/10.1145/2348839.2348843.
Повний текст джерелаAbdel All, Mahmoud, Hanan M. Hassan, Medhat Hamdy, Omar A. Nasr, Karim Mohamed, and Ahmed F. Shalash. "Design and implementation of application‐specific instruction‐set processor design for high‐throughput multi‐standard wireless orthogonal frequency division multiplexing baseband processor." IET Circuits, Devices & Systems 9, no. 3 (May 2015): 191–203. http://dx.doi.org/10.1049/iet-cds.2014.0046.
Повний текст джерелаK.Jain, M., and Deepak Gour. "Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor." International Journal of Computer Applications 43, no. 5 (April 30, 2012): 14–19. http://dx.doi.org/10.5120/6098-8290.
Повний текст джерелаZiebinski, Adam, and Stanwlaw Swierc. "Soft Core Processor Generated Based on the Machine Code of the Application." Journal of Circuits, Systems and Computers 25, no. 04 (February 2, 2016): 1650029. http://dx.doi.org/10.1142/s0218126616500298.
Повний текст джерелаSalmela, Perttu, Harri Sorokin, and Jarmo Takala. "A Programmable Max-Log-MAP Turbo Decoder Implementation." VLSI Design 2008 (December 22, 2008): 1–17. http://dx.doi.org/10.1155/2008/319095.
Повний текст джерелаZhang, Diandian, Han Zhang, Jeronimo Castrillon, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, and Rainer Leupers. "Optimized Communication Architecture of MPSoCs with a Hardware Scheduler." International Journal of Embedded and Real-Time Communication Systems 2, no. 3 (July 2011): 1–20. http://dx.doi.org/10.4018/jertcs.2011070101.
Повний текст джерелаVenkanna, Mood, and Rameshwar Rao. "Static Worst-Case Execution Time Optimization using DPSO for ASIP Architecture." Ingeniería Solidaria 14, no. 25 (May 1, 2018): 1–11. http://dx.doi.org/10.16925/.v14i0.2230.
Повний текст джерелаBispo, João, Nuno Paulino, João M. P. Cardoso, and João Canas Ferreira. "Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units." International Journal of Reconfigurable Computing 2013 (2013): 1–20. http://dx.doi.org/10.1155/2013/340316.
Повний текст джерелаSugiura, Tomoki, Masaharu Imai, Jaehoon Yu, and Yoshinori Takeuchi. "A Low-Energy Application Specific Instruction-Set Processor towards a Low-Computational Lossless Compression Method for Stimuli Position Data of Artificial Vision Systems." Journal of Information Processing 25 (2017): 210–19. http://dx.doi.org/10.2197/ipsjjip.25.210.
Повний текст джерелаVishnoi, U., and T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies." Advances in Radio Science 10 (September 18, 2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.
Повний текст джерелаVassiliadis, N., A. Chormoviti, N. Kavvadias, and S. Nikolaidis. "THE EFFECT OF DATA-REUSE TRANSFORMATIONS ON MULTIMEDIA APPLICATIONS FOR APPLICATION SPECIFIC PROCESSORS." International Journal of Computing, August 1, 2014, 102–9. http://dx.doi.org/10.47839/ijc.4.3.369.
Повний текст джерелаJanwa, Naresh Kumar, and Dr Manoj Kumar Jain. "Identification of Research Gaps in an Efficient Designing of Application Specific Instruction Set Processor (ASIP) for Neural Prosthetics." SSRN Electronic Journal, 2019. http://dx.doi.org/10.2139/ssrn.3349573.
Повний текст джерелаGerlach, Lukas, Guillermo Payá-Vayá, and Holger Blume. "A Survey on Application Specific Processor Architectures for Digital Hearing Aids." Journal of Signal Processing Systems, March 20, 2021. http://dx.doi.org/10.1007/s11265-021-01648-0.
Повний текст джерела"Design of Energy-Efficient Application-Specific Instruction Set Processors (ASIPS) [Book Review]." IEEE Circuits and Devices Magazine 22, no. 2 (March 2006): 31. http://dx.doi.org/10.1109/mcd.2006.1615247.
Повний текст джерелаRizk, Mostafa, Amer Baghdadi, Michel Jézéquel, Youssef Atat, and Yasser Mohanna. "NISC-based MIMO MMSE Detector." Journal of Circuits, Systems and Computers, September 2, 2020, 2150069. http://dx.doi.org/10.1142/s0218126621500699.
Повний текст джерела"Implementation of 5-Stage 32-Bit Microprocessor Based Without Interlocked Pipelining Stages." International Journal of Innovative Technology and Exploring Engineering 9, no. 1 (November 10, 2019): 4557–61. http://dx.doi.org/10.35940/ijitee.a4899.119119.
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