Дисертації з теми "ANALYSIS OF CMOS"

A versatile and efficient computer-aided analysis tool, CUREST, has been developed for the analysis of supply currents in CMOS digital circuits. It is based on Nabavi-Lishi's semi-analytical model for computing the current and delay in a CMOS logic gate which, when compared to HSPICE running the level-3 MOSFET model, is more than three orders of magnitude faster, and accurate to within 10%. CUREST is built on top of the timing analyser TAMIA and, in particular, uses its circuit parser and its data structure to store the circuit topology and primary input pattern.<br>Extension tests on benchmark circuits containing up to 555 gates, which were analysed with CUREST using thousands of primary input patterns, demonstrate that the current analysis time is in the range of 1ms per gate per input pattern, using a SUN4/490 workstation with 32 Mb of main memory, running the SUN OS 4.103 operating system. The peak value of the total supply current, the current rise-time, and the time at which the peak occurs are usually computed to within 10% of HSPICE. However, appreciable errors often occur in the average current. This is because at the moment we do not have a good model for dealing with incomplete transitions associated with glitches in a CMOS gate.

L'auteur n'a pas fourni de résumé en français<br>Integrated circuits evolution is driven by the trend of increasing operating frequencies and downscaling of the device size, while embedding more and more complex functionalities in a single chip. However, the continuation of the device-scaling race generates a number of technology challenges. For instance, the downscaling of transistor channel lengths induce short-channel effects (drain-induced barrier lowering and punch-through phenomena); high electric field in the devices tend to increase Hot electron effect (or Hot Carrier) and Oxide Dielectric Breakdown; higher temperatures in IC products generates an increase of the Negative Bias Temperature Instability (NBTI) effect on pMOS devices. Today, it is considered that the above reliability mechanisms are ones of the main causes of circuit degradation performance in the field. This dissertation will address the Hot Carrier (HC) and NBTI impacts on CMOS product electrical performances. A CAD bottom-up approach will be proposed and analyzed, based on the Design–in Reliability (DiR) methodology. With this purpose, a detailed analysis of the NBTI and the HC behaviours and their impact at different abstraction level is provided throughout this thesis. First, a physical framework presenting the NBTI and the HC mechanisms is given, focusing on electrical parameters weakening of nMOS and pMOS transistors. Moreover, the main analytical HC and NBTI degradation models are treated in details. In the second part, the delay degradation of digital standard cells due to NBTI, HCI is shown; an in-depth electrical CAD analysis illustrates the combined effects of design parameters and HCI/NBTI on the timing performance of standard cells. Additionally, a gate level approach is developed, in which HC and NBTI mechanisms are individually addressed. The consequences of the degradation at system level are presented in the third part of the thesis. With this objective, data extracted from silicon measures are compared against CAD estimations on two complexes IPs fabricated on STCMOS 45nm technologies. It is expected that the findings of this thesis highly contribute to the understanding of the NBTI and HC reliability wearout mechanisms at the system level.STAR

Thesis (Ph. D.)--University of California, San Diego, 2006.<br>Title from first page of PDF file (viewed September 8, 2006). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 121-123).

Personalised medicine is widely considered to be the future of global healthcare, where diagnosis, treatment, and potentially even drug development, will become specific to, and optimised for, each individual patient. Traditional population based cell studies suppress the influence of outlier cells that are frequently those of most clinical relevance. Hence single-cell analysis is becoming increasingly important in understanding disease, aiding diagnosis and selecting tailored treatment; but remains the preserve of biomedical laboratories far from the patient. Current instruments depend upon cell-labelling to identify the cell type(s) of interest, which require that these be chosen a-priori and may not be those most clinically relevant. Furthermore, cell-labelling is fundamentally subjective, requiring highly-skilled operators to decide upon the validity of each and every test. Therefore, new test methods need to be developed to enable the widespread adoption of single-cell analysis. The passive electrical properties of biological cells are known to be indicative of the specific cell type, but no technology has demonstrated their comprehensive measurement within a mass-manufacturable device. This work aims to show that biologically meaningful information can be obtained in the form of identifiable “cell signatures” through broadband frequency measurements spanning 100 kHz to 100 MHz that exploit the properties of differential electric fields. This hypothesis is tested through the design, implementation and experimental testing of a dedicated microsystem that integrates two novel designs of electrical sensor within a standard, mass-manufacturable Complementary Metal-Oxide Semiconductor microelectronics technology. One sensor measures the absolute electrical environment above a single sense electrode. The other measures the difference in electrical environment between a pair of electrodes, with view to provide information regarding the suspended cell only, through rejecting the common signal due to its suspending medium. Both sensors are shown capable of detecting individual biological cells in physiological solution, and the differential sensor capable of identifying individually-fixed red blood cells, cervical cancer HeLa cells, and three diameters of homogeneous polystyrene micro-beads of comparable size, all while suspended in physiological saline. These results confirm the hypothesis that differential electric fields provide greater distinction of suspended cells from their environment than existing electrical methods. This finding shows that electrode polarisation arising from proximity to liquids, and particularly physiological media, can be overcome through fully-differential electrical cell sensing. However, misalignment between cells and sensor electrodes limits the sensitivity achieved with the microsystem. Methods to overcome such alignment issues should be investigated in future work, along with higher frequency measurements beyond those presented here.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.<br>Singh, Adit, Committee Member ; Chatterjee, Abhijit, Committee Chairl May, Gary, Committee Member ; Keezer, David, Committee Member ; Swaminathan, Madhavan, Committee Member. Vita. Includes bibliographical references.

Thesis (Ph. D.) -- University of Maryland, College Park, 2007.<br>Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.<br>Includes bibliographical references (p. 139-140).<br>by Dawn Dougherty Fitzgerald.<br>M.S.

Tese (doutorado) - Universidade Federal de Santa Catarina, Centro Tecnológico, Programa de Pós-Graduação em Engenharia Elétrica, Florianópolis, 2017.<br>Made available in DSpace on 2018-02-06T03:20:46Z (GMT). No. of bitstreams: 1 349773.pdf: 5894584 bytes, checksum: f7cc1810c920ff756724711896de8791 (MD5) Previous issue date: 2017<br>Nesta tese, o disparador Schmitt (ou Schmitt trigger) CMOS clássico (ST) operando em inversão fraca é analisado. A transferência de tensão DC completa é determinada, incluindo expressões analíticas para as tensões dos nós internos. A transferência de tensão DC resultante do ST apresenta um comportamento contínuo mesmo na presença da histerese. Nesse caso, a característica da tensão de saída entre os limites da histerese é formada por um segmento metaestável, que pode ser explicado em termos das resistências negativas dos subcircuitos NMOS e PMOS do ST. A tensão mínima para o aparecimento da histerese é determinada fazendo-se a análise de pequenos sinais. A análise de pequenos sinais também é utilizada para a estimativa da largura do laço de histerese. É mostrado que a histerese não aparece para tensões de alimentação menores que 75 mV em 300 K. A análise do ST operando como amplificador também foi feita. A razão ótima dos transistores foi determinada com o objetivo de se maximizar o ganho de tensão. A comparação do disparador Schmitt com o inversor CMOS convencional destaca as vantagens e desvantagens de cada um para aplicações de ultra-baixa tensão. Também é mostrado que o ST é teoricamente capaz de operar (com ganho de tensão absoluto ?1) com uma tensão de alimentação tão baixa quanto 31.5 mV, a qual é menor do que o conhecido limite prévio de 36 mV, para o inversor convencional. Como amplificador, o ST possui ganho de tensão absoluto consideravelmente maior que o inversor convencional na mesma tensão de alimentação. Três circuitos integrados foram projetados e fabricados para estudar o comportamento do ST com tensões de alimentação entre 50 mV e 1000 mV.<br>Abstract : In this thesis, the classical CMOS Schmitt trigger (ST) operating in weak inversion is analyzed. The complete DC voltage transfer characteristic is determined, including analytical expressions for the internal node voltage. The resulting voltage transfer characteristic of the ST presents a continuous output behavior even when hysteresis is present. In this case, the output voltage characteristic between the hysteresis limits is formed by a metastable segment, which can be explained in terms of the negative resistance of the NMOS and PMOS subcircuits of the ST. The minimum supply voltage at which hysteresis appears is determined carrying out small-signal analysis, which is also used to estimate the hysteresis width. It is shown that hysteresis does not appear for supply voltages lower than 75 mV at 300 K. The analysis of the ST operating as a voltage amplifier was also carried out. Optimum transistor ratios were determined aiming at voltage gain maximization. The comparison of the ST with the standard CMOS inverter highlights the relative benefits and drawbacks of each one in ULV applications. It is also shown that the ST is theoretically capable of operating (voltage gain ?1) at a supply voltage as low as 31.5 mV, which is lower than the well-known limit of 36 mV, for the standard CMOS inverter. As an amplifier, the ST shows considerable higher absolute voltage gains than those showed by the conventional inverter at the same supply voltages. Three test chips were designed and fabricated to study the operation of the ST at supply voltages between 50 mV and 1000 mV.

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1995.<br>Thesis advisor(s): Herschel H. Loomis, Jr., Raymond F. Berstein, Jr., Douglas J. Fouts. "March 1995." Includes bibliographical references. Also available online.

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip.

A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 &Ugrave; antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.<br>Ph.D.<br>Department of Electrical and Computer Engineering<br>Engineering and Computer Science<br>Electrical Engineering

Wireless and communication systems are being run at ever increasing in frequencies, but the conventional complimentary metal oxide semiconductor (CMOS) phase locked loop (PLL) architectures are starting to reach a performance limit. A key part of the PLL is the voltage controlled oscillator (VCO) - for this to achieve high frequency performance, low value inductors are required. However, achieving a large tuning range, high Q, and low noise, with these inductors is extremely difficult. This thesis provides a literature review and background to CMOS VCO design, and in particular, using transmission lines as the critical element for generating oscillations. It then goes on to detail the research and development of two test chips, each consisting of eight individual VCOs outputting a differential signal, divided in frequency by four, to dedicated ports on a purpose built printed circuit board. These circuit boards were built using low cost, industry standard materials and the chips tested using standard lab equipment. This project led to the creation of the fastest VCOs ever designed and tested at Fujitsu Semiconductor Europe and highlighted some of the key issues in transforming a technology from a mature academic knowledge into an industrially ready product.

Os avanços na tecnologia de semicondutores possibilitou que se fabricasse dispositivos com atividade de chaveamento mais rápida e com maior capacidade de integração de transistores. Estes avanços, todavia, impuseram novos empecilhos relacionados com a dissipação de potência e energia. Além disso, a crescente demanda por dispositivos portáteis levaram à uma mudança no paradigma de projeto de circuitos para que se priorize energia ao invés de desempenho. Este cenário motivou à reduzir a tensão de alimentação com qual os dispositivos operam para um regime próximo ou abaixo da tensão de limiar, com o objetivo de aumentar sua duração de bateria. Apesar desta abordagem balancear características de performance e energia, ela traz novos desafios com relação a tolerância à ruído. Ao reduzirmos a tensão de alimentação, também reduz-se a margem de ruído disponível e, assim, os circuitos tornam-se mais suscetíveis à falhas funcionais. Somado à este efeito, circuitos com tensões de alimentação nestes regimes são mais sensíveis à variações do processo de fabricação, logo agravando problemas com ruído. Existem também outros aspectos, tais como a miniaturização das interconexões e a relação de fan-out de uma célula digital, que incentivam a avaliação de ruído nas fases iniciais do projeto de circuitos integrados Por estes motivos, este trabalho investiga como aprimorar a margem de ruído estática de circuitos síncronos digitais que irão operar em tensões no regime de tensão próximo ou abaixo do limiar. Esta investigação produz um conjunto de três contribuições originais. A primeira é uma ferramenta capaz de avaliar automaticamente a margem de ruído estática de células CMOS combinacionais. A segunda contribuição é uma metodologia realista para estimar a margem de ruído estática considerando variações de processo, tensão e temperatura. Os resultados obtidos mostram que a metodologia proposta permitiu reduzir até 70% do pessimismo das margens de ruído estática, Por último, a terceira contribuição é um fluxo de projeto de células combinacionais digitais considerando ruído, e uma abordagem para avaliar a margem de ruído estática de circuitos complexos durante a etapa de síntese lógica. A biblioteca de células resultante deste fluxo obteve maior margem de ruído (até 24%) e menor variação entre diferentes células (até 62%).<br>The advancement of semiconductor technology enabled the fabrication of devices with faster switching activity and chips with higher integration density. However, these advances are facing new impediments related to energy and power dissipation. Besides, the increasing demand for portable devices leads the circuit design paradigm to prioritize energy efficiency instead of performance. Altogether, this scenario motivates engineers towards reducing the supply voltage to the near and subthreshold regime to increase the lifespan of battery-powered devices. Even though operating in these regime offer interesting energy-frequency trade-offs, it brings challenges concerning noise tolerance. As the supply voltage reduces, the available noise margins decrease, and circuits become more prone to functional failures. In addition, near and subthreshold circuits are more susceptible to manufacturing variability, hence further aggravating noise issues. Other issues, such as wire minimization and gate fan-out, also contribute to the relevance of evaluating the noise margin of circuits early in the design Accordingly, this work investigates how to improve the static noise margin of digital synchronous circuits that will operate at the near/subthreshold regime. This investigation produces a set of three original contributions. The first is an automated tool to estimate the static noise margin of CMOS combinational cells. The second contribution is a realistic static noise margin estimation methodology that considers process-voltage-temperature variations. Results show that the proposed methodology allows to reduce up to 70% of the static noise margin pessimism. Finally, the third contribution is the noise-aware cell design methodology and the inclusion of a noise evaluation of complex circuits during the logic synthesis. The resulting library achieved higher static noise margin (up to 24%) and less spread among different cells (up to 62%).

Les dimensions dels transistors disminueixen per a cada nova tecnologia CMOS. Aquest alt nivell d'integració complica el procés de fabricació dels circuits integrats, apareixent nous mecanismes de fallada. En aquest sentit, els mètodes de diagnosi actuals no són capaços d'assumir els nous reptes que sorgeixen per a les tecnologies nanomètriques. A més, la inspecció física de fallades (Failure Analysis) no es pot aplicar des d'un bon començament, ja que els costos de la seva utilització són massa alts. Per aquesta raó, conèixer el comportament dels defectes i dels seus mecanismes de fallada és imprescindible per al desenvolupament de noves metodologies de diagnosi que puguin superar aquests nous reptes. En aquest context, aquesta tesi presenta l'anàlisi dels mecanismes de fallada i proposa noves metodologies de diagnosi per millorar la localització de ponts (bridge) i oberts (open). <br/>Per a la diagnosi de ponts, alguns treballs s'han beneficiat de la informació obtinguda durant el test de corrent (IDDQ). No obstant no han tingut en compte l'impacte del corrent de dowsntream. Per aquesta raó, en aquesta tesi s'analitza l'impacte d'aquest corrent degut als ponts i la seva dependència amb la tensió d'alimentació (VDD). A més, es presenta una nova metodologia de diagnosi basada en els múltiples nivells de corrent. Aquesta tècnica considera els corrents generats per les diferents xarxes connectades pel pont. Aquesta metodologia s'ha aplicat amb èxit a un conjunt de xips defectuosos de tecnologies de 0.18 µm i 90 nm.<br/>Com alternativa a les tècniques basades en corrent, els shmoo plots també poden ser útils per a la diagnosi. Tradicionalment s'ha considerat que valors baixos de VDD són més apropiats per a la detecció de ponts. Tanmateix es demostra en aquesta tesi que en presència de ponts connectant xarxes equilibrades, valors alts de VDD són fins i tot més apropiats que tensions baixes, amb la conseqüent implicació que això té per a la diagnosi.<br/>En relació als oberts, s'ha dissenyat i fabricat un xip amb la inclusió intencionada d'oberts complets (full opens) i oberts resistius. Experiments fets amb els xips demostren l'impacte de les capacitats d'acoblament de les línies veïnes. A més, pels oberts resistius s'ha comprovat la influència de l'efecte història i de la localització de l'obert en el retard. Tradicionalment s'ha considerat que el retard màxim s'obté quan un obert resistiu es troba al principi de la línia. No obstant això no es pot generalitzar a oberts poc resistius, ja que en aquests casos es demostra que el màxim retard s'obté per a una localització intermèdia. A partir dels resultats experimentals obtinguts amb el xip, s'ha desenvolupat una nova metodologia per a la diagnosi d'oberts complets a les línies d'interconnexió. Aquest mètode divideix la línia en diferents segments segons la informació de layout de la pròpia línia. Aleshores coneixent els valors de les línies veïnes, es prediu la tensió del node flotant, la qual es compara amb el resultat experimental obtingut a la màquina de test. Aquest mètode s'ha aplicat amb èxit a un seguit de xips defectuosos pertanyents a una tecnologia de 0.18 µm.<br/>Finalment, s'ha analitzat l'impacte que tenen els corrents de túnel a través del terminal de porta en presència d'un obert complet. Com les dimensions disminueixen per a cada nova tecnologia, l'òxid de porta és suficientment prim com per generar corrents de túnel que influencien el node flotant. Aquests corrents generen una evolució temporal al node flotant fins fer-lo arribar a un estat quiescent, el qual depèn de la tecnologia. Es comprova que aquestes evolucions temporals són de l'ordre de segons per a una tecnologia de 0.18 µm. Tanmateix les simulacions demostren que aquests temps disminueixen fins a uns quants µs per a tecnologies futures. Degut a l'impacte dels corrents de túnel, un seguit d'oberts complets s'han diagnosticat en xips de 0.18 µm.<br>Transistor dimensions are scaled down for every new CMOS technology. Such high level of integration has increased the complexity of the Integrated Circuits (ICs) manufacturing process, arising new complex failure mechanisms. However, present diagnosis methodologies cannot afford the challenges arisen for future technologies. Furthermore, physical failure analysis, although indispensable, is not feasible on its own, since it requires high cost equipment, tools and qualified personnel. For this reason, a detailed understanding and knowledge of defect behaviours is a key factor for the development of improved diagnosed methodologies to overcome the challenges of nanometer technologies. In this context, this thesis presents the analysis of existing and new failure mechanisms and proposed new diagnosis methodologies to improve the diagnosis of faults, focused on bridging and open faults.<br/>IDDQ is a well known technique for the diagnosis of bridging faults. However, previous works have not considered the impact of the downstream current for the diagnosis of such faults. In this thesis, the impact and the dependence of the downstream current with the power supply voltage (VDD) is analyzed and experimentally measured. Furthermore, a multiple level IDDQ based diagnosis technique is presented. This method takes benefit from the currents generated by the different network excitations. This technique is successfully applied to real defective devices from 0.18 µm and 90 nm technologies.<br/>As an alternative to current based techniques, shmoo plots can be also useful for diagnosis purposes. Low voltage has been traditionally considered as an advantageous condition for the detection of bridging faults. However, it is demonstrated that in presence of bridges connecting balanced n- and p-networks, high VDD values are also advantageous for the detection of bridges, which has its direct translation into diagnosis application. Experimental evidence of this fact is presented.<br/>Related to open faults, an experimental chip has been designed and fabricated in a 0.35 µm technology, where full and resistive open defects have been intentionally added. Different experiments have been carried out so that the impact of the neighbouring coupling capacitances has been quantified. Furthermore, for resistive opens, experiments have demonstrated the influence of the history effect and the location of the defect on the delay. Traditionally, it has been reported that the highest delay is obtained when the resistive open is located at the beginning of the net. Nevertheless, this thesis demonstrates that this is not true for low resistive open, since the highest delay is obtained for an intermediate location. Experimental measurements prove this behaviour.<br/>Derived from the results obtained with the fabricated chip, a new methodology for the diagnosis of interconnect full open defects is developed. The FOS (Full Open Segment) method divides the interconnect line into different segments based on the topology of the faulty line. Knowing the logic state of the neighbouring lines, the floating net voltage is predicted and compared with the experimental results obtained on the tester. This method has been successfully applied to a set of 0.18 µm defective devices. <br/>Finally, the impact of the gate tunnelling leakage currents on the behaviour of full open defects has also been analyzed. As technology dimensions are scaled down, the oxide thickness is thin enough so that the gate tunnelling leakage currents influence the behaviour of floating lines. They cause transient evolutions on the floating node until reaching the steady state, which is technology dependent. It is experimentally demonstrated that these evolutions are in the order of seconds for a 0.18µm technology. However, for future technologies, simulations show that the evolutions decrease down to a few µs. Based on this factor, some full open faults present in 0.18 µm technology devices are diagnosed.

碩士<br>國立交通大學<br>電子研究所<br>84<br>Subthreshold CMOS mismatch analysis is one of the most important issues in the low power, low voltage field. We have measured the current mismatch of identically drawn p- and n-type MOSFETs (similar to current mirror) operating in subthreshold or weak inversion to above-threshold regions with different gate width-to-length ratios, transistor spacing distances, and layout orientations. These transistors were characterized with back- gate reverse and forward biases. The first observation is that devices operating in subthreshold region exhibit larger mismatch than those in above-threshold region. This is due to the exponential dependence of current on gate and bulk voltages as well as process parameters. In the case of back-gate reverse bias, we have found that current mismatch increases as the magnitude of back-gate reverse bias increases. On the other hand, with the supply of back-gate forward bias, the current mismatch decreases with increasing the back-gate bias in all operation regions. With the data measured from devices with difference sizes, spacing distances, and layout orientations, we have found that (i) small size devices not only exhibit larger mismatch, but also are more sensitive to back-gate bias; (ii) p- type MOSFET exhibits larger mismatch and less sensitive to back- gate bias than n-type MOSFET; and (iii) drawing transistors closely and in horizontal orientation improves the match. We have also derived an analytical statistical model that has successfully reproduced the mismatch data in weak inversion for different back-gate biases and device dimensions. With this model, the current mismatch can be expressed as a function of the variations in process parameters, namely, flat-band voltage and body effect coefficient. The extracted process variations are shown to appropriately follow the inverse square root of the device area.

碩士<br>國立臺灣科技大學<br>工程技術研究所<br>83<br>CMOS devices are widely used in digital integrated circuits. The opetation of these IC''s may be interfered by electromagnetic interference ( EMI ) .EMI analyses and tests can provide us the EMI emission and susceptibility information of equipments.The analysis of conducted or radiated interference is essential in the design of electromagnetic compatibility (EMC)。 A study of effects of EMI on CMOS NAND GATES is presented in this paper.Supposing an EMI signal has been coupled into a terminal of the CMOS IC ,we have measured and have simulated, with the aid of the general SPICE sofware, the EMI susceptibility of CMOS NAND GATES . The DC characteristics of CMOS NAND GATES under the interference of different EMI frequencies and powers are analyzed. A method of prediction the EMI effects on the DC transfer curve is presented. Moreover,the rise time and fall time of CMOS NAND GATES are also studied.

碩士<br>國立交通大學<br>電子研究所<br>107<br>Today’s integrated circuit technology is mature. Silicon-Based technology is in the process of miniaturization of electronic components. After entering the nanometer size, due to the limitations of process capability and component physics, all methods are considered to solve the dilemma of upgrading. Among them, Silicon Germanium (SiGe) technology utilizes a SiGe /Si heterointerface, lattice mismatch, and is compatible with mainstream complementary metal oxide semiconductor (CMOS) processes features. For high frequency characteristics, it has better low noise and lower power . Compared with gallium arsenide (GaAs), it has superior high integration, high electron conduction frequency, and high manufacturing yield. Now the chips change to System-on-Chip (SoC). In order to solve the problem of different clock phase of each sub-circuit, a phase-locked loop (PLL) is needed to reduce the phase deviation and make the clock phase of the system coincide and reduce the error of the output data. In this paper, the proposed wideband phase-locked loop is used by TSMC SiGe 180-nm BiCMOS process design, using the switch to control three voltage-controlled oscillator, and connecting it to the tripler to generate the signal . It covers the entire Q-band, to provide Q-band receiver a stable local oscillator signal source. The first part of this paper will introduce the basic structure of wideband phase-locked loop, to explore the advantages and disadvantages of each architecture. The second part is the design of the PLL circuit. The third part shows the simulation result and measurement result of the circuits mentioned in the second part. The final part is the paper summary, the problems I encountered in this design and the improvement direction to the future.

碩士<br>朝陽科技大學<br>資訊工程系碩士班<br>93<br>Due to the rapid development of semiconductor fabrication technique and the trends of System-on-chip-based (SoC-based) electronic products, the integrated circuit design becomes more and more complicated. Therefore, the reusable Silicon-intellectual-property (SIP) is desired, because it could shorten a great deal of design time and cost. This thesis is considered in Cadence environment for achieving pre- layout / post-layout simulation based on 0.35μm CMOS 2P4M process of TSMC. First, the priority encoder IP design is performed, then based on this encoder IP, both high-speed comparator and incrementer/decrementer are realized. Besides, the pre-layout / post-layout design of an adder is implemented by the use of multilevel folding and diagonal forwarding techniques. Finally, the serial-parallel multiplier with automatic complement detection is proposed. From the results of Hspice simulation and chip testing, the suggested priority encoder, adder, multiplier, comparator, and incrementer/ decrementer show the pretty better performance than that of traditional circuit scheme.

碩士<br>國立臺灣科技大學<br>電子工程系<br>87<br>As a device scales down and speeds up, the electromagnetic in-terference pollution coming from the device itself and from the envi-ronment can be much more severe. Especially, in a low-voltage and high-speed system, its performance is influenced by the interference noise conducted from the power supply. On the other hand, the elec-tromagnetic emission limit becomes tight. Thus, the electromagnetic compatibility becomes essential. Assuming that the electromagnetic interference signal couples into a CMOS transceiver, device suscepti-bility to electromagnetic interference is presented in this thesis. The influence of loading effect is also presented. Besides, the relationship between individual components and the electromagnetic interference effect are studied, based on the IC layout and device structure. A simulation method is presented to explain experimental data. Further-more, the role of routing capacitance between the metallization and poly-silicon on electromagnetic effect is investigated.

碩士<br>國立交通大學<br>管理學院科技管理學程<br>106<br>The development of semiconductor and package industry lead the CMOS Image sensor technology commercialization. Image sensors are widely used. With the prevalence of multimedia multimedia, digital image has gradually become a trend. The mobile device industry including mobile phone, IOT and Automobile electronics adopt the sensor application provide the market growth momentum of CMOS Image Sensor market The overall image sensor market in 2016 reached 11.6 billion US dollars. According to the analysis report of Yole Développement, they predict the market will enjoy 10% compound annual growth rate (CAGR). There are many players join in the market competition. Faced with fierce market competition, manufacturers must have a faster product development process, complex supply chain management with product life cycle and adopt an effective competitive strategy to meet the Internet of Things era. At the industry level, I use the diamond model and the five forces to analyze the competition strategy of the image sensor manufacturers. At the company level, the case study is used to discuss the suitable business model for the case company and put forward practical management implications through expert interview.

碩士<br>建國科技大學<br>電機工程系暨研究所<br>99<br>The present paper mainly design low voltage current supply circuit, whose properties are high swing, high output impedances, constant output current. In the research, the designed current supply has the properties of low voltage work, proper temperature coefficient compensate, and stable operation. Mainly, the software HSPICE on workstation is used for the circuit design. The devises in circuits are offered by National Chip Implementation Center. Under the 0.35μm regular processes of Taiwan Semiconductor Manufacture Cooperator, this paper is going to investigate, design, and compare.

碩士<br>國立交通大學<br>電信工程系<br>88<br>The fabrication of the VCO via 0.5um CMOS technology is designed for 2GHz wireless application. The architecture is the complementary nMOS and pMOS cross-coupled pair to enhance the negative conductance with internal resonator. The output signals are differential. The gate resistance is especially emphasized to assure the stationary of oscillation. The varactor from nMOS is also discussed. In the application of LNA and Mixer, with gate effect the dynamic range is increased due to conversion gain be reduced. The measurement and simulation have good match. The result is applied to VCO design in order to achieve the stationary of oscillation. The simulated results with output frequency 2.078~2.152GHz, single output power 10mW, and phase noise —102dBc at 600kHz offset are obtained. The power supply is 3V. It can be used as a local oscillator in a wide variety of wireless system.

碩士<br>國立交通大學<br>電子工程學系<br>85<br>The advantages of using OTA's as building blocks for larger subthresholdanalog circuits are that (i) the circuit structures are simple ; and (ii) thecircuits can be implemented by a standard CMOS process. One of the fundamentalfactors that limit the accuracy of the subthreshold MOS analog integratedcircuits is the mismatch in the drain current between identically drawn andbiased devices . Owing to exponential dependencies on the process variations ,however , devices in weak inversion usually exhibit a dramatically large mis-match in current as compared with that in above-threshold. The non- zero offsetvoltage is measured of the mismatch in OTA's. In this paper we extensively measure and analyze the offset voltage mis-match of the operational transconductance amplifier( OTA) circuits operating inthe subthreshold region . We treat the subthreshold offset voltage mismatch ofOTA from a statistical point of view . A statistical subthreshold OTA offsetvoltage mis-match model is derived analytically as function of process para-meter variations , area , and bias . Compared to the measured data, the devicemismatch model can be used to extract the variations in the two procee para-meters such as flat band voltage and body effect coefficients.The subthresholdOTA offset voltage mis-match has further been successfully predicted by meansof those extracted process parameter variations.

碩士<br>國立高雄應用科技大學<br>電子工程系<br>98<br>In this thesis, we analyze and improve the harmonic distortions of the transimpedance amplifiers (TIAs) in the receiver module of optical fiber cable television systems. We propose the nonlinear models of basic MOSFET amplifiers. Using these models and considering the input dc level, we analyze the second-order harmonic distortions for three kinds of series and feedback TIAs. The influences of input signal amplitude, dc level, and frequency on the harmonic distortions of TIAs are investigated. When the MOSFET amplifiers work at the saturation region, the results of harmonic distortions for our nonlinear model agree with the results for HSPICE simulation. In order to reduce the harmonic distortions of TIAs, we use the circuits constructions of the dual feedback and differential. Though HSPICE simulations, the reduction of harmonic distortion can be verified.

In communication systems the data signal gets deteriorated while passing through the transmission medium to the receiver. It becomes difficult for the receiver to retrieve data from this signal since its too weak . This deterioration is often caused due to interference of noise present in the transmission medium . Therefore a low noise amplifier is used at the first stage of the receiver .This amplifier not only strengthens the data signal but also adds minimum noise possible. A good low noise amplifier should have low noise figure, high gain, high linearity, high stability , less sensitivity , and less area. All these attribute are not perfectly best in a practical LNA . Thus engineers design LNAs according to specifications and rely on trade of between different factor to achieve their goals. In this thesis we have worked on a existing LNA circuit and tried to improve its power consumption while keeping the noise figure same and trading off the gain. Also this LNA has been implemented on Cadence Virtuoso at 90nm technology . Use of Current mode to build ciruit has become a choice over voltage mode. This is because current mode can have many advantages like better bandwidth , better gain, better linearity, lower power consumption. In this thesis a have implement and verified a differential difference current conveyor transconductance amplifier (DDCCTA) using LTSPICE.

碩士<br>國立彰化師範大學<br>機電工程學系<br>97<br>In this study, we continue the researches of novel thermal accelerometer based on the existed researches and designs. The importance of Packaging concept on thermal convection accelerometer is proposed firstly, and is proved successfully that the sensitivity of the accelerometer can be increased remarkable by packaging. A new type 2-D thermal accelerometer is manufactured by TSMC0.35μm process in this study, and two-dimension acceleration change is detected by design and analysis of the principle of thermopile sensor, which can apply to technologies of inclinometers and anemometers and flow meters. The temperature difference and change of the thermopiles located on the ends of heater caused by increasing the acceleration is simulated by ANSYS software. The analysis is conducted by changing the spacing between one end of thermopile and the heater and also the optimal design is obtained by analyzing the temperature difference and change. For component packaging, different heights between the roof of package and the chip for the gas convection may result in different responses. We studied the data from different heights and verified the temperature difference. If the temperature difference goes up it means the accelerometer is with good sensitivity. According to our simulation, we can get the best data when the distance from the heater to thermopile is 60μm. Under the packaging height of 500μm, we can obtain the optimum design. For thermal accelerometer sensitivity measurement, the greater the heating power, we will get larger thermopile output voltage. We believe that in addition to the structural components of the design, especially the gas convection, the topics of the packaging and materials, as well as the structure, the configurations of components both in the design and package need to be done to optimize the design considerations. Our research on, through this study explores further values of convection type accelerometers for research beyond many researchers in the world.

碩士<br>國立交通大學<br>電子研究所<br>83<br>In this thesis, an 8-bit 62.5MS/sec A/D converter designed and fabricated in a 0.8um CMOS process, is presented. The A/D converter was designed to have a sampling time of 8ns(including the nonoverlapping time with 2ns) at clock rate of 125MHz. The 8-bit 12.5MS/sec A/D converter cell is implemented by a four- stage architecture. This structure can be designed without the operational amplifiers with either high gain or a large output swing. The parallel processing is applied to the five A/D converters connected in parallel to improve the conversion rate up to five times speed. The linearity error is within 1/2 LSB. The post-simulation result shows the throughout rate can be 12.5MS/sec with 8-bit resolution for the A/D converter cell. The core of the 62.5MS/sec parallel A/D converter array occupies an area of 3.2mm×4.6mm, and the power consumption is about 150mW.

博士<br>國立臺灣大學<br>電子工程學研究所<br>96<br>In recent years, low dropout regulator (LDO) has been widely utilized as the voltage regulation and conversion stage for low power applications. Compare with a switch-mode power supply, an LDO provides an accurate output voltage with only a few off-chip components. Furthermore, an LDO features lower noises, faster transient response, less cost and smaller volume. These advantages make LDO a popular building block for the power management of battery-powered portable electronic systems and for post regulation of switch-mode power supplies. Nevertheless, for a generic CMOS LDO which uses PMOS as the pass device using the conventional compensation scheme, an off-chip load capacitor ranges between 1µF to tens of micro farads is required and its parasitic equivalent series resistance (ESR) values must fall into a specific tunnel-like region to guarantee system stability of the LDO. The off-chip load capacitor hinders board size reduction and the ESR limits the optimization of LDO performance. Moreover, there is inevitable PSR degradation at high frequencies if the conventional compensation scheme is used. In this dissertation, the basic background knowledge of LDO and several existing performance enhancement techniques in literature are discussed. After that, the proposed compensation schemes with three fabricated LDOs are presented. Based on the proposed compensation schemes, two of the LDOs are designed to relieve the stability requirement of load capacitor and its ESR, and the other LDO improves the high-frequency power supply rejection (PSR) performance. Among the three fabricated LDOs, the first LDO uses a novel compensation scheme and a split-structured pass device such that the LDO is stable with a 0.33μF load capacitor. Furthermore, compared with the LDO using the conventional compensation scheme, it has larger stable range for the load capacitor and the ESR. Therefore, different types of capacitors can be used by the proposed LDO and the transient response of the LDO can be optimized by using a load capacitor with ultra low ESR. As for the second LDO, the pole-zero pairs compensation scheme derived from the first LDO is used. In addition to the split-structured pass device, a multi-path error amplifier is employed to realize the compensation scheme. The LDO imposes no specific constraint on the load capacitor and only requires the ESR of the load capacitor less than the equivalent load resistance. As a result, the LDO provides the capacitor-free operation and the flexibility for load capacitor selection. Users can choose any suitable load capacitor for the consideration of cost, board size and transient ripples. To enhance the PSR at high frequencies, a compensation strategy is proposed and verified by the third LDO. Realized by cascading gain stages with lower output impedance, the compensation strategy pushes all internal poles beyond the unity-gain frequency of the loop gain. Since there is no internal low-frequency pole, the PSR degradation at high frequencies is avoided. In this way, The LDO achieves -42dB PSR at DC and the PSR bandwidth is 1MHz at full load. The LDO is suitable for supplying the circuit blocks sensitive to the ripples of the supply rails.

博士<br>國立臺灣大學<br>電機工程學研究所<br>92<br>As the technology continuously scaling down, the short channel effects and the presence of the voltage, process, and temperature variations make the circuit hard to design. For solving these problems, the feedback technique is widely used. To acquire the clock phase and to assure the duty cycle of the clock, it results in the growth of the phase-locked loops (PLLs), delay-locked loops (DLLs), and pulsewidth control loops (PWCLs). This thesis mainly dedicates to the analysis and improvement in these three fields. In this thesis, a PWCL, a PWCL with DLL, and a PLL were explored and fabricated in the 0.35μm process. First, a fast-locking PWCL with its circuit models and mathematical analysis are proposed. The circuit models of the PWCL are derived first. Based on the circuit models, the lock times corresponded to the conventional and the proposed PWCLs can be calculated. The experimental results verify the analysis and achieve fast-locking capability. Second, a new single-path PWCL with built-in DLL is presented. This PWCL can cooperate with a DLL and the voltage-controlled delay line (VCDL) in a DLL can be integrated with the buffer line in a PWCL. The trade-off between the duty cycle precision and the robustness against the process and temperature variations can be eliminated. Also, the tuning range of the duty cycle can theoretically be extended to 100% duty cycle. Moreover, the duty cycle of the output clock is presettable. Finally, the research concentrates on a PLL. The objects of this chapter have two parts: time constant calibration in the loop filter and fast-locking design. Based on the time constant calibration, the loop dynamics, damping factor and natural frequency, can track with the period of the reference clock. In the fast-locking design, two methods are proposed to reduce the lock times in the frequency and phase acquisitions. To compare the lock times spent in the conventional and the proposed PLL mathematically, a method to estimate the lock time in a PLL with the cycle-slipping phenomenon is derived.

The Internet of Things (IoT) paradigm is enabling easy access and interaction with a wide variety of devices, some of them self-powered, equipped with microcontrollers, sensors and sensor networks. Low power and ultra-low-power strategies, as never before, have a huge importance in today’s CMOS integrated circuits, as all portable devices quest for the never-ending battery life, but also with smaller and smaller dimensions every day. The solution is to use clever power management strategies and reduce drastically power consumption in IoT chips. Dynamic Voltage and Frequency Scaling techniques can be rewardingly, and using operation at subthreshold power-supply voltages can effectively achieve significant power savings. However, reducing power-supply voltages impose reduction of performance and, consequently, delay increase, in turn it makes the circuit more vulnerable to operational-induced delay-faults and transientfaults. What is the best compromise between power, delay and performance? This thesis proposes an automatic methodology and tool to perform power-delay analysis in CMOS gates and circuits, to identify automatically the best compromise between power and delay. By instantiating SPICE simulator, the proposed tool can automatically perform analysis such as: power-delay product, energy-delay product, power dissipation, or even dynamic and static power dissipations. The optimum operation point in respect to the power-supply voltage is defined, for each circuit or sub-circuit and considering subthreshold operation or not, to the minimum power-supply voltage where the delays do not increase too much and that implements a compromise between delay and power consumption. The algorithm is presented, along with CMOS circuit examples, all the analysis’ results are shown for typical benchmark circuits. Results indicate that subthreshold voltages can be a good compromise in reducing power and increasing delays.<br>O aparecimento e a expansão de novas tendências da indústria electrónica fortemente direccionadas ao paradigma da Internet of Things (IoT) têm vindo a dar uma relevância cada vez maior à necessidade da evolução da electrónica, no sentido da interligação e intercomunicação entre equipamentos, no sentido da miniaturização em geral e, consequentemente, no sentido de uma melhor eficiência energética. Temos assim, na prática, vindo recentemente a assistir em diversas áreas ao surgimento progressivo de um número exponencial de pequenos dispositivos electrónicos, altamente compactos, com elevado grau de integração de funções e habitualmente interligados entre si em redes de dados. Habitualmente têm como missão genérica a recolha, processamento e transmissão de dados acerca do ambiente que os rodeia. Esta grande variedade de diferentes dispositivos habitualmente relacionados ao campo de IoT tem como principais funções a recolha e transdução de dados obtidos do ambiente circundante por sensores. Tem por isso geralmente uma muito limitada interação com o ambiente circundante, e nesse sentido, justifica-se que as suas principais características sejam as pequenas dimensões e fácil portabilidade. Justifica-se também que não é estritamente essencial que tenham elevada performance a nível de processamento. Sendo alimentados por baterias, ou nalguns casos alimentados por energia do ambiente, estes dispositivos precisam obrigatoriamente de consumir muito pouca energia, sendo os seus requisitos de energia de alimentação muito restritos. Dados os restritos requisitos de consumo energético, são tipos de circuitos muito adequados à aplicação das mais recentes e avançadas estratégias de gestão de potência destinadas a reduzir drasticamente a potência nos modernos circuitos integrados CMOs. Torna-se assim claro, que os mais importantes requisitos futuros de dispositivos na área de IoT, assim como de diversas famílias de dispositivos electrónicos em geral, serão tendencialmente a necessidade de redução de consumo energético, ainda que esta redução seja feita à custa de algum nível de redução em performance. Esta tendência baseia-se no crescimento de importância da temática da eficiência energética em circuitos, num momento em que a concentração de consumo energético e consequentemente de dissipação térmica, em áreas muito reduzidas de circuitos integrados CMOs atinge níveis muito elevados e preocupantes. Uma possível solução para enfrentar este complexo desafio, com crescentes requisitos e restrições para actuais e futuros circuitos CMOs, tendo em atenção princípios globais de eficiência energética, consiste em conjugar as habituais técnicas de gestão de potência dinâmica em circuitos, com as mais recentes e avançadas técnicas de alimentação em ‘ultra-low-power voltage’, tentando alcançar assim ganhos de potência muito consideráveis e significativos. Assim, associando as conhecidas técnicas de gestão de potência como por exemplo a Dynamic Voltage and Frequency Scaling (DVFS) com as mais recentes técnicas de ultra-low-power voltage como a recente técnica de operação em tensões de alimentação subthreshold pode potencialmente se revelar como a melhor solução para enfrentar este complexo problema e assim melhorar significativamente a eficiência energética em futuros circuitos CMOS. Contudo, quando aplicamos técnicas de potência de very-low-power ou ultra-lowpower, como as técnicas de operação a tensões subthreshold, existem algumas desvantagens e alguns efeitos adversos que devem ser cuidadosamente considerados e, se possível, contidos e minimizados. A mais importante destas consequências directas é a perda de performance do circuito que deriva naturalmente do aumento nos atrasos de propagação internos do circuito. As restantes desvantagens da utilização de técnicas de alimentação a níveis muito baixos derivam todas elas do facto do circuito se tornar em geral muito mais sensível a perturbações internas ou externas. Esta é claramente uma consequência natural para uma operação a este nível de reduzida energia. Como seria de esperar, pelo exposto, a operação a níveis de tensão ultra-low-voltage têm a consequência de torná-lo mais sensível a distúrbios e interferências, aumentado assim o risco de falhas operacionais, dado que o nível dos seus sinais internos de operação ao longo do circuito é muito reduzido. Alguns efeitos adversos afectos ao uso de técnicas de ultra-low-power em circuitos CMOs incluem, portanto, o aumento da vulnerabilidade do circuito a Single Event Upsets (SEUs), incluem também o aumento de vulnerabilidade a falhas induzidas de delay de operação, assim como um aumento de sensibilidade do circuito a falhas geradas por transientes. Tendo consciência do incremento de riscos operacionais envolvido em circuitos subthreshold, são necessários cuidados no sentido de conter e minimizar tanto quanto possíveis efeitos indesejados, por exemplo controlando cuidadosamente as condições operacionais do circuito e melhorando a sua blindagem a interferências. Considerando que o uso das técnicas de ultra-low-power pode ser provavelmente a melhor solução para cumprir rigorosos requisitos de eficiência energética para um circuito CMOs, é necessário considerar também que estas técnicas podem gerar uma considerável perda de performance, traduzida por um maior atraso interno. Assim, torna-se necessário estudar claramente, em subthreshold voltages, a evolução da perda de performance face aos grandes ganhos de energia quando caminhamos no sentido da redução da tensão de alimentação de um circuito CMO’s. Tendo como base um estudo custo/benefício da evolução de dois factores cruciais na operação de um circuito, como o factor energia e o factor performance, torna-se possível tentar alcançar uma solução de compromisso entre a potência dissipada (energia consumida) e o atraso de propagação, traduzido como a performance do circuito. O trabalho aqui apresentado propõe uma metodologia automatizada, capaz de enfrentar os desafios do estudo mencionado. Propõe ainda uma ferramenta de software desenhada para analisar em detalhe portas lógicas CMOs de uma livraria de portas existente, assim como circuitos completos composto por diversas portas lógicas. O software proposto analisa um circuito ou sub-circuito lógico, identificando automaticamente o melhor nível de alimentação de baixa tensão (ponto de operação óptimo) que permite obter o melhor compromisso entre potência e atraso, em termos gerais o melhor compromisso entre energia e performance. Como suporte e assistência à metodologia proposta esta ferramenta foi criada para acelerar os testes de simulação Hspice sobre portas lógicas e circuitos, executando cálculos rápidos sobre resultados de simulação e acelerando a obtenção de resultados de eficiência energética e de performance para análise. Através da instanciação directa do simulador Hspice, a ferramenta facilita a análise de importantes parâmetros de definição de portas lógicas e circuitos, como por exemplo: o atraso de propagação, o power-delay-product (PDP), o energy-delay-product (EDP), e a dissipação de potência total e parcial (estática e dinâmica). O desenvolvimento inicial da ferramenta permitiu realizar múltiplos testes e simulações e através da análise destes resultados desenvolver a metodologia low-power apresentada no trabalho, a posterior aplicação da metodologia pela ferramenta a um circuito CMO’s permite eficientemente identificar o seu ponto de operação óptimo para operação em baixo nível. Um ponto de operação óptimo de uma porta lógica é definido pelo método como o mais baixo nível de tensão de alimentação que não compromete a operação válida da porta, reduzindo por isso fortemente a potência dissipada. No entanto este ponto deve ainda minimizar (tanto quanto possível) os atrasos de propagação na porta. Assim, este ponto deriva de um compromisso ponderado para uma alimentação com consumo de energia muito baixo, que contudo não gere ainda atrasos na porta que provoquem significativas perdas em performance. Acima de tudo, o trabalho desenvolvido pretende apresentar uma abordagem clara e directa ao design e implementação de lógica digital em modo de subthreshold, aplicado ao contexto dos modernos circuitos de electrónica digital. Pretende-se estabelecer um conjunto de técnicas e métodos simples e claros, suportados num estudo incidente em regras teóricas e em simulações prácticas, que possam servir como normativos propostos para o design de circuitos adaptados ao funcionamento em modos de muito baixa energia. O objectivo final será enfrentar e a longo prazo tentar resolver o problema cada vez maior e mais importante da melhoria de eficiência energética em circuitos electrónicos genéricos.

碩士<br>義守大學<br>機械與自動化工程學系碩士班<br>94<br>Due to huge demand for optical mouse, digital cameras, photo-mobile phones, web-cam and optoelectronic devices in home entertainment in recent years, the production and packaging techniques for CMOS image sensor (CIS) have been rapidly developed and improved. The CIS will gradually become main product to take over CCD camera for its low price and high performance. The reliability and thermal design for CMOS image sensor has been fully studied in this paper. It has been found that uv glue and solder paste are much easiest to failure in thermal fatigue for CIS structure. Therefore, it would be an important issue to choose suitable materials for CIS package. The thermal and moisture-absorption characteristic of uv glue and molding compound (Dam) for CIS have been studied in this paper. In addition, the predicted thermal fatigue life for different series of lead-free SnAgCu solder paste has been conducted in this research. Because the coefficient of thermal expansion (CTE) of the air is much greater than other materials and the rate of absorbed moisture is faster than other polymer materials, it is important to develop an effective moisture-resistant mechanism for CIS package, which has been carefully studied in this paper. A three-dimensional solid model of CMOS image sensor based on finite element ANSYS software is developed to predict the thermal-induced strain, stress distributions, and the hygroscopic swelling strain. The predicted thermal-induced displacements were found to be excellent agreement with the Moir? Interferometry experimental in-plane deformation. In this paper, the application of sub-model scheme in thermal cycle test prediction was also studied for its efficiency and interesting in recent years.

碩士<br>大同工學院<br>電機工程研究所<br>86<br>This thesis focuses on the analysis and application of PCCL. The PCCL is especially used in low-power VLSI and a universal gate. We try to implement a set of logic functions and discuss the waveforms attenuated by pass-transistors. We discuss the technique improved by inverter-restoring and the waveform can be restored to at 500 MHz operation frequency. We try to replace the level-restoring circuit of PCCL by inverter-latch one. Finally, we don't implement by BDD, but implement by AND and OR gates of convWe simulate the critical-path waveform by HSPICE. The process parameters adopt the UMC 0.5 process for education. In the fixed process, The result of power-delay-product improves to nearly 1/3 compared with CMOS logic-style in high process.

碩士<br>國立中興大學<br>電機工程學系所<br>101<br>The thesis includes four topics. The first design topic a low noise amplifier（LNA）in W-band that used in automotive collision avoidance radar and was fabricated in TSMC 90nm CMOS process. We used coplanar waveguide transmission line for input and output matching in layout, this kind of transmission line adopted ground shielding technique to enhance Q value and decrease signal loss from substrate. This chapter will discuss about how to design the dimension of transistor and proper bias, and also to derive a lower noise figure of the transistor size and passive components from noise model. The measurement shows input and output matching are under -10dB in the operation frequency 78GHz, gain is 12.57dB, 3-dB bandwidth is 74GHz-90GHz, IIPᴣ is -8.1dBm, and noise figure is 6.07dB. Compared with previous references in the same operation frequency, our design had better noise figure. Power consumption in measurement was 28.56mW. The second topic describes a 24GHz direct-conversion receiver which is fabricated in TSMC 0.18µm CMOS. This LNA uses three stages cascode topology to enhance gain, and employs an active balun to transfer single signal to differential. This mixer is double balanced type, and designs active loads to decrease power dissipation, it also parallels an inductor to eliminate parasitic capacitances between the drain of transistor on the transconductance stage. The measured input and output matching are under -10dB in the operation frequency, conversion gain is 18.7dB, IIPᴣ is -22dBm, and noise figure is 8.63dB. The measurement shows power consumption is 62.3mW. The third topic implement a direct-conversion receiver applied to 802.11a fabricated in TSMC 0.18µm CMOS. LNA is current reused topology, and mixer adopts PMOS transistor at switch stage to reduce headroom. The simulation results are input and output matching are under -10dB, conversion gain is 31.56dB, IIPᴣ is -32dBm, P1ɗB is -41dBm and noise figure is 9.22dB. Power consumption is 41mW. The forth topic introduces a 24GHz super-heterodyne receiver frontend uses in TSMC 0.18µm CMOS technology. This design uses three stages cascode topology LNA connects single balanced mixer, that can neglect the problem to transfer single signal to differential. After measurement, conversion gain is 20.4dB, IIPᴣ is -22dBm, P1ɗB is -12dBm and noise is 8.37dB. Power consumption ias 64.8mW, and core area is 54mW.