Дисертації з теми "Analyse des circuits"
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Melcher, Elmar. "Analyse temporelle de circuits combinatoires /." Paris : Ecole nationale supérieure des télécommunications, 1993. http://catalogue.bnf.fr/ark:/12148/cb355884954.
Повний текст джерелаOndo, Ossa Albert. "Analyse des circuits financiers au Gabon." Nancy 2, 1985. http://www.theses.fr/1985NAN20005.
Повний текст джерелаBENBOUDJEMA, KAMEL. "Analyse symbolique des circuits micro-ondes." Paris 6, 1995. http://www.theses.fr/1995PA066524.
Повний текст джерелаOrdas, Thomas. "Analyse des émissions électromagnétiques des circuits intégrés." Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20001.
Повний текст джерелаIn the area of secure integrated circuits, such as smart cards, circuit designers are always looking to innovate to find new countermeasures against attacks by the various side channels that exist today. Indeed, side channels attacks such as the analysis of electromagnetic emissions permit to extract secret information contained in circuits. Based on this observation, in this thesis, we focused on the study of electromagnetic analysis to observe the analysis possibilities. This manuscript is organized as follows. Initially, we presented a measurement system for electromagnetic emissions in time domain, and the results obtained on different circuits. From these results, a summary of opportunities, relating to the security threat, posed by electromagnetic analysis, is proposed as well as solutions proposals to reduce electromagnetic radiations of integrated circuits. In a second step, we are interested in the simulation of electromagnetic emissions. A state of the art of simulation tools which exist today, has allowed us to demonstrate that none of them allowed to have a fine enough resolution in terms of electromagnetic emissions. To fill this gap, a simulation tool has been developed and to validate this flow, a comparison between measurement results and simulation results was performed
Romefort, Dominique Villedieu. "Analyse statistique des circuits intégrès : caractérisation des modèles." Toulouse 3, 1990. http://www.theses.fr/1990TOU30087.
Повний текст джерелаDehbaoui, Amine. "Analyse Sécuritaire des Émanations Électromagnétiques des Circuits Intégrés." Thesis, Montpellier 2, 2011. http://www.theses.fr/2011MON20020.
Повний текст джерелаThe integration of cryptographic primitives in different electronic devices is widely used today incommunications, financial services, government services or PayTV.Foremost among these devices include the smart card. According to a report published in August 2010, IMS Research forecasts that the smart card market will reach 5.8 billion units sold in this year. The vast majority is used in telecommunications (SIM) and banking.The smart card incorporates an integrated circuit which can be a dedicated processor for cryptographic calculations. Therefore, these integrated circuits contain secrets such as secret or private keys used by the symmetric or asymmetric cryptographic algorithms. These keys must remain absolutely confidential to ensure the safety chain.Therefore the robustness of smart cards against attacks is crucial. These attacks can be classifiedinto three main categories: invasive, semi-invasive and non-invasive.Non-invasive attacks can be considered the most dangerous, since this kind of attack can be achieved without any contact with the circuit.Indeed, while using electronic circuits that compose them are subjected to variations in current and voltage. These variations generate an electromagnetic radiation propagating in the vicinity of the circuit.These radiations are correlated with secret information (eg a secret key used for authentication). Several attacks based on these leakages were published by the scientific community.This thesis aims to: (a) understand the different sources of electromagnetic emanations of integrated circuits, and propose a localized near field attack to test the robustness of a cryptographic circuit and (b) propose counter-measures to these attacks
Laurent, Jacques. "Projet ACIME analyse des circuits intégrés par microscopie électronique /." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00311762.
Повний текст джерелаKALFANE, ANISHA. "Analyse de la sensibilite technologique des circuits integres gaas." Université Louis Pasteur (Strasbourg) (1971-2008), 1993. http://www.theses.fr/1993STR13215.
Повний текст джерелаRebaï, Mohamed Mehdi. "Analyse des circuits intégrés par laser en mode sonde." Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0362/document.
Повний текст джерелаThe main objective of the presented research work in this PhD thesis is to help to understand the different mechanisms and phenomena involved in the interaction of a laser with a semiconductor in the analysis of a submicron integrated circuit. The aim is to master and improve the Electro Optical Probing techniques. Miniaturization and densification of electronic components lead the failure analysis techniques using Laser to their limits. Knowing the impact of different physical, optical and electrical parameters on a probing analysis is a key to improve the understanding the measured EOP signals. These studies also show the significant effect of temperature on the EOP techniques
Yahya, Eslam. "Modélisation, analyse et optimisation des performances des circuits asynchrones multi-protocoles." Grenoble INPG, 2009. http://www.theses.fr/2009INPG0145.
Повний текст джерелаAsynchronous circuits show potential interest from many aspects. However modeling, analysis and optimization of asynchronous circuits are stumbling blocks to spread this technology on commercial level. This thesis concerns the development of asynchronous circuit modeling method which is based on analytical models for the underlying handshaking protocols. Based on this modeling method, a fast and accurate circuit analysis method is developed. This analysis provides a full support for statistically variable delays and is able to analyze different circuit structures (Linear/Nonlinear, Unconditional/Conditional). In addition, it enables the implementation of timing analysis, power analysis and process-effect analysis for asynchronous circuits. On top of these modeling and analysis methods, an optimization technique has been developed. This optimization technique is based on selecting the minimum number of asynchronous registers required for satisfying the performance constraints. By using the proposed methods, the asynchronous handshaking protocol effect on speed, power consumption distribution and effect of process variability is studied. For validating the proposed methods, a group of tools is implemented using C++, Java and Matlab. These tools show high efficiency, high accuracy and fast time response
Ouchet, Florent. "Analyse et amélioration de la robustesse des circuits asynchrones QDI." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00680544.
Повний текст джерелаRenaud, Nicolas. "Calculateurs quantiques hamiltoniens : vers une analyse symbolique des circuits quantiques." Toulouse 3, 2009. http://thesesups.ups-tlse.fr/669/.
Повний текст джерелаThe miniaturisation of electronic devices force us to propose solutions to keep increasing computing power of processors when a single transistor will be implemented in a single molecule. We propose here to implement not a simple switch but a complex Boolean function inside a single molecule following the Quantum Hamiltonian Computing (QHC) approach. We present here several methods, based for exemple on the Karnaugh tables or on a symbolic analysis, to implement any Boolean function in a quantum system. We demonstrate the innovative properties of such quantum circuits such as the non-duplication of the logical inputs at several points of the circuit or the parallelisation of any set of logical functions. Based on the symbolic analysis, several experimental set-ups are then proposed to embody such a calculator inside a single molecule inserted in a tunnel junction. One of those set-ups has been realized providing the first experimental proof of the QHC approach feasability
Chotin, Eric. "Placement automatique de circuits intégrés." Phd thesis, Grenoble INPG, 1992. http://tel.archives-ouvertes.fr/tel-00341773.
Повний текст джерелаPerret, Étienne Aubert Hervé. "Application de l'approche par changements d'échelle aux circuits planaires hyperfréquences." Toulouse : INP Toulouse, 2005. http://ethesis.inp-toulouse.fr/archive/00000153.
Повний текст джерелаBerger, Thierry. "Analyse du comportement d'interconnexions damascènes en cuivre testées en électromigrations." Lyon, INSA, 2001. http://www.theses.fr/2001ISAL0009.
Повний текст джерелаThe increase of integrated circuits speed functioning leads to the replacement of Al-based interconnects by copper interconnects integrated with the damascene process. Electromigration, which is a matter migration induced by an electric current, remains the failure mode ruling the reliability of these new interconnects. This reliability failure mode has been studied using moderately accelerated tests performed at package level and highly accelerated tests performed at wafer level. These two kinds of tests provided very consistent results. From the reliability point of view, the substitution of etched aluminum interconnects by damascene copper interconnects provided a substantial benefit whose magnitude depends on both the deposition process for copper and the nature of the diffusion barrier which prevents copper from diffusing towards the silicon substrate. For polycrystalline interconnects, the activation energy values of the diffusion processes are substantially lower than the reference values of copper self diffusion at grain boundaries. Nevertheless, a detailed failure analysis provided evidences that grain boundary diffusion plays a key role in the damaging process of copper interconnects. For bamboo-type interconnects (line width lower than grain size), the dominating transport mechanism is diffusion at the upper interface. The texture of damascene copper interconnects is much more complex than the texture of etched Al-based lines and has no substantial impact on the electromigration behaviour of the copper lines. The systematic observation of butterfly wings-shaped extrusions will necessitate detailed studies for a better understanding of this additional failure mode
Savart, Denis. "Analyse de défaillances de circuits VLSI par testeur à faisceau d'électrons." Phd thesis, Grenoble INPG, 1990. http://tel.archives-ouvertes.fr/tel-00337865.
Повний текст джерелаDIOURY, KARIM. "Analyse temporelle hierarchique des circuits vlsi a tres haute densite d'integration." Paris 6, 1998. http://www.theses.fr/1998PA066096.
Повний текст джерелаKeramat, Mansour. "Analyse statistique et optimisation du rendement de fabrication des circuits electroniques." Paris 11, 1998. http://www.theses.fr/1998PA112015.
Повний текст джерелаSavart, Denis Courtois Bernard. "Analyse de défaillances de circuits VLSI par testeur à faisceau d'électrons." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00337865.
Повний текст джерелаBergher, Laurent Courtois Bernard. "Analyse de défaillances de circuits VLSI par microscopie électronique à balayage." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00315589.
Повний текст джерелаChibani, Kais. "Analyse de robustesse de systèmes intégrés numériques." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT080/document.
Повний текст джерелаIntegrated circuits are not immune to natural or malicious interferences that may cause transient faults which lead to errors (soft errors) and potentially to wrong behavior. This must be mastered particularly in the case of critical systems which impose safety and/or security constraints. To optimize protection strategies of such systems, it is essential to identify the most critical elements. The assessment of the criticality of each block allows limiting the protection to the most sensitive blocks. This thesis aims at proposing approaches in order to analyze, early in the design flow, the robustness of a digital system. The key criterion used is the lifetime of data stored in the registers for a given application. In the case of microprocessor-based systems, an analytical approach has been developed and validated on a SparcV8 microprocessor (LEON3). This approach is based on a new methodology to refine assessments of registers criticality. Then a more generic and complementary approach was implemented to compute the criticality of all flip-flops from a synthesizable description. The tool implementing this approach was tested on significant systems such as hardware crypto accelerators and a hardware/software system based on the LEON3 processor. Fault injection campaigns have validated the two approaches proposed in this thesis. In addition, these approaches are characterized by their generality, their efficiency in terms of accuracy and speed and a low-cost implementation. Another benefit is also their ability to re-use the functional verification environments
Moudjahed, Mohamed. "Amélioration de la stabilité d'un réseau électrique au moyen d'une bobine supraconductrice." Besançon, 1996. http://www.theses.fr/1996BESA2064.
Повний текст джерелаThe use of a power network near its operating limits can provoque its instability when a disturbance occurs. The damping of the system's oscillations can be obtained by the classical means such as automaticvoltage regulator and governor action but also by a SMES (Superconducting Magnetic Energy Storage) which is one of the FACTS (Flexible AC Transmission Systems) devices. These are used more and more in the power systems. The SMES is composed of a superconducting coil and a GTO power converter. It damps the system's oscillations by exchanging the power with the system. Active power and/or reactive power can be consumed or supplied by the SMES according to the system requirement. In this thesis, a 3 machines - 9 nodes network is simulated. The study has showed that the system is instable without regulation. The impacts of the classical regulation and the SMS on the network's behaviour when the system is subject to strong constraints are studied. The impact of the SMS on the system stability is better than the action of the classical regulation. To use the SMES as speed regulator or as compensator depends on the specific problems of the system. The optimal location of the SMES is generally near the machines at risk. In this case, the dominant function of the SMES is its speed regulation. If there is no particular machine which has a dominant impact on the system stability, the SMES is connected to the node near the weak point of the network. In this case, it is used as compensator and it contributes to maintain the voltage stability
Dusausay, Serge. "MAXIM, un logiciel de macrosimulation temporelle de circuits : développement et analyse de sa bibliothèque de macromodèles, application aux circuits bipolaires." Paris 11, 1986. http://www.theses.fr/1986PA112330.
Повний текст джерелаAmmari, Abdelaziz. "Analyse de sûreté des circuits complexes décrits en langage de haut niveau." Grenoble INPG, 2006. https://tel.archives-ouvertes.fr/tel-00101622.
Повний текст джерелаThe probability of transient faults increases with the evolution of the technologies. Several approaches have been proposed to early analyze the impact of these faults in a digital circuit. It is in particular possible to use an approach based on the injection of faults in a RT-Level VHDL description. In this thesis, we make several contributions to this type of analysis. A first considered aspect is to take into account the digital circuit's environment during the injection campaigns. So, an approach based on multi-level dependability analysis has been developed and applied to an example. The injections are performed in the digital circuit described at the RT-Level while the rest of the system is described at a higher level of abstraction. The results' analysis shows that failures appearing at circuit's level have in fact no impact on the system. We then present the advantages of the combination of two types of analyses : classification of faults with respect to their effects, and a more detailed analysis of error configurations activated in the circuit. An injection campaign of SEU-like faults was performed on a 8051 microcontroller described at RT-Level. The results show that the combination of the two type analyses allows a designer to localize the critical points, facilitating the hardening stage. They also show that, in the case of a general processor, the error configurations can be dependent on the executed program. This study also demonstrates that injecting a very small percentage of the possible faults gives useful information to the designer. The same methodology has been used to validate the robustness obtained with a software hardening. The results show that some faults are not detected by the implemented mechanisms although those were previously validated by fault injections based on an instruction set simulator. The last aspect of this thesis concerns the fault injection in analog blocks. In fact very few works cover this subject. We thus propose a global analysis flow for digital, analog or mixed circuits, described at behavioral level. The possibility to inject faults in analog blocks is discussed. The results obtained on a PLL, chosen as case study, have been analysed and show the feasibility of fault injections in analog blocks. To validate this flow, fault injections were also performed at transistor level and compared to those performed at high level. It appears a good correlation between the results obtained at the two levels
Akrout, Fathi. "Analyse macromarketing de la dynamique des circuits de distribution : construction et test d'un modèle intégré." Rennes 1, 1996. http://www.theses.fr/1996REN1A006.
Повний текст джерелаLasbouygues, Benoît. "Analyse statique temporelle des performances en présence de variations de tension d'alimentation et de température." Montpellier 2, 2006. http://www.theses.fr/2006MON20027.
Повний текст джерелаIn the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of numerous new factors that impose a drastic change in validation and physical verification methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical timing engine. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore our work proposes a novel method, based on non-linear derating coefficients, to account of these environmental variations. This method allows computing the delay of logical paths considering specifics conditions of each cell. The combined use of reduced supply voltage with high threshold voltage values may reverse the temperature dependence of designs, the worst case timing conditions becomes less predictable and can occur at different temperatures. This effect, called temperature inversion phenomenon is particularly critical for low power applications. The characterization, at each level (from device to critical paths) allowed us to define some techniques to take into account this effect into the design flow
Nwokoye, Okechukwu Donatus. "Nouveau matériau sandwich pour circuits imprimés : Analyse théorique, réalisation de prototypes et essais de validation." Besançon, 1989. http://www.theses.fr/1989BESA2036.
Повний текст джерелаVachoux, Alain. "Analyse temporelle de grands circuits intégrés MOS par relaxation de formes d'onde /." [S.l.] : [s.n.], 1988. http://library.epfl.ch/theses/?nr=733.
Повний текст джерелаVirazel, Arnaud. "Test intégré des circuits digitaux : analyse et génération de séquences aléatoires adjacentes." Montpellier 2, 2001. http://www.theses.fr/2001MON20094.
Повний текст джерелаAvot, Grégoire. "Analyse temporelle des circuits intégrés digitaux CMOS, pour les technologies profondément submicroniques." Paris 6, 2003. http://www.theses.fr/2003PA066009.
Повний текст джерелаEmonin, Stéphanie. "Analyse de circuits optiques passifs et actifs en microscopie a sonde locale." Dijon, 1998. http://www.theses.fr/1998DIJOS038.
Повний текст джерелаConard, Didier. "Traitement d'images en analyse de défaillances de circuits intégrés par faisceau d'électrons." Grenoble INPG, 1991. http://tel.archives-ouvertes.fr/tel-00339510.
Повний текст джерелаConard, Didier Courtois Bernard Courtois Bernard. "Traitement d'images en analyse de défaillances de circuits intégrés par faisceau d'électrons." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00339510.
Повний текст джерелаEl, Oualkadi Ahmed. "Analyse comportementale des filtres à capacités commutées pour les radiocommunications : conception d'une nouvelle architecture en technologie BiCMOS 0.35 μm". Poitiers, 2004. http://www.theses.fr/2004POIT2354.
Повний текст джерелаThe main objective is to study the feasibility of monolithic switched capacitor filters for radiocommunications. The behavioral analysis of these filters required the establishment of an original algorithm based on the conversion matrixes formalism. This analysis method seems to be nowadays among the more efficient in term of calculation time. At low-frequencies the command of these filters is performed by using a shift register. However, this technique is not feasible in RF domain. An original solution proposed, it consists in the command of the filter by a ring voltage controlled oscillator with XOR gates. The simulation results have shown the impact of the command circuit jitter on the filter behavior and the adaptability of the whole circuit for digital transmission. A prototype has been fabricated in standard BiCMOS 0. 35 μm technology. The experimental results are in agreement with simulations ones and are susceptible to render these filters attractive for RF applications
Surre, Frédéric. "Contribution à l'étude de circuits multi-échelles en électromagnétisme." Toulouse, INPT, 2003. http://www.theses.fr/2003INPT019H.
Повний текст джерелаDusausay, Serge. "MAXIM un logiciel de macrosimulation temporelle de circuits développement et analyse de sa bibliothèque de macro modèles, application aux circuits bipolaires." Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37597358w.
Повний текст джерелаBouchaala, Afef. "Méthode de modélisation prédictive de boîtiers des circuits intégrés en vue d’anticiper avant design l’immunité au bruit du circuit." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S128.
Повний текст джерелаModern electronic systems require a high-level of integrations. As a result, some phenomena which are known as ElectroMagnetic Compatibility (EMC) issues are arising, and they are the major causes of system redesign. This main objective of this work is to develop a predictive methodology for systems immunity. To do so, different fields have been investigated: first, we have developed a predictive method for package parasites called “MCTL Matrix Method” which is based on a virtual package prototyping and Multiconductor transmission lines. Then we have proposed a new methodology for system immunity at the earliest design stages
Rios, Mario Alberto. "Modélisation pour analyses dynamiques des réseaux électriques avec compensateurs de puissance réactive-SVC." Grenoble INPG, 1998. http://www.theses.fr/1998INPG0099.
Повний текст джерелаThis thesis studies the modeling and analysis of power System containing static VAR compensators (SVC). Low-order models, calculated by Hankel singular-value truncation réduction and N4Sid dynamic identification, provide the foundation for the modeling and analysis techniques. For cases where many SVCs or FACTS (Flexible AC Transmission Systems) devices are installed in a power System, a new subsystem structure based on thèse low-order modeling techniques has been developed. The proposed low-order models allow the computation of low-order LQG-type (Linear Quadratic Gaussian Regulator) control laws, as well as low-order robust controls, which provide a better performance relative to traditional SVC controls (proportional type). Using the subsystem structure formulated in this thesis, methods for calculating decentralized controllers for power Systems hâve been conceived. In addition, through the use of structured singular values, a new robustness analysis technique has been developed which allows the détermination of stability boundaries through the calculation of closed-loop transfer functions. The theoretical approaches in this work hâve been applied to a test power system containing 11 nodes, as well as a larger 173-node test system
Perret, Étienne. "Application de l'approche par changements d'échelle aux circuits planaires hyperfréquences." Toulouse, INPT, 2005. http://ethesis.inp-toulouse.fr/archive/00000153/.
Повний текст джерелаAn electromagnetic modeling based on a Scale changing technique formulation has been developed and applied to various microwave planar circuits. This method aims at bypass traditional problems of simulation, related to the multiplicity of scales present in a structure. The multiscale nature of a structure is used to break up this one into sub-structures, still called building blocs of transition. These blocs seem true basic components of any multiscale structure. They characterize the transition of a scale towards another, and are associated with an N-port network. Taking into account the entire problem corresponds to the cascading of these different N-port. The study of MEMS, an active antenna and a phase-shifters cell was carried out. The results obtained, in particular in term of computing time, have confirmed the effectiveness of such an approach compared to the traditional methods
BOSMANS, RICHARD. "Analyse experimentale de la degradation par electromigration d'interconnexions multicouches dans les circuits integres." Caen, 1985. http://www.theses.fr/1985CAEN2009.
Повний текст джерелаHAJJAR, AMJAD. "Modelisation des temps de propagation et analyse temporelle statique des circuits integres cmos." Paris 6, 1992. http://www.theses.fr/1992PA066501.
Повний текст джерелаMorel, Cristina Monica. "Analyse et contrôle de dynamiques chaotiques, application à des circuits électroniques non-linéaires." Angers, 2005. http://www.theses.fr/2005ANGE0020.
Повний текст джерелаSwitch-mode power supplies are highly non-linear systems that can naturally exhibit a chaotic behavior. We first study the control of chaos, i. E, a means to remove chaos, with sliding mode control. Nevertheless, inducing chaos in these systems reduces their electromagnetic interferences emissions, yet at the expense of aggravating the overall magnitude of the output voltage ripple. We then introduce a nonlinear feedback control method, which induces chaos, and which is able at the same time to achieve low spectral emission and to maintain a small ripple in the output. We also propose a new technique to generate several independent chaotic attractors, by designing a switching binary controller of continuous-time systems : this controller can create chaos using an anticontrol of chaos feedback. We show that non-linear continuous-time systems have several attractors and demonstrate that their state space equidistant repartition is on a precise curve. A mathematical formula giving the distance between the attractors is then deduced. Finally, a practical implementation is described, with some experimental measurements
CHAARI, OINIS. "Ondelettes et analyse de prony : application aux courts-circuits dans les reseaux d'energie." Paris 6, 1995. http://www.theses.fr/1995PA066043.
Повний текст джерелаWang, You. "Analyse de fiabilité de circuits logiques et de mémoire basés sur dispositif spintronique." Thesis, Paris, ENST, 2017. http://www.theses.fr/2017ENST0005/document.
Повний текст джерелаSpin transfer torque magnetic tunnel junction (STT-MTJ) has been considered as a promising candidate for next generation of non-volatile memories and logic circuits, because it provides a perfect solution to overcome the bottleneck of increasing static power caused by CMOS technology scaling. However, its commercialization is limited by the poor reliability, which deteriorates severely with device scaling down. This thesis focuses on the reliability investigation of MTJ based non-volatile circuits. Firstly, a compact model of MTJ including main reliability issues is proposed and validated by the comparison with experimental data. Based on this accurate model, the reliability of typical circuits is analyzed and reliability optimization methodology is proposed. Finally, the stochastic switching behavior is utilized in some new designs of conventional applications
Lamnabhi, Moustanir. "Analyse des systèmes non linéaires par les méthodes de développements fonctionnels." Paris 11, 1986. http://www.theses.fr/1986PA112231.
Повний текст джерелаLacour, Jean-Pierre. "Circuits de magasinage dans un centre commercial d'hypermarché : analyse et qualification des circuits de magasinage en tant que pratiques d’appropriation de l’espace commercial." Lyon 3, 2009. https://scd-resnum.univ-lyon3.fr/out/theses/2009_out_lacour_j-p.pdf.
Повний текст джерелаThis exploratory research aims to identify the space appropriation by patrons in a supermarket mall and particularly the shopping paths. The patrons have been observed and interviewed. The semiotical method has been used to identify four types of shopping paths. We tried to link these shopping paths to the emotions of the patrons. We found that the shoppers who have a sequential shopping path seem to feel curiosity about the commercial offer of the mall
Razafindraibe, Alin. "Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés." Phd thesis, Université Montpellier II - Sciences et Techniques du Languedoc, 2006. http://tel.archives-ouvertes.fr/tel-00282762.
Повний текст джерелаTessier, Jayson. "Détermination de la composition de l'alimentation des circuits de broyage par analyse d'images multivariée." Thesis, Université Laval, 2006. http://www.theses.ulaval.ca/2006/23698/23698.pdf.
Повний текст джерелаBolcato, Pascal. "Modélisation et simulation du bruit dans les circuits intégrés : analyse fréquentielle et régime transitoire." Grenoble INPG, 1994. http://www.theses.fr/1994INPG0003.
Повний текст джерелаTessier, Jayson. "Détermination de la composition de l'alimentation des circuits de broyage par analyse d'images multivarié." Master's thesis, Université Laval, 2006. http://hdl.handle.net/20.500.11794/18266.
Повний текст джерела