Дисертації з теми "ANALOG RESOLVER"

Jag har i denna uppsats undersökt hur begränsningarna av analog utrustning förmusikinspelning, i detta fall en kassettporta studio med fyra kanaler, påverkar beslutoch slutresultat. För att komma fram till ett resultat har jag spelat in, mixat och mastrattre låtar via en Tascam 234-kassettportastudio och annan analog utrustning för att helatiden hålla mig i den analoga domänen. Resultatet som nåddes var att många begränsningar som det analoga arbetssättet gerupphov till kunde lösas genom mer noggrann planering och fasta beslut. Antal kanalerbegränsar antalet mikrofoner som kan användas under varje inspelning, men flermikrofoner är inte alltid bättre. Med uttänkta inspelningstekniker kan ett bra resultatfortfarande uppnås. Även bristen på antalet hårdvaru-verktyg för att bearbeta ljudet göratt beslut måste tas tidigt i processen. Detta är skrämmande till en början men befriandenär rädslan släppt. Dessa beslut blir enklare att ta och styrs av en tydlig vision om vart låten ska. Begränsningarna får användaren att nyttja sina verktyg till fullo, vilket ger kunskap somäven gynnar användningen av moderna digitala verktyg.

Reading analogue clocks is a sub-area of ​​mathematics in elementary school that is rarely examined. It is also not clarified in the curriculum. Nevertheless, reading analogue clocks is the basis for calculating time differences. The National Agency for Education explains that measurement of time should be taught. However, the reading of clocks is not explained in the control documents. Reading analog clocks is a complicated process. Different skills and knowledge are required to succeed with a reading. Studies show that presentations of the analog clock tend to look similar in many classrooms. This study aims to investigate how teachers teach reading and time measurement in the analog clock. The theory selected is Williams's theory of image schemes. The method chosen is interview. The main result reveals that level classifications of pupils are common. It also turns out that organizing and building structure around different ways to read the analog clock can lead to students' difficulties in reading the clock correctly. Teaching absolute and relative readings is mixed in such a way that it can lead to confusion for the students. The results may also indicate a lack of knowledge among teachers, about students' misreadings and what they are due to. The result also confirms that even hours and relative clock times are taught through presentations of the positions of the hands. At the same time, teachers are teaching their students, in the passage of time and the movements of the various hands. This is contrary to previous research.
Avläsning av analoga klockor är ett delområde inom matematik i grundskolan som sällan undersökts och som saknar förtydligande i läroplanen. Trots detta utgör avläsning av analoga klockor grunden för att kunna räkna med tidsdifferenser. Skolverkets styrdokument förklarar att mätning av tid ska undervisas. Avläsning av klockor finns däremot inte förklarat i styrdokumenten. Avläsning av analoga klockor är en komplicerad process. Det krävs olika förmågor och kunskaper för att lyckas med en avläsning. Studier visar att presentationer av den analoga klockan tenderar att se ut på ett likartat sätt i många klassrum. Denna studie går ut på att undersöka hur lärare undervisar avläsning och tidmätning i den analoga klockan. Den utvalda teorin är Williams teori om bildscheman. Den utvalda metoden är intervju. I det huvudsakliga resultatet avslöjas att nivåindelningar av elever i undervisningen är vanligt. Det visar sig också att organiserandet och uppbyggandet av struktur kring olika sätt att avläsa den analoga klockan, kan leda till elevers svårigheter med att avläsa klockan rätt. Undervisning i absoluta och relativa avläsningar blandas på ett sådant sätt att det kan leda till förvirring för eleverna. Resultaten visar möjligtvis också på en kunskapsbrist bland lärare, om elevers felavläsningar och vad de beror på. I resultatet bekräftas också att jämna timmar och relativa klocktider undervisas genom presentationer av visarnas positioner. Samtidigt undervisar lärare sina elever i tidens gång och de olika visarnas rörelser. Det står i motsats till vad forskning visar.

Syftet med denna studie är att undersöka elevers fritidsläsning och om elever föredrar digital eller analog läsning och vad de tror om läsningen i framtiden. Studien kommer även att ge svar på vem som rekommenderar skönlitteraturen. Studien är en kvantitativ undersökning där data samlats in genom 59 enkäter. Resultatet visar att ungefär hälften av eleverna läser på fritiden och populärast var analog läsning. Eleverna föredrar även pappersböcker framför e-böcker och det är oftast familjemedlemmar som rekommenderar litteraturen. Slutsatserna av undersökningen är att pappersböcker även fortsättningsvis kan förväntas ha ett egenvärde i fritidsläsningen, och att det stora mediautbudet inte påverkat fritidsläsningen på ett negativt sätt. Vem som rekommenderar litteraturen till högstadieeleverna har förändrats över tiden. Förr var bibliotek mest förekommande och nu är det familjemedlemmarna.

Kommunikationsteknologin befinner sig idag i ett övergångsläge mellan digitala och analoga tekniker. Inte minst påverkar detta dagstidningsindustrin. Samhällets generella uppfattning är att digitala tidningar anses ha låg eller ingen miljöpåverkan i jämförelse med den analoga tidningen. Att minska miljöpåverkan rent generellt ligger i samhällets intresse, därför är kommunikationsteknologiska lösningar under ständig utvärdering vad gäller dess miljöpåverkan och hur denna kan effektiviseras. Syftet med den här undersökningen är därför att analysera olika målgrupper och deras tidningskonsumtion, för att sedan utvärdera den miljömässiga påverkan som den innebär. På så sätt kan vi diskutera huruvida analog eller digital konsumtion är ett miljömässigt bättre alternativ för de studerade målgrupperna.  Genom en litteraturstudie kunde vi uthämta teori för att ge grund till uppbyggnad av fältstudie och för vidare analyser av resultaten. Teorin behandlade tidningars livscykler i relation till miljöpåverkan. Utifrån sex semistrukturerade intervjuer formade vi sex fiktiva personas som representerade sex skilda målgrupper, fokuserade kring deras dagstidningskonsumtion. Dessa personas figurerade i ett moget scenario där det var lika vanligt förekommande att läsa den digitala versionen av dagstidningen som den analoga versionen. I diskussionen kunde vi göra rekommendationer i valet av tidningsformat för respektive målgrupp. Dessa var baserade på våra preliminära beräkningar och diskussioner. Slutsatser vi kunde dra var att valet av tidningsformat utifrån det mest miljömässigt gynnsamma var primärt beroende av lästiden, antalet läsar per version, antalet läsare per upplaga, den digitala enhetens energiförbrukning och avfallshantering.
Communications technology is currently in a transition phase between digital and analog technologies. Not least, this affects the newspaper industry. Society's general view is that digital magazines are considered to have low or no environmental impact in comparison with the analog newspaper. Reducing the environmental impact is in general interests of the society, therefore communications technology solutions lies under constant evaluation in terms of their environmental impact and how this can be streamlined. The purpose of this study is to analyze different target groups and their newspaper consumption, to then evaluate the environmental impact of it. Thus we can discuss whether analog or digital consumption is a more environmentally favourable option for the studied target groups. Through a literature study, we could retrieve theory to provide a scientific basis for the construction of the field study and further analysis of the results. The theory treated newspapers' life cycles in relation to environmental impact. Based on six semi-structured interviews we formed six fictitious personas representing six distinct target groups, focused on their daily newspapers consumption. These personas figured in a mature scenario where reading the digital and the analog version of the newspaper was equally common. In the discussion we were able to establish recommendations for each target group providing the most favourable newspaper version. These were based on our preliminary calculations and discussions.Conclusions we could draw was that the choice of newspaper version based on environmental benefaction was primarily dependent on reading time, the number of readers per version, the number of readers per edition, the digital unit's energy consumption and end-of-life treatment.

Modelica is a language supported by Modelica Association. It is a non-proprietary, object-oriented, equation based language to conveniently model complex physical. OpenModelica is an open source environment for the Modelica language supported by Open Source Modelica Consortium (OSMC). The aim of this thesis is the development of a library of models and components for design and simulation of analog integrated circuits and an OMNotebook-based tutorial for an academic purpose as a design tool for an electronics lab. For implementation of this library we got inspired from SPICELib library [2], but we have tried to make it more user-friendly without losing model complexity. The first difference is how analyses are developed. In our library DC, AC and transient variables are calculated for each simulation while in SPICELib you have to instantiate an analysis model and execute it. Also we have included length and width as parameters in most of the components, what is not included in SPICELib. Another difference is the way voltage and current sources are edited which we have tried to do it easier than in SPICELib. Another difference is the way voltage and current sources are edited which we have tried to do it easier than in SPICELib. To add functionality similar to other simulation tools, we have modified a python script that lets you make a parametric sweep, something that was not available in SPICELib. We have used a script already implemented in, which used to simulate a model several times after changing one of the parameters of that model. Using this script as a reference we have adapted it to do those simulations, change the parameter we want after each simulation and finally, plot one of the variables of the model as a function of the parameter that was changed.

Många mjukvarutillverkare gör idag digitala produkter menade att emulera analog hårdvara för musiker och ljudingenjörer. Denna undersökning utgick ifrån frågan om hur lyssnare upplever emulering av analoga ljudegenskaper, i form av rullband, jämfört med digitalt ljud fritt från detta. Ett kortare utdrag från ett musikstycke inom genren metal användes för att undersöka detta. En digital mjukvaruplugin avsedd för emulering av analogt rullband växlade på och av under styckets gång för att möjliggöra en jämförelse mellan det analoga och det digitala ljudet. Stycket spelades upp tillsammans med en video, och denna visade en bokstav som växlade mellan A och B samtidigt som rullbandsemuleringen slogs av och på. Ett antal testpersoner fick vid enskilda testtillfällen lyssna på stycket och sedan i en semistrukturerad intervju diskutera de skillnader de kunde höra, om några alls. Resultatet visade att upplevelsen inte påverkades nog för att ge ett klart svar. Detta då de hörbara skillnaderna var mycket små.

Läromedel har en viktig roll i skolan, både digitala och analoga. Forskning visar att användandet av läromedel minskar, men att analoga dominerar över digitala i det digitaliserade samhället. Syftet med denna studie är därför att öka kunskapen om hur engelsklärare i den svenska gymnasieskolan förhåller sig till läromedel i sin undervisning. Vidare undersöks förhållningssättet till analoga och digitala läromedel och vad anledningarna till användande av läromedel är. För att ta reda på detta har en enkätstudie utförts bland engelsklärare på gymnasienivå i Sverige. Med en deskriptiv statistisk analys visar resultatet att trots vikten av läromedel enligt styrdokument frångår många lärare användandet av läromedel. Anledningarna till varför man väljer att använda läromedel är främst tidsbesparing och struktur. Orsakerna till varför man väljer att frångå läromedel är främst begränsning. Analoga läromedel används och föredras mer än digitala läromedel, men många kompletterar de båda typerna med varandra. Grunderna till minskat användande av läromedel och olika typer av lärverktyg diskuteras. Huruvida ålder på lärare påverkar användandet av läromedel, både analoga och digitala, samt om hybridprodukter är framtiden vore intressant för vidare forskning.

This study examines the culture and values surrounding the analogue camera and the analogue photography today. The aim is to answer the questions of how the field of analogue photography look like? Why it still exist? And what the role of analogue photography in a digital context is? Through qualitive interviews with six persons who practices analogue photography the study examines their field, and reasons for choosing it over digital. Based on theories by Pierre Bourdieu the analysis shows the fields positions of power, and identifies the capitals that are valued and why they are valued. The interviewees describes the benefits of the analogue in relation to digital photography as more valuable and more esthetic. They say that the randomness and imperfections of the analogue has artistic and esthetic qualities and advantages. The study connects this with analogue nostalgia, and Hartmut Rosas theory of resonance. With a theoretical framework based on Zygmunt Bauman and Christopher Lasch the study analyzes analogue photography in a digital context. The study finds that analogue photography is nostalgic in the sense that it is practiced in relation to the digital, and in some cases as a way to escape and oppose digital society. Further the study suggests that when the interviewees uses analogue photography to oppose the digital in favor of the wellbeing of oneself, it could on the other hand be a practice in conformity with modern society despite the interviewees efforts to oppose it.

This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.

The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.

In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.

Studiens syfte är att jämföra hur elevers narrativa texter i årskurs 6 skiljer sig åt beroende på om de skrivs med hjälp av analoga skrivverktyg eller digitala skrivverktyg med ordbehandlingsprogram. Studien omfattar åtta elevtexter som analyserats utifrån aspekterna stavning, särskrivning samt felanvändning av versaler och gemener. En teoretisk utgångspunkt som studien utgått från är det sociokulturella perspektivets tankesätt om medierande redskap, där dessa redskap i vår studie är penna och tangentbord. Den andra teoretiska utgångspunkten är kognitivismen med fokus på kognitiva och sensomotoriska processers betydelse för elevers textskrivande. Resultatet visade att eleverna hade betydligt fler fel i sina analoga texter jämfört med de digitala gällande stavfel och felanvändning av versaler och gemener men däremot utmärkte sig resultatet för särskrivning eftersom inga skillnader blev framträdande oavsett vilket skrivverktyg som användes. Som förväntat presterade eleverna bättre i sina digitala texter där mycket går att koppla till det ordbehandlingsprogram som eleverna fick hjälp av. En annan viktig iakttagelse är att de analoga texterna innehöll oroväckande mycket fel vilket kan innebära att analoga texter skrivs allt mer sällan och att elever därför går miste om viktiga förmågor kopplat till de kognitiva och sensomotoriska processerna. Med andra ord visar resultatet att valet av medierande redskap har betydelse för elevernas skrivande.

Syftet med denna studie är att få en fördjupad förståelse om undervisningens betydelse för elevers förmåga att avläsa den analoga klockan. Denna studien baseras på en tidigare gjord studie (Hultman, 2019), där fyra cyklar med matematiklektioner har gjorts, och denna kommer utgöra den femte cykeln. Learning study har använts som metod med utgångspunkt i variationsteorin. Ämnesområdet är fortfarande relativt outforskat. Det finns svårigheter med avläsning av klockan för elever. Dessutom uppmärksammas ytterst lite vad det gäller klockan i Läroplanen och kommentarmaterialet avläsning nämns inte alls. I den här studien beskrivs en del av de svårigheter som elever upplever vid avläsning av den analoga klockan och vilka kritiska aspekter lärare bör ha i åtanke vid undervisning. Exempelvis att elever tenderar att blanda ihop visarna och att de svarar i digital tid istället för analog tid.
The aim of this study is to gain a deeper understanding of the importance of teaching and its correlation with students’ ability to read the analogue clock. This study is based on four previously made cycles (Hultman, 2019) which will make this the fifth. The method that has been used is learning study but through a variation theoretical viewpoint. This particular field is as of now not thoroughly researched, however, studies show that the perception of when students are mature enough regarding learning the analogue clock varies. Apart from that, it appears that there are difficulties related to the matter. Furthermore, little or almost no attention connected to the analogue clock can be found throughout the Swedish curriculum nor its commentary material. In this study descriptions of difficulties related to the analogue clock regarding the reading of it and the comprehension will be found as well as the critical aspects the teacher ought to have in mind while teaching. Students tend to mix the two clock-hands and answer with digital time rather than analogue time.

As the rapid development of the wireless communication system and mobile video devices, the integrated chip with low power consuming and high conversion efficiency is widely needed. ADC and DAC are playing an important role in these applications.

The aim of this thesis is to verify a post-correction method which is used for improving the performance of ADC. First of all, this report introduces the development and present status of ADC, and expatiate its important parameters from two different classes (static performance and dynamic performance). Based on the fundamental principle, the report then focuses on the dynamic integral non-linearity modeling of ADC. Refer to this model, one post-correction method is described and verified.

Upon the face of post-correction, this method is to modify the output signals which have been converted from analog to digital format by adding a correction term. Improvement made by the post-correction needs to be checked out. Thus the performance analysis mainly relay on the measures of total harmonic distortion and signal to noise and distortion ratio is also included in this thesis.

This thesis deals with digital post-correction ofanalog-to-digital converters (ADCs). The performance ofpractical ADCs is deteriorated by nonidealities and flaws inthe converter. Methods for mitigating these errors by applyingdigital signal processing to the output of the converter havebeen proposed in the past. These methods are often referred toas postcorrection methods. This work is mainly concerned withpost-correction methods based on look-up tables.

Practical ADCs often exhibit dynamical error behavior,meaning that the error is dependent on the dynamics of theinput signal. In this thesis an extension of previouslyproposed post-correction methods is proposed. The method usesthe present sample in conjunction with a number of past samplesto form the table index. In order to reduce the number of indexbits, and thereby the size of the table, the method comprises a‘bit mask’, which selects a subset of the availablebits to be used in the index. Evaluations using experimentalADC data show that the proposed method improves the converterperformance, but also that the choice of index bits has asignificant impact on the outcome of the correction. Theincorporation of a bit mask enables an analysis of the effectof different bit masks. The analysis results in a framework forcomparing different correction tables.

The framework is then applied in an optimization problem.The goal is to find the best allocation of a fixed number ofindex bits. Two different criterions are applied: minimizationof the total harmonic distortion and maximization of thesignal-to-noise and distortion ratio. The results of theoptimization, performed with experimental data, show that theoptimal bit allocation is different depending on whichcriterion is used. Moreover, the performance of a correctionscheme deteriorates only slowly with decreasing table size, ifappropriate index bits are selected.

As we speak, analogue film is being phased out of the international film industry. The medium that once reigned in capturing and projecting our world's light and the flow of time, has now been rendered obsolete and replaced by digital media technology. However, analogue film remains, and has come to be increasingly used and investigated in contemporary art. In my essay, I examine how our aesthetic perception of analogue film is changing with this shift to digital film technology. How do we experience analogue film – now that it is both on the verge of disappearing from society and is put in contrast to its digital successor? My investigation is based on the thesis that analogue film is now in a state of change. By analyzing three contemporary artists I attempt to discern how this change is aesthetically articulated, and trace alternative forms of continued existence for analogue film. The British artist Tacita Dean, the Italian artist Rosa Barba and the Swedish artist Alexander Gutke all work with film in their own way, and also in the context of the changed status of analogue film today. Furthermore, I examine the possibility that these artists form an active part of a continuous reshaping of analogue film, which is taking place in the fracture created in this shift to digital media technologies.

Denna rapport utreder skärmning som en metod för att minska störningsupptaget hos en blodperfusionsmätare, och därmed öka dess pålitlighet vid medicinsk användning. Ett nytt kretskort för den analoga elektroniken skapades för att underlätta skärmningen, och samtidigt analyserades kretsens karakteristik och anpassades efter behov. Beräkningar och simuleringar utfördes för att undersöka kretskortets teoretiska störningspåverkan, och jämförelser mellan ett skärmat och ett oskärmat kort visar att skärmning gör att kretskortet tar upp markant mindre störningar. Praktiska tester planerades men utfördes inte eftersom COVID-19-epidemin orsakade tidsbrist.
This report examines shielding as a method to reduce interference absorption in a blood perfusion monitor, and consequently increase its reliability in clinical use. A new circuit board for the analog electronics was created to facilitate shielding, and simultaneously the circuit’s charac­teristics were analyzed and adjusted where necessary. Calculations and simulations were made to examine the circuit board’s theoretical interference impact, and com­parisons between a shielded and an unshielded board shows that shielding causes the circuit board to absorb noticeably less interference. Practical tests were prepared but not per­formed because the COVID-19 epidemic caused lack of time.

With increasing amounts of data coming fromconnecting progressively more devices, new machine learningmodels have risen. For wireless networks the idea of using adistributed approach to machine learning has gained increasingpopularity, where all nodes in the network participate in creatinga global machine learning model by training with the localdata stored at each node, an example of this approach is calledfederated learning. However, traditional communication protocolshave been proven inefficient. This opens up opportunities todesign new machine-learning specific communication schemes.The concept ofOver-the-air computationis built on the fact thata wireless communication channel can naturally compute somelinear functions, for instance the sum. If all nodes in a networktransmits simultaneously to a server, the signals are aggregatedbefore reaching the server.
I takt med denökande datamängden frånallt fler uppkopplade enheter har nya modeller för mask-ininlärning dykt upp. För trådlösa nätverk har idén att appliceradecentraliserade maskininlärnings modellerökat i popularitet,där alla noder i nätverket bidrar till en global maskininlärningsmodell genom att träna på den data som finns lokalt på varjenod. Ett exempel på en sådan metodärFederated Learning.Traditionella metoder för kommunikation har visat sig varaineffektiva vilket öppnar upp möjligheten för att designa nyamaskininlärningsspecifika kommunikationsscheman. Konceptetover-the-air computationutnyttjar det faktum att en trådlöskommunikationskanal naturligt kan beräkna vissa funktioner,som exempelvis en summa. Om alla noder i nätverket sändertill en server samtidigt aggregeras signalerna genom interferensinnan de når servern.
Kandidatexjobb i elektroteknik 2020, KTH, Stockholm

Mycronic is a company that manufactures a solder paste printer used to manufacturecircuit boards. Inside the printer solder paste is fed with the help of a screw pump.The solder paste, consisting of relatively soft metals has a tendency to stick to thescrew surface and form particles. These are then detached and passed on in thesystem and can clog the nozzle of the printer. This project investigated the possibilityof creating a model test where different parameters can be varied to evaluate itsinfluence on the amount of solder paste sticking to the surface of the screw. Testingthese parameters directly in the solder paste printer would be time consuming andexpensive.A pin-on-disk set up with some modified parts was used to emulate the solder pastemotion in the screw pump. The results were then analyzed in light optical microscope(LOM) and scanning electron microscope (SEM) equipped with energy dispersivex-ray spectroscopy (EDS).The parameters that were varied were pressure, temperature, rotation speed,substrate, content of the paste and the shape of the profile, which is supposed toemulate the ridge of the screw. It was shown that the profile shape, the substrate andthe pressure was of great importance in the deformation of the solder balls while therotation speed and the paste content had a small or no effect.The goal of the project is to recreate the agglomerates that have led to malfunctionsin the printing and evaluate which parameters that have the greatest significance.

För att på ett fördjupat sätt förstå innebörden i olika svårigheter som elever i årskurs 2–3 kan ha gällande tidsavläsning från den analoga klockan är detta en intervjustudie med sju elever som besvarar frågeställningen: vad urskiljer/urskiljer inte eleverna när de löser olika uppgifter som handlar om att avläsa tid från den analoga klockan? Som teoretisk utgångspunkt används variationsteorin då dess olika begrepp är centrala för att förstå hur en annan person uppfattar ett specifikt ämnesinnehåll. I resultatet redovisas de olika aspekter av innehållet kring tidsavläsning från den analoga klockan som eleverna urskilt eller inte urskilt som i sin tur leder till att olika svårigheter identifieras. Vidare diskuteras studiens styrkor och svagheter i relation till metodval samt hur resultatet förhåller sig till tidigare forskning, styrdokument och yrkesverksamheten. Sammanfattningsvis framgår det ur resultatet att en övergripande svårighet har att göra med att eleverna inte urskilt att klockan är uppbyggd på 60 minuter och till stor del förlitar sig på minnesassociationer vid avläsning av minutvisaren.
This is an interview study with seven students. To understand the deeper meaning of various difficulties that students in grades 2–3 may have regarding time telling on the analogue clock this study answers the question: what does the students discern/not discern when they solve different tasks involving time telling on the analogue clock? As a theoretical framework, the variation theory is used as its various concepts are central to understand how another person perceives a specific curriculum content. The result shows the different aspects of the content, regarding time telling on the analogue clock, that the students did discern or did not discern, which in turn leads to the identification of various difficulties. Furthermore, a discussion is being held regarding the strengths and weaknesses in relation to the chosen method as well as how the result relates to previous research, curriculum documents and the profession of education. In summary, it is clear from the result that an overall difficulty has to do with the students not discerning that the clock is built up in 60 minutes and largely relies on memory associations when reading the minute hand.

Denna avhandling behandlar analog-digitalomvandling. I synnerhet behandlas postkorrektion av analog-digitalomvandlare (A/D-omvandlare). A/D-omvandlare är i praktiken behäftade med vissa fel som i sin tur ger upphov till distorsion i omvandlarens utsignal. Om felen har ett systematiskt samband med utsignalen kan de avhjälpas genom att korrigera utsignalen i efterhand. Detta verk behandlar den form av postkorrektion som implementeras med hjälp av en tabell ur vilken korrektionsvärden hämtas.

Innan en A/D-omvandlare kan korrigeras måste felen i den mätas upp. Detta görs genom att estimera omvandlarens överföringsfunktion. I detta arbete behandlas speciellt problemet att skatta kvantiseringsintervallens mittpunkter. Det antas härvid att en referenssignal finns tillgänglig som grund för skattningen. En skattare som baseras på sorterade data visas vara bättre än den vanligtvis använda skattaren baserad på sampelmedelvärde.

Nästa huvudbidrag visar hur resultatet efter korrigering av en A/D-omvandlare kan predikteras. Omvandlaren antas här ha en viss differentiell olinjäritet och insignalen antas påverkad av ett slumpmässigt brus. Ett postkorrektionssystem, implementerat med begränsad precision, korrigerar utsignalen från A/D-omvandlaren. Ett utryck härleds som beskriver signal-brusförhållandet efter postkorrektion. Förhållandet visar sig bero på den differentiella olinjäritetens varians, det slumpmässiga brusets varians, omvandlarens upplösning samt precisionen med vilken korrektionstermerna beskrivs.

Till sist behandlas indexering av korrektionstabeller. Valet av metod för att indexera en korrektionstabell påverkar såväl tabellens storlek som förmågan att beskriva och korrigera dynamiska fel. I avhandlingen behandlas i synnerhet tillståndsmodellbaserade metoder, det vill säga metoder där tabellindex bildas som en funktion utav flera på varandra följande sampel. Allmänt gäller att ju fler sampel som används för att bilda ett tabellindex, desto större blir tabellen, samtidigt som förmågan att beskriva dynamiska fel ökar. En indexeringsmetod som endast använder en delmängd av bitarna i varje sampel föreslås här. Vidare så påvisas hur valet av indexeringsbitar kan göras optimalt, och experimentella utvärderingar åskådliggör att tabellstorleken kan reduceras avsevärt utan att fördenskull minska prestanda mer än marginellt.

De teorier och resultat som framförs här har utvärderats med experimentella A/D-omvandlardata eller genom datorsimuleringar.

Analog-to-digital conversion and quantization constitute the topic of this thesis. Post-correction of analog-to-digital converters (ADCs) is considered in particular. ADCs usually exhibit non-ideal behavior in practice. These non-idealities spawn distortions in the converters output. Whenever the errors are systematic, it is possible to mitigate them by mapping the output into a corrected value. The work herein is focused on problems associated with post-correction using look-up tables. All results presented are supported by experiments or simulations.

The first problem considered is characterization of the ADC. This is in fact an estimation problem, where the transfer function of the converter should be determined. This thesis deals with estimation of quantization region midpoints, aided by a reference signal. A novel estimator based on order statistics is proposed, and is shown to have superior performance compared with the sample mean traditionally used.

The second major area deals with predicting the performance of an ADC after post-correction. A converter with static differential nonlinearities and random input noise is considered. A post-correction is applied, but with limited (fixed-point) resolution in the corrected values. An expression for the signal-to-noise and distortion ratio after post-correction is provided. It is shown that the performance is dependent on the variance of the differential nonlinearity, the variance of the random noise, the resolution of the converter and the precision of the correction values.

Finally, the problem of addressing, or indexing, the correction look-up table is dealt with. The indexing method determines both the memory requirements of the table and the ability to describe and correct dynamically dependent error effects. The work here is devoted to state-space--type indexing schemes, which determine the index from a number of consecutive samples. There is a tradeoff between table size and dynamics: more samples used for indexing gives a higher dependence on dynamic, but also a larger table. An indexing scheme that uses only a subset of the bits in each sample is proposed. It is shown how the selection of bits can be optimized, and the exemplary results show that a substantial reduction in memory size is possible with only marginal reduction of performance.

Det här arbetet handlar om att ta fram beteendemodeller av analog till digital omvandlare avsedda för tillämpningar i radiofrekvensområdet. Det gäller tillämpningar inom telekommunikation men även in test- och mätinstrument där omvandlingen från analoga till digitala signaler ofta är en prestandamässig flaskhals. Modellerna är avsedda att användas för att efterbehandla utdata från omvandlaren och på så sätt förbättra prestanda på den digitala signalen. Genom att skapa modeller av verkliga omvandlare och hur dessa avviker från ett idealt beteende kan ofullständigheter korrigeras genom så kallad postkorrigering. Beteendemodeller innebär att genererar en lämplig insignal, mäta utdata och beräkna en modell. För omvandlare i radiofrekvensområdet ställs höga krav på instrumentering. Den testutrustningen som används är baserad på moderna högprestanda instrument som har kompletterats med specialbyggd utrustning för signalkonditionering och datainsamling. I avhandlingen har även olika insignaler utvärderats med såväl teoretisk som experimentell analys. Det finns ett flertal olika varianter av modeller för att modulera ett olinjär, dynamisk system. För att få en parametereffektiv modell har utgångspunkten varit att utgå från en Volterramodell som på ett optimalt sätt beskriver svagt olinjära dynamiska system, så som analog till digital omvandlare, men som är alltför omfattande i antal parametrar. Volterramodellens har sedan reducerats till en mindre parameterintensiv, modellerstruktur på så sätt att Volterrakärnans symmetriegenskaper jämförts med symmetrierna hos andra modeller. En alternativ metod är att använda en Kautz-Volterramodell. Den har samma generella egenskaper som Volterramodellen, men är inte lika parameterkrävande. I den här avhandlingen redovisas experimentella resultat av Kautz-Volterramodellen som i framtiden kommer att vara intressanta att använda för postkorrigeringen. För att kunna beskriva beteenden som en dynamiska olinjära modellen inte klarar av har modellen kompletterats med en statisk styckvis linjär modellkomponent. I avhandlingen presenteras en sluten lösning för att identifiera samtliga paramervärden i modellen. Vidare har det i avhandlingen genomförs en analys av hur respektive komponent påverkar prestanda på utsignalen. Därigenom erhålls ett mått på den maximala prestandaförbättring som kan uppnås om felet kan elimineras.
This work considers behavior modeling of analog to digital converters with applications in the radio frequency range, including the field of telecommunication as well as test and measurement instrumentation, where the conversion from analog to digital signals often is a bottleneck in performance. The models are intended to post-process output data from the converter and thereby improve the performance of the digital signal. By building a model of practical converters and the way in which they deviate from ideal, imperfections can be corrected using post-correction methods. Behavior modeling implies generation of a suitable stimulus, capturing the output data, and characterizing a model. The demands on the test setup are high for converters in the radio frequency range. The test-bed used in this thesis is composed of commercial state-of-the-art instruments and components designed for signal conditioning and signal capture. Further, in this thesis, different stimuli are evaluated, theoretically as well as experimentally. There are a large number of available model structures for dynamic nonlinear systems. In order to achieve a parameter efficient model structure, a Volterra model was used as a starting-point, which can describe any weak nonlinear system with fading memory, such as analog to digital converters. However, it requires a large number of coefficients; for this reason the Volterra model was reduced to a model structure with fewer parameters, by comparing the symmetry properties of the Volterra kernels with the symmetries from other models. An alternative method is the Kautz-Volterra model, which has the same general properties as the Volterra model, but with fewer parameters. This thesis gives experimental results of the Kautz-Volterra model, which will be interesting to apply in a post-correction algorithm in the future. To cover behavior not explained by the dynamic nonlinear model, a complementary piecewise linear model component is added. In this thesis, a closed form solution to the estimation problem for both these model components is given. By gradually correcting for each component the performance will improve step by step. In this thesis, the relation between a given component and the performance of the converter is given, as well as potential for improvement of an optimal post-correction.
QC 20100629

A complete analog front-end for portable ECG systems in 65nm technology was modeled and simulated using Cadence Virtuoso. All the required components for the AFE was incorporated into the continuous-time loop filter of a 10-bit ADC. By varying the effective transconductance of the input OTA, preamplification of the input signal was achieved. The required filtering is achieved through the ADC's own loop filter and through digital post-filtering. The ADC meets the IEC60601-2-47 standard. This simple, minimal and digitally assisted converter achieve some attractive features by dynamically adapting the programmable signal gain of the first integrator to keep the output signal range at a more constant level where the SNDR is sufficiently high.The ADC has a 100Hz bandwidth, achieves an ENOB of over 9.4 bits at a power consumption of 3.6 uWatts. The input referred noise ranges from 2.7uV(RMS) to 18.7uV(RMS) depending on gain setting. The estimated area consumption is about 0.2mm2.

Siden digital kommunikasjon krever raskere og raskere systemer for å kunne håndtere økende behov for båndbredde og samplingsrate, kan systemer med èn ADC være utilstrekkelig. En løsning på dette problemet er å bruke TIADC systemer, som kan eliminere nødvendigheten til å stadig utvikle raskere og mer nøyaktige ADCer. Dette siden den totale hastigheten til et TIADC system er lik summen av de individuelle ADCene.I denne oppgaven har signalrekonstruksjon av et båndbegrenset signal fra et 2-TIADC og et 4-TIADC system, med antakelsene ikke-uniform periodisk sampling og kjent tidsforskyvning blitt vist. Den valgte metoden er basert på multirate filterbanker, hvor filterkoeffisientene blir funnet via interpolasjoen med en raised cosine funksjon. Det valgte inngangssignalet er et sinus signal med frekvens på 350 MHz, og samplingsfrekvensen ble valgt til 1 GHz. Lengden på de digitale filtrene blir bestemt av k og intervallet definert som [-2k-1,2k].Simuleringsresultatene viste at inngangssignalet fra 2-TIADC systemet kan, med $k$ valgt mellom 10 til 45 avhengig av roll-off faktoren, rekonstrueres med feil innen den satte feilgrensen på -100dB (MSE). Resultatene for 4-TIADC systemet viste seg å ha større feil, og for å kunne oppnå en rekonstruksjon innen feilgrensen, må k økes til mellom 15 og 50 avhengig av roll-off faktoren.Systemet for 2-TIADC ble også testet for å se hvordan metoden håndterte en økende tidsforskyvning. Tidsforskyvningen varierte fra 0.1-0.99% av Ts, og verdiene av k som ble testet var 25, 50 og 100. Resultatene viste at inngangssignalet kan rekonstrueres med en tidsforskyvning på henholdsvis 0.7, 0.85 og 0.95 Ts med en feil innen den valgte grensen.

Syftet med denna litteraturstudie är att ge en bild av hur matematikdidaktisk forskning beskriver elevers förståelse för den analoga respektive digitala klockan i grundskolans tidigare år. För att ta reda på detta kommer följande frågeställningar användas: vilka svårigheter och missuppfattningar kan elever visa i sin förståelse för den analoga respektive digitala klockan? Vilka arbetssätt och metoder har visat sig kunna utveckla elevers lärande om klockan i undervisning? Studien har baserats på vetenskapliga artiklar som funnits via en systematisk sökprocess i olika databaser och kedjesökning. I studien konstateras att forskare lyfter fram olika arbetsmetoder i undervisning rörande klockan, men även likheter finns. Vi har sett att elevers mognad spelar en viktig roll när det kommer till undervisning om klockan, men hur undervisningen ska bedrivas kan dock se olika ut. Vi presenterar även forskarnas syn på vilka vanliga svårigheter och missuppfattningar som elever kan visa när de ställs inför analog eller digital representation av tid. Exempelvis är timvisaren och minutvisaren något som elever vanligtvis har svårt att särskilja. Vidare är forskarna eniga om att elever har lättare att förstå och avläsa den digitala klockan jämfört med den analoga.

Idag påpekas mer och mer att användaren skall vara delaktig vid utvecklandet av in-formationssystem. Ett systemutvecklingsprojekt kan generellt sägas ha ett antal faser: En förstudie, en genomförandedel och någon form av efterarbete. Fokus i denna rap-port riktas mot förstudien där det görs en analys av problemdomänen. Eftersom beslut som tas i senare delar av projektet är väldigt beroende av hur väl problemdomänen är beskriven är det viktigt att mycket tid läggs ned på att se till att denna beskrivning är korrekt. För att kunna beskriva problemdomänen har systemutvecklaren en mängd beskrivningstekniker till sin hjälp. En typiskt beskrivningsteknik är uppbyggd av ett antal rektanglar, cirklar, romboider etc som kan vara svåra för en lekman att lära sig och förstå. När problemdomänen är beskriven måste användaren verifiera att detta är korrekt gjort. Om användaren inte är väl insatt i hur beskrivningsteknikerna är upp-byggda får denne svårt att göra en korrekt verifiering. Denna rapport diskuterar huru-vida en beskrivningsteknik uppbyggd på analoga representationer kan vara mer för-delaktig än en traditionell (symbolisk) beskrivningsteknik. En minnestest har utförts, med målet att undersöka om analoga representationer underlättar förståelse i jämförel-se med symboliska representationer. Innan försöket genomfördes gjordes ett antagan-de att förståelse och minne har ett starkt samband. Testet misslyckades med att visa någon signifikant skillnad mellan symboliska och analoga representationer. Orsaken till försökets utfall diskuteras i de senare delarna av rapporten.

The thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.

High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.

This project investigates the feasibility of automating the test of ΔΣ-modulators using circuitcomponents available on 8-bit microcontrollers, and by doing so reducing test costs.A Built-In-Self-Test (BIST) scheme, using a binary stream as stimuli and two differentsolutions for signal analysis is suggested and simulated in SPICE to investigate its suitability.The test can not lead to a large area increase, increasing area leads to an increase inproduction cost. The test has to reduce testing time. The extra area occupied by the testarchitecture has to be paid in shorter testing time and therefore a lower unit price. The test hasto remove or lower the requirements of the off-chip tester, and by doing so reducing cost.The proposed BIST requires a very small area and is capable of calculating offset, gain andSignal to Noise Ratio with a high degree of accuracy. The proposed solution enables on-chiptesting without the need for expensive external stimuli and signal analyzers, making testing onwafer possible thus improving production yield.The proposed test will not reduce test time by itself, however by integrating the test on-chipand allowing this to run in the background while other on-chip modules are tested total testtime can be reduced to the time required to shift the stimuli into the chip

Analogue photography is something that many thought died out in the beginning of the 21’st century as a result of the digital revolution. But that’s not the case. As the digital revolution swept over the world a movement of analogue cameras, and so called toycams grew bigger. A toycam was a low quality, plastic, analogue camera, made to be manufactured and sold as cheaply as possible without any considerations of quality. Pictures produced by the camera are often soft focused with intense color changes and contrasts. Every once in a while an orange yellowish field will show up on the photos. This is caused by light leaks caused by the poor quality of the construction of the camera. While these qualities may be considered flaws they’re actually much of the reason to why people use and like toy cameras.  During the last ten years new production of old toycam models and completely new analogue cameras has been picked up. Every year a handful of new cameras enter the market and the interest and movement around toycams just seems to grow the further in to the digital era we get. But despite this, I as a dedicated toycam enthusiast, don’t sense that any real development is happening in the area. The movement is at a standstill.  The objective of the project has been to look for and develop something new, a new function that adds something to the market and movement. This has been done with the design process. The market has been studied and different concepts of form and functions have been developed. Users have been involved during the whole process, including during the final selection of concept. The result is a contemporary camera with discrete inspiration from cameras of the 50s’. But the main thing with the camera is a for compact- and toy cameras whole new feature – exchangeable film cartridges! Film can now be changed, in the middle of a roll in just a few seconds. Perfect when one wants to change film type or just don’t have the time to reload the camera! Flexibility!

Med utgångspunkt i den analoga animationsstilen ”rubber hose” från tidigt 1900-tal undersöker den här uppsatsen vilka spår av den mänskliga handen som människor uppfattar i analog respektive digital animation. Hur värdesätter man de två olika sätten att animera och vilken syn har man på rubber hose som animationsstil? Två nygjorda animationer i rubber hose-stilen, skapade analogt respektive digitalt, samt en autentisk animation av karaktären Mickey Mouse är utgångspunkten i en enkätundersökning med följande forskningsfrågor och svar: Hur ser respondenterna på rubber hose-stilen? Rubber hose är fortfarande bekant och uppfattas som relevant men inte nödvändigtvis i analogt animerad form. Vilka eventuella spår av animatören uppfattade respondenterna i den analoga respektive digitala animationen? Skärpa, pennstreck och bakgrundens ”smutsighet” är några exempel på upplevda spår av animatören i de analoga animationerna. Dock har respondenterna svårare att uppfatta spår i den digitala animationen. Hur påverkas respondenternas upplevelse av en animation av om den är analoga eller digital? En majoritet av respondenterna anser att den digitala animationen har högra kvalité men att den analoga har charm och ger nostalgi. En slutsats man kan dra av undersökningen är att rubber hose-stilen fortfarande uppskattas men att animatören genom att åtminstone delvis ta till digitala medel både kan underlätta processen och behålla känslan

In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters. To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ while consuming 6.8 mW. Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain  frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR. Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist. Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by small non-rechargeable batteries over their entire lifetime, such as medical implant devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. Medical implant devices, such as pacemakers and cardiac defibrillators, typically requirelow-speed, medium-resolution ADCs. The successive approximation register (SAR) ADC exhibits significantly high energy efficiency compared to other prevalent ADC architectures due to its good tradeoffs among power consumption, conversion accuracy, and design complexity. To design an energy-efficient SAR ADC, an understanding of its error sources as well as its power consumption bounds is essential. This thesis analyzes the power consumption bounds of SAR ADC: 1) at low resolution, the power consumption is bounded by digital switching power; 2) at medium-to-high resolution, the power consumption is bounded by thermal noise if digital assisted techniques are used to alleviate mismatch issues; otherwise it is bounded by capacitor mismatch.  Conversion of the low frequency bioelectric signals does not require high speed, but ultra-low-power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. It is not straightforward to effectively reduce the unnecessary speed for lower power consumption using inherently fast components in advanced CMOS technologies. Moreover, the leakage current degrades the sampling accuracy during the long conversion time, and the leakage power consumption contributes to a significant portion of the total power consumption. Two SAR ADCs have been implemented in this thesis. The first ADC, implemented in a 0.13-µm CMOS process, achieves 9.1 ENOB with 53-nW power consumption at 1 kS/s. The second ADC, implemented in a 65-nm CMOS process, achieves the same resolution at 1 kS/s with a substantial (94%) improvement in power consumption, resulting in 3-nW total power consumption. Our work demonstrates that the ultra-low-power operation necessitates maximum simplicity in the ADC architecture.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining >130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

Vision has always been one of the most important cognitive tools of human beings. In this regard, the development of image sensors opens up the potential to view objects that our eyes cannot see. One of the most promising capability in some image sensors is their single-photon sensitivity that provides information at the ultimate fundamental limit of light. Time-resolved single-photon avalanche diode (SPAD) image sensors bring a new dimension as they measure the arrival time of incident photons with a precision in the order of hundred picoseconds. In addition to this characteristic, they can be fabricated in complementary metal-oxide-semiconductor (CMOS) technology enabling the integration of complex signal processing blocks at the pixel level. These unique features made CMOS SPAD sensors a prime candidate for a broad spectrum of applications. This thesis is dedicated to the optimization and characterization of quantum imagers based on the SPADs as part of the E.U. funded SUPERTWIN project to surpass the fundamental diffraction limit known as the Rayleigh limit by exploiting the spatio-temporal correlation of entangled photons. The first characterized sensor is a 32×32-pixel SPAD array, named “SuperEllen”, with in-pixel time-to-digital converters (TDC) that measure the spatial cross-correlation functions of a flux of entangled photons. Each pixel features 19.48% fill-factor (FF) in 44.64-μm pitch fabricated in a 150-nm CMOS standard technology. The sensor is fully characterized in several electro-optical experiments, in order to be used in quantum imaging measurements. Moreover, the chip is calibrated in terms of coincidence detection achieving the minimal coincidence window determined by the SPAD jitter. The second developed sensor in the context of SUPERTWIN project is a 224×272-pixel SPAD-based array called “SuperAlice”, a multi-functional image sensor fabricated in a 110-nm CMOS image sensor technology. SuperAlice can operate in multiple modes (time-resolving or photon counting or binary imaging mode). Thanks to the digital intrinsic nature of SPAD imagers, they have an inherent capability to achieve a high frame rate. However, running at high frame rate means high I/O power consumption and thus inefficient handling of the generated data, as SPAD arrays are employed for low light applications in which data are very sparse over time and space. Here, we present three zero-suppression mechanisms to increase the frame rate without adversely affecting power consumption. A row-skipping mechanism that is implemented in both SuperEllen and SuperAlice detects the absence of SPAD activity in a row to increase the duty cycle. A current-based mechanism implemented in SuperEllen ignores reading out a full frame when the number of triggered pixels is less than a user-defined value. A different zero-suppression technique is developed in the SuperAlice chip that is based on jumping through the non-zero pixels within one row. The acquisition of TDC-based SPAD imagers can be speeded up further by storing and processing events inside the chip without the need to read out all data. An on-chip histogramming architecture based on analog counters is developed in a 150-nm CMOS standard technology. The test structure is a 16-bin histogram with 9 bit depth for each bin. SPAD technology demonstrates its capability in other applications such as automotive that demands high dynamic range (HDR) imaging. We proposed two methods based on processing photon arrival times to create HDR images. The proposed methods are validated experimentally with SuperEllen obtaining >130 dB dynamic range within 30 ms of integration time and can be further extended by using a timestamping mechanism with a higher resolution.

During the spring of 2016 the Swedish government presented a national IT-strategy involving personal computers for each student from grade 1-9. Meanwhile current studies are indicating the importance of handwriting for learning and remembering new skills. However, according to several cognitive scientists, the results from meta studies regarding analogue and digital tools and their contribution to learning processes are contradictory. A survey and a cross sectional study was therefore conducted aiming to compare analogue versus digital note taking and teaching methods. A total of 85 7:th grade students filled out a survey concerning their preferences in note taking and teaching methods. Non-parametric sign-test statistically proved the students in the study preferred typing over writing by hand when taking notes in class (p =0.008). Reasons for their preference included a general positive attitude towards using computers and students acknowledging the benefits of spelling programs. Furthermore, the students in the survey preferred their teacher using whiteboard instead of Powerpoint when lecturing (p=0.012). The students claimed to comprehend the content given in lectures more efficiently when whiteboard was utilized. The cross sectional study was performed in the purpose of comparing two note taking methods: writing by hand and typing. Two 7:th grade classes (N=39) participated in the study and a total of six theme lessons in ecology were conducted. The students’ individual performances were evaluated with exit tickets involving questions of facts and concepts. The differences between the classes’ performances were only marginal according to Mann-Whitney non-parametric analysis. Based on the results of this study, further implementation of computers in classrooms should be conducted methodically with care.

This thesis explores the threshold between the analog and digital realms through various investigation of theories and methods. My interest in this subject came as a result when reflecting upon my 5 years at KTH, describing a gradual transition from analog to digital. This raised questions of the relevance of analog in an otherwise digital reality. The aim of this project was never defined in advance, instead a selection of questions and observations emerged as a result. The intension was never to declaim one or the other but rather to investigate in new possibilities connected to its use.

Syfte: Syftet med denna pilotstudie var att undersöka om anestesisjuksköterskans skattning av postoperativ smärta skiljer sig fran patientens egenskattade VAS. Bakgrund: Flertalet studier visar att sjuksköterskor underskattar patienters smärta och att VAS inte används i tillräcklig utsträckning vid smärtskattning. Många erfarna sjuksköterskor tenderar att lita mer på sin intuitiva känsla om patientens smärta än på vad patienten säger. Metod: Åtta anestesisjuksköterskor på ett sjukhus i storstadsregionen fick genom ett frågeformulär skatta 44 patienters postoperativa smärta utifrån en beteenderelaterad skala och fysiologiska parametrar. Detta värde jämfördes med patientens egenskattade VAS/NRS. Resultat: Anestesisjuksköterskomas beteendeskattning stämde väl överens med patientens egenskattade VAS. De anestesisjuksköterskor som arbetat länge beteendeskattade närmre patientens VAS än de som arbetat kortare tid som anestesisjuksköterskor. De tre vanligaste fysiologiska parametrar anestesisjuksköterskorna bedömde var ansiktsuttryck, kroppsrörelse och tal. Slutsats: Anestesisjuksköterskomas erfarenhet av att bedöma och behandla patienter som är sövda eller sederade kan kanske förklara den högre samstämmigheten mellan deras och patientens smärtskattning.
Aim: The aim of this pilot study was to investigate if the pain assessment made by Swedish nurse anesthetists differ from the patients' own assessed pain, using the visual analogical scale, VAS. Background: Several studies shows that nurses tend to underestimate postoperative pain and that assessment tools seldom is used in pain assessment. Experienced nurses seem to rely more on their own intuitive feeling about patients' pain experience rather than what the patient says. Method: Eight nurse anesthetists in a Swedish hospital answered a questionnaire and made behavior assessments of postoperative pain on 44 patients, using physiological parameters which where compared with the patient's VAS\NRS. Results: Nurse anesthetists' pain assessment using physiological parameters where consistent with the patients' VAS/NRS. More experienced nurses assessed closer to the patient's VAS/NRS than the inexperienced did. The three most common physiological parameters used where facial expression, bodily movements and sounds. Conclusion: The nurse anesthetists' experience of observing patients during anesthesia and sedation might explain the high correlation in pain assessment.

The last few decades the development in the field of electronics has been huge. The components performance gets better at the same time as the manufacturing cost decreases. Many of the design moments that have to be done, are done automatically today, but it can get better. Especially for analog circuit design.

At Electronic System in Linköpings universitet, research is in progress to develop a tool that can design analog circuits in reasonable time. It means that it has to size the components (transistors, resistances, capacitances etc), so that the circuit can fulfill the performance requirements. An optimization method in conjunction with derived equations for the circuit performance is used to solve this task. The tool is created to design e.g. analog amplifiers. The goal is to decrease the design time and at the same time achieve better circuit performance.

This tool has been tested on three different circuits, a power-amplifier, a Nested Miller Compensated amplifier with an active feedback (Active Nested Miller Compensation) and a Nested Miller Compensated amplifier without an active feedback (Nested Miller Compensation). In this report the results from the designing tests are presented.

Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), are interface circuits between the analog and digital domains. They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to modeling, error correction, and implementation of DACs for communication applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering DAC, which is the most commonly used architecture for high-speed applications. Transistor-level simulation of complex circuits using accurate transistor models require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require multiple simulation runs with different parameter values making transistor-level models unsuitable. Therefore, there is a need for behavioral-level models with reasonably short simulation times. Behavioral-level models can also be used to find the requirements on different building blocks on high abstraction levels, enabling the use of efficient topdown design methodologies. Models of different nonideal properties in current-steering DACs are used and developed in this work. Static errors typically dominates the low-frequency behavior of the DAC. One of the limiting factors for the static linearity of a current-steering DAC is mismatch between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity enhancement. The highfrequency behavior of the DAC is typically dominated by dynamic errors. Models oftwo types of dynamic errors are developed in this work. These are the dynamic errors caused by parasitic capacitance in wires and transistors and glitches caused by asymmetry in the settling behavior of a current source. The encoding used for the digital control word in a current steering DAC has a large influence on the circuit performance, e.g., in terms static linearity and glitches. In this work, two DAC architectures are developed. These are denoted the decomposed and partially decomposed architectures and utilize encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the well-known binary-weighted and segmented architectures using behavioral-level simulations. It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve the DAC linearity are studied. The well-known dynamic element matching (DEM) techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. An overview of these techniques are given in this work and a DEM technique for the decomposed DAC architecture is developed. In DS modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given. Four different current-steering DACs implemented in CMOS technology are developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of different techniques for linearity improvement. For example, a 14-bit DEM DAC is implemented and measurement results are compared with simulation results. A good agreement between measured and simulated results is obtained. Moreover, a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level simulations and indicate that the decomposed architecture is a viable alternative to the commonly used segmented architecture.

The biomedical devices often operate only with a battery, e.g., blood glucose monitor, pacemaker. Therefore, it is desirable to fully utilize the energy without sacrificing the performance of the system. The Analog-to-Digital Converter (ADC), as a key component of most of the biomedical devices, needs to be designed for minimum power consumption by exploring various techniques from system level to circuit level. In addition, the nature of bio-signal provides more alternatives to reduce the power. In this thesis work, an 8 bit 11 kS/s modified algorithmic analog-to-digital converter for biomedical applications is proposed. All analog components are designed at circuit level using a 90 nm CMOS technology and digital components are implemented using Verilog-A language in Cadence. The ADC is operating in current mode at sub-threshold region with only 0.5 V supply voltage with an input current from 0 nA to 512 nA. The ADC is designed based on a top-down design with bottom-up verification approach. The system level model is described using top level language and then the circuit level is created and verified using Cadence tools according to the system level model. The INL and DNL obtained from simulation is -1/+0.8 LSB and -0.9/+1 LSB respectively. The SNDR is 47 dB (7.5 ENOB) for a -0.2 dBFS at 1 kHz sinusoidal signal. The power consumption is 2.83 μW without biasing and 4μW with biasing.

Analog games misses a lot of quick games in terms of game time and play time in the FPS genre. This genre often takes more time to play in an analog game. Could the game play become quicker by examining the different game mechanics in order to give the players a smoother game play by a reduction of downtime. Game mechanics that could be found in a digital FPS game such as Doom III, were converted to a prototype. These digital gameplay mechanics were converted so that an analog game could be played simultaneously. These game mechanics decrease the game time and down time in a way that a game using a turn based game order would not. The digital game Doom III was used to create the prototype and eight analog games of different types and genres were examined to collect more unique game mechanics. All were suited for a multiplayer type of gameplay. To get an understanding of what game elements were well liked in both digital and analog games, a questionnaire was created with twelve questions. The participants answered questions on the subjects of their favourite genre, missing game mechanics in both digital and analog games, well liked game mechanics, and also what the participants thought was impossible to create in a game in terms of game mechanics. The results of both the analysis of the eight analog games and the answers from the participants created the base plan for the development of the prototype focusing on low downtime, re-playability, and an average amount of luck. Several game mechanics were discussed and some of them were play tested. This resulted in keeping some game mechanics while others were removed because these game mechanics did not provide a rewarding gameplay. Several game mechanics were nearly impossible to implement without the use of a digital representation. An example on this type of issue was the first person view in the digital game. The perception of skill based game mechanics could be moved to an analog board game but would have to be determined by other game mechanics instead of the player’s physical capabilities. The conclusion lead to a prototype that could be played in an hour, which is a low game time for games in this genre. The FPS gameplay mechanics was converted to an analog game, but all game mechanics could not be transferred to the prototype without a conversion.
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Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent ADC architectures, the successiveapproximation-register (SAR) ADC exhibits significantly high energy efficiency due to its good trade-offs among power consumption, conversion accuracy, and design complexity. This thesis examines the physical limitations and investigates the design methodologies and circuit techniques for low-speed and ultra-low-power SAR ADCs. The power consumption of SAR ADC is analyzed and its lower bounds are formulated. At low resolution, power is bounded by minimum feature sizes; while at medium to high resolution, power is bounded by thermal noise and capacitor mismatch. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity for high resolution, a bottom-up weight calibration technique is further proposed. It utilizes redundancy generated by a non-binary-weighted capacitive network, and measures the actual weights of more significant capacitors using less significant capacitors. Three SAR ADCs have been implemented. The first ADC, fabricated in a 0.13μm CMOS process, achieves 9.1ENOB with 53-nW power consumption at 1kS/s. The main key to achieve the ultra-low-power operation turns out to be the maximal simplicity in the ADC architecture and low transistor count. In addition, a dual-supply voltage scheme allows the SAR digital logic to operate at 0.4V, reducing the overall power consumption of the ADC by 15% without any loss in performance. Based on the understanding from the first ADC and motivated by the predicted power bounds, the second ADC, a single-supply 9.1-ENOB SAR ADC in 65nm CMOS process has been further fabricated. It achieves a substantial (94%) improvement in power consumption with 3-nW total power at 1kS/s and 0.7V. Following the same concept of imposing maximal simplicity in the ADC architecture and taking advantage of the smaller feature size, the ultra-low-power consumption is achieved by a matched splitarray capacitive DAC, a bottom-plate full-range input-sampling scheme, a latch-based SAR control logic, and a multi-VT design approach. The third ADC fabricated in 65nm CMOS process targets at a higher resolution of 14b and a wider bandwidth of 5KHz. It achieves 12.5ENOB  with 1.98-μW power consumption at 0.8V and 10kS/s. To achieve the high resolution, the ADC implements a uniform-geometry non-binary-weighted capacitive DAC and employs a secondary-bit approach to dynamically shift decision levels for error correction. Moreover, a comparator with bias control utilizes the redundancy to reduce the power consumption.

The integrated circuit has, since it was invented in the late 1950's, undergone a tremendous development and is today found in virtually all electric equipment. The small feature size and low production cost have made it possible to implement electronics in everyday objects ranging from computers and mobile phones to smart prize tags. Integrated circuits are typically used for data communication, signal processing and data storage. Data is usually stored in digital format but signal processing can be performed both in the digital and in the analog domain. For best performance, the right partition of signal processing between the analog and digital domain must be used. This is made possible by data converters converting data between the domains. A device converting an analog signal into a digital representation is called an analog-to-digital converter (ADC) and a device converting digital data into an analog representation is called a digital-to-analog converter (DAC). In this work we present research results on these data converters and the results are compiled in three different categories. The first contribution is an error correction technique for DACs called dynamic element matching, the second contribution is a power efficient time-to-digital converter architecture and the third is a design methodology for frequency synthesis using digital oscillators. The accuracy of a data converter, i.e., how accurate data is converted, is often limited by manufacturing errors. One type of error is the so-called matching error and in this work we investigate an error correction technique for DACs called dynamic element matching (DEM). If distortion is limiting the performance of a DAC, the DEM technique increases the accuracy of the DAC by transforming the matching error from being signal dependent, which results in distortion, to become signal independent noise. This noise can then be spectrally shaped or filtered out and hereby increasing the overall resolution of the system. The DEM technique is investigated theoretically and the theory is supported by measurement results from an implemented 14-bit DAC using DEM. From the investigation it is concluded that DEM increases the performance of the DAC when matching errors are dominating but has less effect at conversion speeds when dynamic errors dominate. The next contribution is a new time-to-digital converter (TDC) architecture. A TDC is effectively an ADC converting a time difference into a digital representation. The proposed architecture allows for smaller and more power efficient data conversion than previously reported and the implemented TDC prototype is smaller and more power efficient as compared to previously published TDCs in the same performance segment. The third contribution is a design methodology for frequency synthesis using digital oscillators. Digital oscillators generate a sinusoidal output using recursive algorithms. We show that the performance of digital oscillators, in terms of amplitude and frequency stability, to a large extent depends on the start conditions of the oscillators. Further we show that by selecting the proper start condition an oscillator can be forced to repeat the same output sequence over and over again, hence we have a locked oscillator. If the oscillator is locked there is no drift in amplitude or frequency which are common problems for recursive oscillators not using this approach. To find the optimal start conditions a search algorithm has been developed which has been thoroughly tested in simulations. The digital oscillator output is used for test signal generation for a DAC or used to generate tones with high spectral purity using DACs.
Den integrerade kretsen har sedan den uppfanns i slutet av 1950-talet genomgått en enorm utveckling och återfinns idag i princip i all elektronisk utrustning. Den lilla storleken och den låga produktionskostnaden har gjort det möjligt att integrera elektronik i vardagsföremål som datorer och mobiltelefoner och enklare system som till exempel smarta etiketter. Typiska användningsområden för integrerade kretsar är datakommunikation, signalbehandling och datalagring. Data lagras vanligtvis i digitalt format men signalbehandling kan utföras i både den digitala och i den analoga domänen. För att nå bästa prestanda i en krets måste signalbehandlingen delas upp optimalt mellan den digitala och analoga domänen Denna uppdelning möjliggörs med hjälp av dataomvandlare som översätter data mellan de två domänerna. En krets som omvandlar en analog signal till en digital motsvarighet kallas för en analogtill-digital-omvandlare och en krets som ovandlar digitalt data till en analog signal kallas för en digital-till-analog-omvandlare. Denna doktorsavhandling innehåller resultat från forskning gjord på dessa dataomvandlare och resultaten är sammanfattade i tre huvudkategorier. Det första bidraget är en felkorrigeringsmetod för digitaltill-analog-omvandlare, det andra bidraget är en kretsarkitektur för en energieffektiv tid-till-digital-omvandlare och det tredje bidraget är en konstruktionsmetodik för frekvenssyntes med hjälp av digitala svängningskretsar. Noggrannheten hos en dataomvandlare, med andra ord hur noggrannt dataomvandlaren kan omvandla data mellan de två domänerna, begränsas ofta av de fel som uppstår vid tillverkningen av den integrerade kretsen. En typ av fel som uppstår är att dataomvandlarens jämförelsenivåer inte blir lika stora. I frekvensdomänen kommer denna typ av fel resultera i icke önskade harmoniska frekvenser (distorsion) som begränsar dataomvandlarens noggrannhet. Om distorsion, som uppkommer då ett fel beror på dataomvandlarens insignal, begränsar dataomvandlarens prestanda kan den föreslagna felkorrigeringsmetoden omvandla distortionen till brus genom att göra felet oberoende av insignalen. Det resulterande bruset kan sedan formas spektralt eller filteras bort och därmed öka systemets totala prestanda. Den föreslagna korrigeringsmetiden har undersökts teoretiskt och denna teori har sedan verifierats med mätresultat från en kretsimplementation av en 14-bitars digital-till-analog-omvandlare som använder den föreslagna felkorrigeringsmetoden. Mätresultaten visar att metod en höjer prestandan hos dataomvandlaren för låga insignalfrekvenser då det är felen i jämförelsenivåerna som begränsar prestandan. Vid högre insignalfrekvenser är metoden mindre effektiv då andra dynamiska felkällor hos dataomvandlaren istället begränsar noggranheten. Nästa bidrag är en kretsarkitektur till en tid-till-digital-omvandlare. En tid-tilldigital-omvandlare är en särskild sorts analog-till-digital-omvandlare som omvandlar tidsskillanden mellan två signaler till en digital representation. Mätresultat från en kretsprototyp visar att den föreslagna kretsarkitekturen är både mindre och mer energieffektiv än tidigare publicerade kretslösningar. Det tredje bidraget är en konstruktionsmetodik för frekvenssyntes med hjälp av digitala svängningskretsar (oscillatorer). De digitala oscillatorerna genererar en sinusformad utsignal med hjälp av rekursiva algoritmer. Vi visar att prestandan hos digitala oscillatorer, mätt i termer av amplitud- och frekvensstabilitet, till stor utsträckning beror av starttillstånden hos oscillatorerna. Vi visar också att en del starttillstånd tvingar en oscillator att upprepa samma utsignalssekvens om och om igen, vi har då fått vad vi kallar en låst oscillator. Om oscillatorn har låst finns det inte längre någon drift i amplitud eller frekvens vilka är vanliga problem för rekursiva oscillatorer som inte använder denna metod. För att hitta de op timala startvillkoren för oscillatorerna har en sökalgoritm utvecklats. Denna algoritm har testats noggrannt i datorsimuleringar. En digital oscillator är lämplig att användas för testsignalgenerering för digital-tillanalog-omvandlare där kraven på amplitud- och frekvensstabila testsignaler är höga.

Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential. The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2. The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2. The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.