Дисертації з теми "Analog electronics and interfaces"
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Harikumar, Prakash. "Building Blocks for Low-Voltage Analog-to-Digital Interfaces." Licentiate thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-111958.
Повний текст джерелаU, Seng-Pan. "Tecnicas de interpolacao em filtros multiritmo com condensadores comutados para Interfaces Analogicas com filtragem de alta-frequencia = Multirate Switched-Capacitor interpolation techniques for very high-frequency Analog Front-End filtering." Thesis, University of Macau, 2002. http://umaclib3.umac.mo/record=b1873496.
Повний текст джерелаMosciatti, Thomas. "Nanostructured hybrid interfaces for supramolecular electronics." Thesis, Strasbourg, 2015. http://www.theses.fr/2015STRAF024/document.
Повний текст джерелаThis thesis explored how, by introducing nanostructured interfaces in supramolecular system for electronics, is possible to modulate, tune, add and study properties arising from nano-objects. On these purposes self-assembled functionalization of boundaries, thermal control on intrinsic properties, light modulation of chemical and physical structures have been found as tailored techniques to affect nano-structured functionalized supramolecular system for organic electronics. Gold nanoparticles have been used to generate interfaces that have been functionalized in order to study charge transport effect in organic thin film transistor. Therefore this approach has been stepped up employing photochromic molecules and controlling charge trapping with light irradiation. The same principle has been used to modulate charge injection in high performance transistors, by functionalizing electrodes with appropriate diarylethenes. Finally, a different approach of controlling deposition of graphene flakes on dielectric surface has been successfully employed to design new memory elements by tuning energetic level alignment of graphene with thermal annealing
Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
Повний текст джерелаWang, Haibo. "Field programmable analog array synthesis." Diss., The University of Arizona, 2002. http://hdl.handle.net/10150/289777.
Повний текст джерелаChaumy, Guillaume. "Tunable metal-organic interfaces for spin electronics." Thesis, Strasbourg, 2019. http://www.theses.fr/2019STRAE030.
Повний текст джерелаThis thesis studies the interface between metals and organic materials, aiming the realization of organic spin-valves. To that end, we studied planar electrolyte-gated field-effect organic transistors and analysed their transport and interface properties under the application of different stimuli (temperature, doping, magnetic field…). This structure allowed us to approach the optimal conditions for spin injection and detection but led to redefine the standard intrinsic property of interfaces. We exhibited a very low specific contact resistance, that decreases with the downscaling of the devices, and the magnetoresistance of specific interface resistance
Hematy, Arman. "Digitally programmable analog log-domain filters." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=21302.
Повний текст джерелаFirst, a general state-space formulation is presented; a method of obtaining the state-space coefficients from an equivalent LC ladder network is described. Such a set of coefficients results in a realization with low noise and low sensitivity properties. Next, the effects of coefficient quantization on a state-space filter's response is examined. An optimization procedure is outlined to obtain the best approximation to the desired transfer function.
In order to implement the proposed filter structure, a universal log-domain cell is presented. Such a cell can be used to produce the stages required by any filter design (input, output, and integrator stages). Using the universal log-domain cell, a systematic approach to realizing any arbitrary-order filter is described. Next, the peripheral components needed to complete the filter are presented. Included are a novel 8-bit DAC, used to implement the programmable current sources that bias the filter, and V-to-I and I-to-V converters, used to interface the current-mode filter with voltage-mode instruments.
Finally, experimental results from several prototype boards are used to verify the feasibility of the proposed filter structure. These boards make use of ICs fabricated in a 0.8 mum BiCMOS technology; included are an IC with stand-alone programmable current sources, an IC with a third-order filter, as well as one with a fifth-order filter. The results from the test boards clearly demonstrate the programmability and functionality of digitally programmable state-space filters.
Hawrysh, Evan M. (Evan Mark). "Digital architectures for analog signal generation." Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=24058.
Повний текст джерелаHarikumar, Prakash. "Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces." Doctoral thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-122730.
Повний текст джерелаShen, Shumin. "A floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2004. http://hdl.handle.net/10393/26772.
Повний текст джерелаLu, Albert K. (Albert Keishi). "Analog signal generation using delta-sigma modulation." Thesis, McGill University, 1994. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=68040.
Повний текст джерелаPrototypes of the proposed designs have been assembled using Field-Programmable Gate Array, and BiCMOS technologies. The test results have successfully verified the validity of the proposed concepts indicating dynamic ranges exceeding 80 dB and 60 dB for the single and multi-tone generators respectively.
Braun, Slawomir. "Studies of Materials and Interfaces for Organic Electronics." Doctoral thesis, Linköping : Univ, 2007. http://www.bibl.liu.se/liupubl/disp/disp2007/tek1103s.pdf.
Повний текст джерелаSellner, Stefan. "Organic inorganic interfaces for applications in organic electronics." [S.l. : s.n.], 2006. http://nbn-resolving.de/urn:nbn:de:bsz:93-opus-25843.
Повний текст джерелаSyed, Arsalan Jawed. "Analog-to-Digital Converter Design for Non-Uniform Quantization." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2654.
Повний текст джерелаThe thesis demonstrates a low-cost, low-bandwidth and low-resolution Analog-to- Digital Converter(ADC) in 0.35 um CMOS Process. A second-order Sigma-Delta modulator is used as the basis of the A/D Converter. A Semi-Uniform quantizer is used with the modulator to take advantage of input distributions that are dominated by smaller-amplitude signals e.g. Audio, Voice and Image-sensor signals. A Single-bit feedback topology is used with a multi-bit quantizer in the modulator. This topology avoids the use of a multi-bit DAC in the feedback loop – hence the system does not need to use digital correction techniques to compensate for a multi-bit DAC nonlinearity.
High-Level Simulations of the second-order Sigma-Delta modulator single-bit feedback topology along with a Semi-Uniform quantizer are performed in Cadence. Results indicate that a 5-bit Semi-Uniform quantizer with a Over-Sampling Ratio of 32, can achieve a resolution of 10 bits, in addition, a semi-uniform quantizer exhibits a 5-6 dB gain in SNR over its uniform counterpart for input amplitudes smaller than –10 dB. Finally, this system is designed in 0.35um CMOS process.
Debski, Michal. "Self-calibrating floating-point analog-to-digital converter." Thesis, University of Ottawa (Canada), 2005. http://hdl.handle.net/10393/26884.
Повний текст джерелаPishdad, Bardia. "Nyquist-rate analog-to-digital conversion with calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29544.
Повний текст джерелаAGARWAL, NEETU. "ON FORMAL DEVELOPMENT OF ANALOG/DIGITAL INTERFACES IN MIXED-SIGNAL CIRCUITS." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1123772655.
Повний текст джерелаZareba, Grzegorz Szczepan. "Behavioral simulation of analog to digital converters." Diss., The University of Arizona, 2005. http://hdl.handle.net/10150/290152.
Повний текст джерелаAouini, Sadok. "A programmable analog Gaussian noise generator for test applications /." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=99401.
Повний текст джерелаTaillefer, Christopher. "Analog-to-digital conversion via time-mode signal processing." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=18669.
Повний текст джерелаLes convertisseurs conventionnels pour changer la tension analogique à une tension numérique emploient les amplificateurs de tension, les comparateurs de tension, et les résaux de condensateur sélectionable pour acquir leur traitement de signal. En comparaison le circuit des modules analogues vis-à-vis le circuit numérique nous constatons une augmentation de puissance, une superficie de silicium moins compacte, et un traitement de données beaucoup plus lent. Une méthodologie est proposée pour le traitement du signal qui établi la conversion analogue à numérique sur les signaux de tension et tout en mettant en oeuvre tous les circuits dans un format numérique de type circuit à semiconducteur oxyde-métal à symétrie complémentaire (CMOS). Cette méthodologie reconnue sur le nom de technique-temporelle donne un traitement de signal par domaine temporel en employant la variance de cadence entre les temps comme un signal intermédiare entre la tension d'entrée et la tension de sortie numérique. Les formats numériques de type circuit semiconducteur nous offrent une alternative en temps convertisseur d'analogue à numérique avec l'avantage d'une unité compact, robuste, un coût de puissance réduit, et une haute-vitesse efficace. Il existe cinq topologies principales dans les convertisseurs analogiques à numérique: flash, approximations successives, pipeline, delta-sigma, convertisseurs intégrés. Dans chacune des topologies mentionnées ci-dessus, le traitement de signal par technique-temporelle est une méthode réconnue. Les circuits employés par chaque convertisseur de donnée par technique temporelle sont décrits lorsque le niveau du système est approprié, le niveau du transitor, et les données expérimentales sont identifiés. Trois circuits intégrés (CI) ont été conçus et fabriqués, avec une technologie de 0,18-µm CMOS pour démontrer la possibilité de la méthodologie du techniquetemporelle convertisseur analogique-numéri
Espinosa, Christlieb José Humberto. "Reducing complexity of consumer electronics interfaces using commonsense reasoning." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/33202.
Повний текст джерелаThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 94-100).
User interfaces to consumer electronics devices - Video recorders, phones, cameras, washing machines, microwave ovens, etc. - are getting too complicated to be easily used by ordinary consumers. We believe that what is responsible for such complication is a design philosophy which simply maps functions the device can perform to controls like buttons and menu items. That leaves the users with the difficult cognitive task of mapping their goals onto the devices' capabilities - a frustrating and error-prone process. Our hypothesis is that we can provide better assistance to the user using Commonsense Reasoning leading to shorter interactions with the devices. Commonsense can infer the users' likely goals from watching their actions, and anticipate what capabilities of the device can fulfill the users' needs. As devices gain networking capabilities and interact with other devices, Commonsense can also help devices cooperate in support of the users' goals.
by José Humberto Espinosa Christlieb.
S.M.
Sheriff, Bonnie Ann Collier C. Patrick Heath James M. "Silicon nanowires and silicon/molecular interfaces for nanoscale electronics /." Diss., Pasadena, Calif. : California Institute of Technology, 2009. http://resolver.caltech.edu/CaltechETD:etd-06302008-165534.
Повний текст джерелаQumsieh, Ala. "An analog VLSI implementation of an attention-based saccade generator." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0005/MQ44036.pdf.
Повний текст джерелаWu, Yang 1974. "Monolithic nyquist rate analog to digital converter with digital calibration." Thesis, McGill University, 2002. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=29549.
Повний текст джерелаThe digital reference source consists of flip-flops and RC low-pass filters. By programming flip-flops with appropriate digital bit streams, accurate DC reference levels can be generated. The generated DC reference levels replace the need for reference ladder in Flash ADCs. Furthermore, with programmability provided by the digital reference source, the generated reference levels can be modified to reduce comparator offset. The comparator offset reduction algorithm is also applied to pipeline ADCs to reduce non-linear distortion.
The design details of pipeline ADC is also discussed in this work. Quantitative analyses have been provided in determining design parameters in various subsystems. The analyses ensure that a 10-bit resolution is achieved for the pipeline ADC. Both Flash ADC and pipeline ADC were implemented in a 0.25 mum and 0.18 mum CMOS process respectively, and results demonstrating their successful operation are presented.
Ali-Bakhshian, Mohammad. "Digital processing of analog information adopting time-mode signal processing." Thesis, McGill University, 2013. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114237.
Повний текст джерелаLes technologies CMOS progressant vers les procédés 22 nm et au delà, la abrication des circuits analogiques dans ces technologies se heurte a de nombreuses limitations. Entre autres limitations on peut citer la réduction d'amplitude des signaux, la sensibilité aux effets du bruit thermique et la perte de fonctions précises de commutation. Le traitement de signal en mode temps (TMSP pour Time-Mode Signal Processing) est une technique que l'on croit être bien adapté pour résoudre un grand nombre de problèmes relatifs a ces limitations. TMSP peut être défini comme la détection, le stockage et la manipulation de l'information analogique échantillonnée en utilisant des quantités de temps comme variables. L'un des avantages importants de TMSP est la capacité à réaliser des fonctions analogiques en utilisant des structures logiques digitales. Cette technique a une longue histoire en terme d'application en électronique. Cependant, en raison du manque de certaines fonctions fondamentales, l'utilisation de variables en mode temps a été limitée à une utilisation comme étape intermédiaire dans le traitement d'un signal et toujours dans le contexte d'une conversion tension/courant-temps et temps-tension/courant. Ces conversions nécessitent l'inclusion de blocs analogiques qui vont a l'encontre de l'avantage numérique des TMSP. Cette thèse fournit un fondement approprié pour le développement de TMSP comme outil général de traitement de signal. En proposant le concept nouveau d'interruption de retard, une toute nouvelle approche asynchrone pour la manipulation de variables en mode temps est suggéré. Comme conséquence directe de cette approche, des techniques pratiques pour le stockage, l'addition et la soustraction de variables en mode temps sont présentées. Pour étendre l'implémentation digitale de TMSP à une large gamme d'applications, la conception d'un intégrateur (accumulateur) à double voie temps- à -temps est démontrée. cet intégrateur est ensuite utilisé pour implémenter un modulateur delta-sigma de second ordre.Enfin, pour démontrer l'avantage de TMSP, une Interface de très basse puissance, compacte et réglable pour capteurs capacitifs est présenté. Cette interface est composé d'un certain nombre de blocs de retard associés à des portes logiques typiques. Toutes les théories proposées sont soutenues par des résultats expérimentaux et des simulations post-layout. L'implémentation digitale des circuits proposés a été la première priorité de cette thèse. En effet, une implémentation des bloc avec des structures digitales permet des conceptions simples, synthétisable et reconfigurables où des circuits de calibration très abordables peuvent être adoptées pour éliminer les effets des variations de process.
Gottiparthy, Ramraj Wilamowski Bogdan M. "An accurate CMOS four-quadrant analog multiplier." Auburn, Ala., 2006. http://repo.lib.auburn.edu/2006%20Spring/master's/GOTTIPARTHY_RAMRAJ_15.pdf.
Повний текст джерелаHu, Zongqi. "Analog integrated circuit design of hypertrellis decoders /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20HU.
Повний текст джерелаConway, Kevin Michael. "X-ray studies of solid state layers and interfaces." Thesis, Cardiff University, 1989. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.238154.
Повний текст джерелаPiels, Molly. "Si/Ge photodiodes for coherent and analog communication." Thesis, University of California, Santa Barbara, 2014. http://pqdtopen.proquest.com/#viewpdf?dispub=3612014.
Повний текст джерелаHigh-speed photodiodes have diverse applications in wireless and fiber communications. They can be used as output stages for antenna systems as well as receivers for fiber optic networks. Silicon is an attractive substrate material for photonic components for a number of reasons. Low cost manufacturing in CMOS fabrication facilities, low material loss at telecommunications wavelengths, and relatively simple co-packaging with electronics are all driving interest in silicon photonic devices. Since silicon does not absorb light at telecommunications wavelengths, photodetector fabrication requires the integration of either III-V materials or germanium. Recent work on germanium photodetectors has focused on low-capacitance devices suitable for integration with silicon electronics. These devices have excellent bandwidth and efficiency, but have not been designed for the levels of photocurrent required by coherent and analog systems. This thesis explores the design, fabrication, and measurement of photodetectors fabricated on silicon with germanium absorbing regions for high speed and high power performance.
There are numerous design trade-offs between speed, efficiency, and output power. Designing for high bandwidth favors small devices for low capacitance. Small devices require abrupt absorption profiles for good efficiency, but design for high output power favors large devices with dilute absorption. The absorption profile can be controlled by the absorber layer thickness, but this will also affect the bandwidth and power handling. This work quantifies the trade-offs between high speed, high efficiency, and high power design. Intrinsic region thickness and absorption profile are identified as the most important design variables. For PIN structures, the absorption profile and intrinsic region thickness are both functions of the Ge thickness, but in uni-traveling carrier (UTC) structures the absorption profile and intrinsic region can be designed independently. This allows optimization of the absorption profile independently from the RC-limited frequency response and compression current and ultimately enables larger saturation current-bandwidth products. This thesis includes the first theory, fabrication, and measurement of a uni-traveling carrier photodiode on the Si/Ge platform. Key contributions include an accurate nonlinear device model and a complete set of processes and design rules for fabricating Ge devices in the UCSB nanofab. The UTC structure is shown to be useful in extending the bandwidth and power handling capabilities of waveguide-integrated photodiodes, especially at high frequencies.
Dufort, Benoit. "Analog signal generation using periodic sigma-delta modulated streams." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0018/NQ55325.pdf.
Повний текст джерелаGustafsson, E. Martin I. "Reconfigurable Analog to Digital Converters for Low Power Wireless Applications." Doctoral thesis, Kista : KTH School of Information and Communication Technology, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4774.
Повний текст джерелаSmith, Christopher T. "Graphene oxide material interfaces in electronics, energy and environmental membranes." Thesis, University of Surrey, 2016. http://epubs.surrey.ac.uk/811137/.
Повний текст джерелаJönsson, Stina Karin Maria. "Towards flexible organic electronics : photoelectron spectroscopy of surfaces and interfaces /." Linköping : Univ, 2004. http://www.bibl.liu.se/liupubl/disp/disp2004/tek895s.pdf.
Повний текст джерелаBarrett, Richard. "Novel processing routes for neural interfaces." Thesis, University of Birmingham, 2014. http://etheses.bham.ac.uk//id/eprint/5137/.
Повний текст джерелаLouis, Loai. "A study of delta-sigma modulators for analog-to-digital conversion." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0029/MQ50639.pdf.
Повний текст джерелаMacedo, Marco. "Calibration and high speed techniques for CMOS analog-to- digital converters." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=110482.
Повний текст джерелаL'objectif de cette dissertation est de trouver la meilleure méthode de conception pour les convertisseurs de type analogique à digital. La conception de convertisseurs de type analogique à digital en CMOS qui soient capables de fournir une résolution élevée est un défi de taille à des fréquences très élevées comme les gigahertz, car en CMOS les sources de voltages sont très petites et les dimensions des transistors rendent les composantes analogues (e.g., comparateur, amplicateur, et references de voltage) de plus en plus susceptibles aux variations physiques et chimiques qui se produisent durant la fabrication des puces microélectroniques.Les méthodes traditionnelles de conception pour les convertisseurs de type analogique à digital ne sont plus a la hauteur pour fournir des convertisseurs capables d'une bonne resolution, car elles ne prennent pas avantage des percés technologiques qui ont été réalisées avec la diminution de la taille physique des transistors en CMOS. Par conséquent, le travail de recherche éffectué dans cette thèse consiste à étudier des nouvelles structures de circuits pour faire la conception de track-and-hold qui est necessaire au bon fonctionnement de convertisseurs analogique à digital de très hautes fréquences. De plus, une méthode de calibration digitale qui a pour objectif de corriger les défectuosités engendrées par la fabrication des puces microélectroniques est aussi proposée afin d'ameliorer la performance et la résolution des convertisseurs analogique à digital. Finalement, deux puces microélectroniques ont été fabriquées a des fins expérimentales pour démontrer la performance d'un nouveau track-and-hold ainsi que valider une nouvelle technique de calibration digitale de type foreground qui utilise des résistances.
Taherzadeh-Sani, Mohammad. "Reconfigurable pipelined analog-to-digital converters in low -voltage nanometer CMOS." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=114247.
Повний текст джерелаLa demande croissante de terminaux sans fil multimode et multistandard alimente l'intérêt pour des convertisseurs analogique-numérique (CAN) qui soient largement reconfigurables en terme de bande passante et de résolution. En outre, et pour des raisons d'efficacité énergétique, l'alimentation de ces CANs doit être modulable dans le but de maintenir une constante figure de mérite (FOM) dans tout l'espace de reconfigurabilité. Aussi, ces CANs doivent pouvoir être implémentés dans un technologie CMOS standard pour bénéficier d'un niveau d'intégration élevé de ses composants digitaux et analogiques ainsi qu'un plus faible cout de fabrication. Ceci dit, dans les technologies CMOS nanométriques, la diminution des tensions d'alimentation et la diminution de la taille des dispositifs sont des éléments contraignant la conception des CANs faible puissance. Cette thèse propose un CAN de type pipeline qui est reconfigurable sur une gamme continue de fréquences d'échantillonnage fs = 0.4 à 44 MS/s (bande passante de 0.2 à 22 MHz), pour les résolutions N = 10, 11, et 12 bits. Fabriqué dans une technologie digitale CMOS de 90-nm et 1.2-V, ce CAN est caractérisé par une faible consommation de puissance (FOM = 0.35 to 0.5 pJ/conversion step) sur tout son espace bande-resolution. Ainsi, ce CAN est approprié pour de multiples standards sans fil et cellulaire allant du GSM au LTE/iMax et 802.11g. Aussi, et en raison de son efficacité énergétique, ce CAN est attrayant pour diverses applications ce qui permet des économies de développements ainsi qu'une rapide mise sur le marché.Comparé à ce qui ce se fait aujourd'hui en terme d'efficacité énergétique (FOM < 2 pJ/conversion step), par exemple CAN de type pipeline ou Delta-Sigma, ce CAN offre un large espace de reconfiguration bande-resolution tout en réalisant un FOM hautement concurrentiel sur tout le dit espace. Pour varier la tension d'alimentation, la bande passante et la resolution du CAN sont reconfigurés en utilisant les méthodes dites de current-scaling et de stage-bypass respectivement. Les techniques suivantes sont également introduites pour obtenir des performances faible puissance dans l'espace de reconfigurabilite du CAN et permettre son implémentation dans une technologie CMOS nanométrique basse tension: 1) calibration digitale de gain type background pour permettre la conception du CAN à l'aide d'amplificateurs opérationnels faible gain et faible puissance; 2) compensation pseudo-cascode pour les amplificateurs opérationnels à courants variables; 3) la conception de comparateurs dynamiques type switch-cap à faible charge d'entrée.
Nagarathnam, Premkumar. "Novel carbon nanotube thermal interfaces for microelectronics." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31720.
Повний текст джерелаCommittee Chair: Graham, Sam; Committee Member: Joshi, Yogendra; Committee Member: Kalaitzidou, Kyriaki. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Dida, Bashkim. "Automatiserad konstruktion av analoga förstärkare." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2944.
Повний текст джерелаThe last few decades the development in the field of electronics has been huge. The components performance gets better at the same time as the manufacturing cost decreases. Many of the design moments that have to be done, are done automatically today, but it can get better. Especially for analog circuit design.
At Electronic System in Linköpings universitet, research is in progress to develop a tool that can design analog circuits in reasonable time. It means that it has to size the components (transistors, resistances, capacitances etc), so that the circuit can fulfill the performance requirements. An optimization method in conjunction with derived equations for the circuit performance is used to solve this task. The tool is created to design e.g. analog amplifiers. The goal is to decrease the design time and at the same time achieve better circuit performance.
This tool has been tested on three different circuits, a power-amplifier, a Nested Miller Compensated amplifier with an active feedback (Active Nested Miller Compensation) and a Nested Miller Compensated amplifier without an active feedback (Nested Miller Compensation). In this report the results from the designing tests are presented.
Safi-Harab, Mouna. "Low-power low-voltage high-speed delta-sigma analog-to-digital converters." Thesis, McGill University, 2003. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=79258.
Повний текст джерелаThe first is the extension of the input frequency range to include applications where the input bandwidth exceeds the 1 MHz range.
This challenge in extending the operational speed of DeltaSigmaM is further rendered more complicated by the ever shrinking transistor dimension. As predicted by the Semiconductor Industry Association (SIA) Roadmap for CMOS technology, the transistor dimension will reach 0.05 mum in 2011. With this dramatic shrink in the transistor length, and as a result in the supply voltage, device modelling becomes ambiguous and circuit non-idealities more pronounced. The design of the main analog building blocks that minimize the time-to-market is therefore becoming very complicated.
These two issues will be addressed in this thesis, namely a new design method that will minimize the design cycle of delta-sigma analog-to-digital converters (DeltaSigma ADCs) intended for high-speed applications. This method will be demonstrated efficient in the implementation of two state-of-the-art modulators in terms of performance using a widely adopted figure of merit.
The validity of the top-down design methodology was verified through the fabrication of two prototype integrated circuits (ICs), both in TSMC 0.18 mum CMOS technology. In the first chip, a single-bit, fourth-order DeltaSigma ADC was implemented achieving more than 12-bit resolution. The second chip further validated the methodology to include higher resolution, in the range of 13 bits, multi-bit DeltaSigma ADCs. The experimental results from both prototype ICs closely mimic the system-level behavior of the designed modulator.
Hou, Xiaobo Rosen Warren A. Daryoush Afshin S. "A leaky waveguide all-optical analog-to-digital converter /." Philadelphia, Pa. : Drexel University, 2004. http://dspace.library.drexel.edu/handle/1860/437.
Повний текст джерелаYing, Weidong Larry 1968. "Verification and re-design of communication interfaces with heterogeneous timing." Thesis, McGill University, 2001. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=34002.
Повний текст джерелаWe further exam re-design issues of an existing GALS system as compact design, internal structure optimization and reduced power consumption. Exhaustive verifications are applied to re-designed asynchronous wrapper circuits using our proposed refinement-based technique to ensure hazard-free operation.
We explore a strategy to resolve relative timing conflicts by implementing detected chain constraints as new circuit components to be integrated with the original design. This method is applied on two design cases to demonstrate its benefits and tradeoffs.
Hollinger, Avrum. "Optical sensing, embedded systems, and musical interfaces for functional neuroimaging." Thesis, McGill University, 2014. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=123054.
Повний текст джерелаL'imagerie par résonance magnétique fonctionnelle (IRM) est de plus en plus utilisée pour des expériences de neuroscience comportementale. De telles expériences nécessitent la création de nouvelles interfaces augmentées de capteurs et de systèmes de contrôle électroniques pour capter les comportements, présenter des stimuli et produire des retours d'information de manière synchrone avec le scanner. Ainsi, il est possible pour les neuroscientifiques d'établir des corrélations entre les changements de comportement et les changements d'activité cérébrale; ceci leur permet donc de développer une meilleure compréhension du cerveau humain.Sécurité et compatibilité sont de plus haute importance, bien que des essais répétés de nouvelles interfaces dans le scanner IRM, afin de garantir qu'elle soit sécuritaire, augmente donc le prix de son développement. Les capteurs à fibre optique permettent d'atteindre ces objectifs avec les scanners actuels et les nouvelles générations de scanners qui produisent des champs magnétiques encore plus puissants.J'ai développé et construit de nouveaux capteurs optiques, des systèmes d'acquisition optoélectroniques, et des interfaces musicales compatibles avec les scanners IRM dans le cadre d'études d'imagerie cérébrale. Les capteurs à fibre optique que j'ai concus ont été créés pour mesurer la proximité, la position, le déplacement, la flexion, la force et le champs magnétique. Les systèmes embarqués développés durant cette thèse ont pour objectif de fournir des systèmes autonomes permettant de réaliser des expériences comportementales. à ce titre, ils permettent l'acquisition optoélectronique de signaux, leur communication, leur enregistrement et la production de stimuli auditif en temps-réel (incluant le mapping et la synthèse). Voici une liste des interfaces de contrôle musicales mises au point durant ce projet de doctorat: le Ballagumi, un nouvel instrument flexible fait en silicone; des claviers de piano optoélectroniques; et un violoncelle optoacoustique. Les pianos et le violoncelle ont été mis à contribution lors d'expériences ayant permis, pour la première fois, de capter les gestes d'un instrumentiste au sein d'un scanner. Dans ce qui suit, je présente le processus itératif de développement et de test ayant mené à ces nouvelles interfaces. De plus, l'état de l'art sur les interfaces musicales compatibles avec les scanners IRM est passé en revue, ainsi que les futures évolutions et applications de ces technologies aux domaines de la neuroscience comportementale, de la réhabilitation cérébrale et de la performance musicale.
Dugger, Jeffery Don. "Adaptive Analog VLSI Signal Processing and Neural Networks." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5294.
Повний текст джерелаAbcarius, John 1972. "High-speed low-cost Delta-Sigma modulation techniques for analog-to-digital conversion." Thesis, McGill University, 1998. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=20898.
Повний текст джерелаThis thesis investigates the potential of DeltaSigma modulation techniques in addressing both of these issues through the design, implementation and experimentation of several prototype integrated circuits. Delta-Sigma modulation has recently become widely recognized for its ability to perform high performance data conversion without the use of high precision components. To extend these benefits to wireless applications, a novel eighth-order bandpass DeltaSigma modulator for A/D conversion will be presented. The modulator design is developed beginning at the signal processing level and realized in a 0.8mu BiCMOS process using the switched-capacitor (SC) technique. To address the cost issue, the design of a data conversion system based on the DeltaSigma modulation technique using an economical purely digital CMOS implementation is investigated. The distortion performance of experimental prototypes implemented using switched-capacitor (with capacitors realized using MOSFETs) and switched-current techniques is assessed.
This work therefore contributes to the ongoing drive to improve the performance and applicability of the DeltaSigma modulation technique in meeting modern-day data conversion needs.
Shoukry, Ehab. "Design of a fully integrated array of high-voltage digital-to-analog converters." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=83933.
Повний текст джерелаSmith, O'neil Lohanica. "Design and use of surface modifiers as tools for understanding and controlling interfaces in organic electronics." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51838.
Повний текст джерелаDghais, Wael. "Behavioral modeling optimization and enhancement for high-speed analog mixed-signal I/O interfaces." Doctoral thesis, Universidade de Aveiro, 2013. http://hdl.handle.net/10773/12094.
Повний текст джерелаA integridade do sinal em sistemas digitais interligados de alta velocidade, e avaliada através da simulação de modelos físicos (de nível de transístor) é custosa de ponto vista computacional (por exemplo, em tempo de execução de CPU e armazenamento de memória), e exige a disponibilização de detalhes físicos da estrutura interna do dispositivo. Esse cenário aumenta o interesse pela alternativa de modelação comportamental que descreve as características de operação do equipamento a partir da observação dos sinais eléctrico de entrada/saída (E/S). Os interfaces de E/S em chips de memória, que mais contribuem em carga computacional, desempenham funções complexas e incluem, por isso, um elevado número de pinos. Particularmente, os buffers de saída são obrigados a distorcer os sinais devido à sua dinâmica e não linearidade. Portanto, constituem o ponto crítico nos de circuitos integrados (CI) para a garantia da transmissão confiável em comunicações digitais de alta velocidade. Neste trabalho de doutoramento, os efeitos dinâmicos não-lineares anteriormente negligenciados do buffer de saída são estudados e modulados de forma eficiente para reduzir a complexidade da modelação do tipo caixa-negra paramétrica, melhorando assim o modelo standard IBIS. Isto é conseguido seguindo a abordagem semi-física que combina as características de formulação do modelo caixa-negra, a análise dos sinais eléctricos observados na E/S e propriedades na estrutura física do buffer em condições de operação práticas. Esta abordagem leva a um processo de construção do modelo comportamental fisicamente inspirado que supera os problemas das abordagens anteriores, optimizando os recursos utilizados em diferentes etapas de geração do modelo (ou seja, caracterização, formulação, extracção e implementação) para simular o comportamento dinâmico não-linear do buffer. Em consequência, contributo mais significativo desta tese é o desenvolvimento de um novo modelo comportamental analógico de duas portas adequado à simulação em overclocking que reveste de um particular interesse nas mais recentes usos de interfaces de E/S para memória de elevadas taxas de transmissão. A eficácia e a precisão dos modelos comportamentais desenvolvidos e implementados são qualitativa e quantitativamente avaliados comparando os resultados numéricos de extracção das suas funções e de simulação transitória com o correspondente modelo de referência do estado-da-arte, IBIS.
Signal integrity (SI) simulation of high-speed digital interconnected system via transistor level models is computational expensive (e.g. CPU time and memory storage), and requires the availability of physical details information of device’s internal structure. This scenario raises the interest for a behavioral modeling alternative which describes the device’s operation characteristics based on the observed input/output (I/O) electrical signal. I/O buffers that interface memory’s interconnects have major share in the computational load containing a very active complex functional part and high numbers of pins. Particularly, output buffers/drivers are forced to distort the I/O signals due to their nonlinear dynamics. In this concern, they constitute the integrated circuit (IC) bottleneck of ensuring reliable data transmission in the high-speed digital communication link. In this PhD work, the previously neglected driver’s nonlinear dynamic effects are efficiently captured to significantly reduce the state of the art black-box parametric modeling complexities and enhance the input/output buffers information specifications (IBIS). This is achieved by following the gray-box approach that merges the features of the black-box model’s formulation, the analysis of the observed I/O electrical signals and the buffer’s physical structure properties under practical operation conditions. This approach leads to physically inspired behavioral model’s construction procedure that overcomes the issues of the previous modeling approaches by optimizing the resources used at different model’s generation steps (i.e. characterization, formulation, extraction, and implementation) to mimic the driver’s nonlinear dynamic behavior. Moreover, the most important achievement is the development of a new two-port analog behavioral model for overclocking simulation that copes with the recent trends in I/O memory interfaces characterized by higher data rate transmission. The effectiveness and the accuracy of the developed and implemented behavioral models are qualitatively and quantitatively assessed by comparing the numerical results of their functions extraction and transient simulation to the ones simulated and extracted with transistor level models and the state of the art IBIS in order to validate their predictive and the generalization capabilities.
Salim, J. Athfal. "Digital-To-Analog Converter for FSK." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8349.
Повний текст джерелаThis thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.
The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.
In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.
Fan, Yongquan. "Accelerating jitter and BER qualifications of high speed serial communication interfaces." Thesis, McGill University, 2010. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=86531.
Повний текст джерелаThe thesis first proposes a new algorithm, suitable for extrapolating the receiver jitter tolerance performance from higher BER regions down to the 10-12 level or lower [2]. This algorithm enables us to perform the jitter tolerance characterization and production test more than 1000 times faster [3]. Then an under-sampling based transmitter test scheme is presented. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100ms [4] while the test usually takes seconds. All the receiver and transmitter testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with speed up to 6 Gigabits per second (Gbps).
The thesis also presents an external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay lines. The scheme can be applied to test HSSIs with data rate up to 12.5 Gbps. It is also suitable for multi-lane HSSI testing with a lower cost than pure ATE solutions. By using high-speed relays, we combine the proposed ATE based approaches and the loopback approach along with an FPGA-based BER tester to provide a more versatile scheme for HSSI post-silicon validation, testing and debugging [5]. In addition, we further explore the unparallel advantages of our digital Gaussian noise generator in low BER evaluation [6].
Les interfaces sérielles à haute vitesse (interfaces HSSI) ont connu une utilisation accrue dans les télécommunications. Le taux d'erreur sur les bits (BER), mesure de la fréquence des erreurs, est d'une importance cruciale dans les interfaces modernes de télécommunication. Cette thèse traite de l'accélération de la caractérisation du vacillement et des tests BER.
Cette thèse propose tout d'abord un nouvel algorithme, approprié pour l'extrapolation de la performance de la tolérance au vacillement d'un récepteur pour un taux d'erreur sur les bits (BER) à un niveau de 10-12 ou moins. Cet algorithme permet de caractériser la tolérance au vacillement dans les tests de production plus de 1000 fois plus rapidement. Ensuite, une conception de transmetteur à sous-échantillonnage est présenté. Cette conception permet d'extraire précisément le vacillement du transmetteur et de compléter les tests de ce dernier en moins de 100 ms alors que ces tests durent normalement plusieurs secondes. Toutes les méthodes de test de récepteurs et de transmetteurs ont été utilisées avec succès sur un équipement d'éssai automatique (ATE) pour qualifier des millions d'interfaces HSSI à des vitesses allant jusqu'à 6 gigabits par seconde (6 Gbps).
Cette thèse présente aussi une conception de test en bouclage où une nouvelle méthode d'injection de vacillement est proposée en utilisant des lignes de délai de phase. Cette méthode peut être appliquée pour tester des interfaces HSSI avec un taux de transfer allant jusqu'à 12.5 Gbps. Elle permet aussi de tester des interface HSSI multi-lignes à un coût moindre qu'une solution utilisant un ATE. En utilisant des relais à haute vitesse, les approches sur ATE et par test en bouclage peuvent être combinées en incorporant un testeur de BER sur circuit intégré prédiffusé programmable (FPGA), ce qui permet une méthode de tests HSSI polyvalente pour la validation post-fabrication, les tests et le débogage. Finalement, nous explorons les avantages de notre générateur de bruit Gaussien dans l'évaluation de BER à bas niveau.