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Статті в журналах з теми "Algorithm co-design"
Chen, Andrew, Rohaan Gupta, Anton Borzenko, Kevin Wang, and Morteza Biglari-Abhari. "Accelerating SuperBE with Hardware/Software Co-Design." Journal of Imaging 4, no. 10 (October 18, 2018): 122. http://dx.doi.org/10.3390/jimaging4100122.
Повний текст джерелаDrumond, Mario, Alexandros Daglis, Nooshin Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi, Boris Grot, and Dionisios Pnevmatikatos. "Algorithm/Architecture Co-Design for Near-Memory Processing." ACM SIGOPS Operating Systems Review 52, no. 1 (August 28, 2018): 109–22. http://dx.doi.org/10.1145/3273982.3273992.
Повний текст джерелаLi, Min, Frederico Guimarães, and David A. Lowther. "Competitive co-evolutionary algorithm for constrained robust design." IET Science, Measurement & Technology 9, no. 2 (March 1, 2015): 218–23. http://dx.doi.org/10.1049/iet-smt.2014.0204.
Повний текст джерелаLópez, M., J. Daugman, and E. Cantó. "Hardware–software co-design of an iris recognition algorithm." IET Information Security 5, no. 1 (2011): 60. http://dx.doi.org/10.1049/iet-ifs.2009.0267.
Повний текст джерелаLi, Shih-An, Chen-Chien Hsu, Ching-Chang Wong, and Chia-Jun Yu. "Hardware/software co-design for particle swarm optimization algorithm." Information Sciences 181, no. 20 (October 2011): 4582–96. http://dx.doi.org/10.1016/j.ins.2010.07.017.
Повний текст джерелаKrawczyk, Kamil, Paweł Tomaszewicz, and Mariusz Rawski. "Whirlpool SoPC Implementation - Hardware/Software Co-Design Example." International Journal of Electronics and Telecommunications 58, no. 1 (March 1, 2012): 21–26. http://dx.doi.org/10.2478/v10177-012-0003-9.
Повний текст джерелаByun, Kwang-Sub, Chang-Hyun Park, and Kwee-Bo Sim. "Co-Evolution of Fuzzy Controller for the Mobile Robot Control." Journal of Advanced Computational Intelligence and Intelligent Informatics 8, no. 4 (July 20, 2004): 356–61. http://dx.doi.org/10.20965/jaciii.2004.p0356.
Повний текст джерелаRaghunathan, Shriram, Sumeet K. Gupta, Himanshu S. Markandeya, Kaushik Roy, and Pedro P. Irazoqui. "A hardware-algorithm co-design approach to optimize seizure detection algorithms for implantable applications." Journal of Neuroscience Methods 193, no. 1 (October 2010): 106–17. http://dx.doi.org/10.1016/j.jneumeth.2010.08.008.
Повний текст джерелаAlecsa, Bogdan, and Alexandru Onea. "Hardware-Software Co-Design for BLDC Motor Speed Controller Design." Advanced Materials Research 463-464 (February 2012): 1256–59. http://dx.doi.org/10.4028/www.scientific.net/amr.463-464.1256.
Повний текст джерелаBenxian Yue, Yishou Wang, Yanjun Shi, and Hongfei Teng. "Satellite Payloads Configuration and Layout Design Using Co-evolutionary Algorithm." International Journal of Advancements in Computing Technology 3, no. 11 (December 31, 2011): 223–30. http://dx.doi.org/10.4156/ijact.vol3.issue11.28.
Повний текст джерелаДисертації з теми "Algorithm co-design"
Zhang, Zhengdong Ph D. Massachusetts Institute of Technology. "Efficient computing for autonomous navigation using algorithm-and-hardware co-design." Thesis, Massachusetts Institute of Technology, 2019. https://hdl.handle.net/1721.1/122691.
Повний текст джерелаThesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2019
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 211-221).
Autonomous navigation algorithms are the backbone of many robotic systems, such as self-driving cars and drones. However, state-of-the-art autonomous navigation algorithms are computationally expensive, requiring powerful CPUs and GPUs to enable them to run in real time. As a result, it is prohibitive to deploy them on miniature robots with limited computational resources onboard. To tackle this challenge, this thesis presents an algorithm-and-hardware co-design approach to design energy-efficient algorithms that are optimized for dedicated hardware architectures at the same time. It covers the design for three essential modules of an autonomous navigation system: perception, localization, and exploration.
Compared with previous research that considers either algorithmic improvements or hardware architecture optimizations, our approach leads to algorithms that not only have lower time and space complexity but also map efficiently to specialized hardware architectures, resulting in significantly improved energy efficiency and throughput. First, this thesis studies how to design an energy-efficient visual perception system using the deformable part models (DPM) based object detection algorithm. It describes an algorithm that enforces sparsity in the data stored on a chip, which reduces the memory requirement by 34% and lowers the cost of the classification by 43%. Together with other hardware optimizations, this technique leads to an object detection chip that runs at 30 fps on 1920 x 1080 videos while consuming only 58.6mW of power.
Second, this thesis describes a systematic way to explore algorithm-hardware design choices to build a low-power chip that performs visual inertial odometry (VIO) to localize a vehicle. Each of the components in a VIO pipeline has multiple algorithmic choices with different time and space complexity. However, some algorithms of lower time complexity can be more expensive when implemented on-chip. This thesis examines each of the design choices from both the algorithm and hardware's point of view and presents a design that consumes 24mW of power while running at up to 90 fps and achieving near state-of-the-art localization accuracy Third, this thesis presents an efficient information theoretic mapping system for exploration. It features a novel algorithm called Fast computation of Shannon Mutual Information (FSMI) that computes the Shannon mutual information (MI) between perspective range measurements and the environment.
FSMI algorithm features an analytic solution that avoids the expensive numerical integration required by the previous state-of-the-art algorithms, enabling FSMI to run three orders-of-magnitude faster in practice. We also present an extension of the FSMI algorithm to 3D mapping; the algorithm leverages the compression of a large 3D map using run-length encoding (RLE) and achieves 8x acceleration in a real-world exploration task. In addition, this thesis presents a hardware architecture designed for the FSMI algorithm. The design consists of a novel memory banking method that increases the memory bandwidth so that multiple FSMI cores can run in parallel while maintaining high utilization. A novel arbiter is proposed to resolve the memory read conflicts between multiple cores within one clock cycle. The final design on an FPGA achieves more than 100x higher throughput compared with a CPU while consuming less than 1/10 of the power.
by Zhengdong Zhang.
Ph. D.
Ph.D. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Sherbaf, Behtash Mohammad. "A Decomposition-based Multidisciplinary Dynamic System Design Optimization Algorithm for Large-Scale Dynamic System Co-Design." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535468984437623.
Повний текст джерелаChee, Kenneth W. "APPLIED HW/SW CO-DESIGN: Using the Kendall Tau Algorithm for Adaptive Pacing." DigitalCommons@CalPoly, 2013. https://digitalcommons.calpoly.edu/theses/1038.
Повний текст джерелаNarasimhan, Seetharam. "Ultralow-Power and Robust Implantable Neural Interfaces: An Algorithm-Architecture-Circuit Co-Design Approach." Case Western Reserve University School of Graduate Studies / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=case1333743306.
Повний текст джерелаTzou, Nicholas. "Low-cost sub-Nyquist sampling hardware and algorithm co-design for wideband and high-speed signal characterization and measurement." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51876.
Повний текст джерелаCooksey, Kenneth Daniel. "A portfolio approach to design in the presence of scenario-based uncertainty." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/49036.
Повний текст джерелаMartelli, Maxime. "Approche haut niveau pour l’accélération d’algorithmes sur des architectures hétérogènes CPU/GPU/FPGA. Application à la qualification des radars et des systèmes d’écoute électromagnétique." Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLS581/document.
Повний текст джерелаAs the semiconductor industry faces major challenges in sustaining its growth, new High-Level Synthesis tools are repositioning FPGAs as a leading technology for algorithm acceleration in the face of CPU and GPU-based clusters. But as it stands, for a software engineer, these tools do not guarantee, without expertise of the underlying hardware, that these technologies will be harnessed to their full potential. This can be a game breaker for their democratization. From this observation, we propose a methodology for algorithm acceleration on FPGAs. After presenting a high-level model of this architecture, we detail possible optimizations in OpenCL, and finally define a relevant exploration strategy for accelerating algorithms on FPGA. Applied to different case studies, from tomographic reconstruction to the modelling of an airborne radar jammer, we evaluate our methodology according to three main performance criteria: development time, execution time, and energy efficiency
Bahri, Imen. "Contribution des systèmes sur puce basés sur FPGA pour les applications embarquées d’entraînement électrique." Thesis, Cergy-Pontoise, 2011. http://www.theses.fr/2011CERG0529/document.
Повний текст джерелаDesigning embedded control systems becomes increasingly complex due to the growing of algorithm complexity, the rising of industrials requirements and the nature of application domains. One way to handle with this complexity is to design the corresponding controllers on performing powerful and open digital platforms. More specifically, this PhD deals with the use of FPGA System-on-Chip (SoC) platforms for the implementation of complex AC drive controllers for avionic applications. These latters are characterized by stringent technical issues such as environment conditions (pressure, high temperature) and high performance requirements (high integration, flexibility and efficiency). During this thesis, the author has contributed to design and to test a digital controller for a high temperature synchronous drive that must operate at 200°C ambient. It consists on the Flux Oriented Controller (FOC) for a Permanent Magnet Synchronous Machine (PMSM) associated with a Resolver sensor. A design and validation method has been proposed and tested using a FPGA ProAsicPlus board from Actel-Microsemi Company. The impact of the temperature on the operating frequency has been also analyzed. A state of the art FPGA SoC technology has been also presented. A detailed description of the recent digital platforms and constraints in link with embedded applications was investigated. Thus, the interest of a SoC-based approach for AC drives applications was also established. Additionally and to have full advantages of a SoC based approach, an appropriate HW-SW Co-design methodology for electrical AC drive has been proposed. This method covers the whole development steps of the control application from the specifications to the final experimental validation. One of the main important steps of this method is the HW-SW partitioning. The goal is to find an optimal combination between modules to be implemented in software and those to be implemented in hardware. This multi-objective optimization problem was performed with the Non-Dominated Sorting Genetic Algorithm (NSGA-II). Thus, the Pareto-Front of optimal solution can be deduced. The illustration of the proposed Co-design methodology was made based on the sensorless speed controller using the Extended Kalman Filter (EKF). The choice of this benchmark corresponds to a major trend in embedded control of AC drives. Besides, the management of SoC-based architecture of the embedded controller was allowed using an efficient Real-Time Operating System (RTOS). To accelerate the services of this operating system, a Real-Time Unit (RTU) was developed in VHDL and associated to the RTOS. It consists in hardware operating system that moves the scheduling and communication process from software RTOS to hardware. Thus, a significant acceleration has been achieved. The experimentation tests based on digital current controller were also carried out using a laboratory set-up. The obtained results prove the interest of the proposed approach
Trindade, Alessandro Bezerra. "Aplicando verificação de modelos baseada nas teorias do módulo da satisfabilidade para o particionamento de hardware/software em sistemas embarcados." Universidade Federal do Amazonas, 2015. http://tede.ufam.edu.br/handle/tede/4091.
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When performing hardware/software co-design for embedded systems, does emerge the problem of allocating properly which functions of the system should be implemented in hardware (HW) or in software (SW). This problem is known as HW/SW partitioning and in the last ten years, a significant research effort has been carried out in this area. In this proposed project, we present two new approaches to solve the HW/SW partitioning problem by using SMT-based verification techniques, and comparing the results using the traditional technique of Integer Linear Programming (ILP) and a modern method of optimization by Genetic Algorithm (GA). The goal is to show with experimental results that model checking techniques can be effective, in particular cases, to find the optimal solution of the HW/SW partitioning problem using a state-of-the-art model checker based on Satisfiability Modulo Theories (SMT) solvers, when compared to the traditional techniques.
Quando se realiza um coprojeto de hardware/software para sistemas embarcados, emerge o problema de se decidir qual função do sistema deve ser implementada em hardware (HW) ou em software (SW). Este tipo de problema recebe o nome de particionamento de HW/SW. Na última década, um esforço significante de pesquisa tem sido empregado nesta área. Neste trabalho, são apresentadas duas novas abordagens para resolver o problema de particionamento de HW/SW usando técnicas de verificação formal baseadas nas teorias do módulo da satisfabilidade (SMT). São comparados os resultados obtidos com a tradicional técnica de programação linear inteira (ILP) e com o método moderno de otimização por algoritmo genético (GA). O objetivo é demonstrar, com os resultados empíricos, que as técnicas de verificação de modelos podem ser efetivas, em casos particulares, para encontrar a solução ótima do problema de particionamento de HW/SW usando um verificador de modelos baseado no solucionador SMT, quando comparado com técnicas tradicionais.
Zhang, Yuanzhi. "Algorithms and Hardware Co-Design of HEVC Intra Encoders." OpenSIUC, 2019. https://opensiuc.lib.siu.edu/dissertations/1769.
Повний текст джерелаКниги з теми "Algorithm co-design"
Mazumder, Pinaki, and Nanchuan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Limited, John, 2020.
Знайти повний текст джерелаMazumder, Pinaki, and Nan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Incorporated, John, 2019.
Знайти повний текст джерелаMazumder, Pinaki, and Nan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Incorporated, John, 2019.
Знайти повний текст джерелаMazumder, Pinaki, and Nan Zheng. Learning in Energy-Efficient Neuromorphic Computing: Algorithm and Architecture Co-Design. Wiley & Sons, Limited, John, 2019.
Знайти повний текст джерелаLi, Huanglong, J. Joshua Yang, and Hongsik Jeong, eds. Memristive Neuromorphics: Materials, Devices, Circuits, Architectures, Algorithms and their Co-Design. Frontiers Media SA, 2022. http://dx.doi.org/10.3389/978-2-88974-460-2.
Повний текст джерелаЧастини книг з теми "Algorithm co-design"
Vuduc, Richard, and Kenneth Czechowski. "Toward a Theory of Algorithm-Architecture Co-design." In Lecture Notes in Computer Science, 4–8. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38718-0_2.
Повний текст джерелаSelvabala, B., and D. Devaraj. "Co-ordinated Design of AVR-PSS Using Multi Objective Genetic Algorithm." In Swarm, Evolutionary, and Memetic Computing, 481–93. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-17563-3_57.
Повний текст джерелаParras-Gutierrez, Elisabet, Víctor M. Rivas, and Maria Jose del Jesus. "Automatic Neural Net Design by Means of a Symbiotic Co-evolutionary Algorithm." In Lecture Notes in Computer Science, 140–47. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-87656-4_18.
Повний текст джерелаGhimire, Manisha, Emma Regentova, and Venkatesan Muthukumar. "A -SLIC: Acceleration of SLIC Superpixel Segmentation Algorithm in a Co-Design Framework." In Advances in Intelligent Systems and Computing, 663–67. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-43020-7_90.
Повний текст джерелаLodha, Nupur, Nivesh Rai, Rahul Dubey, and Hrishikesh Venkataraman. "Hardware-Software Co-design of QRD-RLS Algorithm with Microblaze Soft Core Processor." In Information Systems, Technology and Management, 197–207. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-00405-6_23.
Повний текст джерелаPatil, Vilabha S., Shraddha S. Deshpande, and Yashwant B. Mane. "FPGA Based Acceleration of Security Algorithm Using Co-design Approach for WSN Applications." In Advances in Intelligent Systems and Computing, 592–603. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30465-2_66.
Повний текст джерелаMerchant, Farhad, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, and Ranjani Narayan. "Achieving Efficient Realization of Kalman Filter on CGRA Through Algorithm-Architecture Co-design." In Applied Reconfigurable Computing. Architectures, Tools, and Applications, 119–31. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-78890-6_10.
Повний текст джерелаLai, Kok Choong, M. L. Dennis Wong, and Syed Zahidul Islam. "A HW/SW Co-Design Implementation of Viola-Jones Algorithm for Driver Drowsiness Detection." In Lecture Notes in Electrical Engineering, 427–35. Dordrecht: Springer Netherlands, 2013. http://dx.doi.org/10.1007/978-94-007-6516-0_46.
Повний текст джерелаRamteke, Pradnya G., Meghana Hasamnis, and S. S. Limaye. "Co-design Approach for Implementation of Decryption Block of Rijndael’s Algorithm Using Soft Core Processor." In Communications in Computer and Information Science, 721–29. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36321-4_67.
Повний текст джерелаWolf, Wayne. "Hardware/Software Co-Synthesis Algorithms." In Hardware/Software Co-Design: Principles and Practice, 47–73. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2649-7_2.
Повний текст джерелаТези доповідей конференцій з теми "Algorithm co-design"
Batarseh, Fadi, Uwe Paul Schroeder, Jeff Nelson, Ya-Chieh Lai, Piyush Pathak, Sriram Madhavan, and Philippe Hurat. "Pattern similarity profiling using semi-supervised learning algorithm." In Design-Technology Co-optimization XV, edited by Chi-Min Yuan and Ryoung-Han Kim. SPIE, 2021. http://dx.doi.org/10.1117/12.2586112.
Повний текст джерелаJi, Hao, Masha Sosonkina, and Yaohang Li. "An Implementation of Block Conjugate Gradient Algorithm on CPU-GPU Processors." In 2014 Hardware-Software Co-Design for High Performance Computing (Co-HPC). IEEE, 2014. http://dx.doi.org/10.1109/co-hpc.2014.10.
Повний текст джерелаTramm, John R., Kazutomo Yoshii, and Andrew R. Siegel. "Power Profiling of a Reduced Data Movement Algorithm for Neutron Cross Section Data in Monte Carlo Simulations." In 2014 Hardware-Software Co-Design for High Performance Computing (Co-HPC). IEEE, 2014. http://dx.doi.org/10.1109/co-hpc.2014.9.
Повний текст джерелаSchroeder, Uwe Paul, Ahmed Shalabi, Janam Bakshi, Mohamed Ismail, and Ahmed M. Elsemary. "Optimizing DFM scores by using a genetic evolution algorithm." In Design-Process-Technology Co-optimization for Manufacturability XIII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2019. http://dx.doi.org/10.1117/12.2515094.
Повний текст джерелаHuang, Qijing, Dequan Wang, Yizhao Gao, Yaohui Cai, Zhen Dong, Bichen Wu, Kurt Keutzer, and John Wawrzynek. "Algorithm-hardware Co-design for Deformable Convolution." In 2019 Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing - NeurIPS Edition (EMC2-NIPS). IEEE, 2019. http://dx.doi.org/10.1109/emc2-nips53020.2019.00019.
Повний текст джерелаLucarz, Christophe, Marco Mattavelli, and Julien Dubois. "A co-design platform for algorithm/architecture design exploration." In 2008 IEEE International Conference on Multimedia and Expo (ICME). IEEE, 2008. http://dx.doi.org/10.1109/icme.2008.4607623.
Повний текст джерелаDick, Gregory J., Abhishek Asthana, Liang Cao, Jing Cheng, and David Power. "Optimization of optical proximity correction to reduce mask write time using genetic algorithm." In Design-Process-Technology Co-optimization for Manufacturability XII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2018. http://dx.doi.org/10.1117/12.2297400.
Повний текст джерелаGai, Tianyang, Ying Chen, Pengzheng Gao, Xiaojing Su, Lisong Dong, Yajuan Su, Yayi Wei, and Tianchun Ye. "Sample patterns extraction from layout automatically based on hierarchical cluster algorithm for lithography process optimization." In Design-Process-Technology Co-optimization for Manufacturability XIII, edited by Jason P. Cain and Chi-Min Yuan. SPIE, 2019. http://dx.doi.org/10.1117/12.2514177.
Повний текст джерела"Session TP7a: Algorithm/architecture co-design [breaker page]." In 2013 Asilomar Conference on Signals, Systems and Computers. IEEE, 2013. http://dx.doi.org/10.1109/acssc.2013.6810531.
Повний текст джерелаCzechowski, Kenneth, and Richard Vuduc. "A Theoretical Framework for Algorithm-Architecture Co-design." In 2013 IEEE International Symposium on Parallel & Distributed Processing (IPDPS). IEEE, 2013. http://dx.doi.org/10.1109/ipdps.2013.99.
Повний текст джерелаЗвіти організацій з теми "Algorithm co-design"
Daudelin, Francois, Lina Taing, Lucy Chen, Claudia Abreu Lopes, Adeniyi Francis Fagbamigbe, and Hamid Mehmood. Mapping WASH-related disease risk: A review of risk concepts and methods. United Nations University Institute for Water, Environment and Health, December 2021. http://dx.doi.org/10.53328/uxuo4751.
Повний текст джерела