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1
Fletcher, R. G. "Power semiconductor devices in A.C. circuit protection." Thesis, Imperial College London, 1987. http://hdl.handle.net/10044/1/7921.
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Gupta, Narendra Kumar. "Inductive interference into a lineside signalling cable in A.C. electric railway systems." Thesis, University of Manchester, 1985. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.252792.
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Couto, Barone Dante Augusto Mazaré Guy. "Conception d'un circuit intégré arbitre de bus de communication multiprotocoles ABC M /." S.l. : Université Grenoble 1, 2008. http://tel.archives-ouvertes.fr/tel-00311675.
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Gibson, Andrew A. P. "Variational finite element analysis of microwave circuits and gyrotropic components." Thesis, University of Manchester, 2003. http://www.manchester.ac.uk/escholar/uk-ac-man-scw:98230.
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Chen, Jian. "ULTRA LOW POWER READ-OUT INTEGRATED CIRCUIT DESIGN." Wright State University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=wright1345480982.
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Pagliarani, Stefano <1978>. "Progetto del circuito di lubrificazione di una trattrice agricola." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2009. http://amsdottorato.unibo.it/2109/1/Pagliarani_Stefano_tesi.pdf.
Повний текст джерелаАнотація:
Today the design of hydraulic and lubrication circuits is becoming more and more important. The aim of this study is to develop a methodology for the design of the lubrication circuit of an agricultural tractor. In this paper the lubrication circuit of a continuously variable transmission is analysed. Several lines of the circuit are considered and in particular the lubrication of gears is discussed. The worst possible working condition which corresponds to the highest power dissipation for each part of the transmission is determined. The model of the lubrication circuit is developed with two different software simulations (Automation Studio & Amesim). In order to check the reliability of the simulation models and to characterise the lubrication circuit, experimental tests are performed. The comparison between the values of pressure drops obtained by the models and by the experimental test, demonstrates that it is possible to use these programs for the set up of a simple model of the lubrication circuit. The calculation of oil flows necessary for a force-fed lubrication of the gears, the simulation of the circuit by commercial software, and the validation of the circuit design allow to set up a preliminary equilibrium among the pipes and a proper flow rate distribution. Optimising the circuit design in the initial phase of the project is very important. The experimental adjustment of the circuit, which is often difficult, can be simplified; time and cost production can be reduced.
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Pagliarani, Stefano <1978>. "Progetto del circuito di lubrificazione di una trattrice agricola." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2009. http://amsdottorato.unibo.it/2109/.
Повний текст джерелаАнотація:
Today the design of hydraulic and lubrication circuits is becoming more and more important. The aim of this study is to develop a methodology for the design of the lubrication circuit of an agricultural tractor. In this paper the lubrication circuit of a continuously variable transmission is analysed. Several lines of the circuit are considered and in particular the lubrication of gears is discussed. The worst possible working condition which corresponds to the highest power dissipation for each part of the transmission is determined. The model of the lubrication circuit is developed with two different software simulations (Automation Studio & Amesim). In order to check the reliability of the simulation models and to characterise the lubrication circuit, experimental tests are performed. The comparison between the values of pressure drops obtained by the models and by the experimental test, demonstrates that it is possible to use these programs for the set up of a simple model of the lubrication circuit. The calculation of oil flows necessary for a force-fed lubrication of the gears, the simulation of the circuit by commercial software, and the validation of the circuit design allow to set up a preliminary equilibrium among the pipes and a proper flow rate distribution. Optimising the circuit design in the initial phase of the project is very important. The experimental adjustment of the circuit, which is often difficult, can be simplified; time and cost production can be reduced.
8
Kandala, Veera Raghavendra Sai Mallik. "ENERGY EFFICIENT CIRCUIT TECHNIQUES FOR SUCCESSIVE APPROXIMATION REGISTER ADC." OpenSIUC, 2012. https://opensiuc.lib.siu.edu/dissertations/539.
Повний текст джерелаАнотація:
Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in the design of low power electronics. Significant portions of CS-SAR ADC power are consumed by CS capacitor arrays and comparator circuits. This Dissertation presents circuit techniques to reduce the power consumption of both CS capacitor array and the latch comparator during ADC operations. The impacts of the proposed techniques on ADC accuracies are analyzed and circuit techniques are presented to address the accuracy concerns. The dissertation also presents techniques to cope with capacitor mismatches, which becomes more significant with the use of very small unit capacitors in the CS array. These techniques rely on a novel programmable CS capacitor array that allow optimally grouping the unit capacitors. Based on a 0.13um CMOS technology the proposed techniques are verified with extensive circuit simulation. Post layout simulations are done to evaluate the proposed techniques for energy efficient CS capacitor array.
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Li, Yu. "Redressing timing issues for speed-independent circuits in deep sub-micron age." Thesis, University of Newcastle Upon Tyne, 2012. http://hdl.handle.net/10443/1793.
Повний текст джерелаАнотація:
With continued advancement in semiconductor manufacturing tech- nologies, process variations become more and more severe. These variations not only impair circuit performance but may also cause po- tential hazards in integrated circuits (IC). Asynchronous IC design, which does not rely on the use of an explicit clock, is more robust to process variations compared to synchronous design and is suggested to be a promising design approach in deep-submicron age, especially for low-power or harsh environment applications. However, the correctness of asynchronous circuits is also becoming challenged by the shrinking technology. The increased wire delays compared to gate delays and threshold variations could bring glitches into the circuit. This work proposes a method to generate a set of su cient timing constraints for a given speed-independent circuit to work correctly when the isochronic fork timing assumption is lifted into a weaker timing assumption. The complexity of the entire process is polyno- mial to the number of gates. The generated timing constraints are relative orderings between the transition events at the input of each gate and the circuit is guaranteed to work correctly by ful lling these constraints under the timing assumption. The benchmarks show that both the number of total constraints and the constraints that are only needed to eliminate strong adversary paths are reduced by around 40% compared to those suggested in the current literature, thus claiming the weakest formally proved condi- tions.
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Malloug, Hani. "Conception de générateurs sinusoïdaux embarqués pour l'auto-test des circuits mixtes." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT069/document.
Повний текст джерелаАнотація:
Développer un générateur de signal analogique efficace est un élément clés pour les BIST des circuits analogiques et mixtes afin de produire le stimulus de test approprié, et remplacer les générateurs de signaux externes couteux dans les protocoles de standard de test fonctionnel analogique et mixte. Dans cette optique, nous présentons dans cette thèse des stratégies différentes de génération de signal sinusoïdal, basées sur les techniques d’annulation d’harmonique, pour le design d’un synthétiseur embarqué de signal sinusoïdal à haute fréquence. Les générateurs proposés utilisent des circuits numériques pour produire un ensemble de signaux carrés déphasés. Ces signaux carrés sont pondérés et combinés en appliquant différentes stratégies d’annulation d’harmonique dans un convertisseur numérique-analogique simplifié. Le générateur sélectionné permet d’annuler toutes les harmoniques en dessous de la 11ème. De plus, une simple stratégie de calibration a été conçue pour compenser l’effet de mismatch et de la variation de process de fabrication sur l’efficacité de la technique d’annulation d’harmonique. La simplicité du circuit rend cette approche adaptable pour le BIST des circuits intégrés analogique et mixte. Les modèles comportementaux, les simulations électriques d’un design en 28nm FDSOI et les résultats expérimentaux sont fournis pour valider la fonctionnalité du générateur proposé. Les résultats obtenus montrent des performances du circuit calibré autour de 52dB de SFDR pour un signal généré à 166MHzOne of the main key points to enable mixed-signal BIST solutions is the development of efficient on-chip analog signal generators that can provide appropriate test stimuli and replace costly external signal generators in standard analog and mixed-signal functional test protocols. In this line, we present in this thesis different sinewave generation strategies based on harmonic cancellation techniques to design a high-frequency on-chip sinusoidal synthetize. The proposed generators employ digital hardware to provide a set of phase-shifted digital square-wave signals. These square-wave signals are scaled and combined using different harmonic cancellation strategies in a simplified current-steering DAC. The selected generator allows the cancellation of all harmonic components up to the eleventh. Additionally, a simple calibration strategy has been devised to compensate the impact of process variations and mismatch on the effectiveness of the harmonic cancellation. The simplicity of the circuitry makes this approach suitable for mixed-signal BIST applications. Electrical simulations of a 28nm FDSOI design and experimental results are provided to validate the functionality of the proposed signal generator. Obtained results show a calibrated performance around 52dB of SFDR for a generated sinusoidal signal at 166 MHz
11
Zhang, Ling. "System and circuit design techniques for WLAN-enabled multi-standard receiver." Columbus, Ohio : Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1131432639.
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12
Brenneman, Cody R. "Circuit Design for Realization of a 16 bit 1MS/s Successive Approximation Register Analog-to-Digital Converter." Digital WPI, 2010. https://digitalcommons.wpi.edu/etd-theses/423.
Повний текст джерелаАнотація:
As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.
13
Matyáš, Jiří. "Využití přibližné ekvivalence při návrhu přibližných obvodů." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-363841.
Повний текст джерелаАнотація:
This thesis is concerned with the utilization of formal verification techniques in the design of the functional approximations of combinational circuits. We thoroughly study the existing formal approaches for the approximate equivalence checking and their utilization in the approximate circuit development. We present a new method that integrates the formal techniques into the Cartesian Genetic Programming. The key idea of our approach is to employ a new search strategy that drives the evolution towards promptly verifiable candidate solutions. The proposed method was implemented within ABC synthesis tool. Various parameters of the search strategy were examined and the algorithm's performance was evaluated on the functional approximations of multipliers and adders with operand widths up to 32 and 128 bits respectively. Achieved results show an unprecedented scalability of our approach.
14
Regis, Guillaume. "Conception de circuits analogique-numérique pour le conditionnement de micro-capteurs embarqués." Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00923134.
Повний текст джерелаАнотація:
Le domaine de l'instrumentation des capteurs est en constante évolution. Ce travail propose la conception des éléments clefs qui constituent les chaines d'instrumentations de capteurs d'aujourd'hui au travers de 3 applications concrètes. La première application est la mesure de vitesse et de position, par exemple dans un roulement. Nous présentons la conception et la réalisation d'un circuit analogique pour le conditionnement d'un capteur de type magnétorésistif. Ce capteur mesure le champ magnétique généré par les pôles magnétiques d'une roue codeuse. Le circuit est optimisé en bruit, en consommation et travaille sur une bande passante de plusieurs kHz. Pour compenser la dispersion des capteurs, le circuit permet des réglages d'offset et une calibration de gains. Il contient également une mémoire de type OTP (One Time Programmable Memory) qui sauvegarde les réglages associés au capteur. La deuxième application est la mesure de signaux de type EcoG afin d'interfacer le cerveau humain. Nous décrivons la conception et la réalisation d'un convertisseur Analogique/Numérique de type SAR. Il possède un convertisseur numérique analogique capacitif avec une capacité d'atténuation afin de réduire le nombre total de condensateur et ainsi la consommation. Le comparateur possède une entrée rail-to-rail et un système de préamplification avec auto zéro pour diminuer l'offset. Sa consommation est de 86µW pour une vitesse de 24Ks/S et 12bits de résolution. Enfin la troisième application est la mesure de pression stationnaire sur la voilure des avions afin d'en connaître les contraintes. Nous décrivons l'étude architecturale d'un convertisseur sigma-delta permettant d'atteindre une grande résolution pour des signaux de faible fréquence. Il sera de type incrémentale et répondra à des applications de type instrumentation de capteur. Sa résolution est de 16bits ENOB pour une fréquence maximale d'entrée de 100Hz et minimale de sortie d'1Ks/S. Le mode incrémental permettra d'obtenir une sortie en réponse à une requête de manière asynchrone. Une modélisation de chaque élément du système complet convertisseur plus capteur a été effectuée sous Matlab. L'étude de la partie filtrage numérique du convertisseur et l'optimisation de son implémentation numérique sont présentées. Cette étude architecturale complète aboutit au dimensionnement de chaque élément pour répondre au cahier des charges de l'application .
15
Yu, Xinyu. "High-temperature Bulk CMOS Integrated Circuits for Data Acquisition." Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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16
Carr, Richard D. "Analog preprocessing in a SNS 2 [mu] low-noise CMOS folding ADC." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1994. http://handle.dtic.mil/100.2/ADA293356.
Повний текст джерелаАнотація:
Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1994."December 1994." Thesis advisor(s): Phillip E. Pace, Douglas J. Fouts. Bibliography: p. 103. Also available online.
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Hedayati, Raheleh. "High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology." Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
Повний текст джерелаАнотація:
Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.QC 20170905
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Zhang, Chenglong. "LOW-POWER LOW-VOLTAGE ANALOG CIRCUIT TECHNIQUES FOR WIRELESS SENSORS." OpenSIUC, 2014. https://opensiuc.lib.siu.edu/dissertations/982.
Повний текст джерелаАнотація:
This research investigates lower-power lower-voltage analog circuit techniques suitable for wireless sensor applications. Wireless sensors have been used in a wide range of applications and will become ubiquitous with the revolution of internet of things (IoT). Due to the demand of low cost, miniature desirable size and long operating cycle, passive wireless sensors which don't require battery are more preferred. Such sensors harvest energy from energy sources in the environment such as radio frequency (RF) waves, vibration, thermal sources, etc. As a result, the obtained energy is very limited. This creates strong demand for low power, lower voltage circuits. The RF and analog circuits in the wireless sensor usually consume most of the power. This motivates the research presented in the dissertation. Specially, the research focuses on the design of a low power high efficiency regulator, low power Resistance to Digital Converter (RDC), low power Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with parasitic error reduction and a low power low voltage Low Dropout (LDO) regulator. This dissertation includes a low power analog circuit design for the RFID wireless sensor which consists of the energy harvest circuits (an optimized rectifier and a regulator with high current efficiency) and a sensor measurement circuit (RDC), a single end sampling SAR ADC with no error induced by the parasitic capacitance and a digital loop LDO whose line and load variation response is improved. These techniques will boost the design of the wireless sensor and they can also be used in other similar low power design.
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Rarbi, Fatah-Ellah. "Conception d’un convertisseur analogique numérique pipeline de grande dynamique et de faible consommation pour le codage des signaux de détecteurs à forte granularité." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0128.
Повний текст джерелаАнотація:
L’objectif de cette thèse est la conception de convertisseur analogique-numérique (CAN) de type pipeline pour le codage des signaux de détecteurs à forte granularité. Au cours de cette thèse, nous avons développé un modèle pour une étude approfondie des différentes sources d’erreurs et leurs conséquences sur les caractéristiques du convertisseur pipeline 12 bits à 25 MHz. Nous avons également finalisé un prototype aux limites de la technologie choisie par la collaboration CALICE dans le cadre du projet ILC. Une nouvelle architecture de CAN pipeline avec un premier étage MDAC multi-bits incluant une structure DEM a été conçue pour alles au-delà des limites de la technologie. Enfin, en parallèle avec les travaux de conception, un effort a été consacré au développement de programmes de test pour la caractérisation des différents prototypes de convertisseur A/N. Nous expliquons les résultats de tests de trois prototypes de CAN pipeline 12 bits réalisés au cours de ces trois années de thèse. Une comparaison est faite par rapport à d’autres études en cours pour le calorimètre électromagnétique d’ILDThe objective of this thesis is the design of a low power and high dynamic pipeline ADC for high granularity detector read-out. In this thesis, we developed a model for further study of different sources of errors and their consequences on the characteristics of a 12-bit pipeline converter. We also completed an ADC prototype in the limit of technology selected by the CALICE collaboration within the ILC project. New pipeline ADC architecture with a multi-bit MDAC first stage structure including a DEM has been designed to go beyong the limits of technology. Finally, in parallel with the design work, an effort has been devoted to developing test programs for the characterization of different prototypes of A/D converters. We explain the results of testing three prototype 12-bit pipeline ADC achieved during these three years of thesis. A comparison is made with respect to other ongoing studies for the electromagnetic calorimeter of ILD
20
Ravert, Russell D. (Russell Douglas). "Hospitalized School-Age Children: Psychosocial Issues and Use of a Live, Closed-Circuit Television Program." Thesis, University of North Texas, 1993. https://digital.library.unt.edu/ark:/67531/metadc500433/.
Повний текст джерелаАнотація:
This descriptive study utilized semi-structured interviews and observations to examine the experiences of hospitalized school-age children, and explore the potential of a live, closed-circuit television program as a psychosocial intervention. Among findings, Phase I data from 16 subjects indicates a) concern with painful medical procedures, particularly intraveneous (IV) injections, b) a desire for more information, especially concerning medical equipment, c) a variety of responses to social issues among subjects, d) the importance of activities, and e) the central role of the hospital playroom. Phase II data indicates that live, closed-circuit television can provide ambulatory and room-bound children opportunities for making choices, social interaction, participation, and information on their environment. Conclusions and implications are included.
21
Webster, Christopher W. R. "The policy process and governance in the information age : the case of closed circuit television." Thesis, Glasgow Caledonian University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.404665.
Повний текст джерелаАнотація:
This thesis seeks to account for and understand the reasons for the rapid diffusion of Closed Circuit Television (CCTV) surveillance systems in public places across the UK. This is achieved by examining the policy processes and governance structures associated with the diffusion of CCTV systems in local authority settings. An underlying theme in the thesis is that because CCTV is a uniquely powerful technology, its introduction and subsequent diffusion, must be understood in its political and policy environment. To address this concern the thesis develops a framework of understanding based on different perspectives of the policy process, where each perspective is based on the evolution of a core idea or concept. Each of the dominant perspectives identified, offer a different way of `seeing' or comprehending the policy process, and consequently, a different way of explaining the diffusion of CCTV. This is significant as it shows that CCTV must be understood as a policy and a technological phenomenon, and that the processes that explain policy development and technological diffusion are closely intertwined. A key objective of the thesis has been to design a scientific methodology in which to embed the development of the theoretical framework and the empirical research process. In doing so the thesis developed a coherent and comprehensive way of understanding contemporary information age policy processes and the diffusion of CCTV. The main empirical elements of the research were a national survey of local authorities and three detailed local authority case studies. These established that local authorities had installed CCTV into a wide range of public places and that diffusion had involved a variety of strategic, deliberative, consultative and evaluative processes. For local authorities, CCTV represents both a radical shift in policy and a highly institutionalised response to perceived problems in society.
22
Dufor, Tom. "Low intensity rTMS to the cerebellum : age dependent effects and mechanisms underlying neural circuit plasticity." Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066270/document.
Повний текст джерелаАнотація:
Les mécanismes de neuroplasticité sont essentiels pour la mise en place et le renforcement des circuits neuronaux lors de périodes critiques du développement, et permettent au cerveau de s'adapter au cours des différentes étapes de la vie. Ces mécanismes varient avec l'âge, sont généralement plus difficile à activer chez l'adulte, et diminuent dans le cerveau âgé. La stimulation magnétique transcrânienne répétée (rTMS) est actuellement utilisée pour moduler l'excitabilité corticale et est décrite comme prometteuse dans le traitement de certains troubles neurologiques. La rTMS de faible intensité (LI-rTMS), ne déclenchant pas directement de potentiels d'action dans les neurones stimulés, a aussi montré des effets thérapeutiques, il est donc important de comprendre les effets biologiques de ces champs magnétiques d'intensités similaires à celles présentes dans les régions adjacentes à la région ciblée par la rTMS de haute intensité. Nous avons utilisé une stimulation magnétique focale de faible intensité (10 mT), ciblant le cervelet ainsi que la voie olivocérébelleuse chez la souris, afin d'aborder certaines de ces questions. Le cervelet est un modèle pertinent, en effet son développement, sa structure, son vieillissement et ses fonctions sont bien décrits, facilitant la détection d'éventuelles modifications dans cette région. Nous avons étudié les effets de LI-rTMS, in vivo ou in vitro, sur la morphologie neuronale, le comportement, et la plasticité post-lésionnelle. Dans une première étude nous avons montré que la LI-rTMS in vivo modifie les épines et la morphologie dendritique des cellules de Purkinje, ces modifications sont associées à une amélioration de la mémoireNeuroplasticity is essential for the establishment and strengthening of neural circuits during the critical period of development, and are required for the brain to adapt to its environment. The mechanisms of plasticity vary throughout life, are generally more difficult to induce in the adult brain, and decrease with advancing age. Repetitive transcranial magnetic stimulation (rTMS) is commonly used to modulate cortical excitability and shows promise in the treatment of some neurological disorders. Low intensity magnetic stimulation (LI-rTMS), which does not directly elicit action potentials in the stimulated neurons, have also shown some therapeutic effects, and it is important to determine the biological mechanisms underlying the effects of these low intensity magnetic fields, such as would occur in the regions surrounding the central high-intensity focus of rTMS. We have used a focal low-intensity magnetic stimulation (10mT) to address some of these issues in the mouse cerebellum and olivocerebellar path. The cerebellum model is particularly useful as its development, structure, ageing and function are well described which allows us to easily detect eventual modifications. We assessed effects of in vivo or in vitro LI-rTMS on neuronal morphology, behavior, and post-lesion plasticity. We first showed that LI-rTMS treatment in vivo alters dendritic spines and dendritic morphology, in association with improved spatial memory. These effects were age dependent. To optimize stimulation parameters in order to induce post-lesion reinnervation we used our in vitro model of post-lesion repair to systematically investigate the effects of different LI-rTMS stimulation patterns and frequencies. We showed that the pattern of stimulation is critical for allowing repair, rather than the total number of stimulation pulses. Finally, we looked for potential underlying mechanisms participating in the effects of the LI-rTMS, using mouse mutants in vivo or in vitro. We found that the cryptochromes, which have magnetoreceptor properties, must be present for the response to magnetic stimulation to be transduced into biological effects. The ensemble of our results indicate that the effects of LI-rTMS depend upon the presence of magnetoreceptors, the stimulation protocol, and the age of the animal suggesting that future therapeutic strategies must be adapted to the neuronal context in each individual person
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Koyada, Suresh. "IMPLEMENTATION OF A 10-BIT A-SAR ADC CIRCUIT BASED ON VOLTAGE TO TIME CONVERSION." OpenSIUC, 2016. https://opensiuc.lib.siu.edu/theses/1879.
Повний текст джерелаАнотація:
SURESH KOYADA, for the Master of Science degree in Electrical and Computer Engineering, presented on November 17th 2015, at Southern Illinois University Carbondale. TITLE: IMPLEMENTATION OF A 10-BIT A-SAR ADC CIRCUIT BASED ON VOLTAGE TO TIME CONVERSION MAJOR PROFESSOR: Dr. Haibo Wang Comparators are widely used in analog to digital converters. However, the scaling of CMOS technologies makes the design of low power voltage comparators difficult. In order to overcome this problem time-based comparators are introduced which are suitable for nanometer CMOS technology and low supply voltages. This thesis presents the transistor level implementation of a 10-bit time-based accelerated SAR ADC with a supply voltage of 0.5 V. The design increases the conversion speed compared to conventional SAR ADC by updating the upper bound and lower bound of the search space more aggressively. Various design issues, including optimal switch design, glitch minimization at the charge scaling capacitor array output are discussed. This design achieves a SNDR of 58.78dB at a sampling rate of 90.9kS/s and ENOB (effective number of bits) of 9.47 bits with a power consumption of 280nW.
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Liu, Shaolong. "SAR ADCs Design and Calibration in Nano-scaled Technologies." Research Showcase @ CMU, 2017. http://repository.cmu.edu/dissertations/1073.
Повний текст джерелаАнотація:
The rapid progress of scaling and integration of modern complimentary metal oxide semiconductor (CMOS) technology motivates the replacement of traditional analog signal processing by digital alternatives. Thus, analog-to-digital converters (ADCs), as the interfaces between the analog world and the digital one, are driven to enhance their performance in terms of speed, resolution and power efficiency. However, in the presence of imperfections of device mismatch, thermal noise and reduced voltage headroom, efficient ADC design demands new strategies for design, calibration and optimization. Among various ADC architectures, successive-approximation-register (SAR) ADCs have received renewed interest from the design community due to their low hardware complexity and scaling-friendly property. However, the conventional SAR architecture has many limitations for high-speed, high-resolution applications. Many modified SAR architectures and hybrid SAR architectures have been reported to break the inherent constraints in the conventional SAR architecture. Loop-unrolled (LU) SAR ADCs have been recognized as a promising architecture for high-speed applications. However, mismatched comparator offsets introduce input-level dependent errors to the conversion result, which deteriorates the linearity and limits the resolution and the resolution of most reported SAR ADCs of this kind are limited to 6 bits. Also, for high-resolution SAR ADCs, the comparator noise specification is very stringent, which imposes a limitation on ADC speed and power-efficiency. Lastly, capacitor mismatch is an important limiting factor for SAR ADC linearity, and generally requires dedicated calibration to achieve efficient designs in terms of power and area. In this work, we investigate the impacts of offset mismatch, comparator noise and capacitor mismatch on high-speed SAR ADCs. An analytical model is proposed to estimate the resolution and predict the yield of LU-SAR ADCs with presence of comparator offset mismatch. A background calibration technique is proposed for resolving the comparator mismatch issue. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7-dB to 42.9-dB. The ADC consumes 640 μW from a 1.2 V supply with a Figure-of-Merit (FoM) of 37.5-fJ/conv-step. Moreover, the bit-wise impact of comparator noise is studied for LU-SAR ADCs. Lastly, an extended statistical element selection (SES) calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. Based on these techniques, a high-resolution, asynchronous SAR architecture employing multiple comparators with different speed and noise specifications to optimize speed and power efficiency. A 12-bit prototype ADC is fabricated in a 1P9M 65nm CMOS technology, and fits into an active area of 500 μm × 200 μm. At 125 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 64.4 dB and a spurious-free-dynamic-range (SFDR) of 75.1 dB at the Nyquist input frequency while consuming 1.7 mW from a 1.2 V supply. The resultant figure-of-merit (FoM) is 10.3 fJ/conv-step.
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RAVIOLA, ERICA. "Novel Solutions to Mitigate the Switching Noise in Power Circuit Applications." Doctoral thesis, Politecnico di Torino, 2021. http://hdl.handle.net/11583/2932743.
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Gao, Wu. "Design of a monolithic front-end readout chip with a high-precision TDC and a time-based ADC in CMOS technology for PET imaging." Strasbourg, 2011. http://www.theses.fr/2011STRA6002.
Повний текст джерелаАнотація:
La technique de tomographie à émission de positrons (TEP) se présente comme une imagerie non invasive moléculaire mesurant la biodistribution in vivo d'agents etiquettes pour l'imagerie avec des radioisotopes. Le principe se base sur la détection des radiations gamma est la désintégration de positrons émis par le radiotraceur. Cette thèse porte sur la conception d'un ASIC de lecture dédié au photodétecteur multi-canaux (MCP, Photonis Corp. ) munis de cristaux LYSO. Dans cette étude, les cristaux sont orientés dans la direction axiale mesurés des deux côtés par des canaux individuels de photo détecteurs permettant d'obtenir une résolution spatiale et une efficacité de détection indépendantes les unes des autres. Depuis 2007, trois prototypes ont été conçus et fabriqués en technologies CMOS 0,35 m. Il s'agit d'un circuit analogique "front-end" de traitement du signal, d'un CTN basé sur des techniques de compteur et de matrice des DLLs, et enn d'un CAN multi-canaux basé sur le temps à haute résolution. Pour les futures conceptions, l'intégration des circuits de lecture en mode courant et de convertisseur de données basé sur le temps sera effectuée en fonction des applications spécifiques. Parce que la technologie CMOS a développé à l'ordre de nanomètres, les considérations de conception pour les dés en raison de l'échelle de la technologie seront prises en comptePositron Emission Tomography (PET) is a noninvasive molecular imaging that measures in vivo biodistribution of imaging agents labeled with positron-emitting radionuclides. The physical principle is based on the detection of gamma radiations resulting from the disintegration of positrons emitted by the radiotracer. This thesis focuses on the design of a full-custom front-end readout ASIC dedicated to the Photonics Corp. Multi-channel plate photodetector (MCP) with LYSO crystals. In this study, the crystals are oriented in the axial direction and read out on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both the energy quantity and the time information should be measured. Three prototype chips are designed in AMS 0. 35 μm CMOS technology. They include front-end analog signal processing circuits, a high-precision multi-channel time-to-digital converter, and a high-resolution multi-channel time-based ADC. For the future developments, the performance evaluation of a monolithic front-end readout ASIC including front-end analog processing circuits, multi-channel TDC circuits and proposed time-based ADC circuits will be carried out. Moreover, since CMOS technology scaling has moved the process node to nanometers, design considerations for the challenges due to technology scaling will be taken into account
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Puech, Gabriel. "Conception d'un ADC de résolution 8 bits basse consommation et 2 GHz de fréquence d'échantillonnage en technologie CMOS 180 nm." Thesis, Université Clermont Auvergne (2017-2020), 2017. http://www.theses.fr/2017CLFAC094/document.
Повний текст джерелаАнотація:
Après un rappel du contexte dans lequel ce travail de recherche a été conduit, le 1er chapitre présente les caractéristiques communes aux convertisseurs analogiques numériques (ADC) avec leurs figures de mérites. Un état de l’art exhaustif sur les ADC réalisés et plus particulièrement avec le nœud technologique CMOS 1 180 nm y est présenté. Ce travail préliminaire permet de donner un aperçu du défi relevé. Les architectures multi-étapes à échantillonnage analogique ont été éliminées de l’étude du fait des limitations de la technologie pour les contraintes de performances de l’ADC. Le chapitre 2 présente plus en détail les différentes implémentations possibles d’une famille d’ADC à échantillonnage numérique, les flash. Le portage de l’architecture TIQ est détaillé dans ce chapitre. Le chapitre 3 détaille l’étude et le portage en CMOS 180 nm des ADC à échantillonnage numérique à repliement de signal. Cette première partie conclut par le choix de l’architecture flash. La conception des briques de bases de l’ADC flash est détaillée dans les chapitres constituant la partie II du document. Le chapitre 4 est dédié à l’étude et au portage en CMOS 180 nm des étages de comparateurs latchés responsables de l’échantillonnage à 2 GHz de l’ADC flash. La non linéarité ramenée en entrée de l’architecture retenue ayant défini les contraintes sur l’étage de pré-amplification, celui ci est présenté dans le chapitre 5. Le chapitre 5, présente les différentes charges actives étudiées pour l’étage de pré-amplification. Le passage en différentiel passif avec le comparateur full différentiel et l’architecture retenue y sont détaillés. La technique du QV et son portage sur l’architecture de préamplificateur retenu sont présentés. Le décodeur thermométrique 2 binaire est présenté dans le chapitre 6. Deux implémentations de cette logique de décodage sont étudiées et portées. L’une est réalisée à partir d’un code de description matériel (VHDL) et la synthèse de cellules numériques en logique CMOS pull-up pull-down 3 . L’autre est réalisé à partir de multiplexeurs 1 bit et des flip flop à verrou en logique Pass gates complémentaire. Le chapitre 7 présente les limitations et l’implémentation de l’interpolation avec l’emploi des pré-amplificateurs et du comparateur latché retenus. L’étude de l’insertion de paires de suiveurs en drain commun, nécessaire à la polarisation des étages de pré-amplification y est présentée. Enfin, les analyses de tirage de Monte Carlo en mismatch 4 des résistances comme échelle de références sont comparées pour différents dimensionnements et topologies. Le synoptique global de l’ADC est présenté avec les cellules et techniques retenues. L’approche bottom-up incontournable pour la conception de circuits analogiques ou full custom présentée dans cette deuxième partie conclut sur le choix de concevoir un ASIC de preuve de concept. Ce dernier contient ainsi les briques de bases ayant une valeur ajoutée et potentiellement critiques pour la conversion de signaux. L’approche Top-down pour la conception est ainsi détaillée dans la 3e partie en partant du synoptique global de l’ASIC de preuve de concept envoyé en fonderie de circuit multi projet BuBlC1. contenant les cellules critiques à tester. La conception front-end de l’ASIC BuBlC1 avec notamment l’arbre d’horloge et les pads d’entrées sorties est présentée dans le chapitre 8. La phase de back-end avec les layouts des cellules retenues dans la partie II ainsi que leur intégration dans des ensembles (clusters) est présentée dans le chapitre 9 avec le padring et l’intégration finale des macro-ensembles (Cores analogiques et numériques)After a a brief recall of the context this research work have been carried, the 1st chapter present the common analog to digital converters (ADC) characteristics with their figures of merit (FoM). A relevant state of the art on realized ADC architectures is presented. A particular emphasis has been done on 180 nm CMOS process node. This preliminary work gives a pertinent overview of the faced challenge. Multi step analog sampling architectures have been avoided from the study because of the transistors limited frequency performances. Chapter 2 presents the different implementations of the Flash digital sampling ADC family architecture. The TIQ architecture embedding in the 180 nm CMOS process are detailed in this chapter. Chapter 3 details the study and the design of an other digital sampling ADC family architecture on 180 nm CMOS process i.e. the signal folding architecture. This 1st part of the document conclude with the choice of the Flash ADC architecture. The building bloc design for this ADC are detailed in the following chapters constituting the part II. Chapter 4 is dedicated to the study and the design on 180 nm CMOS process of the latch comparator responsible of the 2 GHz sampling constraint of the overall ADC. As the retained comparator architecture input refereed non linearity defined the gain constraints of the preamplifier stage, the preamplifier is presented in the next chapter. Chapter 5 present the different characteristics and techniques of the quantifier stage. The comparator preamplifier stage with its different actives loads, its passive full differential transposition and the retained architecture are detailed. The QV technique and its embedding in the retained preamplifier architecture are presented. The thermometric 1 to binary encoder tree is presented in chapter 6. Two implementations of this encoding are studied and design on the Front-End (FE) level. The 1st one is a pipelined Wallace tree realized with a register transfer level (RTL) code on VHDL hardware description language. The synthesis flow on CMOS pull-up pull-down 2 combinatorial logic and rising edge flip flops are used for this architecture. The other architecture is designed using 1 bits multiplexers combinatorial pipelined with pass gated D latches with a full custom schematic implementation. Chapter 7 presents the limitations and the embedding of the interpolation with the retained preamplifier and comparator latch. The study of common drain source follower (CDSF) pairs insertion, mandatory for the biasing of the preamplifier input stage to reach the 8 bits resolution is studied with details. Finally, Monte Carlo sampling mismatch 3 analysis on the resistor references are studied by comparing different topologies and sizing. The overall ADC synoptic is presented with the retained cells and techniques. The bottom-up design approach, mandatory for analog and full-custom design, exposed in this 2nd part conclude on the choice to design a proof of concept ASIC (BuBlC1) including all the critical piece of circuits of the overall ADC with added value and potentially critical for signal conversion. The top-down approach for this ASIC design is detailed in the IIIrd part with the overall ASIC synoptic of the BuBlC1 ASIC sent to multi project wafer (MPW) foundry run integrating all the critical cells.The FE design of this ASIC with its clock tree and its input/output PAD are presented in chapter 8. The Back-End design with the retained cells layout in part II with the cells integration in clusters are presented in chapter 9 with the pad-ring and final integration in digital and analog macro-cells cores
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Levski, Dimitrov Deyan. "A Cyclic Analog to Digital Converter for CMOS image sensors." Thesis, Linköpings universitet, Elektroniksystem, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-103193.
Повний текст джерелаАнотація:
The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.
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Galluzzo, Junior Mario. "O video como processo de interação entre realizador e comunidade : uma experiencia no ABC paulista." [s.n.], 1996. http://repositorio.unicamp.br/jspui/handle/REPOSIP/284193.
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Orientador: Haydee Dourado de Faria CardosoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Artes
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Resumo: O surgimento do realizador no contexto das novas tecnologias nos anos 80 marca uma década de experiências alternativas com o vídeo, fora das TVs broadcast ao tempo que estas se desenvolviam e se sofisticavam tecnologicamente na América Latina. O vídeo como suporte eletrônico, particularmente o vídeo-tape portátil, chega ao Brasil de forma mais marcante por volta de 1978. Os modelos mais acessíveis eram de formato doméstico, como o VHS -Vídeo Home System, que permitia agilidade e fácil portabilidade. Essas experiências alternativas no Brasil polarizaram-se principalmente em tomo de dois grupos produtores: os independentes e os populares. Ambos contestavam a velhà ordem das comunicações. Esse ponto comum entre realizadores independentes e populares é o deflagrador de várias experiências que se materializaram em documentários que atestavam a preocupação social. Os independentes buscaram dar um tratamento mais cultural aos seus trabalhos e os populares um tratamento mais político, porém ambos visavam um espectador que não fosse passivo como aquele habituado ao sistema de rede. A experiência aqui analisada desenvolveu-se na região do ABC paulista num primeiro momento no CEPS - Centro de Estudos Políticos e Sociais, uma entidade civil em Santo André, Organização Não Governamental (ONG), que visava a produção de conhecimento junto a setores da população. No CEPS o vídeo era usado, principalmente, como registro pedagógico. O segundo momento desenvolveu-se numa instituição sindical também em Santo André, no Sindicato dos Trabalhadores Rodoviários, onde o vídeo era usado como registro/infonT1ativo. Paralelamente acontecia uma experimentação com "câmera aberta", gravando-se e exibindo-se simultaneamente a partir de um ônibus adaptado para este tlm, batizado de "Gabriela Eletrônica". O terceiro momento efetivou-se numa instituição pública, Prefeitura de Santo André, onde o vídeo era usado na produção de institucionais, e numa prática que se desenvolveu num carro utilitário. A"Perua Eletrônica", como foi chamada, visava experimentar uma programação de "TV de rua", que servisse de base para a criação de uma emissora de TV na localidade. Além disso, vários serviços de atendimento ao público foram criados pela coordenação de vídeo, ligada ao Departamento de Cultura (TVSA). Nas considerações finais coloca.se que nesta experiência de três momentos distintos entre sí, o vídeo foi tomado como um importante suporte de mediação entre o realizador e a comunidade local e, para isso, a prospecção de sua especificidade foi considerada prioridade. O vídeo foi se tornando mais eficiente, durante o desenrolar da experiência, na medida em que iam sendo consideradas as particularidades deste meio. No processo constatou-se também a incompatibilidade entre a ação com objetivo de instalar uma TV numa região e a etemeridade que cerca experiências de Tvs de rua. Portanto, uma Tv localizada ampliará consideravelmente suas chances de estruturação, se tiver em conta a especificidade do meio, numa investigação permanente do que seja em essência sua programação e como concebê.la a partir da interação com o público
Abstract: The appearance ofthe maker in the context ofnew technologies at the 80's marks a decade of alternative experiences with video, out of TVs Broadcasting while they were developed and technologically sofisticated in Latin America. Video as eletronic support, particulary portable videotape, anives Brasil with more distinctionaround 1978. The most accessible models were the domestic one, like VHS . Video Home System, that allows agility and easy portability. These alternative experiences in Brasil stayed, principally, around two groups of producers: independents and populars. 80th contested the old order of communication. This commom point among independents and populars makers is the deflagater of many expedences that were materialized in documentaries that showed social preocupation. The independents tried to give a more cultural treatment to their works and the populars a more political treatment. However, both pointed a spectator that wasn't passive as that one accostumated with net system. The experience analised here was developed at ABC, a São Paulo section, first on CEPS -Politics and Sociais Study Center, a civil group of Santo André city, ONG - Non Governamental Organization, that had the objective of producing knowledge beside sectors of the population. At CEPS video was principally used like pedagogic register. At a second moment, it was developed ina sindical institution, in Santo André city, at Highway's Workers Sindicate, where video was used as register/infonnative. Besides, there would be an experimentation with "open camera" recording and exhibiting simulltaneously, by a bus that was adapted for this, called "Eletronic Gabriela". The third moment was brollght about at a public institlltion, the City Hall of Santo André, where video was lIsed in institutionals productions and in a way that was developed at an utilitarium car. The "Eletronic Turkey", as it was called, had the objective of testing the schedule of a "Street TV", that was used to base the creation of a local TV Station. In addition, severals Pllblic attending services was created by the video coordination, connected to Culture Department (TVSA). In final considerations it could be said that in three distinct moments video was used as an important intermediate support between the video maker and the local community and, for this, the search of its specificity was considered priority. Video was becoming more efficient while the experience was done, and at the time that was beeing considered the particularities of this enviroment. In the process also was found out the incompability between the action with the objective of establishing a TV in a region, and the ephemerality that is around the "TV StreetS" experiences. Therefore, a local TV will considerably increase its chances of structuring, if it takes into account the specificity of this enviroment in a permanent investigation of what is its sl:hedule in essence, and how to conceive that &omthe interaction with the spectator
Mestrado
Mestre em Multimeios
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Alleaume, Pierre-Franck. "Etude et conception de circuits oscillateurs millimétriques à faible bruit de phase en technologie MMIC AsGa pour application radar anticollision automobile à 77GHz." Limoges, 1999. http://www.theses.fr/1999LIMO0047.
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Ganguli, Ameya Vivekanand. "Cmos Design of an 8-bit 1MS/s Successive Approximation Register ADC." DigitalCommons@CalPoly, 2019. https://digitalcommons.calpoly.edu/theses/2074.
Повний текст джерелаАнотація:
Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance.
This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm
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Deza, Julien. "Etude, Conception et Caractérisation de circuits pour la Conversion Analogique Numérique à très hautes performances en technologie TBH InP 0.7µm." Thesis, Cergy-Pontoise, 2013. http://www.theses.fr/2013CERG0680/document.
Повний текст джерелаАнотація:
Ce travail de thèse concerne les circuits ultra-rapides pour la conversion analogique numérique performante en technologie bipolaire à hétérojonctions sur substrat Indium Phosphore (TBDH/InP). L'étude s'intéresse à la fonction principale qui est l'échantillonnage blocage. Elle a été menée par simulation de l'ensemble des blocs composant cette fonction. En particulier une étude extensive des cœurs des circuits Echantillonneurs/Bloqueurs a été effectuée pour différents paramètres électriques pour aboutir à des valeurs optimales réalisant un compromis entre la bande passante la résolution et la linéarité.Des architectures de circuits Echantillonneurs/Bloqueurs (E/B) avec ou sans l'étage d'amplification à gain variable ont été conçues, optimisées, réalisées et caractérisées et des performances à l'état de l'art ont été obtenues : des circuits E/B de bande passante supérieure à 50 GHz et cadencées à 70 Gs/s ont été réalisés pour les applications de communications optiques et des circuits de bande passante supérieure à 16 GHz cadencés à (2-8) Gs/s ont été réalisés pour la transposition de fréquenceThis thesis concerns the design of high speed circuits in Indium phosphide heterojunction Bipolar technology for High performance analog to digital conversion (ADC).The study focuses on the Track and Hold block (THA) which is the main function of the ADC. The study was conducted by simulating all blocks of the THA circuit. In particular, an extensive study of the THA main block was performed for various electrical parameters to achieve optimal conditions in order to obtain a good tradeoff between resolution bandwidth and linearity. THA architectures circuits with or without Voltage Gain Amplifier stage were designed, optimized and characterized. High THA performances were achieved: THA circuit with a bandwidth greater than 50 GHz at 70 Gs/s were achieved for optical communications and circuits of bandwidth more than16 GHz at (2-8 GS /s) have been realized for down conversion operation
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Jung, Seungwoo. "Optimization of SiGe HBT BiCMOS analog building blocks for operation in extreme environments." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54419.
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The objective of this research is to optimize silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS analog circuit building blocks for operation in extreme environments utilizing design techniques. First, negative feedback effects on single-event transient (SET) in SiGe HBT analog circuits were investigated. In order to study the role of internal and external negative feedback effects on SET in circuits, two different types of current mirrors (a basic common-emitter current mirror and a Wilson current mirror) were fabricated using a SiGe HBT BiCMOS technology and exposed to laser-induced single events. The SET measurements were performed at the U.S. Naval Research Laboratory using a two-photon absorption (TPA) pulsed laser. The measured data showed that negative feedback improved SET response in the analog circuits; the highest peak output transient current was reduced by more than 50%, and the settling time of the output current upon a TPA laser strike was shortened with negative feedback. This proven negative feedback radiation hardening technique was applied later in the high-speed 5-bit flash analog-to-digital converter (ADC) for receiver chains of radar systems to improve SET response of the system.
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Koecher, Matthew R. "Hardware Synthesis of Synchronous Data Flow Models." BYU ScholarsArchive, 2004. https://scholarsarchive.byu.edu/etd/20.
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Synchronous Dataflow (SDF) graphs are a convenient way to represent many signal processing and dataflow operations. Nodes within SDF graphs represent computation while arcs represent dependencies between nodes. Using a graph representation, SDF graphs formally specify a dataflow algorithm without any assumptions on the final implementation. This allows an SDF model to be synthesized into a variety of implementation techniques including both software and hardware. This thesis presents a technique for generating an abstract hardware representation from SDF models. The techniques presented here operate on SDF models defined structurally within the Ptolemy modeling environment. The behavior of the nodes within Ptolemy SDF models is specified in software and can be simple, such as a single arithmetic operation, or arbitrarily complex. This thesis presents a technique for extracting the behavior of a limited class of SDF nodes defined in software and generating a structural description of the SDF model based on primitive arithmetic and logical operations. This synthesized graph can be used for subsequent hardware synthesis transformations.
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COELHO, A. L. S. "Entre o Circus e o Forum: poder, amor e amantes na Ars Amatoria de Ovídio (Séc. I a.C. I d.C)." Universidade Federal do Espírito Santo, 2014. http://repositorio.ufes.br/handle/10/3506.
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Previous issue date: 2014-08-08Nesta dissertação, analisamos as relações de amor e de poder na Urbs de Augusto protagonizadas pelas mulheres representadas pelo poeta Públio Ovídio Naso. Para tanto, tomamos como fonte a obra Ars Amatoria, escrita por esse autor entre os anos I a.C. e I d.C., a qual apresenta conselhos amorosos aos homens e mulheres que viviam na Roma imperial. Nosso estudo teve como recorte temporal a segunda metade do século I a.C. e o primeiro quartel do século seguinte, período em que Augusto fundou o Principado e impôs à sociedade romana um programa de Reforma Moral. Nesse contexto, nosso objetivo geral foi compreender, a partir da Ars Amatoria, as adesões e os confrontos realizados pelo poeta diante das imposições morais do imperador. Dessa forma, analisamos as relações amorosas protagonizadas pelas mulheres representadas pelo poeta, e investigamos como os espaços da Urbs augustana foram concebidos e utilizados por Ovídio no âmbito dessas relações. O referencial teórico empregado nessa pesquisa foi o da História Cultural, pautado nos conceitos de representação, gênero, cidade, corpo e coqueteria. Já a metodologia empregada foi a Análise de Conteúdo. Consideramos, finalmente, que Ovídio concebeu estratégias de escrita para expressar suas concepções de amor na Ars Amatoria, sem necessariamente ser punido pelo imperador. Demonstramos, assim, que o poeta não confrontou, de modo público e explícito, o poder do soberano e seu programa de Reforma Moral, mas propôs, ao mesmo tempo, conselhos que promoviam comportamentos conflitantes com a reformulação dos costumes sociais projetada por Augusto.
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Zegmout, Hanae. "Echantillonneur opto-electronique femto seconde." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT084.
Повний текст джерелаАнотація:
Dans un monde de plus en plus connecté, il devient indispensable de trouver des moyens d’augmenter le débit d’informations qu’il est possible de véhiculer et de traiter. Ce besoin impose aux ingénieurs des contraintes plus serrées en termes de bande passante et de fréquence d’horloge des circuits qu’ils conçoivent.Or, les circuits d’horloge en microélectroniques sont limités par leur performance en termes de stabilité de la période d’horloge, i.e., en termes de « gigue d’horloge » ; cette limitation provient du bruit inhérent au circuit des horloges et rend donc le signal échantillonné inexploitable.Un moyen de se libérer de cette contrainte pourrait être de passer par la photonique intégrée. En effet, les horloges optiques, i.e les lasers pulsés, présentent des performances très intéressantes en termes de stabilité ou de gigue en comparaison avec les horloges en microélectroniques: les gigues des horloges optiques sont cinq fois plus faibles que la plus faible gigue d’horloge électronique citée dans la littérature.L’idée principale de cette thèse est de concevoir un circuit d’échantillonnage qui utilise les pulses du laser comme horloge et qui échantillonne un signal électronique. La brique de base du circuit en question est un photoconducteur en Germanium : une résistance en Germanium dont la résistivité varie selon la puissance du signal optique qu’elle reçoit du laser pulsé. Le photoconducteur dans ce cas précis jour le rôle d’un interrupteur piloté par le laser, et connecte l’entrée RF à la capacité d’échantillonnage. Quand l’interrupteur reçoit un pulse de lumière sa résistance chute et le signal RF peut être copié vers la capacité. Dès que le pulse de lumière s’arrête, le photoconducteur en Germanium retrouve sa résistance initiale et déconnecte ainsi l’entrée RF de la capacité qui contient le signal échantillonné.Cette thèse se propose d’étudier la faisabilité d’un tel circuit et la possibilité d’exploiter la performance des lasers en termes de stabilité de l’horloge dans l’échantillonnage d’un signal électrique.Dans le cadre de la thèse, nous avons essayé d’implémenter le circuit de base présenté auparavant et avons rencontré plusieurs défis. D’abord, les valeurs des résistances Off du photoconducteur n’étaient pas assez élevées pour permettre de déconnecter entièrement le signal RF de la capacité d’échantillonnage. Cela est dû à la présence d’un dopage résiduel lié au procédé de fabrication des photoconducteurs. L’utilisation du Germanium implique également que le passage de l’état On à l’état Off du photoconducteur n’est pas instantané, mais est fonction de la durée de vie des porteurs de charge créés suite à l’exposition aux pulses de lumière (de l’ordre de la nanoseconde).Nous avons contourné ces problèmes en utilisant trois méthodes : une nouvelle géométrie des photoconducteurs en Germanium qui permet de maximiser le rapport Roff/Ron (géométrie brevetée), un contre-dopage pour augmenter la résistivité du matériau et finalement un circuit électronique qui permet de re-échantillonner le signal en utilisant une horloge photonique basée sur les pulses du laser. Nous avons également exploré la possibilité de concevoir des horloges photoniques qui présentent une très faible valeur de gigue et dont la longueur du pulse peut être modifiée de manière indépendante de la longueur du pulse laser utilisé pour les générerAs the world becomes more and more connected, the need for higher data throughput becomes increasingly urgent. This implied more creativity from circuit designers to come up with higher bandwidth circuits and faster pace clocks to drive them.However, the traditional microelectronics clock circuits fail short to fulfill the ever-increasing need for higher sampling frequencies because of their inherent noise. The latter renders the sampled data altogether unusable and therefore hinders the efforts towards higher streams of data.Integrated photonics, the optics alternative to microelectronics, may bring an end to this problem. Indeed, when it comes to pulsed lasers, a not that new technology, the optical pulses clocking features a very low noise compared to its microelectronics counterpart, i.e a jitter that is five folds lower than the best literature microelectronics clock.The main idea of this thesis is to design a sampling circuit that uses the laser pulses as a clock, but samples an electronic signal. This circuit design is mainly based on the use of a Germanium photoconductor, i.e, a Germanium resistor that changes its resistance according to the value of the optical signal it receives. This photoconductor plays then the role of a clocked switch and connects the RF input signal to the hold capacitor. When the switch receives a pulse of light, its resistance drops and the signal can be copied to the capacitor, and once the pulse of light is over, the Germanium photoconductor recovers its first resistance value and the input signal node is disconnected from the capacitor that holds the sampled signal.The aim of this thesis is to study the feasibility of such a design and whether or not it allows taking advantage of the very low jitter value of the laser. Within the thesis, we tried to implement the up said design and stumbled upon many challenges. First, the values of the off switch resistance were not high enough to disconnect the hold capacitor from the input node due to the low resistivity of the used Germanium (residual doping). The Germanium implies also that the switching from one resistance value to another is not instantaneous but rather as long as the photo-generated carriers exist, which lasts for at least a nanosecond. We resolved these problems using three methods: a novel geometry of Germanium photoconductors that allows for high Roff/Ron ratios (patented geometry), a counter-doping to increase the resistivity of the material and finally, a re-sampling circuit driven by a photonic clock based on the laser pulses. We also explored the possibility of making very steep-edged clocks with customizable pulse lengths based on the laser pulses
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Main, Keith Leonard. "Visual rehabilitation and reorganization: case studies of cortical plasticity in patients with age-related macular degeneration." Diss., Georgia Institute of Technology, 2010. http://hdl.handle.net/1853/37098.
Повний текст джерелаАнотація:
The extent to which cortical maps may reorganize in adult humans is a significant and topical debate in visual neuroscience. Though there are conflicting findings, evidence from humans and animals indicates that the topography of the visual cortex may change after retinal deafferentation. Remarkably, this reorganization seems to be possible in adults, whose brains are less amenable to plastic change. If adult visual reorganization is legitimate, an understanding of its causes and consequences could be profound considering the millions suffering from age-related visual disorders.
This dissertation explores whether visual training may yield a reorganization of sensory maps in the adult visual cortex. It describes research in which patients, diagnosed with age-related macular degeneration (AMD), underwent visual rehabilitation therapy. Functional brain scans and behavioral tests were conducted pre and post training. These interventions generated valuable knowledge regarding whether "reorganized" activity is a true rewiring of feed forward cortical processes or an artifact of attentional feedback.
The rehabilitation training produced demonstrable differences in activation patterns along the primary visual cortex (V1), but sparse improvement in the behavioral tests. In contrast, there was significant improvement in fixation tests which assessed oculomotor control. These results suggest that the nature of reorganized activity has more to do with attentional mechanisms than feed forward reorganization. Future investigations could benefit from examining the brain sites that govern visual attention in the frontal and parietal cortices. These areas may have more to do with visual adaptation in AMD patients than V1.
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Khan, Shehryar, and Muhammad Asfandyar Awan. "Study on Zero-Crossing-Based ADCs for Smart Dust Applications." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-73065.
Повний текст джерелаАнотація:
The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions. Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordination amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as itsdesign feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features ofenergy harvesting, regulation and power management present in the smart dustmote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilogto layout models and MATLAB and Simulink models.
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Kim, Tae Hong. "Electromagnetic Band Gap (EBG) synthesis and its application in analog-to-digital converter load boards." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/22712.
Повний текст джерелаАнотація:
With increase in frequency and convergence toward mixed signal systems, supplying stable voltages to integrated circuits and blocking noise coupling in the systems are major problems. Electromagnetic band gap (EBG) structures have been in the limelight for power/ground noise isolation in mixed signal applications due to their capability to suppress unwanted electromagnetic mode transmission in certain frequency bands. The EBG structures have proven effective in isolating the power/ground noise in systems that use a common power supply. However, while the EBG structures have the potential to present many advantages in noise suppression applications, there is no method in the prior art that enables reliable and efficient synthesis of these EBG structures.
Therefore, in this research, a novel EBG synthesis method for mixed signal applications is presented. For one-dimensional periodic structures, three new approaches such as current path approximation method, border to border radius, power loss method have been introduced and combined for synthesis. For two-dimensional EBG structures, a novel EBG synthesis method using genetic algorithm (GA) has been presented. In this method, genetic algorithm (GA) is utilized as a solution-searching technique. Synthesis procedure has been automated by combining GA with multilayer finite-difference method and dispersion diagram analysis method. As a real application for EBG structures, EBG structures have been applied to a GHz ADC load board design for power/ground noise suppression.
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Colom, Mendoza Enric. "Ex Figlinis Tarraconensibus. Sistematización y caracterización de las figlinae amphorales de la costa oriental de la Provincia Hispania Citerior, circuitos de exportación y clasificación tipológica de sus producciones (siglos II a.C.-III d.C.)." Doctoral thesis, Universitat Rovira i Virgili, 2021. http://hdl.handle.net/10803/673170.
Повний текст джерелаАнотація:
El present treball consisteix en la sistematizació de totes les figlinae amphorales de la costa oriental de la Provincia
Hispania Citerior (segles II a.C.-III d.C.) des d’un punt de vista interdisciplinari, analitzant les tres vessants més
importants: descripció i anàlisi de les estructures productores, catalogació de marques epigràfiques i patrons de
dispersió pel Mediterrani occidental i, en darrer lloc, la caracterització tipològica de les seves produccions amforals. Es
tracta, per tant, del primer treball d’aquesta magnitud en els estudis relatius a les àmfores tarraconenses. També, i
gràcies a l’aplicació de noves metodologies basades en les tècniques d’aixecament fotogramètric, així com de
computació i modelat tridimensional, hem pogut crear una base de dades morfològica de les principals produccions
amforals tarraconenses. Això ens ha permès la creació, per primera vegada en la història de la investigació, d’una
taula tipològica, extensa i detallada, dels envasos més comuns (Dressel 2, Dressel 3 i Pascual 1), que recull les
variades tradicions terrisseres presents en les diferents àrees productores que composen la costa oriental de la
Provincia Hispania Citerior en època romana.El presente trabajo consiste en la sistematización de todas las figlinae amphorales de la costa oriental de la Provincia Hispania Citerior (siglos II a.C. – III d.C.) desde un punto de vista interdisciplinar, analizando las tres vertientes más importantes: descripción y análisis de las estructuras productoras, catalogación de marcas epigráficas y patrones de dispersión por el Mediterráneo occidental y, en último lugar, la caracterización tipológica sus producciones anfóricas. Se trata, por tanto, del primer trabajo de esta magnitud en los estudios relativos a las ánforas tarraconenses. También, y gracias a la aplicación de nuevas metodologías basadas en las técnicas de levantamiento fotogramétrico, así como de computación y modelado tridimensional, hemos podido crear una base de datos morfológica de las principales producciones anfóricas tarraconenses. Esto nos ha permitido la creación, por primera vez en la historia de la investigación, de una tabla tipológica, extensa y detallada, de los envases más comunes (Dressel 2, Dressel 3 y Pascual 1), que recoge las variadas tradiciones alfareras presentes en las diferentes áreas productoras que componen la costa oriental de la Provincia Hispania Citerior en época romana.
The present work consists on asystematization of all the figlinae amphorales of the eastern coast of the Provincia Hispania Citerior (2nd BC - 3rd AD) from an interdisciplinary point of view, analyzing the three most important aspects: description and analysis of the producing structures, the catalogue of epigraphic stamps and dispersal patterns in the western Mediterranean and, finally, the typological characterization of its amphora productions. It is, therefore, the first work of this magnitude in studies related to tarraconensis amphorae. Also, and thanks to the application of new methodologies based on photogrammetric survey techniques, as well as computation and three-dimensional modeling, we have been able to create a morphological database of the main tarraconensian amphora productions. This has allowed us to create, for the first time in the history of the research, an extensive and detailed typological table of the most common containers (Dressel 2, Dressel 3 and Pascual 1), which collects the various pottery traditions present in the different producing areas that make up the eastern coast of the Provincia Hispania Citerior in Roman times.
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Balasubramanian, Sidharth. "Low-voltage and low-power libraries for Medical SoCs." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1259776639.
Повний текст джерела
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Forichon, Sylvain. "Les spectateurs du cirque à Rome (du Ier siècle a.C. au VIe siècle p.C.) : passion, émotions et politique." Thesis, Bordeaux 3, 2015. http://www.theses.fr/2015BOR30004.
Повний текст джерелаАнотація:
La passion des Romains pour les jeux du cirque, et surtout pour les courses de chars, apparaît comme un topos dans la littérature ancienne. Si les auteurs anciens ont maintes fois évoqué l’état d’excitation du public, les jugements moraux et les stéréotypes l’emportent sur toute tentative d’analyse et très peu d’amateurs de courses ont laissé de témoignage, comme la première partie de cette thèse le met en évidence. Il nous a donc fallu dépasser ces préjugés afin d’expliquer les raisons d’un tel engouement. La confrontation des données issues des sources textuelles aux résultats de travaux récents en psychologie des émotions et en sociologie du sport nous a permis de démontrer, dans la seconde partie, le lien entre la passion des jeux et les émotions provoquées par ces spectacles. En effet, cette passion se nourrissait largement des émotions intenses éprouvées par les spectateurs, elles-mêmes conséquence d’un phénomène d’hyperstimulation sensorielle auquel ils étaient soumis depuis leur arrivée aux abords du bâtiment jusqu’à la fin des jeux. Cet engouement pour les ludi circenses avait donc des causes intrinsèques aux spectacles. Face à ce constat et à l’intérêt croissant du pouvoir pour les circenses dès la fin de la République, la troisième partie de cette thèse examine la question de l’instrumentalisation de ces jeux à des fins politiques. Si des chefs d’armées, comme Pompée ou Jules César, comprirent tout le bénéfice qu’ils pouvaient en retirer en terme de popularité et si, à partir d’Auguste, les circenses font partie intégrante de la politique impériale, il serait néanmoins erroné de percevoir les spectateurs du cirque comme une foule manipulée par le pouvoir. Ils jouissaient en ce lieu d’une autorité considérable, non seulement sur le déroulement des jeux, mais aussi à l’égard de l’empereur, à tel point que le rapport de force avec ce dernier pouvait même éventuellement s’inverser. Le cirque a été en effet parfois le cadre de manifestations d’hostilité de la foule à l’encontre de l’empereur ou de ses proches et dans la plupart des cas les manifestants ont obtenu gain de cause. La clémence du prince semble donc avoir été l’usage en ce lieu. Cependant, il convient de ne pas réduire les acteurs de ces mouvements de protestation à la plèbe. Ces manifestations étaient vraisemblablement souvent orchestrées et soigneusement préparées à l’avance, or il nous est apparu que seuls des membres de l’ordre sénatorial ou équestre avaient les moyens humains et logistiques d’y parvenirPassion for Roman circus games, and especially for chariot races, appears as a topos in ancient literature. Even if ancient authors frequently evoke the excitement of the audience, this excitement often attracts moral condemnations and stereotypes rather than critical analysis and there are very few testimonies coming from chariot races enthusiasts, as it may be noted in the first part of the thesis. This study aims to overcome these prejudices in order to explain the reasons for such an enthusiasm. In the second part, after confronting data coming from textual sources with what recent works in psychology of emotion and sociology of sport can teach us, we demonstrate the link between passion for the games and the emotions provoked by those spectacles. This passion, indeed, was mainly entertained by the intensity of the emotions, resulting themselves from the sensory overload which the spectators experienced, from the moment they were reaching the circus to the end of the games. This passion may be due to factors intrinsic to the show. Considering this aspect as well as the growing interest of the power for circenses at the end of the Republic, the third part examines the exploitation of the games for political purposes. Even if army leaders, such as Pompey and Caesar, well understood all the benefits they could derive in terms of popularity, and even if the circenses started to be, from Augustus on, an integral part of imperial policy, it would be a mistake to see the spectators simply as a crowd manipulated by political power. It appears that the spectators enjoyed considerable authority over this place, not only in relation to the conduct of the games, but also even in relation to the emperor, insomuch as the power struggle between the emperor and his subjects could sometimes be reversed. On several occasions, indeed, the circus was the scene of the crowd’s hostility against the emperor or his relatives, and in many such cases, the demonstrators were successful. It seems that it was customary for the emperor to show clemency within the circus. However, it is important not to generalise about the participants of protests and not to consider them simply as a plebeian mob. Such protests were in all likelihood often carefully orchestrated and planned in advance; it seems clear that only members of the senatorial or equestrian orders had the human resources and logistical capacity to achieve that
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Frankeser, Sophia. "Monitoring of age-relevant parameters in an integrated inverter system for electrical drives based on SiC-BJTs." Universitätsverlag der Technischen Universität Chemnitz, 2018. https://monarch.qucosa.de/id/qucosa%3A31470.
Повний текст джерелаАнотація:
The Silicon Carbide Bipolar Transistor is a device that is barely brought into real application so far. It features very low conduction losses and a high power density. The application is in some points different and unusual in comparison to the mainstream power semiconductors as IGBTs or MOSFETs. The Silicon Carbide Bipolar Transistor, the SiC-BJT, is a current driven device and the effort in driving is uncommonly high. As an outcome of the present work it can be said that it is more like a shift of requirements from the power semiconductor power unit to the driver stage. With consideration of all system losses, including driving losses, the final unoptimized COSIVU prototype inverter system gained an increase of efficiency of 40-60% in comparison to the IGBT-based reference system dependent on the applied load points.
In terms of reliability and possible failure modes, the SiC-BJT behaves differently from the mainstream devices. One result of the project is that the chips itself are quite robust but the packaging needs some improvements. Thermal impedance spectroscopy is a method for detecting possible deterioration in the cooling path of a device. A method for temperature estimation of the SiC-BJT during on-state will be presented in this work. The electronic hardware for thermal impedance spectroscopy has been developed to do the measurements in a non-laboratory setup in the inverter in real application. Furthermore, the hardware implementation was realized on a very small space for integration into an in-wheel motor inverter system.Der Siliciumkarbid Bipolartransistor ist ein leistungselektronisches Bauelement, was bis heute kaum über Labor- und Forschungsprojekte hinaus anwendungsnah zum Einsatz kam. Er verfügt über sehr geringe Durchlassverluste und eine hohe Leistungsdichte. Seine Verwendung und Anwendung ist in mancher Hinsicht anders und unüblich im Vergleich zu den etablierten leistungselektronischen Bauelementen wie IGBT und MOSFET. Der Siliciumkarbid Bipolartransistor, also der SiC-BJT, ist ein stromgesteuertes Bauteil, weswegen der Aufwand für die Treiber sehr hoch ist. Die praktische Arbeit im Rahmen des Forschungsprojektes „COSIVU“ mit den SiC-BJTs in Verbindung mit dem fertigen integrierten Invertersystem hat unter anderem gezeigt, dass es mehr eine Verschiebung der Anforderungen von der Leistungselektronik hin zu den Treibern für die Leistungselektronik ist. Unter Betrachtung der Verluste des gesamten Systems, einschließlich der Motor-, Treiber- und Steuerverluste, hat das fertige Prototyp-Invertersystem, welches durchaus noch Potential zur Optimierung besaß, eine deutliche Verbesserung des Wirkungsgrades erreicht. Gegenüber dem auf IGBT basierenden Referenz-Invertersystem, hat das COSIVU Invertersystem eine Verbesserung des Wirkungsgrades um 40-60 % erreicht. Eine Erkenntnis aus dem Forschungsprojekt in Bezug auf Zuverlässigkeit und mögliche Fehler und Defekte ist, dass der Chip selbst zwar ziemlich robust ist, aber dass die Gehäuse-, Aufbau- und Verbindungstechnik angepasst und verbessert werden sollte. Thermische Impedanzspektroskopie ist eine Methode um Verschlechterungen im Kühlpfad eines leistungselektronischen Halbleiters zu erkennen, was ein Kriterium für die Alterung des Bauteils ist. Eine Methode zur Bestimmung der Sperrschichttemperatur von SiC-BJTs während des normalen Durchlassbetriebes wird in dieser Arbeit vorgestellt. Die Platine für die thermische Impedanzspektroskopie wurde entwickelt, um die Messung in einem laborfernen Aufbau in einer echten Inverteranwendung durchzuführen. Zudem wurden die Platinenaufbauten auf sehr kleiner Fläche realisiert. Die Integration musste nämlich sehr kompakt gestaltet werden, da es sich um ein „in-wheel“ Motor-Inverter-System handelt, was zum größten Teil innerhalb eines Fahrzeugrades untergebracht ist.
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Stanovský, Peter. "Technika ALPS v kartézském genetickém programování." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2009. http://www.nusl.cz/ntk/nusl-236776.
Повний текст джерелаАнотація:
This work introduces a brief summary of softcomputing and the solutions to NP-hard problems. It especially deals with evolution algorithms and their basic types. The next part involves the study of cartesian genetic programming, which belongs to the field of evolution algorithms, used mainly in the evolution of digital circuits, symbolic regression, etc. A special chapter is devoted to the studies of new technique Age layered population structure, which deals with the problems of premature convergence, which suggests the way of how the population could be divided into subpopulations split up according to the age criteria. Thanks to the maintaining of sufficient diversity, it achieves substantially better solutions in comparison to the classical evolution algorithms. This papier includes the suggestion of two ways of incorporation of the ALPS technique into CGP. In the next part of work there were carried out tests on the classic problems, that would be solved with evolution algorithms. These tests were made with and without using ALPS technique. In the part of work "Experimental results" there was discussed a contribution of using ALPS technique in CGP against the classic CGP.
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McMahon, Joel C. ""Our Good and Faithful Servant": James Moore Wayne and Georgia Unionism." Digital Archive @ GSU, 2010. http://digitalarchive.gsu.edu/history_diss/15.
Повний текст джерелаАнотація:
Since the Civil War, historians have tried to understand why eleven southern states seceded from the Union to form a new nation, the Confederate States of America. What compelled the South to favor disunion over union? While enduring stereotypes perpetuated by the Myth of the Lost Cause cast most southerners of the antebellum era as ardent secessionists, not all southerners favored disunion. In addition, not all states were enthusiastic about the prospects of leaving one Union only to join another. Secession and disunion have helped shape the identity of the imagined South, but many Georgians opposed secession. This dissertation examines the life of U.S. Supreme Court Justice James Moore Wayne (1790-1867), a staunch Unionist from Savannah, Georgia. Wayne remained on the U.S. Supreme Court during the American Civil War, and this study explores why he remained loyal to the Union when his home state joined the Confederacy. Examining the nature of Wayne’s Unionism opens many avenues of inquiry into the nature of Georgia’s attitudes toward union and disunion in the antebellum era. By exploring the political, economic and social dimensions of Georgia Unionism and long opposition to secession, this work will add to the growing list of studies of southern Unionists.
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Fouathia, Ouahab. "Stratégie de maintenance centrée sur la fiabilité dans les réseaux électriques de haute tension." Doctoral thesis, Universite Libre de Bruxelles, 2005. http://hdl.handle.net/2013/ULB-DIPOT:oai:dipot.ulb.ac.be:2013/211003.
Повний текст джерелаАнотація:
Aujourd’hui les réseaux électriques sont exploités dans un marché dérégulé. Les gestionnaires des réseaux électriques sont tenus d’assurer un certain nombre de critères de fiabilité et de continuité du service, tout en minimisant le coût total consacré aux efforts effectués pour maintenir la fiabilité des installations. Il s’agit de trouver une stratégie, qui répond à plusieurs exigences, comme :le coût, les performances, la législation, les exigences du régulateur, etc. Cependant, le processus de prise de décision est subjectif, car chaque participant ramène sa contribution sur base de sa propre expérience. Bien que ce processus permette de trouver la « meilleure » stratégie, cette dernière n’est pas forcément la stratégie « optimale ». Ce compromis technico-économique a sensibilisé les gestionnaires des réseaux électriques à la nécessité d’un recours à des outils d’aide à la décision, qui doivent se baser sur des nouvelles approches quantitatives et une modélisation plus proches de la réalité physique.Cette thèse rentre dans le cadre d’un projet de recherche lancé par ELIA, et dénommé COMPRIMa (Cost-Optimization Models for the Planning of the Renewal, Inspection, and Maintenance of Belgian power system facilities). Ce projet vise à développer une méthodologie qui permet de modéliser une partie du réseau électrique de transport (par les réseaux de Petri stochastiques) et de simuler son comportement dynamique sur un horizon donné (simulation de Monte Carlo). L’évaluation des indices de fiabilité permet de comparer les différents scénarios qui tentent d’améliorer les performances de l’installation. L’approche proposée est basée sur la stratégie RCM (Reliability-Centered Maintenance).
La méthodologie développée dans cette thèse permet une modélisation plus réaliste du réseau qui tient compte, entre autres, des aspects suivants :
- La corrélation quantitative entre le processus de maintenance et le processus de vieillissement des composants (par un modèle d’âge virtuel) ;
- Les dépendances liées à l’aspect multi-composant du système, qui tient compte des modes de défaillance spécifiques des systèmes de protection ;
- L’aspect économique lié à la stratégie de maintenance (inspection, entretien, réparation, remplacement), aux coupures (programmées et forcées) et aux événements à risque (refus disjoncteur, perte d’un client, perte d’un jeu de barres, perte d’une sous-station, etc.).
Doctorat en sciences appliquées
info:eu-repo/semantics/nonPublished
47
Nouman, Ziad. "Užití programovatelných hradlových polí v systémech průmyslové automatizace." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2016. http://www.nusl.cz/ntk/nusl-234615.
Повний текст джерелаАнотація:
Tato disertační práce se zabývá využitím programovatelných hradlových polí (FPGA) v diagnostice měničů, využívajících spínaných IGBT tranzistorů. Je zaměřena na budiče těchto výkonových tranzistorů a jejich struktury. Přechodné jevy veličin, jako jsou IG, VGE, VCE během procesu přepínání (zapnutí, vypnutí), mohou poukazovat na degradaci IGBT. Pro měření a monitorování těchto veličin byla navržena nová architektura budiče IGBT. Rychlé měření a monitorování během přepínacího děje vyžaduje vysokou vzorkovací frekvenci. Proto jsou navrhovány paralelní vysokorychlostní AD převodníky (> 50 MSPS). Práce je zaměřena převážně na návrh zařízení s FPGA včetně hardware a software. Byla navržena nová deska plošných spojů s FPGA, která plní požadované funkce, jako je řízení IGBT pomocí vícenásobných paralelních koncových stupňů, monitorování a diagnostiku, a propojení s řídicí jednotkou měniče.
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Ysasi, Alonso Alejandro. "La obra gráfica de Pedro Quetglas “Xam” (1915-2001): la riqueza de un patrimonio." Doctoral thesis, Universitat de les Illes Balears, 2014. http://hdl.handle.net/10803/284394.
Повний текст джерелаАнотація:
És una investigació, anàlisis, i aproximació a l’obra gràfica de l’artista mallorquí, del segle XX, Pere Quetglas, conegut pel pseudònim de “Xam”. La seva activitat s'ha sistematitzat sobre la base la biografia, tècniques treballades i el seu entorn.
Xam, es va exercitar en la caricatura, el dibuix, el cartell, el gravat xilogràfic, la pintura, els monotips, la serigrafia i en el gravat calcogràfic. Del conjunt de tota la seva producció l’autor se centra en l'obra gràfica produïda a partir de 1944, quan pot datar-se la seva primera xilografia, i la seva defunció, l’any 2001, en el qual realitza la seva última litografia.
El treball s'insereix en un àmbit sense tradició immediata sobre l'obra gràfica a Mallorca, pràcticament desapareguda després de la important impremta Guasp.
S'han pogut documentar més de 400 matrius. Alhora, s'han treballat les estampacions d'aquestes, que ascendeixen a 600 estampes calcogràfiques, xilogràfiques, serigràfiques i litogràfiques.Es una investigación, análisis, y aproximación a la obra gráfica del artista mallorquín, del siglo XX, Pedro Quetglas, conocido por el seudónimo de “Xam”. Su actividad se ha sistematizado en base a la biografía, técnicas trabajadas y a su entorno. Xam, se ejercitó en la caricatura, el dibujo, el cartel, el grabado xilográfico, la pintura, los monotipos, la serigrafía y en el grabado calcográfico. Del conjunto de toda su producción se centra en la obra gráfica producida a partir de 1944, cuando puede datarse su primera xilografía, y su fallecimiento, en 2001, en el cual realiza su última litografía. La tarea se inserta en un ámbito sin tradición inmediata sobre la obra gráfica en Mallorca, prácticamente desaparecida tras la importante imprenta Guasp. Se han podido documentar más de 400 matrices. A su vez, se han trabajado las estampaciones de estas, que ascienden a 600 estampas calcográficas, xilográficas, serigráficas y litográficas.
The thesis is research, analysis and approach to the graphic work of the Majorcan artist of the 20th century, Pedro Quetglas, known by his pseudonym "Xam". Xam worked in several art fields, such as caricature, drawing, designing and painting posters, woodcut, painting, monotype, serigraphy and calcography engraving. From the sum of his work the thesis is centred in the graphic work produced between 1944, when we can date the first xylography, and his death, 2001, when he finished his last lithography. The task was inserted in a field without immediate tradition on the graphic work in Mallorca, which practically went missing after the important Guasp printing house closed down. It has been possible to document more than 400 blocks and, at the same time, the prints of those which add up to 600 prints on chalcography, xylography, serigraphy and lithography.
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KAUSHIK, NIKHIL. "DESIGN OF AGC CIRCUITS FOR OSCILLATOR USING CURRENT CONVEYOR BASED TRANSLINEAR LOOPS." Thesis, 2013. http://dspace.dtu.ac.in:8080/jspui/handle/repository/15721.
Повний текст джерелаАнотація:
With the increasing demand of portable and battery driven devices a low
voltage operating devices has become necessary and for this current
mode techniques are ideally suited. This thesis is focused on current
conveyor based translinear(TL) loops in which a novel topology for TL
loops comprising of CMOS second Generation Current Conveyors (CC-II)
and diodes is studied. Using the same a new circuit of an integrator is
implemented using log-domain principle. Further, three circuits for
automatic gain control are proposed and implemented. All the proposed
circuits are verified for the functionality using PSPICE and 0.18μm TSMC
CMOS technology parameters.
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Cheng, Chih-Wei, and 鄭志蔚. "ADC circuits based on FPGA for VOA control circuits." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/33534406235187269851.
Повний текст джерелаАнотація:
碩士明新科技大學
電子工程研究所
101
In this dissertation, a variable optical attenuator control circuit among the FPGA making ADC to substitute an independent ADC IC has been designed and implemented. FPGA design makes ADC conversion time of one-fifth of the ADC0820CCN’s, and its total cost is reduced. The actual fastest conversion time of ADC0820CCN is 5μs. The actual fastest conversion time of the FPGA design is up 1μs. In the whole system, the analog circuits include two O/E (Optical to Electro) convertors, two ADCs (Analog to Digital Converters), one DAC (Digital to Analog Converter), one VOA driver, and two rectifier circuits. The digital circuits are designed on FPGA development board (the Max II Starter Kit) and the software are programmed, simulated, and burn by ALTEAR Quartus II 7.2. In the system, the clock frequency is 1 MHz. When fine tune method is employed, the translation times of the attenuation ratios changing from 2 to 10 and from 10 to 2 are 2 ms and 2.2 ms, respectively, and the translation times of the attenuation ratios changing from 1 to 97 and from 97 to 1 are 2.8 ms and 4.2 ms, respectively. While table-lookup method is used, the translation times of the attenuation ratios changing from 2 to 10 and from 10 to 2 are 0.64 ms and 0.72 ms, respectively, and the translation times of the attenuation ratios changing from 1 to 97 and from 97 to 1 are 0.48 ms and 0.52 ms, respectively. The experiment results of the FPGA making the ADC can be achieved optimization and fastest conversion time of the system.